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| author |   Wade Farnsworth <wfarnsworth@users.noreply.github.com> | 2020-01-23 09:02:30 -0700 |
|---|---|---|
| committer |   GitHub <noreply@github.com> | 2020-01-23 09:02:30 -0700 |
| commit | 02094cdceeeb622cac0c2969484455d7d64c8d4f (patch) | |
| tree | 200a6d37b37388f499676f1e51b448ac739f1704 | |
| parent | 8e04a3f15f6fa7a18d63625091cfd0795a211305 (diff) | |
| parent | d92b4b16d487e2722707edd866cb07dbdc518549 (diff) | |
| download | meta-amd-02094cdceeeb622cac0c2969484455d7d64c8d4f.tar.gz meta-amd-02094cdceeeb622cac0c2969484455d7d64c8d4f.tar.bz2 meta-amd-02094cdceeeb622cac0c2969484455d7d64c8d4f.zip | |
Merge pull request #675 from chaudharyak/warrior
R1000_LP : add 4.19.8 amdgpu patch for R1000 LP
642 files changed, 86893 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_asd.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_asd.bin Binary files differindex 186cb5b4..2c4cda74 100644 --- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_asd.bin +++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_asd.bin diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_ce.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_ce.bin Binary files differindex 015bb206..5e915181 100644 --- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_ce.bin +++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_ce.bin diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_me.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_me.bin Binary files differindex b2e0ec2d..3abf70a0 100644 --- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_me.bin +++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_me.bin diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec.bin Binary files differindex 5b68507f..738dc4c5 100644 --- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec.bin +++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec.bin diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec2.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec2.bin Binary files differindex 5b68507f..738dc4c5 100644 --- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec2.bin +++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec2.bin diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_pfp.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_pfp.bin Binary files differindex 17597231..77caf229 100644 --- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_pfp.bin +++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_pfp.bin diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_sdma.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_sdma.bin Binary files differindex 80e4fb65..139b9553 100644 --- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_sdma.bin +++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_sdma.bin diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4103-modifying-link-and-led-state-with-respect-to-cable-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4103-modifying-link-and-led-state-with-respect-to-cable-c.patch new file mode 100644 index 00000000..447629ee --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4103-modifying-link-and-led-state-with-respect-to-cable-c.patch @@ -0,0 +1,210 @@ +From 89a9f6eee64e54ce282584cfc7bedcdd944f7c4b Mon Sep 17 00:00:00 2001 +From: Pavan Kumar Ramayanam <pavan.ramayanam@amd.com> +Date: Tue, 12 Nov 2019 18:15:16 +0530 +Subject: [PATCH 4103/4736] modifying link and led state with respect to cable + connection + + Enable Marvell PHY 10G linkup on Bilby. The current + 10G linkup happens only in backplane mode, meaning there will be no sideband + to talk to the external PHY connected onboard. So, when the driver reads the + port property as BACKPLANE, technically we are not supposed to go and read + what is the external PHY connected through MDIO. This changes are only a + workaround to read the external phy through MDIO in backplane mode. +--- + drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c | 30 ++++++-- + drivers/net/phy/marvell10g.c | 80 ++++++++++++++++++++- + 2 files changed, 105 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +index 9cddcc8433e1..a6fb6754984f 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +@@ -156,6 +156,11 @@ + /* RRC frequency during link status check */ + #define XGBE_RRC_FREQUENCY 10 + ++/* Enable Marvell PHY writes by forcing the MDIO connections */ ++static int force_mdio_mv_bp_con = 1; ++module_param(force_mdio_mv_bp_con, uint, 0644); ++MODULE_PARM_DESC(force_mdio_mv_bp_con, ++ " Enable Marvell PHY writes by forcing the MDIO connections"); + enum xgbe_port_mode { + XGBE_PORT_MODE_RSVD = 0, + XGBE_PORT_MODE_BACKPLANE, +@@ -985,8 +990,15 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) + pdata->an_again = 0; + + /* Check for the use of an external PHY */ +- if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) +- return 0; ++ if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) { ++ if(force_mdio_mv_bp_con) { ++ phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; ++ phy_data->conn_type = XGBE_CONN_TYPE_MDIO; ++ netif_dbg(pdata, drv, pdata->netdev, "*** DEBUG: %s - bypass phydev_mode check\n", __func__); ++ } else { ++ return 0; ++ } ++ } + + /* For SFP, only use an external PHY if available */ + if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && +@@ -1011,7 +1023,7 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) + return -ENODEV; + } + netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n", +- phydev->phy_id); ++ (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45) ? phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] : phydev->phy_id); + + /*TODO: If c45, add request_module based on one of the MMD ids? */ + +@@ -1034,6 +1046,14 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) + + xgbe_phy_external_phy_quirks(pdata); + ++ if(force_mdio_mv_bp_con) { ++ phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; ++ phy_data->conn_type = XGBE_CONN_TYPE_BACKPLANE; ++ netif_dbg(pdata, drv, pdata->netdev, "phy_dev removed!\n"); ++ xgbe_phy_free_phy_device(pdata); ++ return 0; ++ } ++ + ethtool_convert_link_mode_to_legacy_u32(&advertising, + lks->link_modes.advertising); + phydev->advertising &= advertising; +@@ -2551,8 +2571,10 @@ static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) + return 0; + + if ((pdata->phy.autoneg == AUTONEG_ENABLE) && +- !phy_aneg_done(phy_data->phydev)) ++ !phy_aneg_done(phy_data->phydev)) { ++ netif_dbg(pdata, drv, pdata->netdev,"%s Ext phy AN not complete!\n", __func__); + return 0; ++ } + + if (!phy_data->phydev->link) + return 0; +diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c +index f77a2d9e7f9d..080272a3d2b6 100644 +--- a/drivers/net/phy/marvell10g.c ++++ b/drivers/net/phy/marvell10g.c +@@ -25,6 +25,7 @@ + #include <linux/hwmon.h> + #include <linux/marvell_phy.h> + #include <linux/phy.h> ++#include <linux/delay.h> + + enum { + MV_PCS_BASE_T = 0x0000, +@@ -48,7 +49,12 @@ enum { + MV_V2_TEMP_CTRL_MASK = 0xc000, + MV_V2_TEMP_CTRL_SAMPLE = 0x0000, + MV_V2_TEMP_CTRL_DISABLE = 0xc000, ++ MV_V2_MODE_CFG = 0xf000, ++ MV_V2_PORT_CTRL = 0xf001, ++ MV_V2_LED0_CTRL = 0xf020, + MV_V2_TEMP = 0xf08c, ++ MV_V2_HOST_KR_ENABLE = 0xf084, ++ MV_V2_HOST_KR_TUNE = 0xf07c, + MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ + }; + +@@ -75,7 +81,7 @@ static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg, + return ret < 0 ? ret : 1; + } + +-#ifdef CONFIG_HWMON ++#ifdef CONFIG_HWMON_MV + static umode_t mv3310_hwmon_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +@@ -249,6 +255,77 @@ static int mv3310_resume(struct phy_device *phydev) + return mv3310_hwmon_config(phydev, true); + } + ++ ++/* Some PHYs within the Alaska family like 88x3310 has problems with the ++ * KR Auto-negotiation. marvell datasheet for 88x3310 section 6.2.11 says that ++ * KR auto-negotitaion can be enabled to adapt to the incoming SERDES by writing ++ * to autoneg registers and the PMA/PMD registers ++ */ ++static int mv3310_amd_quirk(struct phy_device *phydev) ++{ ++ int reg=0, count=0; ++ int version, subversion; ++ ++ version = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 0xC011); ++ subversion = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 0xC012); ++ dev_dbg(&phydev->mdio.dev,"%s: Marvell FW Version: %x.%x \n", __func__, version, subversion); ++ ++ if(subversion != 0x400) ++ return 0; ++ ++ reg = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MV_V2_HOST_KR_ENABLE); ++ reg |= 0x8000; ++ phy_write_mmd(phydev, MDIO_MMD_PHYXS, MV_V2_HOST_KR_ENABLE, reg); ++ ++ reg = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MV_V2_HOST_KR_TUNE); ++ reg = (reg & ~0x8000) | 0x4000; ++ phy_write_mmd(phydev, MDIO_MMD_PHYXS, MV_V2_HOST_KR_TUNE, reg); ++ ++ if((reg & BIT(8)) && (reg & BIT(11))) { ++ reg = phy_read_mmd(phydev, MDIO_MMD_AN, MV_PCS_BASE_R); ++ /* disable BASE-R */ ++ phy_write_mmd(phydev, MDIO_MMD_AN, MV_PCS_BASE_R, reg); ++ } else { ++ reg = phy_read_mmd(phydev, MDIO_MMD_AN, MV_PCS_BASE_R); ++ /* enable BASE-R for KR initiation */ ++ reg |= 0x1000; ++ phy_write_mmd(phydev, MDIO_MMD_AN, MV_PCS_BASE_R, reg); ++ } ++ ++ /* down the port if no link */ ++ reg = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_MODE_CFG); ++ reg &= 0xFFF7; ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_MODE_CFG, reg); ++ ++ /* reset port to effect above change */ ++ reg = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); ++ reg |= 0x8000; ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, reg); ++ ++ /* wait till reset complete */ ++ count = 50; ++ do { ++ msleep(10); ++ reg = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); ++ } while ((reg & 0x8000) && --count); ++ ++ if(reg & 0x8000){ ++ dev_warn(&phydev->mdio.dev,"%s: Port Reset taking long time\n", __func__); ++ return -ETIMEDOUT; ++ } ++ ++ /* LED0 Amber light On-Off settings [1:0]=01 */ ++ reg = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_LED0_CTRL); ++ if((reg & 0x3) != 0x1) { ++ reg &= 0xFFFC; ++ reg |= 0x1; ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_LED0_CTRL, reg); ++ } ++ ++ dev_dbg(&phydev->mdio.dev,"%s: quirk applied\n", __func__); ++ return 0; ++} ++ + static int mv3310_config_init(struct phy_device *phydev) + { + __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, }; +@@ -274,6 +351,7 @@ static int mv3310_config_init(struct phy_device *phydev) + __set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); + } + ++ mv3310_amd_quirk(phydev); + val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); + if (val < 0) + return val; +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4104-Fix-hot-plug-failure-with-SFP-RJ45-module.-Do-force-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4104-Fix-hot-plug-failure-with-SFP-RJ45-module.-Do-force-.patch new file mode 100644 index 00000000..9bbb1ee4 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4104-Fix-hot-plug-failure-with-SFP-RJ45-module.-Do-force-.patch @@ -0,0 +1,42 @@ +From e33b0e04ddd97a9ed4a04f001255fb23263cfa13 Mon Sep 17 00:00:00 2001 +From: Sudheer Anumolu <sudheer.anumolu@amd.com> +Date: Tue, 26 Nov 2019 18:37:56 +0530 +Subject: [PATCH 4104/4736] Fix hot plug failure with SFP+RJ45 module. Do force + MDIO only if an external phy is available. + +--- + drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c | 11 +++++++---- + 1 file changed, 7 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +index a6fb6754984f..3fcfd7cb04d6 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +@@ -989,6 +989,13 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) + /* Clear the extra AN flag */ + pdata->an_again = 0; + ++ /* For SFP, only use an external PHY if available */ ++ if (phy_data->port_mode == XGBE_PORT_MODE_SFP) { ++ force_mdio_mv_bp_con = 0; ++ if(!phy_data->sfp_phy_avail) ++ return 0; ++ } ++ + /* Check for the use of an external PHY */ + if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) { + if(force_mdio_mv_bp_con) { +@@ -1000,10 +1007,6 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) + } + } + +- /* For SFP, only use an external PHY if available */ +- if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && +- !phy_data->sfp_phy_avail) +- return 0; + + /* Set the proper MDIO mode for the PHY */ + ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4105-Reverting-enable-VCN-DPG-on-Raven-and-Raven2-due-to-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4105-Reverting-enable-VCN-DPG-on-Raven-and-Raven2-due-to-.patch new file mode 100644 index 00000000..27db294f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4105-Reverting-enable-VCN-DPG-on-Raven-and-Raven2-due-to-.patch @@ -0,0 +1,39 @@ +From d5b814c2e71b2bb51b3f24ef7fb0b5ea6e5f418c Mon Sep 17 00:00:00 2001 +From: Pavan Kumar Ramayanam <pavan.ramayanam@amd.com> +Date: Fri, 29 Nov 2019 09:44:24 +0530 +Subject: [PATCH 4105/4736] Reverting enable VCN DPG on Raven and Raven2 due to + power efficiency degradation and hang issues + +--- + drivers/gpu/drm/amd/amdgpu/soc15.c | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index 3acfdc1e2bfd..a77f9b708f7f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -1121,9 +1121,7 @@ static int soc15_common_early_init(void *handle) + AMD_CG_SUPPORT_SDMA_LS | + AMD_CG_SUPPORT_VCN_MGCG; + +- adev->pg_flags = AMD_PG_SUPPORT_SDMA | +- AMD_PG_SUPPORT_VCN | +- AMD_PG_SUPPORT_VCN_DPG; ++ adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; + } else if (adev->pdev->device == 0x15d8) { + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_MGLS | +@@ -1166,9 +1164,7 @@ static int soc15_common_early_init(void *handle) + AMD_CG_SUPPORT_SDMA_LS | + AMD_CG_SUPPORT_VCN_MGCG; + +- adev->pg_flags = AMD_PG_SUPPORT_SDMA | +- AMD_PG_SUPPORT_VCN | +- AMD_PG_SUPPORT_VCN_DPG; ++ adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; + } + break; + case CHIP_ARCTURUS: +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4106-drm-amdgpu-sdma5-fix-mask-value-of-POLL_REGMEM-packe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4106-drm-amdgpu-sdma5-fix-mask-value-of-POLL_REGMEM-packe.patch new file mode 100644 index 00000000..9ea16d73 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4106-drm-amdgpu-sdma5-fix-mask-value-of-POLL_REGMEM-packe.patch @@ -0,0 +1,30 @@ +From 55c838d55e504ca7834858d16a72f644adbb59d3 Mon Sep 17 00:00:00 2001 +From: Xiaojie Yuan <xiaojie.yuan@amd.com> +Date: Thu, 10 Oct 2019 01:01:23 +0800 +Subject: [PATCH 4106/4736] drm/amdgpu/sdma5: fix mask value of POLL_REGMEM + packet for pipe sync + +sdma will hang once sequence number to be polled reaches 0x1000_0000 + +Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +index ad5c3566337c..3460c00f3eaa 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +@@ -1126,7 +1126,7 @@ static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) + amdgpu_ring_write(ring, addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); + amdgpu_ring_write(ring, seq); /* reference */ +- amdgpu_ring_write(ring, 0xfffffff); /* mask */ ++ amdgpu_ring_write(ring, 0xffffffff); /* mask */ + amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ + } +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4107-drm-amdgpu-powerplay-fix-typo-in-mvdd-table-setup.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4107-drm-amdgpu-powerplay-fix-typo-in-mvdd-table-setup.patch new file mode 100644 index 00000000..6d8301bd --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4107-drm-amdgpu-powerplay-fix-typo-in-mvdd-table-setup.patch @@ -0,0 +1,50 @@ +From 6a850ace36127bc4ed674ce691f282c0aeeb930b Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Wed, 2 Oct 2019 16:10:24 -0500 +Subject: [PATCH 4107/4736] drm/amdgpu/powerplay: fix typo in mvdd table setup + +Polaris and vegam use count for the value rather than +level. This looks like a copy paste typo from when +the code was adapted from previous asics. + +I'm not sure that the SMU actually uses this value, so +I don't know that it actually is a bug per se. + +Bug: https://bugs.freedesktop.org/show_bug.cgi?id=108609 +Reported-by: Robert Strube <rstrube@gmail.com> +Reviewed-by: Evan Quan <evan.quan@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 2 +- + drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +index a1a9f6196009..2ab589e33b7b 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +@@ -653,7 +653,7 @@ static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, + count = SMU_MAX_SMIO_LEVELS; + for (level = 0; level < count; level++) { + table->SmioTable2.Pattern[level].Voltage = +- PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE); ++ PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE); + /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/ + table->SmioTable2.Pattern[level].Smio = + (uint8_t) level; +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c +index 7c960b07746f..ae18fbcb26fb 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c +@@ -456,7 +456,7 @@ static int vegam_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, + count = SMU_MAX_SMIO_LEVELS; + for (level = 0; level < count; level++) { + table->SmioTable2.Pattern[level].Voltage = PP_HOST_TO_SMC_US( +- data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE); ++ data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE); + /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/ + table->SmioTable2.Pattern[level].Smio = + (uint8_t) level; +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4108-drm-amdgpu-powerplay-Use-swap-where-appropriate.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4108-drm-amdgpu-powerplay-Use-swap-where-appropriate.patch new file mode 100644 index 00000000..2c20817a --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4108-drm-amdgpu-powerplay-Use-swap-where-appropriate.patch @@ -0,0 +1,93 @@ +From 2fb67226c024d6c53c787651d548933ca91b9309 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com> +Date: Thu, 10 Oct 2019 16:11:58 +0300 +Subject: [PATCH 4108/4736] drm/amdgpu/powerplay: Use swap() where appropriate +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +@swap@ +identifier TEMP; +expression A,B; +@@ +- TEMP = A; +- A = B; +- B = TEMP; ++ swap(A, B); + +@@ +type T; +identifier swap.TEMP; +@@ +( +- T TEMP; +| +- T TEMP = {...}; +) +... when != TEMP + +Cc: Rex Zhu <rex.zhu@amd.com> +Cc: Evan Quan <evan.quan@amd.com> +Cc: Alex Deucher <alexander.deucher@amd.com> +Cc: "Christian König" <christian.koenig@amd.com> +Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> +Cc: amd-gfx@lists.freedesktop.org +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 ++---- + drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 6 ++---- + 2 files changed, 4 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index 25e68f245dba..897fd494fe33 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -1993,7 +1993,6 @@ static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr, + struct phm_ppt_v1_voltage_lookup_table *lookup_table) + { + uint32_t table_size, i, j; +- struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record; + table_size = lookup_table->count; + + PP_ASSERT_WITH_CODE(0 != lookup_table->count, +@@ -2004,9 +2003,8 @@ static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr, + for (j = i + 1; j > 0; j--) { + if (lookup_table->entries[j].us_vdd < + lookup_table->entries[j - 1].us_vdd) { +- tmp_voltage_lookup_record = lookup_table->entries[j - 1]; +- lookup_table->entries[j - 1] = lookup_table->entries[j]; +- lookup_table->entries[j] = tmp_voltage_lookup_record; ++ swap(lookup_table->entries[j - 1], ++ lookup_table->entries[j]); + } + } + } +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index ccceaba5914a..c31ef4262c9e 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -711,7 +711,6 @@ static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr, + struct phm_ppt_v1_voltage_lookup_table *lookup_table) + { + uint32_t table_size, i, j; +- struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record; + + PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count, + "Lookup table is empty", return -EINVAL); +@@ -723,9 +722,8 @@ static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr, + for (j = i + 1; j > 0; j--) { + if (lookup_table->entries[j].us_vdd < + lookup_table->entries[j - 1].us_vdd) { +- tmp_voltage_lookup_record = lookup_table->entries[j - 1]; +- lookup_table->entries[j - 1] = lookup_table->entries[j]; +- lookup_table->entries[j] = tmp_voltage_lookup_record; ++ swap(lookup_table->entries[j - 1], ++ lookup_table->entries[j]); + } + } + } +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4109-drm-amdgpu-swSMU-navi-add-feature-toggles-for-more-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4109-drm-amdgpu-swSMU-navi-add-feature-toggles-for-more-t.patch new file mode 100644 index 00000000..a68d1424 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4109-drm-amdgpu-swSMU-navi-add-feature-toggles-for-more-t.patch @@ -0,0 +1,73 @@ +From 685533c7ed2d5c4ad8d10df1f5d8a4868f440309 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Wed, 9 Oct 2019 08:14:03 -0500 +Subject: [PATCH 4109/4736] drm/amdgpu/swSMU/navi: add feature toggles for more + things + +Add toggles for more power features. Helpful in debugging. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Kevin Wang <kevin1.wang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 24 ++++++++++++++++------ + 1 file changed, 18 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +index 68cbcc792ec1..52a2feef7893 100644 +--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c ++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +@@ -327,11 +327,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, + memset(feature_mask, 0, sizeof(uint32_t) * num); + + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) +- | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) +- | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) + | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) +- | FEATURE_MASK(FEATURE_DPM_LINK_BIT) +- | FEATURE_MASK(FEATURE_GFX_ULV_BIT) + | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) + | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) + | FEATURE_MASK(FEATURE_PPT_BIT) +@@ -342,8 +338,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, + | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) + | FEATURE_MASK(FEATURE_THERMAL_BIT) + | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) +- | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) +- | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT) + | FEATURE_MASK(FEATURE_DS_LCLK_BIT) + | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) + | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) +@@ -354,11 +348,29 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, + | FEATURE_MASK(FEATURE_FW_CTF_BIT) + | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); + ++ if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) ++ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); ++ ++ if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) ++ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); ++ ++ if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) ++ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); ++ ++ if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) ++ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); ++ + if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) + | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) + | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); + ++ if (adev->pm.pp_feature & PP_ULV_MASK) ++ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); ++ ++ if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) ++ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); ++ + if (adev->pm.pp_feature & PP_GFXOFF_MASK) { + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); + /* TODO: remove it once fw fix the bug */ +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch new file mode 100644 index 00000000..8804632e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch @@ -0,0 +1,144 @@ +From 38ff634117407a29df3b641470f954694492b934 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Thu, 10 Oct 2019 11:34:51 +0800 +Subject: [PATCH 4110/4736] drm/amd/powerplay: enable df cstate control on + powerplay routine + +Currently this is only supported on Vega20 with 40.50 and later +SMC firmware. + +Change-Id: I4f2f7936a3bc6e1a32d590bc76ebfc9a5a53f9cb +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> +--- + .../gpu/drm/amd/include/kgd_pp_interface.h | 6 ++++++ + drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 ++++++++++++++++++ + .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 19 +++++++++++++++++++ + drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 + + .../gpu/drm/amd/powerplay/inc/vega20_ppsmc.h | 3 ++- + 5 files changed, 46 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h +index 27cf0afaa0b4..5902f80d1fce 100644 +--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h ++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h +@@ -179,6 +179,11 @@ enum pp_mp1_state { + PP_MP1_STATE_RESET, + }; + ++enum pp_df_cstate { ++ DF_CSTATE_DISALLOW = 0, ++ DF_CSTATE_ALLOW, ++}; ++ + #define PP_GROUP_MASK 0xF0000000 + #define PP_GROUP_SHIFT 28 + +@@ -312,6 +317,7 @@ struct amd_pm_funcs { + int (*get_ppfeature_status)(void *handle, char *buf); + int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); + int (*asic_reset_mode_2)(void *handle); ++ int (*set_df_cstate)(void *handle, enum pp_df_cstate state); + }; + + #endif +diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +index fa8ad7db2b3a..83196b79edd5 100644 +--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c ++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +@@ -1548,6 +1548,23 @@ static int pp_smu_i2c_bus_access(void *handle, bool acquire) + return ret; + } + ++static int pp_set_df_cstate(void *handle, enum pp_df_cstate state) ++{ ++ struct pp_hwmgr *hwmgr = handle; ++ ++ if (!hwmgr) ++ return -EINVAL; ++ ++ if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate) ++ return 0; ++ ++ mutex_lock(&hwmgr->smu_lock); ++ hwmgr->hwmgr_func->set_df_cstate(hwmgr, state); ++ mutex_unlock(&hwmgr->smu_lock); ++ ++ return 0; ++} ++ + static const struct amd_pm_funcs pp_dpm_funcs = { + .load_firmware = pp_dpm_load_fw, + .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, +@@ -1606,4 +1623,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = { + .set_ppfeature_status = pp_set_ppfeature_status, + .asic_reset_mode_2 = pp_asic_reset_mode_2, + .smu_i2c_bus_access = pp_smu_i2c_bus_access, ++ .set_df_cstate = pp_set_df_cstate, + }; +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +index f5915308e643..6629c475fe5d 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +@@ -4155,6 +4155,24 @@ static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire) + return res; + } + ++static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr, ++ enum pp_df_cstate state) ++{ ++ int ret; ++ ++ /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */ ++ if (hwmgr->smu_version < 0x283200) { ++ pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n"); ++ return -EINVAL; ++ } ++ ++ ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DFCstateControl, state); ++ if (ret) ++ pr_err("SetDfCstate failed!\n"); ++ ++ return ret; ++} ++ + static const struct pp_hwmgr_func vega20_hwmgr_funcs = { + /* init/fini related */ + .backend_init = vega20_hwmgr_backend_init, +@@ -4223,6 +4241,7 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = { + .set_asic_baco_state = vega20_baco_set_state, + .set_mp1_state = vega20_set_mp1_state, + .smu_i2c_bus_access = vega20_smu_i2c_bus_access, ++ .set_df_cstate = vega20_set_df_cstate, + }; + + int vega20_hwmgr_init(struct pp_hwmgr *hwmgr) +diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +index 7bf9a14bfa0b..bd8c922dfd3e 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +@@ -355,6 +355,7 @@ struct pp_hwmgr_func { + int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state); + int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode); + int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire); ++ int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state); + }; + + struct pp_table_func { +diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h +index a0883038f3c3..0c66f0fe1aaf 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h +@@ -120,7 +120,8 @@ + #define PPSMC_MSG_SetMGpuFanBoostLimitRpm 0x5D + #define PPSMC_MSG_GetAVFSVoltageByDpm 0x5F + #define PPSMC_MSG_BacoWorkAroundFlushVDCI 0x60 +-#define PPSMC_Message_Count 0x61 ++#define PPSMC_MSG_DFCstateControl 0x63 ++#define PPSMC_Message_Count 0x64 + + typedef uint32_t PPSMC_Result; + typedef uint32_t PPSMC_Msg; +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4111-drm-amd-powerplay-enable-df-cstate-control-on-swSMU-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4111-drm-amd-powerplay-enable-df-cstate-control-on-swSMU-.patch new file mode 100644 index 00000000..d777f677 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4111-drm-amd-powerplay-enable-df-cstate-control-on-swSMU-.patch @@ -0,0 +1,138 @@ +From b3603c96916c7799c3efaf21bf9038ceca4fb521 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Thu, 10 Oct 2019 11:40:37 +0800 +Subject: [PATCH 4111/4736] drm/amd/powerplay: enable df cstate control on + swSMU routine + +Currently this is only supported on Vega20 with 40.50 and later +SMC firmware. + +Change-Id: I8397f9ccc5dec32dc86ef7635c5ed227c77e61a3 +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> +--- + drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 23 +++++++++++++++++ + .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++ + drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 1 + + drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 25 ++++++++++++++++++- + 4 files changed, 51 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +index 054376342454..a37a1b1d8abd 100644 +--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +@@ -1834,6 +1834,29 @@ int smu_set_mp1_state(struct smu_context *smu, + return ret; + } + ++int smu_set_df_cstate(struct smu_context *smu, ++ enum pp_df_cstate state) ++{ ++ int ret = 0; ++ ++ /* ++ * The SMC is not fully ready. That may be ++ * expected as the IP may be masked. ++ * So, just return without error. ++ */ ++ if (!smu->pm_enabled) ++ return 0; ++ ++ if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) ++ return 0; ++ ++ ret = smu->ppt_funcs->set_df_cstate(smu, state); ++ if (ret) ++ pr_err("[SetDfCstate] failed!\n"); ++ ++ return ret; ++} ++ + const struct amd_ip_funcs smu_ip_funcs = { + .name = "smu", + .early_init = smu_early_init, +diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +index ccf711c327c8..401affdee49d 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +@@ -468,6 +468,7 @@ struct pptable_funcs { + int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default); + int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type clk_type, + uint32_t dpm_level, uint32_t *freq); ++ int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); + }; + + struct smu_funcs +@@ -852,5 +853,7 @@ int smu_force_clk_levels(struct smu_context *smu, + uint32_t mask); + int smu_set_mp1_state(struct smu_context *smu, + enum pp_mp1_state mp1_state); ++int smu_set_df_cstate(struct smu_context *smu, ++ enum pp_df_cstate state); + + #endif +diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h +index 12a1de55ce3c..d8c9b7f91fcc 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h +@@ -169,6 +169,7 @@ + __SMU_DUMMY_MAP(PowerGateAtHub), \ + __SMU_DUMMY_MAP(SetSoftMinJpeg), \ + __SMU_DUMMY_MAP(SetHardMinFclkByFreq), \ ++ __SMU_DUMMY_MAP(DFCstateControl), \ + + #undef __SMU_DUMMY_MAP + #define __SMU_DUMMY_MAP(type) SMU_MSG_##type +diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +index 99effde33ac1..1050566cb69a 100644 +--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c ++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +@@ -143,6 +143,7 @@ static struct smu_11_0_cmn2aisc_mapping vega20_message_map[SMU_MSG_MAX_COUNT] = + MSG_MAP(PrepareMp1ForShutdown), + MSG_MAP(SetMGpuFanBoostLimitRpm), + MSG_MAP(GetAVFSVoltageByDpm), ++ MSG_MAP(DFCstateControl), + }; + + static struct smu_11_0_cmn2aisc_mapping vega20_clk_map[SMU_CLK_COUNT] = { +@@ -3135,6 +3136,27 @@ static int vega20_get_thermal_temperature_range(struct smu_context *smu, + return 0; + } + ++static int vega20_set_df_cstate(struct smu_context *smu, ++ enum pp_df_cstate state) ++{ ++ uint32_t smu_version; ++ int ret; ++ ++ ret = smu_get_smc_version(smu, NULL, &smu_version); ++ if (ret) { ++ pr_err("Failed to get smu version!\n"); ++ return ret; ++ } ++ ++ /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */ ++ if (smu_version < 0x283200) { ++ pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n"); ++ return -EINVAL; ++ } ++ ++ return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state); ++} ++ + static const struct pptable_funcs vega20_ppt_funcs = { + .tables_init = vega20_tables_init, + .alloc_dpm_context = vega20_allocate_dpm_context, +@@ -3177,7 +3199,8 @@ static const struct pptable_funcs vega20_ppt_funcs = { + .get_fan_speed_percent = vega20_get_fan_speed_percent, + .get_fan_speed_rpm = vega20_get_fan_speed_rpm, + .set_watermarks_table = vega20_set_watermarks_table, +- .get_thermal_temperature_range = vega20_get_thermal_temperature_range ++ .get_thermal_temperature_range = vega20_get_thermal_temperature_range, ++ .set_df_cstate = vega20_set_df_cstate, + }; + + void vega20_set_ppt_funcs(struct smu_context *smu) +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4112-drm-amdgpu-avoid-ras-error-injection-for-retired-pag.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4112-drm-amdgpu-avoid-ras-error-injection-for-retired-pag.patch new file mode 100644 index 00000000..604ab73f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4112-drm-amdgpu-avoid-ras-error-injection-for-retired-pag.patch @@ -0,0 +1,87 @@ +From 881a616e2e79841ce68a3cd7426a40f41c495a74 Mon Sep 17 00:00:00 2001 +From: Tao Zhou <tao.zhou1@amd.com> +Date: Mon, 30 Sep 2019 14:48:19 +0800 +Subject: [PATCH 4112/4736] drm/amdgpu: avoid ras error injection for retired + page + +check whether a page is bad page before umc error injection, bad page +should not be accessed again + +Signed-off-by: Tao Zhou <tao.zhou1@amd.com> +Reviewed-by: Guchun Chen <guchun.chen@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 44 +++++++++++++++++++++++++ + 1 file changed, 44 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +index 18af80f1cffd..f3f3a98f93b3 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +@@ -69,6 +69,9 @@ const char *ras_block_string[] = { + + atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); + ++static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, ++ uint64_t addr); ++ + static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) + { +@@ -289,6 +292,14 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user * + break; + } + ++ /* umc ce/ue error injection for a bad page is not allowed */ ++ if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && ++ amdgpu_ras_check_bad_page(adev, data.inject.address)) { ++ DRM_WARN("RAS WARN: 0x%llx has been marked as bad before error injection!\n", ++ data.inject.address); ++ break; ++ } ++ + /* data.inject.address is offset instead of absolute gpu address */ + ret = amdgpu_ras_error_inject(adev, &data.inject); + break; +@@ -1429,6 +1440,39 @@ static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) + return ret; + } + ++/* ++ * check if an address belongs to bad page ++ * ++ * Note: this check is only for umc block ++ */ ++static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, ++ uint64_t addr) ++{ ++ struct amdgpu_ras *con = amdgpu_ras_get_context(adev); ++ struct ras_err_handler_data *data; ++ int i; ++ bool ret = false; ++ ++ if (!con || !con->eh_data) ++ return ret; ++ ++ mutex_lock(&con->recovery_lock); ++ data = con->eh_data; ++ if (!data) ++ goto out; ++ ++ addr >>= AMDGPU_GPU_PAGE_SHIFT; ++ for (i = 0; i < data->count; i++) ++ if (addr == data->bps[i].retired_page) { ++ ret = true; ++ goto out; ++ } ++ ++out: ++ mutex_unlock(&con->recovery_lock); ++ return ret; ++} ++ + /* called in gpu recovery/init */ + int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev) + { +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4113-drm-amdgpu-fix-memory-leak.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4113-drm-amdgpu-fix-memory-leak.patch new file mode 100644 index 00000000..e8a01f08 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4113-drm-amdgpu-fix-memory-leak.patch @@ -0,0 +1,68 @@ +From 6ab8eec947ae191bede5fc2d9b9208a82a55196c Mon Sep 17 00:00:00 2001 +From: Nirmoy Das <nirmoy.das@amd.com> +Date: Fri, 4 Oct 2019 11:53:37 +0200 +Subject: [PATCH 4113/4736] drm/amdgpu: fix memory leak +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +cleanup error handling code and make sure temporary info array +with the handles are freed by amdgpu_bo_list_put() on +idr_replace()'s failure. + +Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> +Reviewed-by: Christian König <christian.koenig@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +index ea05784624ed..e143d9e110bd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +@@ -270,7 +270,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, + + r = amdgpu_bo_create_list_entry_array(&args->in, &info); + if (r) +- goto error_free; ++ return r; + + switch (args->in.operation) { + case AMDGPU_BO_LIST_OP_CREATE: +@@ -283,8 +283,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, + r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, GFP_KERNEL); + mutex_unlock(&fpriv->bo_list_lock); + if (r < 0) { +- amdgpu_bo_list_put(list); +- return r; ++ goto error_put_list; + } + + handle = r; +@@ -306,9 +305,8 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, + mutex_unlock(&fpriv->bo_list_lock); + + if (IS_ERR(old)) { +- amdgpu_bo_list_put(list); + r = PTR_ERR(old); +- goto error_free; ++ goto error_put_list; + } + + amdgpu_bo_list_put(old); +@@ -325,8 +323,10 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, + + return 0; + ++error_put_list: ++ amdgpu_bo_list_put(list); ++ + error_free: +- if (info) +- kvfree(info); ++ kvfree(info); + return r; + } +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch new file mode 100644 index 00000000..ec27a9f0 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch @@ -0,0 +1,138 @@ +From e2eaca86311ae7819b9b62f77287bd1165d0a6f9 Mon Sep 17 00:00:00 2001 +From: Ramalingam C <ramalingam.c@intel.com> +Date: Mon, 29 Oct 2018 15:15:50 +0530 +Subject: [PATCH 4114/4736] drm: HDMI and DP specific HDCP2.2 defines + +This patch adds HDCP register definitions for HDMI and DP HDCP +adaptations. + +HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h, +where as HDCP2.2 register offsets in DPCD offsets are defined at +drm_dp_helper.h. + +v2: + bit_field definitions are replaced by macros. [Tomas and Jani] +v3: + No Changes. +v4: + Comments style and typos are fixed [Uma] +v5: + Fix for macros. +v6: + Adds _MS to the timeouts to represent units [Sean Paul] +v7: + Macro DP_HDCP_2_2_REG_EKH_KM_OFFSET renamed [Uma] + Redundant macro is removed [Uma] + +Signed-off-by: Ramalingam C <ramalingam.c@intel.com> +Reviewed-by: Sean Paul <seanpaul@chromium.org> +Acked-by: Sean Paul <seanpaul@chromium.org> (for merging through drm-intel) +Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> +Link: https://patchwork.freedesktop.org/patch/msgid/1540806351-7137-6-git-send-email-ramalingam.c@intel.com +--- + include/drm/drm_dp_helper.h | 51 +++++++++++++++++++++++++++++++++++++ + include/drm/drm_hdcp.h | 28 ++++++++++++++++++++ + 2 files changed, 79 insertions(+) + +diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h +index b81ec228ab8e..432e93ac3b3c 100644 +--- a/include/drm/drm_dp_helper.h ++++ b/include/drm/drm_dp_helper.h +@@ -913,6 +913,57 @@ + #define DP_AUX_HDCP_KSV_FIFO 0x6802C + #define DP_AUX_HDCP_AINFO 0x6803B + ++/* DP HDCP2.2 parameter offsets in DPCD address space */ ++#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000 ++#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008 ++#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B ++#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215 ++#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D ++#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220 ++#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0 ++#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0 ++#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0 ++#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0 ++#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0 ++#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8 ++#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318 ++#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328 ++#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330 ++#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332 ++#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335 ++#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345 ++#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0 ++#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0 ++#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3 ++#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5 ++#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473 ++#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493 ++#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 ++#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 ++ ++/* DP HDCP message start offsets in DPCD address space */ ++#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET ++#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET ++#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET ++#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET ++#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET ++#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \ ++ DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET ++#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET ++#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET ++#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET ++#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET ++#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET ++#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET ++#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET ++ ++#define HDCP_2_2_DP_RXSTATUS_LEN 1 ++#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0)) ++#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1)) ++#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2)) ++#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) ++#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4)) ++ + /* DP 1.2 Sideband message defines */ + /* peer device type - DP 1.2a Table 2-92 */ + #define DP_PEER_DEVICE_NONE 0x0 +diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h +index 98e63d870139..5e93faaa7015 100644 +--- a/include/drm/drm_hdcp.h ++++ b/include/drm/drm_hdcp.h +@@ -38,4 +38,32 @@ + #define DRM_HDCP_DDC_BSTATUS 0x41 + #define DRM_HDCP_DDC_KSV_FIFO 0x43 + ++/* HDCP2.2 TIMEOUTs in mSec */ ++#define HDCP_2_2_CERT_TIMEOUT_MS 100 ++#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000 ++#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200 ++#define HDCP_2_2_PAIRING_TIMEOUT_MS 200 ++#define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20 ++#define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 7 ++#define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000 ++#define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100 ++ ++/* HDMI HDCP2.2 Register Offsets */ ++#define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50 ++#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60 ++#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70 ++#define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80 ++#define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0 ++ ++#define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2) ++#define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02 ++#define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF ++#define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200 ++ ++/* Below macros take a byte at a time and mask the bit(s) */ ++#define HDCP_2_2_HDMI_RXSTATUS_LEN 2 ++#define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3) ++#define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2)) ++#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) ++ + #endif +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4115-drm-Add-link-training-repeaters-addresses.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4115-drm-Add-link-training-repeaters-addresses.patch new file mode 100644 index 00000000..3c5430bb --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4115-drm-Add-link-training-repeaters-addresses.patch @@ -0,0 +1,86 @@ +From 274e6cebf8d87f79c433c4d13ce82eb1d549aad3 Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> +Date: Mon, 9 Sep 2019 21:21:47 +0000 +Subject: [PATCH 4115/4736] drm: Add link training repeaters addresses +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +DP 1.3 specification introduces the Link Training-tunable PHY Repeater, +and DP 1.4* supplemented it with new features. In the 1.4a spec, it was +introduced some innovations to make handy to add support for systems +with Thunderbolt or other repeater devices. + +It is important to highlight that DP specification had some updates from +1.3 through 1.4a. In particular, DP 1.4 defines Repeater_FEC_CAPABILITY +at the address 0xf0004, and DP 1.4a redefined the address 0xf0004 to +DP_MAX_LANE_COUNT_PHY_REPEATER. + +Changes since V4: +- Update commit message +- Fix misleading comments related to the spec version +Changes since V3: +- Replace spaces by tabs +Changes since V2: +- Drop the kernel-doc comment +- Reorder LTTPR according to register offset +Changes since V1: +- Adjusts registers names to be aligned with spec and the rest of the + file +- Update spec comment from 1.4 to 1.4a + +Cc: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> +Cc: Harry Wentland <harry.wentland@amd.com> +Cc: Leo Li <sunpeng.li@amd.com> +Cc: Jani Nikula <jani.nikula@linux.intel.com> +Cc: Manasi Navare <manasi.d.navare@intel.com> +Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> +Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> +Signed-off-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> +Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com> +Link: https://patchwork.freedesktop.org/patch/msgid/20190909212144.deeomlsqihwg4l3y@outlook.office365.com +--- + include/drm/drm_dp_helper.h | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h +index 432e93ac3b3c..b2a2c92ac67c 100644 +--- a/include/drm/drm_dp_helper.h ++++ b/include/drm/drm_dp_helper.h +@@ -941,6 +941,32 @@ + #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 + #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 + ++/* Link Training (LT)-tunable PHY Repeaters */ ++#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */ ++#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */ ++#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */ ++#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */ ++#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ ++#define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ ++#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ ++#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ ++#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */ ++#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */ ++#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */ ++#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */ ++#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ ++#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */ ++#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */ ++#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */ ++#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */ ++#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */ ++#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */ ++#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */ ++#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */ ++#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */ ++#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */ ++#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */ ++ + /* DP HDCP message start offsets in DPCD address space */ + #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET + #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4116-drm-amdkfd-update-for-drmP.h-removal.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4116-drm-amdkfd-update-for-drmP.h-removal.patch new file mode 100644 index 00000000..b590044a --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4116-drm-amdkfd-update-for-drmP.h-removal.patch @@ -0,0 +1,37 @@ +From c9926ea4a27022847c208c12d17c6b90206d71f1 Mon Sep 17 00:00:00 2001 +From: Stephen Rothwell <sfr@canb.auug.org.au> +Date: Wed, 9 Oct 2019 11:35:57 +1100 +Subject: [PATCH 4116/4736] drm/amdkfd: update for drmP.h removal + +Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +index f856c14a6ed0..e7913212c1f6 100644 +--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h ++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +@@ -40,6 +40,9 @@ + #include <linux/interval_tree.h> + #include <linux/device_cgroup.h> + #include <drm/drmP.h> ++#include <drm/drm_file.h> ++#include <drm/drm_drv.h> ++#include <drm/drm_device.h> + #include <kgd_kfd_interface.h> + + #include "amd_shared.h" +@@ -51,8 +54,6 @@ + /* GPU ID hash width in bits */ + #define KFD_GPU_ID_HASH_WIDTH 16 + +-struct drm_device; +- + /* Use upper bits of mmap offset to store KFD driver specific information. + * BITS[63:62] - Encode MMAP type + * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4117-drm-amdgpu-Do-not-implement-power-on-for-SDMA-after-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4117-drm-amdgpu-Do-not-implement-power-on-for-SDMA-after-.patch new file mode 100644 index 00000000..3bdc66a4 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4117-drm-amdgpu-Do-not-implement-power-on-for-SDMA-after-.patch @@ -0,0 +1,35 @@ +From a6ee800e9b828b18b24f685e85de0aa79ee36fcb Mon Sep 17 00:00:00 2001 +From: chen gong <curry.gong@amd.com> +Date: Sun, 29 Sep 2019 10:58:43 +0800 +Subject: [PATCH 4117/4736] drm/amdgpu: Do not implement power-on for SDMA + after do mode2 reset on Renoir + +Find that ring sdma0 test failed if turn on SDMA powergating after do +mode2 reset. + +Perhaps the mode2 reset does not reset the SDMA PG state, SDMA is +already powered up so there is no need to ask the SMU to power it up +again. So I skip this function for a moment. + +Signed-off-by: chen gong <curry.gong@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +index 26f13de35b2c..78e21c12c17a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -1792,7 +1792,7 @@ static int sdma_v4_0_hw_init(void *handle) + + if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs && + adev->powerplay.pp_funcs->set_powergating_by_smu) || +- adev->asic_type == CHIP_RENOIR) ++ (adev->asic_type == CHIP_RENOIR && !adev->in_gpu_reset)) + amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); + + if (!amdgpu_sriov_vf(adev)) +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4118-drm-amdgpu-discovery-reserve-discovery-data-at-the-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4118-drm-amdgpu-discovery-reserve-discovery-data-at-the-t.patch new file mode 100644 index 00000000..9b42282e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4118-drm-amdgpu-discovery-reserve-discovery-data-at-the-t.patch @@ -0,0 +1,122 @@ +From 34c14c75f78c119fe8a7e2c666131a225710fd72 Mon Sep 17 00:00:00 2001 +From: Xiaojie Yuan <xiaojie.yuan@amd.com> +Date: Thu, 10 Oct 2019 20:44:20 +0800 +Subject: [PATCH 4118/4736] drm/amdgpu/discovery: reserve discovery data at the + top of VRAM + +IP Discovery data is TMR fenced by the latest PSP BL, +so we need to reserve this region. + +Tested on navi10/12/14 with VBIOS integrated with latest PSP BL. + +v2: use DISCOVERY_TMR_SIZE macro as bo size + use amdgpu_bo_create_kernel_at() to allocate bo + +Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 ++-- + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 2 ++ + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 17 +++++++++++++++++ + drivers/gpu/drm/amd/include/discovery.h | 1 - + 5 files changed, 22 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index 3bb4b7c6a42d..a994117c4edc 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -799,6 +799,7 @@ struct amdgpu_device { + uint8_t *bios; + uint32_t bios_size; + struct amdgpu_bo *stolen_vga_memory; ++ struct amdgpu_bo *discovery_memory; + uint32_t bios_scratch_reg_offset; + uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +index 1481899f86c1..71198c5318e1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +@@ -136,7 +136,7 @@ static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *bin + { + uint32_t *p = (uint32_t *)binary; + uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; +- uint64_t pos = vram_size - BINARY_MAX_SIZE; ++ uint64_t pos = vram_size - DISCOVERY_TMR_SIZE; + unsigned long flags; + + while (pos < vram_size) { +@@ -179,7 +179,7 @@ int amdgpu_discovery_init(struct amdgpu_device *adev) + uint16_t checksum; + int r; + +- adev->discovery = kzalloc(BINARY_MAX_SIZE, GFP_KERNEL); ++ adev->discovery = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL); + if (!adev->discovery) + return -ENOMEM; + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h +index 85b8c4d4d576..5a6693d7d269 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h +@@ -24,6 +24,8 @@ + #ifndef __AMDGPU_DISCOVERY__ + #define __AMDGPU_DISCOVERY__ + ++#define DISCOVERY_TMR_SIZE (64 << 10) ++ + int amdgpu_discovery_init(struct amdgpu_device *adev); + void amdgpu_discovery_fini(struct amdgpu_device *adev); + int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev); +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +index 87284e8c8ece..0c1af24f8bc0 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +@@ -2063,6 +2063,20 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) + NULL, &stolen_vga_buf); + if (r) + return r; ++ ++ /* ++ * reserve one TMR (64K) memory at the top of VRAM which holds ++ * IP Discovery data and is protected by PSP. ++ */ ++ r = amdgpu_bo_create_kernel_at(adev, ++ adev->gmc.real_vram_size - DISCOVERY_TMR_SIZE, ++ DISCOVERY_TMR_SIZE, ++ AMDGPU_GEM_DOMAIN_VRAM, ++ &adev->discovery_memory, ++ NULL); ++ if (r) ++ return r; ++ + DRM_INFO("amdgpu: %uM of VRAM memory ready\n", + (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); + +@@ -2132,6 +2146,9 @@ void amdgpu_ttm_late_init(struct amdgpu_device *adev) + void *stolen_vga_buf; + /* return the VGA stolen memory (if any) back to VRAM */ + amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf); ++ ++ /* return the IP Discovery TMR memory back to VRAM */ ++ amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL); + } + + /** +diff --git a/drivers/gpu/drm/amd/include/discovery.h b/drivers/gpu/drm/amd/include/discovery.h +index 5dcb776548d8..7ec4331e67f2 100644 +--- a/drivers/gpu/drm/amd/include/discovery.h ++++ b/drivers/gpu/drm/amd/include/discovery.h +@@ -25,7 +25,6 @@ + #define _DISCOVERY_H_ + + #define PSP_HEADER_SIZE 256 +-#define BINARY_MAX_SIZE (64 << 10) + #define BINARY_SIGNATURE 0x28211407 + #define DISCOVERY_TABLE_SIGNATURE 0x53445049 + +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4119-drm-amd-display-Use-swap-where-appropriate.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4119-drm-amd-display-Use-swap-where-appropriate.patch new file mode 100644 index 00000000..c3713e34 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4119-drm-amd-display-Use-swap-where-appropriate.patch @@ -0,0 +1,122 @@ +From 5c9a30d8d57a134edb1e491aefc4b53f73335305 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com> +Date: Thu, 10 Oct 2019 16:11:57 +0300 +Subject: [PATCH 4119/4736] drm/amd/display: Use swap() where appropriate +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Mostly a cocci-job, but it flat out refused to remove the +declaration in drivers/gpu/drm/amd/display/dc/core/dc.c so +had to do that part manually. + +@swap@ +identifier TEMP; +expression A,B; +@@ +- TEMP = A; +- A = B; +- B = TEMP; ++ swap(A, B); + +@@ +type T; +identifier swap.TEMP; +@@ +( +- T TEMP; +| +- T TEMP = {...}; +) +... when != TEMP + +Cc: Harry Wentland <harry.wentland@amd.com> +Cc: Leo Li <sunpeng.li@amd.com> +Cc: Alex Deucher <alexander.deucher@amd.com> +Cc: "Christian König" <christian.koenig@amd.com> +Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> +Cc: amd-gfx@lists.freedesktop.org +Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 7 ++----- + drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 8 ++------ + drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +----- + 3 files changed, 5 insertions(+), 16 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +index 207f6084525c..7466e6332299 100644 +--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +@@ -2541,7 +2541,6 @@ static enum bp_result construct_integrated_info( + + /* Sort voltage table from low to high*/ + if (result == BP_RESULT_OK) { +- struct clock_voltage_caps temp = {0, 0}; + uint32_t i; + uint32_t j; + +@@ -2551,10 +2550,8 @@ static enum bp_result construct_integrated_info( + info->disp_clk_voltage[j].max_supported_clk < + info->disp_clk_voltage[j-1].max_supported_clk) { + /* swap j and j - 1*/ +- temp = info->disp_clk_voltage[j-1]; +- info->disp_clk_voltage[j-1] = +- info->disp_clk_voltage[j]; +- info->disp_clk_voltage[j] = temp; ++ swap(info->disp_clk_voltage[j - 1], ++ info->disp_clk_voltage[j]); + } + } + } +diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +index c9f65c4df530..b4bbfb7bde12 100644 +--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +@@ -1611,8 +1611,6 @@ static enum bp_result construct_integrated_info( + + struct atom_common_table_header *header; + struct atom_data_revision revision; +- +- struct clock_voltage_caps temp = {0, 0}; + uint32_t i; + uint32_t j; + +@@ -1642,10 +1640,8 @@ static enum bp_result construct_integrated_info( + info->disp_clk_voltage[j-1].max_supported_clk + ) { + /* swap j and j - 1*/ +- temp = info->disp_clk_voltage[j-1]; +- info->disp_clk_voltage[j-1] = +- info->disp_clk_voltage[j]; +- info->disp_clk_voltage[j] = temp; ++ swap(info->disp_clk_voltage[j - 1], ++ info->disp_clk_voltage[j]); + } + } + } +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 7142c014502a..699a215ca8ce 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -936,15 +936,11 @@ static void program_timing_sync( + + /* set first pipe with plane as master */ + for (j = 0; j < group_size; j++) { +- struct pipe_ctx *temp; +- + if (pipe_set[j]->plane_state) { + if (j == 0) + break; + +- temp = pipe_set[0]; +- pipe_set[0] = pipe_set[j]; +- pipe_set[j] = temp; ++ swap(pipe_set[0], pipe_set[j]); + break; + } + } +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4120-drm-amdgpu-display-clean-up-dcn2-_pp_smu-functions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4120-drm-amdgpu-display-clean-up-dcn2-_pp_smu-functions.patch new file mode 100644 index 00000000..1b2718c3 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4120-drm-amdgpu-display-clean-up-dcn2-_pp_smu-functions.patch @@ -0,0 +1,88 @@ +From 363163a7abaed056e01ce4019c9b449a80fb588d Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 10 Oct 2019 10:07:40 -0500 +Subject: [PATCH 4120/4736] drm/amdgpu/display: clean up dcn2*_pp_smu functions + +Use the dcn21 functions in dcn21_resource.c and make the +dcn20 functions static since they are only used in +dcn20_resource now. + +Cc: bhawanpreet.lakha@amd.com +Reviewed-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 6 ++++-- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 3 --- + drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 4 +++- + 3 files changed, 7 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index 4ca819c223bd..968dc5fe4f1b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -1185,6 +1185,8 @@ static const struct resource_create_funcs res_create_maximus_funcs = { + .create_hwseq = dcn20_hwseq_create, + }; + ++static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu); ++ + void dcn20_clock_source_destroy(struct clock_source **clk_src) + { + kfree(TO_DCE110_CLK_SRC(*clk_src)); +@@ -2959,7 +2961,7 @@ bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) + return true; + } + +-struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) ++static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) + { + struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); + +@@ -2974,7 +2976,7 @@ struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) + return pp_smu; + } + +-void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu) ++static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu) + { + if (pp_smu && *pp_smu) { + kfree(*pp_smu); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h +index 44f95aa0d61e..55006462f481 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h +@@ -95,9 +95,6 @@ struct display_stream_compressor *dcn20_dsc_create( + struct dc_context *ctx, uint32_t inst); + void dcn20_dsc_destroy(struct display_stream_compressor **dsc); + +-struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx); +-void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu); +- + struct hubp *dcn20_hubp_create( + struct dc_context *ctx, + uint32_t inst); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +index 9fdfa213b47c..2cc93e2e6ec0 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +@@ -636,6 +636,8 @@ static const struct dcn10_stream_encoder_mask se_mask = { + SE_COMMON_MASK_SH_LIST_DCN20(_MASK) + }; + ++static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu); ++ + static struct input_pixel_processor *dcn21_ipp_create( + struct dc_context *ctx, uint32_t inst) + { +@@ -939,7 +941,7 @@ static void destruct(struct dcn21_resource_pool *pool) + dcn_dccg_destroy(&pool->base.dccg); + + if (pool->base.pp_smu != NULL) +- dcn20_pp_smu_destroy(&pool->base.pp_smu); ++ dcn21_pp_smu_destroy(&pool->base.pp_smu); + } + + +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4121-drm-amd-powerplay-re-enable-FW_DSTATE-feature-bit.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4121-drm-amd-powerplay-re-enable-FW_DSTATE-feature-bit.patch new file mode 100644 index 00000000..b8cb80d7 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4121-drm-amd-powerplay-re-enable-FW_DSTATE-feature-bit.patch @@ -0,0 +1,34 @@ +From 7380d973669042490c0d393daa5e972b5dc0ed09 Mon Sep 17 00:00:00 2001 +From: Xiaojie Yuan <xiaojie.yuan@amd.com> +Date: Wed, 9 Oct 2019 18:52:51 +0800 +Subject: [PATCH 4121/4736] drm/amd/powerplay: re-enable FW_DSTATE feature bit + +SMU firmware has fix the bug, so remove this workaround. + +Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Kevin Wang <kevin1.wang@amd.com> +--- + drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +index 52a2feef7893..e8e5c889cc95 100644 +--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c ++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +@@ -371,11 +371,8 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, + if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); + +- if (adev->pm.pp_feature & PP_GFXOFF_MASK) { ++ if (adev->pm.pp_feature & PP_GFXOFF_MASK) + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); +- /* TODO: remove it once fw fix the bug */ +- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT); +- } + + if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4122-drm-amdgpu-soc15-disable-doorbell-interrupt-as-part-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4122-drm-amdgpu-soc15-disable-doorbell-interrupt-as-part-.patch new file mode 100644 index 00000000..451dd4bb --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4122-drm-amdgpu-soc15-disable-doorbell-interrupt-as-part-.patch @@ -0,0 +1,91 @@ +From 7bf9158b5981fbca65e8819df93fb2fc721c95bd Mon Sep 17 00:00:00 2001 +From: Le Ma <le.ma@amd.com> +Date: Fri, 11 Oct 2019 18:21:16 +0800 +Subject: [PATCH 4122/4736] drm/amdgpu/soc15: disable doorbell interrupt as + part of BACO entry sequence + +Workaround to make RAS recovery work in BACO reset. + +Change-Id: I4e4a81f719dcc88dfd49f583c4be3a373b5eab2c +Signed-off-by: Le Ma <le.ma@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++ + drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 8 ++++++++ + drivers/gpu/drm/amd/amdgpu/soc15.c | 9 +++++++++ + 3 files changed, 19 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h +index 1f26a17e6561..919bd566ba3c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h +@@ -67,6 +67,8 @@ struct amdgpu_nbio_funcs { + bool enable); + void (*ih_doorbell_range)(struct amdgpu_device *adev, + bool use_doorbell, int doorbell_index); ++ void (*enable_doorbell_interrupt)(struct amdgpu_device *adev, ++ bool enable); + void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, + bool enable); + void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, +diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +index 238c2483496a..0db458f9fafc 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c ++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +@@ -502,6 +502,13 @@ static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, + } + } + ++static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev, ++ bool enable) ++{ ++ WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL, ++ DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); ++} ++ + const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { + .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset, + .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset, +@@ -516,6 +523,7 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { + .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture, + .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture, + .ih_doorbell_range = nbio_v7_4_ih_doorbell_range, ++ .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt, + .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating, + .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep, + .get_clockgating_state = nbio_v7_4_get_clockgating_state, +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index a77f9b708f7f..82b5bc4ddf9b 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -492,10 +492,15 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev) + { + void *pp_handle = adev->powerplay.pp_handle; + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; ++ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); + + if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state) + return -ENOENT; + ++ /* avoid NBIF got stuck when do RAS recovery in BACO reset */ ++ if (ras && ras->supported) ++ adev->nbio.funcs->enable_doorbell_interrupt(adev, false); ++ + /* enter BACO state */ + if (pp_funcs->set_asic_baco_state(pp_handle, 1)) + return -EIO; +@@ -504,6 +509,10 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev) + if (pp_funcs->set_asic_baco_state(pp_handle, 0)) + return -EIO; + ++ /* re-enable doorbell interrupt after BACO exit */ ++ if (ras && ras->supported) ++ adev->nbio.funcs->enable_doorbell_interrupt(adev, true); ++ + dev_info(adev->dev, "GPU BACO reset\n"); + + adev->in_baco_reset = 1; +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4123-drm-amd-powerplay-avoid-disabling-ECC-if-RAS-is-enab.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4123-drm-amd-powerplay-avoid-disabling-ECC-if-RAS-is-enab.patch new file mode 100644 index 00000000..b7fb76fd --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4123-drm-amd-powerplay-avoid-disabling-ECC-if-RAS-is-enab.patch @@ -0,0 +1,58 @@ +From d222b18bf2136356f9fae2b6df597e372ebf9da7 Mon Sep 17 00:00:00 2001 +From: Le Ma <le.ma@amd.com> +Date: Fri, 11 Oct 2019 18:37:49 +0800 +Subject: [PATCH 4123/4736] drm/amd/powerplay: avoid disabling ECC if RAS is + enabled for VEGA20 + +Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when +BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting +for ECC supported SKU. + +Change-Id: I2a82c128fa5e9731b886dd61f1273dc48ea1923c +Signed-off-by: Le Ma <le.ma@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 12 +++++++----- + 1 file changed, 7 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c +index df6ff9252401..b068d1c7b44d 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c +@@ -29,7 +29,7 @@ + #include "vega20_baco.h" + #include "vega20_smumgr.h" + +- ++#include "amdgpu_ras.h" + + static const struct soc15_baco_cmd_entry clean_baco_tbl[] = + { +@@ -74,6 +74,7 @@ int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) + int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) + { + struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); ++ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); + enum BACO_STATE cur_state; + uint32_t data; + +@@ -84,10 +85,11 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) + return 0; + + if (state == BACO_STATE_IN) { +- data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); +- data |= 0x80000000; +- WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data); +- ++ if (!ras || !ras->supported) { ++ data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); ++ data |= 0x80000000; ++ WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data); ++ } + + if(smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnterBaco, 0)) + return -EINVAL; +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4124-drm-amd-powerplay-send-EnterBaco-msg-with-argument-a.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4124-drm-amd-powerplay-send-EnterBaco-msg-with-argument-a.patch new file mode 100644 index 00000000..7d00c82b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4124-drm-amd-powerplay-send-EnterBaco-msg-with-argument-a.patch @@ -0,0 +1,42 @@ +From f8e3ee206137a22a4172be249df166ebc49325ad Mon Sep 17 00:00:00 2001 +From: Le Ma <le.ma@amd.com> +Date: Fri, 11 Oct 2019 18:50:44 +0800 +Subject: [PATCH 4124/4736] drm/amd/powerplay: send EnterBaco msg with argument + as RAS recovery flag + +1 indicates RAS recovery flag in SMU FW. + +Change-Id: Icb8c14586fca1b8ae443bbde764570a9e41850fa +Signed-off-by: Le Ma <le.ma@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c +index b068d1c7b44d..9b5e72bdceca 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c +@@ -89,10 +89,15 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) + data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); + data |= 0x80000000; + WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data); +- } + +- if(smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnterBaco, 0)) +- return -EINVAL; ++ if(smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_EnterBaco, 0)) ++ return -EINVAL; ++ } else { ++ if(smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_EnterBaco, 1)) ++ return -EINVAL; ++ } + + } else if (state == BACO_STATE_OUT) { + if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco)) +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4125-drm-amd-powerplay-add-BACO-platformCaps-for-VEGA20.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4125-drm-amd-powerplay-add-BACO-platformCaps-for-VEGA20.patch new file mode 100644 index 00000000..32d03754 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4125-drm-amd-powerplay-add-BACO-platformCaps-for-VEGA20.patch @@ -0,0 +1,32 @@ +From 2aa549a55977d90e59688b551961ced291631f8f Mon Sep 17 00:00:00 2001 +From: Le Ma <le.ma@amd.com> +Date: Fri, 11 Oct 2019 19:00:00 +0800 +Subject: [PATCH 4125/4736] drm/amd/powerplay: add BACO platformCaps for VEGA20 + +BACO reset is needed for RAS recovery. + +Change-Id: I8207fc314744468c89ba4a030cb2bb15b082aac7 +Signed-off-by: Le Ma <le.ma@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +index 6629c475fe5d..3d3c647a63ff 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +@@ -182,6 +182,9 @@ static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr) + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_TablelessHardwareInterface); + ++ phm_cap_set(hwmgr->platform_descriptor.platformCaps, ++ PHM_PlatformCaps_BACO); ++ + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EnableSMU7ThermalManagement); + +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4126-drm-amdgpu-Bail-earlier-when-amdgpu.cik_-si_support-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4126-drm-amdgpu-Bail-earlier-when-amdgpu.cik_-si_support-.patch new file mode 100644 index 00000000..c84b68c4 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4126-drm-amdgpu-Bail-earlier-when-amdgpu.cik_-si_support-.patch @@ -0,0 +1,121 @@ +From a2d92bf0a020c9db4eb2c9e4c53fd274813f8ad4 Mon Sep 17 00:00:00 2001 +From: Hans de Goede <hdegoede@redhat.com> +Date: Thu, 10 Oct 2019 18:28:17 +0200 +Subject: [PATCH 4126/4736] drm/amdgpu: Bail earlier when + amdgpu.cik_/si_support is not set to 1 + +Bail from the pci_driver probe function instead of from the drm_driver +load function. + +This avoid /dev/dri/card0 temporarily getting registered and then +unregistered again, sending unwanted add / remove udev events to +userspace. + +Specifically this avoids triggering the (userspace) bug fixed by this +plymouth merge-request: +https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/59 + +Note that despite that being a userspace bug, not sending unnecessary +udev events is a good idea in general. + +BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1490490 +Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> +Signed-off-by: Hans de Goede <hdegoede@redhat.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 35 +++++++++++++++++++++++++ + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 32 ---------------------- + 2 files changed, 35 insertions(+), 32 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +index 50927cd86cc9..9ca74f242fd1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +@@ -1067,6 +1067,41 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, + return -ENODEV; + } + ++#ifdef CONFIG_DRM_AMDGPU_SI ++ if (!amdgpu_si_support) { ++ switch (flags & AMD_ASIC_MASK) { ++ case CHIP_TAHITI: ++ case CHIP_PITCAIRN: ++ case CHIP_VERDE: ++ case CHIP_OLAND: ++ case CHIP_HAINAN: ++ dev_info(&pdev->dev, ++ "SI support provided by radeon.\n"); ++ dev_info(&pdev->dev, ++ "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" ++ ); ++ return -ENODEV; ++ } ++ } ++#endif ++#ifdef CONFIG_DRM_AMDGPU_CIK ++ if (!amdgpu_cik_support) { ++ switch (flags & AMD_ASIC_MASK) { ++ case CHIP_KAVERI: ++ case CHIP_BONAIRE: ++ case CHIP_HAWAII: ++ case CHIP_KABINI: ++ case CHIP_MULLINS: ++ dev_info(&pdev->dev, ++ "CIK support provided by radeon.\n"); ++ dev_info(&pdev->dev, ++ "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" ++ ); ++ return -ENODEV; ++ } ++ } ++#endif ++ + /* Get rid of things like offb */ + ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb"); + if (ret) +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +index 20b11c024b87..ff47dd26e35a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +@@ -141,38 +141,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) + struct amdgpu_device *adev; + int r, acpi_status; + +-#ifdef CONFIG_DRM_AMDGPU_SI +- if (!amdgpu_si_support) { +- switch (flags & AMD_ASIC_MASK) { +- case CHIP_TAHITI: +- case CHIP_PITCAIRN: +- case CHIP_VERDE: +- case CHIP_OLAND: +- case CHIP_HAINAN: +- dev_info(dev->dev, +- "SI support provided by radeon.\n"); +- dev_info(dev->dev, +- "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" +- ); +- return -ENODEV; +- } +- } +-#endif +-#ifdef CONFIG_DRM_AMDGPU_CIK +- if (!amdgpu_cik_support) { +- switch (flags & AMD_ASIC_MASK) { +- case CHIP_KAVERI: +- case CHIP_BONAIRE: +- case CHIP_HAWAII: +- case CHIP_KABINI: +- case CHIP_MULLINS: +- dev_info(dev->dev, +- "CIK support disabled by module param\n"); +- return -ENODEV; +- } +- } +-#endif +- + adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); + if (adev == NULL) { + return -ENOMEM; +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4127-drm-amdgpu-change-to-query-the-actual-EDC-counter.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4127-drm-amdgpu-change-to-query-the-actual-EDC-counter.patch new file mode 100644 index 00000000..3d1ddf2c --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4127-drm-amdgpu-change-to-query-the-actual-EDC-counter.patch @@ -0,0 +1,914 @@ +From ffae45c6e296a3acaedd96fab920fb43672b2f50 Mon Sep 17 00:00:00 2001 +From: Dennis Li <Dennis.Li@amd.com> +Date: Sat, 12 Oct 2019 13:00:22 +0800 +Subject: [PATCH 4127/4736] drm/amdgpu: change to query the actual EDC counter + +For the potential request in the future, change to +query the actual EDC counter. + +Change-Id: I783ccd76f4c65f9829f7a8967a539a23ae5484b5 +Signed-off-by: Dennis Li <Dennis.Li@amd.com> +Reviewed-by: Hawking Zhang <hawking.zhang@amd.com> +Reviewed-by: Tao Zhou <tao.zhou1@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 821 ++++++++++++++++---------- + drivers/gpu/drm/amd/amdgpu/soc15.h | 2 + + 2 files changed, 498 insertions(+), 325 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 2e316e9da4cf..2d7140e57113 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -127,6 +127,18 @@ MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); + #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c + #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0 + ++struct ras_gfx_subblock_reg { ++ const char *name; ++ uint32_t hwip; ++ uint32_t inst; ++ uint32_t seg; ++ uint32_t reg_offset; ++ uint32_t sec_count_mask; ++ uint32_t sec_count_shift; ++ uint32_t ded_count_mask; ++ uint32_t ded_count_shift; ++}; ++ + enum ta_ras_gfx_subblock { + /*CPC*/ + TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, +@@ -3976,6 +3988,7 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = { + { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16}, + { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16}, + { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16}, ++ { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16}, + { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16}, + { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6}, + { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16}, +@@ -5443,301 +5456,446 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, + return 0; + } + +-static const struct { +- const char *name; +- uint32_t ip; +- uint32_t inst; +- uint32_t seg; +- uint32_t reg_offset; +- uint32_t per_se_instance; +- int32_t num_instance; +- uint32_t sec_count_mask; +- uint32_t ded_count_mask; +-} gfx_ras_edc_regs[] = { +- { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, +- REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, SEC_COUNT), +- REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, DED_COUNT) }, +- { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, +- REG_FIELD_MASK(CPC_EDC_UCODE_CNT, SEC_COUNT), +- REG_FIELD_MASK(CPC_EDC_UCODE_CNT, DED_COUNT) }, +- { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, +- REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME1), 0 }, +- { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, +- REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME2), 0 }, +- { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, +- REG_FIELD_MASK(CPF_EDC_TAG_CNT, SEC_COUNT), +- REG_FIELD_MASK(CPF_EDC_TAG_CNT, DED_COUNT) }, +- { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, +- REG_FIELD_MASK(CPG_EDC_DMA_CNT, ROQ_COUNT), 0 }, +- { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, +- REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_SEC_COUNT), +- REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_DED_COUNT) }, +- { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, +- REG_FIELD_MASK(CPG_EDC_TAG_CNT, SEC_COUNT), +- REG_FIELD_MASK(CPG_EDC_TAG_CNT, DED_COUNT) }, +- { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, +- REG_FIELD_MASK(DC_EDC_CSINVOC_CNT, COUNT_ME1), 0 }, +- { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, +- REG_FIELD_MASK(DC_EDC_RESTORE_CNT, COUNT_ME1), 0 }, +- { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, +- REG_FIELD_MASK(DC_EDC_STATE_CNT, COUNT_ME1), 0 }, +- { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, +- REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_SEC), +- REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_DED) }, +- { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, +- REG_FIELD_MASK(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 0 }, ++ ++static const struct ras_gfx_subblock_reg ras_subblock_regs[] = { ++ { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), ++ SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT), ++ SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) ++ }, ++ { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), ++ SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT), ++ SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) ++ }, ++ { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), ++ SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1), ++ 0, 0 ++ }, ++ { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), ++ SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2), ++ 0, 0 ++ }, ++ { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), ++ SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT), ++ SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) ++ }, ++ { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), ++ SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT), ++ 0, 0 ++ }, ++ { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), ++ SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT), ++ SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT) ++ }, ++ { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), ++ SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT), ++ SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT) ++ }, ++ { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), ++ SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1), ++ 0, 0 ++ }, ++ { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), ++ SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1), ++ 0, 0 ++ }, ++ { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), ++ SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1), ++ 0, 0 ++ }, ++ { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), ++ SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC), ++ SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) ++ }, ++ { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), ++ SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), ++ 0, 0 ++ }, + { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), +- 0, 1, REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), +- REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) }, ++ SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), ++ SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) ++ }, + { "GDS_OA_PHY_PHY_CMD_RAM_MEM", +- SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, +- REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), +- REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) }, ++ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), ++ SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), ++ SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) ++ }, + { "GDS_OA_PHY_PHY_DATA_RAM_MEM", +- SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, +- REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 0 }, ++ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), ++ SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), ++ 0, 0 ++ }, + { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM", +- SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, +- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), +- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) }, ++ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), ++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), ++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) ++ }, + { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM", +- SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, +- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), +- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) }, ++ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), ++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), ++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) ++ }, + { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM", +- SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, +- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), +- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) }, ++ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), ++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), ++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) ++ }, + { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM", +- SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, +- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), +- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) }, +- { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 1, 1, +- REG_FIELD_MASK(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 0 }, +- { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, +- REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), +- REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) }, +- { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, +- REG_FIELD_MASK(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 0 }, +- { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, +- REG_FIELD_MASK(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 0 }, +- { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, +- REG_FIELD_MASK(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 0 }, +- { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, +- REG_FIELD_MASK(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 0 }, +- { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2, +- REG_FIELD_MASK(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 0 }, +- { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2, +- REG_FIELD_MASK(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 0 }, +- { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, +- REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), +- REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) }, +- { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, +- REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), +- REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) }, +- { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, +- REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), +- REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) }, +- { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, +- REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), +- REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) }, +- { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, +- REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), +- REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) }, +- { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, +- REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 0 }, +- { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, +- REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 0 }, +- { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, +- REG_FIELD_MASK(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 0 }, +- { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, +- REG_FIELD_MASK(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 0 }, +- { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, +- REG_FIELD_MASK(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 0 }, +- { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, +- REG_FIELD_MASK(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 0 }, +- { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16, +- REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 0 }, +- { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16, +- REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 0 }, +- { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, +- 16, REG_FIELD_MASK(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 0 }, ++ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), ++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), ++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) ++ }, ++ { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), ++ SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), ++ 0, 0 ++ }, ++ { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), ++ SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), ++ SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) ++ }, ++ { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), ++ SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), ++ SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), ++ SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), ++ SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), ++ SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), ++ SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) ++ }, ++ { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) ++ }, ++ { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) ++ }, ++ { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) ++ }, ++ { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) ++ }, ++ { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), ++ SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), ++ SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), ++ SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), ++ SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), ++ 0, 0 ++ }, + { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), +- 0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT), +- 0 }, +- { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, +- 16, REG_FIELD_MASK(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 0 }, ++ SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), ++ SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), ++ 0, 0 ++ }, + { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), +- 0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT), +- 0 }, +- { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, +- 16, REG_FIELD_MASK(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 0 }, +- { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 72, +- REG_FIELD_MASK(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 0 }, +- { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, +- REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), +- REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) }, +- { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, +- REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), +- REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) }, +- { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, +- REG_FIELD_MASK(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 0 }, +- { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, +- REG_FIELD_MASK(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 0 }, +- { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, +- REG_FIELD_MASK(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 0 }, +- { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, +- REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), +- REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) }, +- { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, +- REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), +- REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) }, +- { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16, +- REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), +- REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) }, +- { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16, +- REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), +- REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) }, +- { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16, +- REG_FIELD_MASK(TD_EDC_CNT, CS_FIFO_SED_COUNT), 0 }, +- { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, +- REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_SEC_COUNT), +- REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_DED_COUNT) }, +- { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, +- REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_SEC_COUNT), +- REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_DED_COUNT) }, +- { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, +- REG_FIELD_MASK(SQ_EDC_CNT, SGPR_SEC_COUNT), +- REG_FIELD_MASK(SQ_EDC_CNT, SGPR_DED_COUNT) }, +- { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, +- REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_SEC_COUNT), +- REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_DED_COUNT) }, +- { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, +- REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_SEC_COUNT), +- REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_DED_COUNT) }, +- { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, +- REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_SEC_COUNT), +- REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_DED_COUNT) }, +- { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, +- REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_SEC_COUNT), +- REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_DED_COUNT) }, ++ SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), ++ SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), ++ SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), ++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), ++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) ++ }, ++ { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), ++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), ++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) ++ }, ++ { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), ++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), ++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), ++ 0, 0 ++ }, ++ { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), ++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), ++ 0, 0 ++ }, ++ { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), ++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), ++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) ++ }, ++ { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), ++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), ++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) ++ }, ++ { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), ++ SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), ++ SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) ++ }, ++ { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), ++ SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), ++ SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) ++ }, ++ { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), ++ SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), ++ SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT), ++ SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) ++ }, ++ { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), ++ SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT), ++ SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) ++ }, ++ { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), ++ SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT), ++ SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) ++ }, ++ { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), ++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT), ++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) ++ }, ++ { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), ++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT), ++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) ++ }, ++ { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), ++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT), ++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) ++ }, ++ { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), ++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT), ++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) ++ }, + { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), +- 1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) }, +- { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) }, ++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) ++ }, ++ { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) ++ }, + { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), +- 1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) }, +- { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) }, ++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) ++ }, ++ { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) ++ }, + { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), +- 1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) }, +- { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) }, +- { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) }, +- { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) }, +- { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) }, +- { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) }, +- { "SQC_INST_BANKA_UTCL1_MISS_FIFO", +- SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6, +- REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT), +- 0 }, +- { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 0 }, +- { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 0 }, +- { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 0 }, +- { "SQC_DATA_BANKA_DIRTY_BIT_RAM", +- SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6, +- REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 0 }, +- { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6, +- REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) }, +- { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) }, +- { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) }, +- { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) }, +- { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), +- REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) }, +- { "SQC_INST_BANKB_UTCL1_MISS_FIFO", +- SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6, +- REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT), +- 0 }, +- { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 0 }, +- { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 0 }, +- { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, +- 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 0 }, +- { "SQC_DATA_BANKB_DIRTY_BIT_RAM", +- SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6, +- REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 0 }, +- { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), +- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) }, +- { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), +- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) }, +- { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), +- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) }, +- { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), +- REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) }, +- { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), +- REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) }, +- { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0 }, +- { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0 }, +- { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0 }, +- { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0 }, +- { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 0 }, +- { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), +- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) }, +- { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), +- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) }, +- { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), +- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) }, +- { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0 }, +- { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0 }, +- { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 0 }, +- { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 0 }, +- { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 0 }, +- { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, +- REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 0 }, ++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) ++ }, ++ { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) ++ }, ++ { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) ++ }, ++ { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) ++ }, ++ { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) ++ }, ++ { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) ++ }, ++ { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), ++ 0, 0 ++ }, ++ { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) ++ }, ++ { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), ++ SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) ++ }, ++ { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), ++ SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) ++ }, ++ { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), ++ SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) ++ }, ++ { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), ++ SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), ++ SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) ++ }, ++ { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), ++ SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), ++ SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), ++ SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), ++ SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), ++ 0, 0 ++ }, ++ { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), ++ SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), ++ 0, 0 ++ }, ++ { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) ++ }, ++ { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) ++ }, ++ { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) ++ }, ++ { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) ++ }, ++ { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) ++ }, ++ { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), ++ 0, 0 ++ }, ++ { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), ++ 0, 0 ++ }, ++ { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), ++ 0, 0 ++ }, ++ { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), ++ 0, 0 ++ }, ++ { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), ++ 0, 0 ++ }, ++ { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), ++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) ++ }, ++ { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), ++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) ++ }, ++ { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), ++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), ++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) ++ }, ++ { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), ++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), ++ 0, 0 ++ }, ++ { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), ++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), ++ 0, 0 ++ }, ++ { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), ++ SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), ++ 0, 0 ++ }, ++ { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), ++ SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), ++ 0, 0 ++ }, ++ { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), ++ SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), ++ 0, 0 ++ }, ++ { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), ++ SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), ++ 0, 0 ++ } + }; + + static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, +@@ -5786,14 +5944,52 @@ static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, + return ret; + } + ++static int __get_ras_error_count(const struct soc15_reg_entry *reg, ++ uint32_t se_id, uint32_t inst_id, uint32_t value, ++ uint32_t *sec_count, uint32_t *ded_count) ++{ ++ uint32_t i; ++ uint32_t sec_cnt, ded_cnt; ++ ++ for (i = 0; i < ARRAY_SIZE(ras_subblock_regs); i++) { ++ if(ras_subblock_regs[i].reg_offset != reg->reg_offset || ++ ras_subblock_regs[i].seg != reg->seg || ++ ras_subblock_regs[i].inst != reg->inst) ++ continue; ++ ++ sec_cnt = (value & ++ ras_subblock_regs[i].sec_count_mask) >> ++ ras_subblock_regs[i].sec_count_shift; ++ if (sec_cnt) { ++ DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n", ++ ras_subblock_regs[i].name, ++ se_id, inst_id, ++ sec_cnt); ++ *sec_count += sec_cnt; ++ } ++ ++ ded_cnt = (value & ++ ras_subblock_regs[i].ded_count_mask) >> ++ ras_subblock_regs[i].ded_count_shift; ++ if (ded_cnt) { ++ DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n", ++ ras_subblock_regs[i].name, ++ se_id, inst_id, ++ ded_cnt); ++ *ded_count += ded_cnt; ++ } ++ } ++ ++ return 0; ++} ++ + static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, + void *ras_error_status) + { + struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; +- uint32_t sec_count, ded_count; +- uint32_t i; ++ uint32_t sec_count = 0, ded_count = 0; ++ uint32_t i, j, k; + uint32_t reg_value; +- uint32_t se_id, instance_id; + + if (adev->asic_type != CHIP_VEGA20) + return -EINVAL; +@@ -5802,49 +5998,24 @@ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, + err_data->ce_count = 0; + + mutex_lock(&adev->grbm_idx_mutex); +- for (se_id = 0; se_id < adev->gfx.config.max_shader_engines; se_id++) { +- for (instance_id = 0; instance_id < 256; instance_id++) { +- for (i = 0; +- i < sizeof(gfx_ras_edc_regs) / sizeof(gfx_ras_edc_regs[0]); +- i++) { +- if (se_id != 0 && +- !gfx_ras_edc_regs[i].per_se_instance) +- continue; +- if (instance_id >= gfx_ras_edc_regs[i].num_instance) +- continue; + +- gfx_v9_0_select_se_sh(adev, se_id, 0, +- instance_id); +- +- reg_value = RREG32( +- adev->reg_offset[gfx_ras_edc_regs[i].ip] +- [gfx_ras_edc_regs[i].inst] +- [gfx_ras_edc_regs[i].seg] + +- gfx_ras_edc_regs[i].reg_offset); +- sec_count = reg_value & +- gfx_ras_edc_regs[i].sec_count_mask; +- ded_count = reg_value & +- gfx_ras_edc_regs[i].ded_count_mask; +- if (sec_count) { +- DRM_INFO( +- "Instance[%d][%d]: SubBlock %s, SEC %d\n", +- se_id, instance_id, +- gfx_ras_edc_regs[i].name, +- sec_count); +- err_data->ce_count++; +- } +- +- if (ded_count) { +- DRM_INFO( +- "Instance[%d][%d]: SubBlock %s, DED %d\n", +- se_id, instance_id, +- gfx_ras_edc_regs[i].name, +- ded_count); +- err_data->ue_count++; +- } ++ for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) { ++ for (j = 0; j < sec_ded_counter_registers[i].se_num; j++) { ++ for (k = 0; k < sec_ded_counter_registers[i].instance; k++) { ++ gfx_v9_0_select_se_sh(adev, j, 0, k); ++ reg_value = ++ RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i])); ++ if (reg_value) ++ __get_ras_error_count(&sec_ded_counter_registers[i], ++ j, k, reg_value, ++ &sec_count, &ded_count); + } + } + } ++ ++ err_data->ce_count += sec_count; ++ err_data->ue_count += ded_count; ++ + gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h +index a3dde0c31f57..9af6c6ffbfa2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.h ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.h +@@ -67,6 +67,8 @@ struct soc15_allowed_register_entry { + #define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \ + { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask } + ++#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT ++ + void soc15_grbm_select(struct amdgpu_device *adev, + u32 me, u32 pipe, u32 queue, u32 vmid); + int soc15_set_ip_blocks(struct amdgpu_device *adev); +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4128-drm-amd-include-add-register-define-for-VML2-and-ATC.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4128-drm-amd-include-add-register-define-for-VML2-and-ATC.patch new file mode 100644 index 00000000..3a3cdbe6 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4128-drm-amd-include-add-register-define-for-VML2-and-ATC.patch @@ -0,0 +1,92 @@ +From b4d660a216d1ef77aca09688ec730030d34befb9 Mon Sep 17 00:00:00 2001 +From: Dennis Li <Dennis.Li@amd.com> +Date: Fri, 9 Aug 2019 14:30:29 +0800 +Subject: [PATCH 4128/4736] drm/amd/include: add register define for VML2 and + ATCL2 + +Add VML2 and ATCL2 ECC registers to support VEGA20 RAS + +Change-Id: I8860f2e37fa7afd8d6123290fb7b9dcee56edd6e +Signed-off-by: Dennis Li <Dennis.Li@amd.com> +Reviewed-by: Hawking Zhang <hawking.zhang@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../amd/include/asic_reg/gc/gc_9_0_offset.h | 18 ++++++++++++++++-- + .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 18 ++++++++++++++++-- + 2 files changed, 32 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h +index ca16d9125fbc..2bfaaa8157d0 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h +@@ -1146,7 +1146,14 @@ + #define mmATC_L2_MEM_POWER_LS_BASE_IDX 0 + #define mmATC_L2_CGTT_CLK_CTRL 0x080c + #define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 +- ++#define mmATC_L2_CACHE_4K_EDC_INDEX 0x080e ++#define mmATC_L2_CACHE_4K_EDC_INDEX_BASE_IDX 0 ++#define mmATC_L2_CACHE_2M_EDC_INDEX 0x080f ++#define mmATC_L2_CACHE_2M_EDC_INDEX_BASE_IDX 0 ++#define mmATC_L2_CACHE_4K_EDC_CNT 0x0810 ++#define mmATC_L2_CACHE_4K_EDC_CNT_BASE_IDX 0 ++#define mmATC_L2_CACHE_2M_EDC_CNT 0x0811 ++#define mmATC_L2_CACHE_2M_EDC_CNT_BASE_IDX 0 + + // addressBlock: gc_utcl2_vml2pfdec + // base address: 0xa100 +@@ -1206,7 +1213,14 @@ + #define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 + #define mmVM_L2_CGTT_CLK_CTRL 0x085e + #define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 +- ++#define mmVM_L2_MEM_ECC_INDEX 0x0860 ++#define mmVM_L2_MEM_ECC_INDEX_BASE_IDX 0 ++#define mmVM_L2_WALKER_MEM_ECC_INDEX 0x0861 ++#define mmVM_L2_WALKER_MEM_ECC_INDEX_BASE_IDX 0 ++#define mmVM_L2_MEM_ECC_CNT 0x0862 ++#define mmVM_L2_MEM_ECC_CNT_BASE_IDX 0 ++#define mmVM_L2_WALKER_MEM_ECC_CNT 0x0863 ++#define mmVM_L2_WALKER_MEM_ECC_CNT_BASE_IDX 0 + + // addressBlock: gc_utcl2_vml2vcdec + // base address: 0xa200 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h +index 064c4bb1dc62..d4c613a85352 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h +@@ -6661,7 +6661,6 @@ + #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L + #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L + +- + // addressBlock: gc_utcl2_vml2pfdec + //VM_L2_CNTL + #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +@@ -6991,7 +6990,22 @@ + #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L + #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L + #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L +- ++//VM_L2_MEM_ECC_INDEX ++#define VM_L2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 ++#define VM_L2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL ++//VM_L2_WALKER_MEM_ECC_INDEX ++#define VM_L2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT 0x0 ++#define VM_L2_WALKER_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL ++//VM_L2_MEM_ECC_CNT ++#define VM_L2_MEM_ECC_CNT__SEC_COUNT__SHIFT 0xc ++#define VM_L2_MEM_ECC_CNT__DED_COUNT__SHIFT 0xe ++#define VM_L2_MEM_ECC_CNT__SEC_COUNT_MASK 0x00003000L ++#define VM_L2_MEM_ECC_CNT__DED_COUNT_MASK 0x0000C000L ++//VM_L2_WALKER_MEM_ECC_CNT ++#define VM_L2_WALKER_MEM_ECC_CNT__SEC_COUNT__SHIFT 0xc ++#define VM_L2_WALKER_MEM_ECC_CNT__DED_COUNT__SHIFT 0xe ++#define VM_L2_WALKER_MEM_ECC_CNT__SEC_COUNT_MASK 0x00003000L ++#define VM_L2_WALKER_MEM_ECC_CNT__DED_COUNT_MASK 0x0000C000L + + // addressBlock: gc_utcl2_vml2vcdec + //VM_CONTEXT0_CNTL +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4129-drm-amdgpu-add-RAS-support-for-VML2-and-ATCL2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4129-drm-amdgpu-add-RAS-support-for-VML2-and-ATCL2.patch new file mode 100644 index 00000000..ca6b0fa0 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4129-drm-amdgpu-add-RAS-support-for-VML2-and-ATCL2.patch @@ -0,0 +1,205 @@ +From 3524f56effff32b75337729b56e3209600be45a0 Mon Sep 17 00:00:00 2001 +From: Dennis Li <Dennis.Li@amd.com> +Date: Sun, 29 Sep 2019 16:04:10 +0800 +Subject: [PATCH 4129/4736] drm/amdgpu: add RAS support for VML2 and ATCL2 + +v1: Add codes to query the EDC count of VML2 & ATCL2 +v2: Rename VML2/ATCL2 registers and drop their mask define +v3: Add back the ECC mask for VML2 registers + +Change-Id: If2c251481ba0a1a34ce3405a85f86d65eecee461 +Signed-off-by: Dennis Li <Dennis.Li@amd.com> +Reviewed-by: Hawking Zhang <hawking.zhang@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 167 ++++++++++++++++++++++++++ + 1 file changed, 167 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 2d7140e57113..24802e4d25e5 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -5944,6 +5944,171 @@ static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, + return ret; + } + ++static const char *vml2_mems[] = { ++ "UTC_VML2_BANK_CACHE_0_BIGK_MEM0", ++ "UTC_VML2_BANK_CACHE_0_BIGK_MEM1", ++ "UTC_VML2_BANK_CACHE_0_4K_MEM0", ++ "UTC_VML2_BANK_CACHE_0_4K_MEM1", ++ "UTC_VML2_BANK_CACHE_1_BIGK_MEM0", ++ "UTC_VML2_BANK_CACHE_1_BIGK_MEM1", ++ "UTC_VML2_BANK_CACHE_1_4K_MEM0", ++ "UTC_VML2_BANK_CACHE_1_4K_MEM1", ++ "UTC_VML2_BANK_CACHE_2_BIGK_MEM0", ++ "UTC_VML2_BANK_CACHE_2_BIGK_MEM1", ++ "UTC_VML2_BANK_CACHE_2_4K_MEM0", ++ "UTC_VML2_BANK_CACHE_2_4K_MEM1", ++ "UTC_VML2_BANK_CACHE_3_BIGK_MEM0", ++ "UTC_VML2_BANK_CACHE_3_BIGK_MEM1", ++ "UTC_VML2_BANK_CACHE_3_4K_MEM0", ++ "UTC_VML2_BANK_CACHE_3_4K_MEM1", ++}; ++ ++static const char *vml2_walker_mems[] = { ++ "UTC_VML2_CACHE_PDE0_MEM0", ++ "UTC_VML2_CACHE_PDE0_MEM1", ++ "UTC_VML2_CACHE_PDE1_MEM0", ++ "UTC_VML2_CACHE_PDE1_MEM1", ++ "UTC_VML2_CACHE_PDE2_MEM0", ++ "UTC_VML2_CACHE_PDE2_MEM1", ++ "UTC_VML2_RDIF_LOG_FIFO", ++}; ++ ++static const char *atc_l2_cache_2m_mems[] = { ++ "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM", ++ "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM", ++ "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM", ++ "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM", ++}; ++ ++static const char *atc_l2_cache_4k_mems[] = { ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6", ++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6", ++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7", ++}; ++ ++static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, ++ struct ras_err_data *err_data) ++{ ++ uint32_t i, data; ++ uint32_t sec_count, ded_count; ++ ++ WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); ++ WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); ++ WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); ++ WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); ++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); ++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); ++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); ++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); ++ ++ for (i = 0; i < 16; i++) { ++ WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); ++ data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); ++ ++ sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT); ++ if (sec_count) { ++ DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, ++ vml2_mems[i], sec_count); ++ err_data->ce_count += sec_count; ++ } ++ ++ ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT); ++ if (ded_count) { ++ DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i, ++ vml2_mems[i], ded_count); ++ err_data->ue_count += ded_count; ++ } ++ } ++ ++ for (i = 0; i < 7; i++) { ++ WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); ++ data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); ++ ++ sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, ++ SEC_COUNT); ++ if (sec_count) { ++ DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, ++ vml2_walker_mems[i], sec_count); ++ err_data->ce_count += sec_count; ++ } ++ ++ ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, ++ DED_COUNT); ++ if (ded_count) { ++ DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i, ++ vml2_walker_mems[i], ded_count); ++ err_data->ue_count += ded_count; ++ } ++ } ++ ++ for (i = 0; i < 4; i++) { ++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); ++ data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); ++ ++ sec_count = (data & 0x00006000L) >> 0xd; ++ if (sec_count) { ++ DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, ++ atc_l2_cache_2m_mems[i], sec_count); ++ err_data->ce_count += sec_count; ++ } ++ } ++ ++ for (i = 0; i < 32; i++) { ++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); ++ data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); ++ ++ sec_count = (data & 0x00006000L) >> 0xd; ++ if (sec_count) { ++ DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, ++ atc_l2_cache_4k_mems[i], sec_count); ++ err_data->ce_count += sec_count; ++ } ++ ++ ded_count = (data & 0x00018000L) >> 0xf; ++ if (ded_count) { ++ DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i, ++ atc_l2_cache_4k_mems[i], ded_count); ++ err_data->ue_count += ded_count; ++ } ++ } ++ ++ WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); ++ WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); ++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); ++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); ++ ++ return 0; ++} ++ + static int __get_ras_error_count(const struct soc15_reg_entry *reg, + uint32_t se_id, uint32_t inst_id, uint32_t value, + uint32_t *sec_count, uint32_t *ded_count) +@@ -6019,6 +6184,8 @@ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, + gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + ++ gfx_v9_0_query_utc_edc_status(adev, err_data); ++ + return 0; + } + +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4130-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_crea.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4130-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_crea.patch new file mode 100644 index 00000000..bfa13d6e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4130-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_crea.patch @@ -0,0 +1,38 @@ +From 883eb361081a64867284c669a6263995512bcb59 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Wed, 18 Sep 2019 19:42:14 +0200 +Subject: [PATCH 4130/4736] drm/amdgpu: fix error handling in + amdgpu_bo_list_create +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +We need to drop normal and userptr BOs separately. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Acked-by: Huang Rui <ray.huang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +index e143d9e110bd..92df38fd794d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +@@ -140,7 +140,12 @@ int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp, + return 0; + + error_free: +- while (i--) { ++ for (i = 0; i < last_entry; ++i) { ++ struct amdgpu_bo *bo = ttm_to_amdgpu_bo(array[i].tv.bo); ++ ++ amdgpu_bo_unref(&bo); ++ } ++ for (i = first_userptr; i < num_entries; ++i) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(array[i].tv.bo); + + amdgpu_bo_unref(&bo); +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4131-drm-amdgpu-fix-potential-VM-faults.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4131-drm-amdgpu-fix-potential-VM-faults.patch new file mode 100644 index 00000000..80b32dc1 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4131-drm-amdgpu-fix-potential-VM-faults.patch @@ -0,0 +1,34 @@ +From 34b82c5346e844f2f9ffb12745b79fce980f4542 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Thu, 19 Sep 2019 10:38:57 +0200 +Subject: [PATCH 4131/4736] drm/amdgpu: fix potential VM faults +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +When we allocate new page tables under memory +pressure we should not evict old ones. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +index acb0755fe724..1350666355e0 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +@@ -538,7 +538,8 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, + .interruptible = (bp->type != ttm_bo_type_kernel), + .no_wait_gpu = bp->no_wait_gpu, + .resv = bp->resv, +- .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT ++ .flags = bp->type != ttm_bo_type_kernel ? ++ TTM_OPT_FLAG_ALLOW_RES_EVICT : 0 + }; + struct amdgpu_bo *bo; + unsigned long page_align, size = bp->size; +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4132-drm-amdgpu-Fix-tdr3-could-hang-with-slow-compute-iss.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4132-drm-amdgpu-Fix-tdr3-could-hang-with-slow-compute-iss.patch new file mode 100644 index 00000000..6813b358 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4132-drm-amdgpu-Fix-tdr3-could-hang-with-slow-compute-iss.patch @@ -0,0 +1,53 @@ +From bacf25c006ff8772febc7f022976b07bd2b31882 Mon Sep 17 00:00:00 2001 +From: Emily Deng <Emily.Deng@amd.com> +Date: Tue, 15 Oct 2019 10:08:22 +0800 +Subject: [PATCH 4132/4736] drm/amdgpu: Fix tdr3 could hang with slow compute + issue + +When index is 1, need to set compute ring timeout for sriov and passthrough. + +Signed-off-by: Emily Deng <Emily.Deng@amd.com> +Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++++- + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++++-- + 2 files changed, 8 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 1b972f531740..521af22ad916 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -2622,8 +2622,11 @@ static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) + * There is only one value specified and + * it should apply to all non-compute jobs. + */ +- if (index == 1) ++ if (index == 1) { + adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; ++ if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) ++ adev->compute_timeout = adev->gfx_timeout; ++ } + } + + return ret; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +index 9ca74f242fd1..658fa3fd5fad 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +@@ -252,9 +252,11 @@ module_param_named(msi, amdgpu_msi, int, 0444); + * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) + * jobs is 10000. And there is no timeout enforced on compute jobs. + */ +-MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and infinity timeout for compute jobs." ++MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " ++ "for passthrough or sriov, 10000 for all jobs." + " 0: keep default value. negative: infinity timeout), " +- "format is [Non-Compute] or [GFX,Compute,SDMA,Video]"); ++ "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " ++ "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); + module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); + + /** +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4133-drm-amd-powerplay-bug-fix-for-pcie-parameters-overri.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4133-drm-amd-powerplay-bug-fix-for-pcie-parameters-overri.patch new file mode 100644 index 00000000..1907ed9b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4133-drm-amd-powerplay-bug-fix-for-pcie-parameters-overri.patch @@ -0,0 +1,273 @@ +From 0d3a43711fc55bba4355010ec4c165bafad46c69 Mon Sep 17 00:00:00 2001 +From: Kenneth Feng <kenneth.feng@amd.com> +Date: Fri, 11 Oct 2019 17:51:34 +0800 +Subject: [PATCH 4133/4736] drm/amd/powerplay: bug fix for pcie parameters + override + +Bug fix for pcie paramerers override on swsmu. +Below is a scenario to have this problem. +pptable definition on pcie dpm: +0 -> pcie gen speed:1, pcie lanes: *16 +1 -> pcie gen speed:4, pcie lanes: *16 +Then if we have a system only have the capbility: +pcie gen speed: 3, pcie lanes: *8, +we will override dpm 1 to pcie gen speed 3, pcie lanes *8. +But the code skips the dpm 0 configuration. +So the real pcie dpm parameters are: +0 -> pcie gen speed:1, pcie lanes: *16 +1 -> pcie gen speed:3, pcie lanes: *8 +Then the wrong pcie lanes will be toggled. + +Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Evan Quan <evan.quan@amd.com> +--- + drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 44 ------------------- + .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 8 ++++ + drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 23 ++++++++++ + drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 44 +++++++++++++++++++ + drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 23 ++++++++++ + 5 files changed, 98 insertions(+), 44 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +index a37a1b1d8abd..26cacc899dfe 100644 +--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +@@ -945,50 +945,6 @@ static int smu_fini_fb_allocations(struct smu_context *smu) + return 0; + } + +-static int smu_override_pcie_parameters(struct smu_context *smu) +-{ +- struct amdgpu_device *adev = smu->adev; +- uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg; +- int ret; +- +- if (adev->flags & AMD_IS_APU) +- return 0; +- +- if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) +- pcie_gen = 3; +- else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) +- pcie_gen = 2; +- else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) +- pcie_gen = 1; +- else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) +- pcie_gen = 0; +- +- /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 +- * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 +- * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 +- */ +- if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) +- pcie_width = 6; +- else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) +- pcie_width = 5; +- else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) +- pcie_width = 4; +- else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) +- pcie_width = 3; +- else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) +- pcie_width = 2; +- else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) +- pcie_width = 1; +- +- smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width; +- ret = smu_send_smc_msg_with_param(smu, +- SMU_MSG_OverridePcieParameters, +- smu_pcie_arg); +- if (ret) +- pr_err("[%s] Attempt to override pcie params failed!\n", __func__); +- return ret; +-} +- + static int smu_smc_table_hw_init(struct smu_context *smu, + bool initialize) + { +diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +index 401affdee49d..cdb845f5f23e 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +@@ -469,6 +469,7 @@ struct pptable_funcs { + int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type clk_type, + uint32_t dpm_level, uint32_t *freq); + int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); ++ int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap); + }; + + struct smu_funcs +@@ -551,6 +552,7 @@ struct smu_funcs + int (*mode2_reset)(struct smu_context *smu); + int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); + int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); ++ int (*override_pcie_parameters)(struct smu_context *smu); + }; + + #define smu_init_microcode(smu) \ +@@ -783,6 +785,12 @@ struct smu_funcs + #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \ + ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL) + ++#define smu_override_pcie_parameters(smu) \ ++ ((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0) ++ ++#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \ ++ ((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap), (pcie_width_cap)) : 0) ++ + extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table, + uint16_t *size, uint8_t *frev, uint8_t *crev, + uint8_t **addr); +diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +index e8e5c889cc95..b88aae9bb242 100644 +--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c ++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +@@ -1628,6 +1628,28 @@ static int navi10_get_power_limit(struct smu_context *smu, + return 0; + } + ++static int navi10_update_pcie_parameters(struct smu_context *smu, ++ uint32_t pcie_gen_cap, ++ uint32_t pcie_width_cap) ++{ ++ PPTable_t *pptable = smu->smu_table.driver_pptable; ++ int ret, i; ++ uint32_t smu_pcie_arg; ++ ++ for (i = 0; i < NUM_LINK_LEVELS; i++) { ++ smu_pcie_arg = (i << 16) | ++ ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) : ++ (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? ++ pptable->PcieLaneCount[i] : pcie_width_cap); ++ ret = smu_send_smc_msg_with_param(smu, ++ SMU_MSG_OverridePcieParameters, ++ smu_pcie_arg); ++ } ++ ++ return ret; ++} ++ ++ + static const struct pptable_funcs navi10_ppt_funcs = { + .tables_init = navi10_tables_init, + .alloc_dpm_context = navi10_allocate_dpm_context, +@@ -1666,6 +1688,7 @@ static const struct pptable_funcs navi10_ppt_funcs = { + .get_thermal_temperature_range = navi10_get_thermal_temperature_range, + .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch, + .get_power_limit = navi10_get_power_limit, ++ .update_pcie_parameters = navi10_update_pcie_parameters, + }; + + void navi10_set_ppt_funcs(struct smu_context *smu) +diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +index 9883f0a4471a..df1f2b99fed7 100644 +--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c ++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +@@ -32,6 +32,7 @@ + #include "vega20_ppt.h" + #include "arcturus_ppt.h" + #include "navi10_ppt.h" ++#include "amd_pcie.h" + + #include "asic_reg/thm/thm_11_0_2_offset.h" + #include "asic_reg/thm/thm_11_0_2_sh_mask.h" +@@ -1791,6 +1792,48 @@ static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum s + return ret; + } + ++static int smu_v11_0_override_pcie_parameters(struct smu_context *smu) ++{ ++ struct amdgpu_device *adev = smu->adev; ++ uint32_t pcie_gen = 0, pcie_width = 0; ++ int ret; ++ ++ if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) ++ pcie_gen = 3; ++ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) ++ pcie_gen = 2; ++ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) ++ pcie_gen = 1; ++ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) ++ pcie_gen = 0; ++ ++ /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 ++ * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 ++ * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 ++ */ ++ if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) ++ pcie_width = 6; ++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) ++ pcie_width = 5; ++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) ++ pcie_width = 4; ++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) ++ pcie_width = 3; ++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) ++ pcie_width = 2; ++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) ++ pcie_width = 1; ++ ++ ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); ++ ++ if (ret) ++ pr_err("[%s] Attempt to override pcie params failed!\n", __func__); ++ ++ return ret; ++ ++} ++ ++ + static const struct smu_funcs smu_v11_0_funcs = { + .init_microcode = smu_v11_0_init_microcode, + .load_microcode = smu_v11_0_load_microcode, +@@ -1843,6 +1886,7 @@ static const struct smu_funcs smu_v11_0_funcs = { + .baco_reset = smu_v11_0_baco_reset, + .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq, + .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, ++ .override_pcie_parameters = smu_v11_0_override_pcie_parameters, + }; + + void smu_v11_0_set_smu_funcs(struct smu_context *smu) +diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +index 1050566cb69a..a76ffd58404e 100644 +--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c ++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +@@ -3157,6 +3157,28 @@ static int vega20_set_df_cstate(struct smu_context *smu, + return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state); + } + ++static int vega20_update_pcie_parameters(struct smu_context *smu, ++ uint32_t pcie_gen_cap, ++ uint32_t pcie_width_cap) ++{ ++ PPTable_t *pptable = smu->smu_table.driver_pptable; ++ int ret, i; ++ uint32_t smu_pcie_arg; ++ ++ for (i = 0; i < NUM_LINK_LEVELS; i++) { ++ smu_pcie_arg = (i << 16) | ++ ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) : ++ (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? ++ pptable->PcieLaneCount[i] : pcie_width_cap); ++ ret = smu_send_smc_msg_with_param(smu, ++ SMU_MSG_OverridePcieParameters, ++ smu_pcie_arg); ++ } ++ ++ return ret; ++} ++ ++ + static const struct pptable_funcs vega20_ppt_funcs = { + .tables_init = vega20_tables_init, + .alloc_dpm_context = vega20_allocate_dpm_context, +@@ -3201,6 +3223,7 @@ static const struct pptable_funcs vega20_ppt_funcs = { + .set_watermarks_table = vega20_set_watermarks_table, + .get_thermal_temperature_range = vega20_get_thermal_temperature_range, + .set_df_cstate = vega20_set_df_cstate, ++ .update_pcie_parameters = vega20_update_pcie_parameters + }; + + void vega20_set_ppt_funcs(struct smu_context *smu) +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4134-drm-amd-powerplay-enable-Arcturus-runtime-VCN-dpm-on.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4134-drm-amd-powerplay-enable-Arcturus-runtime-VCN-dpm-on.patch new file mode 100644 index 00000000..86f15b3d --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4134-drm-amd-powerplay-enable-Arcturus-runtime-VCN-dpm-on.patch @@ -0,0 +1,99 @@ +From 7af8f2b4309f81b47562e1a04053d6073c7e47f0 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Thu, 10 Oct 2019 16:42:31 +0800 +Subject: [PATCH 4134/4736] drm/amd/powerplay: enable Arcturus runtime VCN dpm + on/off + +Enable runtime VCN DPM on/off on Arcturus. + +Change-Id: Ie7d94d67cb4c622c96acced1b5ef0f4e63db5aad +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 7 +++++ + drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 30 ++++++++++++++++++++ + 2 files changed, 37 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +index 2608c932a775..d270df892223 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +@@ -25,6 +25,7 @@ + #include <drm/drmP.h> + #include "amdgpu.h" + #include "amdgpu_vcn.h" ++#include "amdgpu_pm.h" + #include "soc15.h" + #include "soc15d.h" + #include "vcn_v2_0.h" +@@ -709,6 +710,9 @@ static int vcn_v2_5_start(struct amdgpu_device *adev) + uint32_t rb_bufsz, tmp; + int i, j, k, r; + ++ if (adev->pm.dpm_enabled) ++ amdgpu_dpm_enable_uvd(adev, true); ++ + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + if (adev->vcn.harvest_config & (1 << i)) + continue; +@@ -939,6 +943,9 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev) + ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); + } + ++ if (adev->pm.dpm_enabled) ++ amdgpu_dpm_enable_uvd(adev, false); ++ + return 0; + } + +diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c +index 37ac01d37ae8..b33e451c7133 100644 +--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c ++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c +@@ -1898,6 +1898,35 @@ static bool arcturus_is_dpm_running(struct smu_context *smu) + return !!(feature_enabled & SMC_DPM_FEATURE); + } + ++static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable) ++{ ++ struct smu_power_context *smu_power = &smu->smu_power; ++ struct smu_power_gate *power_gate = &smu_power->power_gate; ++ int ret = 0; ++ ++ if (enable) { ++ if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { ++ ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1); ++ if (ret) { ++ pr_err("[EnableVCNDPM] failed!\n"); ++ return ret; ++ } ++ } ++ power_gate->vcn_gated = false; ++ } else { ++ if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { ++ ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0); ++ if (ret) { ++ pr_err("[DisableVCNDPM] failed!\n"); ++ return ret; ++ } ++ } ++ power_gate->vcn_gated = true; ++ } ++ ++ return ret; ++} ++ + static const struct pptable_funcs arcturus_ppt_funcs = { + /* translate smu index into arcturus specific index */ + .get_smu_msg_index = arcturus_get_smu_msg_index, +@@ -1936,6 +1965,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = { + .dump_pptable = arcturus_dump_pptable, + .get_power_limit = arcturus_get_power_limit, + .is_dpm_running = arcturus_is_dpm_running, ++ .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable, + }; + + void arcturus_set_ppt_funcs(struct smu_context *smu) +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4135-drm-amdgpu-display-hook-renoir-dc-to-pplib-funcs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4135-drm-amdgpu-display-hook-renoir-dc-to-pplib-funcs.patch new file mode 100644 index 00000000..f8616d1f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4135-drm-amdgpu-display-hook-renoir-dc-to-pplib-funcs.patch @@ -0,0 +1,142 @@ +From 61eca185219bdd4755932490ad86d255017c75ba Mon Sep 17 00:00:00 2001 +From: Hersen Wu <hersenxs.wu@amd.com> +Date: Tue, 15 Oct 2019 10:34:54 -0400 +Subject: [PATCH 4135/4736] drm/amdgpu/display: hook renoir dc to pplib funcs + +enable dc get dmp clock table and set dcn watermarks +via pplib. + +Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> +Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 93 +++++++++++++++++++ + drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 2 +- + 2 files changed, 94 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +index 9b2ce0264df6..33564c707051 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +@@ -902,6 +902,90 @@ enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp, + return PP_SMU_RESULT_FAIL; + } + ++#ifdef CONFIG_DRM_AMD_DC_DCN2_1 ++enum pp_smu_status pp_rn_get_dpm_clock_table( ++ struct pp_smu *pp, struct dpm_clocks *clock_table) ++{ ++ const struct dc_context *ctx = pp->dm; ++ struct amdgpu_device *adev = ctx->driver_context; ++ struct smu_context *smu = &adev->smu; ++ ++ if (!smu->ppt_funcs) ++ return PP_SMU_RESULT_UNSUPPORTED; ++ ++ if (!smu->ppt_funcs->get_dpm_clock_table) ++ return PP_SMU_RESULT_UNSUPPORTED; ++ ++ if (!smu->ppt_funcs->get_dpm_clock_table(smu, clock_table)) ++ return PP_SMU_RESULT_OK; ++ ++ return PP_SMU_RESULT_FAIL; ++} ++ ++enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp, ++ struct pp_smu_wm_range_sets *ranges) ++{ ++ const struct dc_context *ctx = pp->dm; ++ struct amdgpu_device *adev = ctx->driver_context; ++ struct smu_context *smu = &adev->smu; ++ struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges; ++ struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks = ++ wm_with_clock_ranges.wm_dmif_clocks_ranges; ++ struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks = ++ wm_with_clock_ranges.wm_mcif_clocks_ranges; ++ int32_t i; ++ ++ if (!smu->funcs) ++ return PP_SMU_RESULT_UNSUPPORTED; ++ ++ wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets; ++ wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets; ++ ++ for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) { ++ if (ranges->reader_wm_sets[i].wm_inst > 3) ++ wm_dce_clocks[i].wm_set_id = WM_SET_A; ++ else ++ wm_dce_clocks[i].wm_set_id = ++ ranges->reader_wm_sets[i].wm_inst; ++ ++ wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz = ++ ranges->reader_wm_sets[i].min_drain_clk_mhz; ++ ++ wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz = ++ ranges->reader_wm_sets[i].max_drain_clk_mhz; ++ ++ wm_dce_clocks[i].wm_min_mem_clk_in_khz = ++ ranges->reader_wm_sets[i].min_fill_clk_mhz; ++ ++ wm_dce_clocks[i].wm_max_mem_clk_in_khz = ++ ranges->reader_wm_sets[i].max_fill_clk_mhz; ++ } ++ ++ for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) { ++ if (ranges->writer_wm_sets[i].wm_inst > 3) ++ wm_soc_clocks[i].wm_set_id = WM_SET_A; ++ else ++ wm_soc_clocks[i].wm_set_id = ++ ranges->writer_wm_sets[i].wm_inst; ++ wm_soc_clocks[i].wm_min_socclk_clk_in_khz = ++ ranges->writer_wm_sets[i].min_fill_clk_mhz; ++ ++ wm_soc_clocks[i].wm_max_socclk_clk_in_khz = ++ ranges->writer_wm_sets[i].max_fill_clk_mhz; ++ ++ wm_soc_clocks[i].wm_min_mem_clk_in_khz = ++ ranges->writer_wm_sets[i].min_drain_clk_mhz; ++ ++ wm_soc_clocks[i].wm_max_mem_clk_in_khz = ++ ranges->writer_wm_sets[i].max_drain_clk_mhz; ++ } ++ ++ smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges); ++ ++ return PP_SMU_RESULT_OK; ++} ++#endif ++ + void dm_pp_get_funcs( + struct dc_context *ctx, + struct pp_smu_funcs *funcs) +@@ -946,6 +1030,15 @@ void dm_pp_get_funcs( + funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support; + break; + #endif ++ ++#ifdef CONFIG_DRM_AMD_DC_DCN2_1 ++ case DCN_VERSION_2_1: ++ funcs->ctx.ver = PP_SMU_VER_RN; ++ funcs->rn_funcs.pp_smu.dm = ctx; ++ funcs->rn_funcs.set_wm_ranges = pp_rn_set_wm_ranges; ++ funcs->rn_funcs.get_dpm_clock_table = pp_rn_get_dpm_clock_table; ++ break; ++#endif + default: + DRM_ERROR("smu version is not supported !\n"); + break; +diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +index 6aa1686f59ab..ad082181a448 100644 +--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h ++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +@@ -246,7 +246,7 @@ struct pp_smu_funcs_nv { + #if defined(CONFIG_DRM_AMD_DC_DCN2_1) + + #define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8 +-#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 4 ++#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8 + #define PP_SMU_NUM_FCLK_DPM_LEVELS 4 + #define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4 + +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4136-drm-amdgpu-display-fix-build-error-casused-by-CONFIG.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4136-drm-amdgpu-display-fix-build-error-casused-by-CONFIG.patch new file mode 100644 index 00000000..c941254c --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4136-drm-amdgpu-display-fix-build-error-casused-by-CONFIG.patch @@ -0,0 +1,40 @@ +From 1250d2c1f6d25613622af93f47b3bc9f24197a10 Mon Sep 17 00:00:00 2001 +From: Hersen Wu <hersenxs.wu@amd.com> +Date: Tue, 15 Oct 2019 12:47:31 -0400 +Subject: [PATCH 4136/4736] drm/amdgpu/display: fix build error casused by + CONFIG_DRM_AMD_DC_DCN2_1 + +when CONFIG_DRM_AMD_DC_DCN2_1 is not enable in .config, +there is build error. struct dpm_clocks shoud not be +guarded. + +Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> +Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +index ad082181a448..95f3193da951 100644 +--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h ++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +@@ -243,8 +243,6 @@ struct pp_smu_funcs_nv { + }; + #endif + +-#if defined(CONFIG_DRM_AMD_DC_DCN2_1) +- + #define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8 + #define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8 + #define PP_SMU_NUM_FCLK_DPM_LEVELS 4 +@@ -282,7 +280,6 @@ struct pp_smu_funcs_rn { + enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp, + struct dpm_clocks *clock_table); + }; +-#endif + + struct pp_smu_funcs { + struct pp_smu ctx; +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4137-drm-amd-display-change-PP_SM-defs-to-8.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4137-drm-amd-display-change-PP_SM-defs-to-8.patch new file mode 100644 index 00000000..35a27b2b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4137-drm-amd-display-change-PP_SM-defs-to-8.patch @@ -0,0 +1,31 @@ +From 6296a192954b9f8740eacd7c13acd58e8b4d8cbe Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Thu, 3 Oct 2019 13:49:30 -0400 +Subject: [PATCH 4137/4736] drm/amd/display: change PP_SM defs to 8 + +DPM level is 8 these were incorrect before. Fix them + +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Reviewed-by: Roman Li <Roman.Li@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +index 95f3193da951..60d6620530a8 100644 +--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h ++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h +@@ -245,8 +245,8 @@ struct pp_smu_funcs_nv { + + #define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8 + #define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8 +-#define PP_SMU_NUM_FCLK_DPM_LEVELS 4 +-#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4 ++#define PP_SMU_NUM_FCLK_DPM_LEVELS 8 ++#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 8 + + struct dpm_clock { + uint32_t Freq; // In MHz +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4138-drm-amdgpu-powerplay-add-renoir-funcs-to-support-dc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4138-drm-amdgpu-powerplay-add-renoir-funcs-to-support-dc.patch new file mode 100644 index 00000000..034871d6 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4138-drm-amdgpu-powerplay-add-renoir-funcs-to-support-dc.patch @@ -0,0 +1,376 @@ +From c96339fb3bc2f93450f7df258c119580584619f1 Mon Sep 17 00:00:00 2001 +From: Hersen Wu <hersenxs.wu@amd.com> +Date: Wed, 18 Sep 2019 09:53:30 -0400 +Subject: [PATCH 4138/4736] drm/amdgpu/powerplay: add renoir funcs to support + dc + +there are two paths for renoir dc access smu. +one dc access smu directly using bios smc +interface: set disply, dprefclk, etc. +another goes through pplib for get dpm clock +table and set watermmark. + +Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> +Reviewed-by: Kevin Wang <kevin1.wang@amd.com> +--- + .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 16 +--- + drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 35 +++++++ + .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 16 ++-- + drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 96 +++++++++++++++++++ + drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 39 -------- + 5 files changed, 141 insertions(+), 61 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +index 33564c707051..8a5eedb6a37a 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +@@ -590,10 +590,9 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp, + if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges) + pp_funcs->set_watermarks_for_clocks_ranges(pp_handle, + &wm_with_clock_ranges); +- else if (adev->smu.funcs && +- adev->smu.funcs->set_watermarks_for_clock_ranges) ++ else + smu_set_watermarks_for_clock_ranges(&adev->smu, +- &wm_with_clock_ranges); ++ &wm_with_clock_ranges); + } + + void pp_rv_set_pme_wa_enable(struct pp_smu *pp) +@@ -666,7 +665,6 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp, + { + const struct dc_context *ctx = pp->dm; + struct amdgpu_device *adev = ctx->driver_context; +- struct smu_context *smu = &adev->smu; + struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges; + struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks = + wm_with_clock_ranges.wm_dmif_clocks_ranges; +@@ -709,15 +707,7 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp, + ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000; + } + +- if (!smu->funcs) +- return PP_SMU_RESULT_UNSUPPORTED; +- +- /* 0: successful or smu.funcs->set_watermarks_for_clock_ranges = NULL; +- * 1: fail +- */ +- if (smu_set_watermarks_for_clock_ranges(&adev->smu, +- &wm_with_clock_ranges)) +- return PP_SMU_RESULT_UNSUPPORTED; ++ smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges); + + return PP_SMU_RESULT_OK; + } +diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +index 26cacc899dfe..a5255116785b 100644 +--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +@@ -1813,6 +1813,41 @@ int smu_set_df_cstate(struct smu_context *smu, + return ret; + } + ++int smu_write_watermarks_table(struct smu_context *smu) ++{ ++ int ret = 0; ++ struct smu_table_context *smu_table = &smu->smu_table; ++ struct smu_table *table = NULL; ++ ++ table = &smu_table->tables[SMU_TABLE_WATERMARKS]; ++ ++ if (!table->cpu_addr) ++ return -EINVAL; ++ ++ ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr, ++ true); ++ ++ return ret; ++} ++ ++int smu_set_watermarks_for_clock_ranges(struct smu_context *smu, ++ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges) ++{ ++ int ret = 0; ++ struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS]; ++ void *table = watermarks->cpu_addr; ++ ++ if (!smu->disable_watermark && ++ smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && ++ smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { ++ smu_set_watermarks_table(smu, table, clock_ranges); ++ smu->watermarks_bitmap |= WATERMARKS_EXIST; ++ smu->watermarks_bitmap &= ~WATERMARKS_LOADED; ++ } ++ ++ return ret; ++} ++ + const struct amd_ip_funcs smu_ip_funcs = { + .name = "smu", + .early_init = smu_early_init, +diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +index cdb845f5f23e..bf13bf33ba0c 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +@@ -470,6 +470,7 @@ struct pptable_funcs { + uint32_t dpm_level, uint32_t *freq); + int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); + int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap); ++ int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); + }; + + struct smu_funcs +@@ -495,7 +496,6 @@ struct smu_funcs + int (*set_min_dcef_deep_sleep)(struct smu_context *smu); + int (*set_tool_table_location)(struct smu_context *smu); + int (*notify_memory_pool_location)(struct smu_context *smu); +- int (*write_watermarks_table)(struct smu_context *smu); + int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu); + int (*system_features_control)(struct smu_context *smu, bool en); + int (*send_smc_msg)(struct smu_context *smu, uint16_t msg); +@@ -533,8 +533,6 @@ struct smu_funcs + int (*get_current_shallow_sleep_clocks)(struct smu_context *smu, + struct smu_clock_info *clocks); + int (*notify_smu_enable_pwe)(struct smu_context *smu); +- int (*set_watermarks_for_clock_ranges)(struct smu_context *smu, +- struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges); + int (*conv_power_profile_to_pplib_workload)(int power_profile); + uint32_t (*get_fan_control_mode)(struct smu_context *smu); + int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); +@@ -599,9 +597,6 @@ struct smu_funcs + ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0) + #define smu_gfx_off_control(smu, enable) \ + ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0) +- +-#define smu_write_watermarks_table(smu) \ +- ((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0) + #define smu_set_last_dcef_min_deep_sleep_clk(smu) \ + ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0) + #define smu_system_features_control(smu, en) \ +@@ -741,8 +736,6 @@ struct smu_funcs + ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0) + #define smu_notify_smu_enable_pwe(smu) \ + ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0) +-#define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \ +- ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0) + #define smu_dpm_set_uvd_enable(smu, enable) \ + ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0) + #define smu_dpm_set_vce_enable(smu, enable) \ +@@ -781,9 +774,10 @@ struct smu_funcs + ((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0) + #define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \ + ((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL) +- + #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \ + ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL) ++#define smu_get_dpm_clock_table(smu, clock_table) \ ++ ((smu)->ppt_funcs->get_dpm_clock_table ? (smu)->ppt_funcs->get_dpm_clock_table((smu), (clock_table)) : -EINVAL) + + #define smu_override_pcie_parameters(smu) \ + ((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0) +@@ -823,6 +817,10 @@ int smu_sys_get_pp_table(struct smu_context *smu, void **table); + int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size); + int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info); + enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu); ++int smu_write_watermarks_table(struct smu_context *smu); ++int smu_set_watermarks_for_clock_ranges( ++ struct smu_context *smu, ++ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges); + + /* smu to display interface */ + extern int smu_display_configuration_change(struct smu_context *smu, const +diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c +index 6aedffd739db..fa314c275a82 100644 +--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c ++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c +@@ -416,6 +416,40 @@ static int renoir_get_profiling_clk_mask(struct smu_context *smu, + return 0; + } + ++/** ++ * This interface get dpm clock table for dc ++ */ ++static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) ++{ ++ DpmClocks_t *table = smu->smu_table.clocks_table; ++ int i; ++ ++ if (!clock_table || !table) ++ return -EINVAL; ++ ++ for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) { ++ clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq; ++ clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol; ++ } ++ ++ for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) { ++ clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq; ++ clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol; ++ } ++ ++ for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) { ++ clock_table->FClocks[i].Freq = table->FClocks[i].Freq; ++ clock_table->FClocks[i].Vol = table->FClocks[i].Vol; ++ } ++ ++ for (i = 0; i< PP_SMU_NUM_MEMCLK_DPM_LEVELS; i++) { ++ clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq; ++ clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol; ++ } ++ ++ return 0; ++} ++ + static int renoir_force_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, uint32_t mask) + { +@@ -546,6 +580,66 @@ static int renoir_set_performance_level(struct smu_context *smu, enum amd_dpm_fo + return ret; + } + ++/* save watermark settings into pplib smu structure, ++ * also pass data to smu controller ++ */ ++static int renoir_set_watermarks_table( ++ struct smu_context *smu, ++ void *watermarks, ++ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges) ++{ ++ int i; ++ int ret = 0; ++ Watermarks_t *table = watermarks; ++ ++ if (!table || !clock_ranges) ++ return -EINVAL; ++ ++ if (clock_ranges->num_wm_dmif_sets > 4 || ++ clock_ranges->num_wm_mcif_sets > 4) ++ return -EINVAL; ++ ++ /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/ ++ for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) { ++ table->WatermarkRow[WM_DCFCLK][i].MinClock = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz)); ++ table->WatermarkRow[WM_DCFCLK][i].MaxClock = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz)); ++ table->WatermarkRow[WM_DCFCLK][i].MinMclk = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz)); ++ table->WatermarkRow[WM_DCFCLK][i].MaxMclk = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz)); ++ table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t) ++ clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; ++ } ++ ++ for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) { ++ table->WatermarkRow[WM_SOCCLK][i].MinClock = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz)); ++ table->WatermarkRow[WM_SOCCLK][i].MaxClock = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz)); ++ table->WatermarkRow[WM_SOCCLK][i].MinMclk = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz)); ++ table->WatermarkRow[WM_SOCCLK][i].MaxMclk = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz)); ++ table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t) ++ clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id; ++ } ++ ++ /* pass data to smu controller */ ++ ret = smu_write_watermarks_table(smu); ++ ++ return ret; ++} ++ + static const struct pptable_funcs renoir_ppt_funcs = { + .get_smu_msg_index = renoir_get_smu_msg_index, + .get_smu_table_index = renoir_get_smu_table_index, +@@ -562,6 +656,8 @@ static const struct pptable_funcs renoir_ppt_funcs = { + .force_clk_levels = renoir_force_clk_levels, + .set_power_profile_mode = renoir_set_power_profile_mode, + .set_performance_level = renoir_set_performance_level, ++ .get_dpm_clock_table = renoir_get_dpm_clock_table, ++ .set_watermarks_table = renoir_set_watermarks_table, + }; + + void renoir_set_ppt_funcs(struct smu_context *smu) +diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +index df1f2b99fed7..ac02bcd24da0 100644 +--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c ++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +@@ -771,23 +771,6 @@ static int smu_v11_0_write_pptable(struct smu_context *smu) + return ret; + } + +-static int smu_v11_0_write_watermarks_table(struct smu_context *smu) +-{ +- int ret = 0; +- struct smu_table_context *smu_table = &smu->smu_table; +- struct smu_table *table = NULL; +- +- table = &smu_table->tables[SMU_TABLE_WATERMARKS]; +- +- if (!table->cpu_addr) +- return -EINVAL; +- +- ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr, +- true); +- +- return ret; +-} +- + static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) + { + int ret; +@@ -1337,26 +1320,6 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu, + return ret; + } + +-static int +-smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct +- dm_pp_wm_sets_with_clock_ranges_soc15 +- *clock_ranges) +-{ +- int ret = 0; +- struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS]; +- void *table = watermarks->cpu_addr; +- +- if (!smu->disable_watermark && +- smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && +- smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { +- smu_set_watermarks_table(smu, table, clock_ranges); +- smu->watermarks_bitmap |= WATERMARKS_EXIST; +- smu->watermarks_bitmap &= ~WATERMARKS_LOADED; +- } +- +- return ret; +-} +- + static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable) + { + int ret = 0; +@@ -1854,7 +1817,6 @@ static const struct smu_funcs smu_v11_0_funcs = { + .parse_pptable = smu_v11_0_parse_pptable, + .populate_smc_tables = smu_v11_0_populate_smc_pptable, + .write_pptable = smu_v11_0_write_pptable, +- .write_watermarks_table = smu_v11_0_write_watermarks_table, + .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep, + .set_tool_table_location = smu_v11_0_set_tool_table_location, + .init_display_count = smu_v11_0_init_display_count, +@@ -1870,7 +1832,6 @@ static const struct smu_funcs smu_v11_0_funcs = { + .read_sensor = smu_v11_0_read_sensor, + .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk, + .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, +- .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges, + .get_fan_control_mode = smu_v11_0_get_fan_control_mode, + .set_fan_control_mode = smu_v11_0_set_fan_control_mode, + .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent, +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4139-drm-amdgpu-add-GFX_PIPELINE-capacity-check-for-updat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4139-drm-amdgpu-add-GFX_PIPELINE-capacity-check-for-updat.patch new file mode 100644 index 00000000..702b5411 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4139-drm-amdgpu-add-GFX_PIPELINE-capacity-check-for-updat.patch @@ -0,0 +1,31 @@ +From 8f499afce3448349e730f7865d953f1ef96085f9 Mon Sep 17 00:00:00 2001 +From: Prike Liang <Prike.Liang@amd.com> +Date: Tue, 15 Oct 2019 17:24:25 +0800 +Subject: [PATCH 4139/4736] drm/amdgpu: add GFX_PIPELINE capacity check for + updating gfx cgpg + +Before disable gfx pipeline power gating need check the flag AMD_PG_SUPPORT_GFX_PIPELINE. + +Signed-off-by: Prike Liang <Prike.Liang@amd.com> +Reviewed-by: Huang Rui <ray.huang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 24802e4d25e5..f5322313f93c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -4294,7 +4294,8 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, + gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); + } else { + gfx_v9_0_enable_gfx_cg_power_gating(adev, false); +- gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); ++ if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) ++ gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); + } + + amdgpu_gfx_rlc_exit_safe_mode(adev); +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4140-drm-amdgpu-fix-S3-failed-as-RLC-safe-mode-entry-stuc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4140-drm-amdgpu-fix-S3-failed-as-RLC-safe-mode-entry-stuc.patch new file mode 100644 index 00000000..6cd21b6e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4140-drm-amdgpu-fix-S3-failed-as-RLC-safe-mode-entry-stuc.patch @@ -0,0 +1,64 @@ +From 3056eac53726a1cb97a3d989fb62d0cd57cf27e4 Mon Sep 17 00:00:00 2001 +From: Prike Liang <Prike.Liang@amd.com> +Date: Tue, 15 Oct 2019 17:11:49 +0800 +Subject: [PATCH 4140/4736] drm/amdgpu: fix S3 failed as RLC safe mode entry + stucked in polloing gfx acq + +Fix gfx cgpg setting sequence for RLC deadlock at safe mode entry in polling gfx response. +The patch can fix VCN IB test failed and DAL get dispaly count failed issue. + +Signed-off-by: Prike Liang <Prike.Liang@amd.com> +Reviewed-by: Huang Rui <ray.huang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 ----- + drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++ + 2 files changed, 4 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index f5322313f93c..16043b824f97 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -4285,9 +4285,6 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, + { + amdgpu_gfx_rlc_enter_safe_mode(adev); + +- if (is_support_sw_smu(adev) && !enable) +- smu_set_gfx_cgpg(&adev->smu, enable); +- + if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { + gfx_v9_0_enable_gfx_cg_power_gating(adev, true); + if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) +@@ -4564,8 +4561,6 @@ static int gfx_v9_0_set_powergating_state(void *handle, + gfx_v9_0_enable_cp_power_gating(adev, false); + + /* update gfx cgpg state */ +- if (is_support_sw_smu(adev) && enable) +- smu_set_gfx_cgpg(&adev->smu, enable); + gfx_v9_0_update_gfx_cg_power_gating(adev, enable); + + /* update mgcg state */ +diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +index a5255116785b..d0a25dd8fcfc 100644 +--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +@@ -1188,6 +1188,7 @@ static int smu_hw_init(void *handle) + if (adev->flags & AMD_IS_APU) { + smu_powergate_sdma(&adev->smu, false); + smu_powergate_vcn(&adev->smu, false); ++ smu_set_gfx_cgpg(&adev->smu, true); + } + + if (!smu->pm_enabled) +@@ -1350,6 +1351,9 @@ static int smu_resume(void *handle) + if (ret) + goto failed; + ++ if (smu->is_apu) ++ smu_set_gfx_cgpg(&adev->smu, true); ++ + mutex_unlock(&smu->mutex); + + pr_info("SMU is resumed successfully!\n"); +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4141-drm-amdgpu-set-debug-register-values-at-init-time.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4141-drm-amdgpu-set-debug-register-values-at-init-time.patch new file mode 100644 index 00000000..17141737 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4141-drm-amdgpu-set-debug-register-values-at-init-time.patch @@ -0,0 +1,34 @@ +From 4bde2a3a41934d91fdbf726420c657fa1ce6e143 Mon Sep 17 00:00:00 2001 +From: Philip Cox <Philip.Cox@amd.com> +Date: Wed, 14 Aug 2019 09:09:19 -0400 +Subject: [PATCH 4141/4736] drm/amdgpu: set debug register values at init time + +We need to initialize the SPI_GDBG_TRAP_MASK EXCP_EN and REPLACE +to 0, along with SPI_GDBG_TRAP_DATA0, and SPI_GDBG_TRAP_DATA1 when +we initialize the debug vmid. + +Change-Id: Ib3887397578d63c110a4247d6b61bf62111bc1c5 +Signed-off-by: Philip Cox <Philip.Cox@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 16043b824f97..5e7a01c322ea 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -2273,6 +2273,11 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) + data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, + TRAP_EN, 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); ++ ++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); ++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); ++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); ++ + } + + static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4142-drm-amdkfd-No-longer-support-debug-reg-data-vars.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4142-drm-amdkfd-No-longer-support-debug-reg-data-vars.patch new file mode 100644 index 00000000..deb670f1 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4142-drm-amdkfd-No-longer-support-debug-reg-data-vars.patch @@ -0,0 +1,225 @@ +From 6d39c416f207a26d59b46ecff9aeb6023b29043d Mon Sep 17 00:00:00 2001 +From: Philip Cox <Philip.Cox@amd.com> +Date: Wed, 14 Aug 2019 09:05:52 -0400 +Subject: [PATCH 4142/4736] drm/amdkfd: No longer support debug reg data vars + +The KFD debugger uses data0/data1 for the debug trap handler, we +we need to prevent the them being updated from userspace. + +Change-Id: I91086062c744a70a2706050aa35f61014551c5ef +Signed-off-by: Philip Cox <Philip.Cox@amd.com> +--- + .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 1 - + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 22 ---------------- + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h | 3 --- + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 ----- + .../gpu/drm/amd/include/kgd_kfd_interface.h | 3 --- + include/uapi/linux/kfd_ioctl.h | 26 +++++++------------ + 6 files changed, 9 insertions(+), 52 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c +index db39c6653cce..7288810e0df5 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c +@@ -288,7 +288,6 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = { + .get_hive_id = amdgpu_amdkfd_get_hive_id, + .enable_debug_trap = kgd_gfx_v9_enable_debug_trap, + .disable_debug_trap = kgd_gfx_v9_disable_debug_trap, +- .set_debug_trap_data = kgd_gfx_v9_set_debug_trap_data, + .set_wave_launch_trap_override = kgd_gfx_v9_set_wave_launch_trap_override, + .set_wave_launch_mode = kgd_gfx_v9_set_wave_launch_mode, + .get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times, +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +index 530b8ada1f8f..dae572c776cc 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +@@ -845,9 +845,6 @@ uint32_t kgd_gfx_v9_enable_debug_trap(struct kgd_dev *kgd, + data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data); + +- WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); +- WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); +- + data = 0; + WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data); + +@@ -864,9 +861,6 @@ uint32_t kgd_gfx_v9_disable_debug_trap(struct kgd_dev *kgd) + + mutex_lock(&adev->grbm_idx_mutex); + +- WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); +- WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); +- + WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); + + mutex_unlock(&adev->grbm_idx_mutex); +@@ -874,21 +868,6 @@ uint32_t kgd_gfx_v9_disable_debug_trap(struct kgd_dev *kgd) + return 0; + } + +-uint32_t kgd_gfx_v9_set_debug_trap_data(struct kgd_dev *kgd, +- int trap_data0, +- int trap_data1) +-{ +- struct amdgpu_device *adev = get_amdgpu_device(kgd); +- +- mutex_lock(&adev->grbm_idx_mutex); +- +- WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), trap_data0); +- WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), trap_data1); +- +- mutex_unlock(&adev->grbm_idx_mutex); +- return 0; +-} +- + uint32_t kgd_gfx_v9_set_wave_launch_trap_override(struct kgd_dev *kgd, + uint32_t trap_override, + uint32_t trap_mask) +@@ -1037,7 +1016,6 @@ const struct kfd2kgd_calls gfx_v9_kfd2kgd = { + .get_hive_id = amdgpu_amdkfd_get_hive_id, + .enable_debug_trap = kgd_gfx_v9_enable_debug_trap, + .disable_debug_trap = kgd_gfx_v9_disable_debug_trap, +- .set_debug_trap_data = kgd_gfx_v9_set_debug_trap_data, + .set_wave_launch_trap_override = kgd_gfx_v9_set_wave_launch_trap_override, + .set_wave_launch_mode = kgd_gfx_v9_set_wave_launch_mode, + .get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times, +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h +index 7611ba466aa4..2b41d810c68e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h +@@ -67,9 +67,6 @@ uint32_t kgd_gfx_v9_enable_debug_trap(struct kgd_dev *kgd, + uint32_t trap_debug_wave_launch_mode, + uint32_t vmid); + uint32_t kgd_gfx_v9_disable_debug_trap(struct kgd_dev *kgd); +-uint32_t kgd_gfx_v9_set_debug_trap_data(struct kgd_dev *kgd, +- int trap_data0, +- int trap_data1); + uint32_t kgd_gfx_v9_set_wave_launch_trap_override(struct kgd_dev *kgd, + uint32_t trap_override, + uint32_t trap_mask); +diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +index c60c4480d124..52acb0064939 100644 +--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c ++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +@@ -2763,12 +2763,6 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep, + } + break; + +- case KFD_IOC_DBG_TRAP_SET_TRAP_DATA: +- r = dev->kfd2kgd->set_debug_trap_data(dev->kgd, +- data1, +- data2); +- break; +- + case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE: + r = dev->kfd2kgd->set_wave_launch_trap_override( + dev->kgd, +diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +index db00c2ec9277..975961a298d9 100644 +--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h ++++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +@@ -327,9 +327,6 @@ struct kfd2kgd_calls { + uint32_t trap_debug_wave_launch_mode, + uint32_t vmid); + uint32_t (*disable_debug_trap)(struct kgd_dev *kgd); +- uint32_t (*set_debug_trap_data)(struct kgd_dev *kgd, +- int trap_data0, +- int trap_data1); + uint32_t (*set_wave_launch_trap_override)(struct kgd_dev *kgd, + uint32_t trap_override, + uint32_t trap_mask); +diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h +index 8c9a5ab34d9e..760b3d6159fa 100644 +--- a/include/uapi/linux/kfd_ioctl.h ++++ b/include/uapi/linux/kfd_ioctl.h +@@ -28,8 +28,8 @@ + + #define KFD_IOCTL_MAJOR_VERSION 1 + #define KFD_IOCTL_MINOR_VERSION 2 +-#define KFD_IOCTL_DBG_MAJOR_VERSION 0 +-#define KFD_IOCTL_DBG_MINOR_VERSION 2 ++#define KFD_IOCTL_DBG_MAJOR_VERSION 1 ++#define KFD_IOCTL_DBG_MINOR_VERSION 0 + + struct kfd_ioctl_get_version_args { + __u32 major_version; /* from KFD */ +@@ -219,21 +219,13 @@ struct kfd_ioctl_dbg_wave_control_args { + */ + #define KFD_IOC_DBG_TRAP_ENABLE 0 + +-/* KFD_IOC_DBG_TRAP_SET_TRAP_DATA: +- * ptr: unused +- * data1: SPI_GDBG_TRAP_DATA0 +- * data2: SPI_GDBG_TRAP_DATA1 +- * data3: unused +- */ +-#define KFD_IOC_DBG_TRAP_SET_TRAP_DATA 1 +- + /* KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE: + * ptr: unused + * data1: override mode: 0=OR, 1=REPLACE + * data2: mask + * data3: unused + */ +-#define KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE 2 ++#define KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE 1 + + /* KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE: + * ptr: unused +@@ -241,7 +233,7 @@ struct kfd_ioctl_dbg_wave_control_args { + * data2: unused + * data3: unused + */ +-#define KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE 3 ++#define KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE 2 + + /* KFD_IOC_DBG_TRAP_NODE_SUSPEND: + * ptr: pointer to an array of Queues IDs +@@ -249,7 +241,7 @@ struct kfd_ioctl_dbg_wave_control_args { + * data2: number of queues + * data3: grace period + */ +-#define KFD_IOC_DBG_TRAP_NODE_SUSPEND 4 ++#define KFD_IOC_DBG_TRAP_NODE_SUSPEND 3 + + /* KFD_IOC_DBG_TRAP_NODE_RESUME: + * ptr: pointer to an array of Queues IDs +@@ -257,7 +249,7 @@ struct kfd_ioctl_dbg_wave_control_args { + * data2: number of queues + * data3: unused + */ +-#define KFD_IOC_DBG_TRAP_NODE_RESUME 5 ++#define KFD_IOC_DBG_TRAP_NODE_RESUME 4 + + /* KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT: + * ptr: unused +@@ -265,7 +257,7 @@ struct kfd_ioctl_dbg_wave_control_args { + * data2: flags (IN) + * data3: suspend[2:2], event type [1:0] (OUT) + */ +-#define KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT 6 ++#define KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT 5 + + /* KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT: + * ptr: user buffer (IN) +@@ -273,7 +265,7 @@ struct kfd_ioctl_dbg_wave_control_args { + * data2: number of queue snapshots (IN/OUT) - 0 for IN ignores buffer writes + * data3: unused + */ +-#define KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT 7 ++#define KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT 6 + + /* KFD_IOC_DBG_TRAP_GET_VERSION: + * prt: unsused +@@ -281,7 +273,7 @@ struct kfd_ioctl_dbg_wave_control_args { + * data2: minor version (OUT) + * data3: unused + */ +-#define KFD_IOC_DBG_TRAP_GET_VERSION 8 ++#define KFD_IOC_DBG_TRAP_GET_VERSION 7 + + struct kfd_ioctl_dbg_trap_args { + __u64 ptr; /* to KFD -- used for pointer arguments: queue arrays */ +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4143-drm-amdkfd-Debugger-block-non-default-trap-masks.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4143-drm-amdkfd-Debugger-block-non-default-trap-masks.patch new file mode 100644 index 00000000..2ab9fda2 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4143-drm-amdkfd-Debugger-block-non-default-trap-masks.patch @@ -0,0 +1,40 @@ +From 572c9105eb8273143b2327887ef08c9c06362ed0 Mon Sep 17 00:00:00 2001 +From: Philip Cox <Philip.Cox@amd.com> +Date: Wed, 14 Aug 2019 09:32:55 -0400 +Subject: [PATCH 4143/4736] drm/amdkfd: Debugger: block non default trap masks + +On the current hardware, we only support the default trap mask, +so we need to block non default values until supported in by +future hardware. + +Change-Id: Iad94057bb33564b972cc3e7e0f401340f215c8ba +Signed-off-by: Philip Cox <Philip.Cox@amd.com> +--- + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +index 52acb0064939..22f7aa576c7e 100644 +--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c ++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +@@ -2764,6 +2764,17 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep, + break; + + case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE: ++ if (data2 != 0) { ++ /* On current hardware, we only support a trap ++ * mask value of 0. This is because the debug ++ * trap mask is global and shared by all processes ++ * on current hardware. ++ */ ++ pr_err("Invalid trap override option: %i\n", ++ data2); ++ r = -EINVAL; ++ goto unlock_out; ++ } + r = dev->kfd2kgd->set_wave_launch_trap_override( + dev->kgd, + data1, +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4144-drm-amdgpu-user-pages-array-memory-leak-fix.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4144-drm-amdgpu-user-pages-array-memory-leak-fix.patch new file mode 100644 index 00000000..482f0848 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4144-drm-amdgpu-user-pages-array-memory-leak-fix.patch @@ -0,0 +1,62 @@ +From b375022c24b01407c736e4a959632368abab0ec1 Mon Sep 17 00:00:00 2001 +From: Philip Yang <Philip.Yang@amd.com> +Date: Thu, 3 Oct 2019 14:18:25 -0400 +Subject: [PATCH 4144/4736] drm/amdgpu: user pages array memory leak fix +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +user_pages array should always be freed after validation regardless if +user pages are changed after bo is created because with HMM change parse +bo always allocate user pages array to get user pages for userptr bo. + +v2: remove unused local variable and amend commit + +v3: add back get user pages in gem_userptr_ioctl, to detect application +bug where an userptr VMA is not ananymous memory and reject it. + +Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962 + +Signed-off-by: Philip Yang <Philip.Yang@amd.com> +Tested-by: Joe Barnett <thejoe@gmail.com> +Reviewed-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +index ba43f3f6467b..e8dfbcfad034 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +@@ -475,7 +475,6 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, + + list_for_each_entry(lobj, validated, tv.head) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo); +- bool binding_userptr = false; + struct mm_struct *usermm; + + usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm); +@@ -492,17 +491,14 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, + + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, + lobj->user_pages); +- binding_userptr = true; + } + + r = amdgpu_cs_validate(p, bo); + if (r) + return r; + +- if (binding_userptr) { +- kvfree(lobj->user_pages); +- lobj->user_pages = NULL; +- } ++ kvfree(lobj->user_pages); ++ lobj->user_pages = NULL; + } + return 0; + } +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4145-dmr-amdgpu-Fix-crash-on-SRIOV-for-ERREVENT_ATHUB_INT.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4145-dmr-amdgpu-Fix-crash-on-SRIOV-for-ERREVENT_ATHUB_INT.patch new file mode 100644 index 00000000..b52437d4 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4145-dmr-amdgpu-Fix-crash-on-SRIOV-for-ERREVENT_ATHUB_INT.patch @@ -0,0 +1,35 @@ +From a8345914d289569a43abf805e2492c036e8d1cae Mon Sep 17 00:00:00 2001 +From: Andrey Grodzovsky <andrey.grodzovsky@amd.com> +Date: Fri, 11 Oct 2019 10:32:59 -0400 +Subject: [PATCH 4145/4736] dmr/amdgpu: Fix crash on SRIOV for + ERREVENT_ATHUB_INTERRUPT interrupt. + +Ignre the ERREVENT_ATHUB_INTERRUPT for systems without RAS. + +Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> +Reviewed-and-tested-by: Jack Zhang <Jack.Zhang1@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +index f3f3a98f93b3..1ca613014126 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +@@ -1886,6 +1886,12 @@ int amdgpu_ras_fini(struct amdgpu_device *adev) + + void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) + { ++ uint32_t hw_supported, supported; ++ ++ amdgpu_ras_check_supported(adev, &hw_supported, &supported); ++ if (!hw_supported) ++ return; ++ + if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { + DRM_WARN("RAS event of type ERREVENT_ATHUB_INTERRUPT detected!\n"); + +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4146-drm-amdgpu-move-pci_save_state-into-suspend-path.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4146-drm-amdgpu-move-pci_save_state-into-suspend-path.patch new file mode 100644 index 00000000..d96baf07 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4146-drm-amdgpu-move-pci_save_state-into-suspend-path.patch @@ -0,0 +1,31 @@ +From a2d71268b375d0bb2a5a0f2ad251ada05b44be49 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 4 Oct 2019 14:33:39 -0500 +Subject: [PATCH 4146/4736] drm/amdgpu: move pci_save_state into suspend path + +for amdgpu_device_suspend. This follows the logic +in the resume path. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 521af22ad916..cb4192e6062a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -3179,8 +3179,8 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) + */ + amdgpu_bo_evict_vram(adev); + +- pci_save_state(dev->pdev); + if (suspend) { ++ pci_save_state(dev->pdev); + /* Shut down the device */ + pci_disable_device(dev->pdev); + pci_set_power_state(dev->pdev, PCI_D3hot); +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4147-drm-amdgpu-move-gpu-reset-out-of-amdgpu_device_suspe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4147-drm-amdgpu-move-gpu-reset-out-of-amdgpu_device_suspe.patch new file mode 100644 index 00000000..e4be600c --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4147-drm-amdgpu-move-gpu-reset-out-of-amdgpu_device_suspe.patch @@ -0,0 +1,54 @@ +From d36140c553925eecd978e388bc78d10af37eb90f Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 4 Oct 2019 14:57:21 -0500 +Subject: [PATCH 4147/4736] drm/amdgpu: move gpu reset out of + amdgpu_device_suspend + +Move it into the caller. There are cases were we don't +want it. We need it for hibernation, but we don't need +it for runtime pm, so drop it for runtime pm. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ---- + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 ++++++- + 2 files changed, 6 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index cb4192e6062a..46723a10d98a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -3184,10 +3184,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) + /* Shut down the device */ + pci_disable_device(dev->pdev); + pci_set_power_state(dev->pdev, PCI_D3hot); +- } else { +- r = amdgpu_asic_reset(adev); +- if (r) +- DRM_ERROR("amdgpu asic reset failed\n"); + } + + return 0; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +index 658fa3fd5fad..5ab426726849 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +@@ -1201,8 +1201,13 @@ static int amdgpu_pmops_resume(struct device *dev) + static int amdgpu_pmops_freeze(struct device *dev) + { + struct drm_device *drm_dev = dev_get_drvdata(dev); ++ struct amdgpu_device *adev = drm_dev->dev_private; ++ int r; + +- return amdgpu_device_suspend(drm_dev, false, true); ++ r = amdgpu_device_suspend(drm_dev, false, true); ++ if (r) ++ return r; ++ return amdgpu_asic_reset(adev); + } + + static int amdgpu_pmops_thaw(struct device *dev) +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4148-drm-amdgpu-remove-in_baco_reset-hack.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4148-drm-amdgpu-remove-in_baco_reset-hack.patch new file mode 100644 index 00000000..247673fd --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4148-drm-amdgpu-remove-in_baco_reset-hack.patch @@ -0,0 +1,60 @@ +From a3b613233260dda95131f1651b3eb869ad0c9bbe Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 4 Oct 2019 11:01:11 -0500 +Subject: [PATCH 4148/4736] drm/amdgpu: remove in_baco_reset hack + +It was a vega20 specific hack. Check if we are in reset +and what reset method we are using. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 -- + drivers/gpu/drm/amd/amdgpu/soc15.c | 2 -- + drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 4 ++-- + 3 files changed, 2 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index a994117c4edc..e4172f9bece6 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -1008,8 +1008,6 @@ struct amdgpu_device { + int asic_reset_res; + struct work_struct xgmi_reset_work; + +- bool in_baco_reset; +- + long gfx_timeout; + long sdma_timeout; + long video_timeout; +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index 82b5bc4ddf9b..5fadb237d103 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -515,8 +515,6 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev) + + dev_info(adev->dev, "GPU BACO reset\n"); + +- adev->in_baco_reset = 1; +- + return 0; + } + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +index 3d3c647a63ff..9295bd90b792 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +@@ -493,8 +493,8 @@ static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr) + "Failed to init sclk threshold!", + return ret); + +- if (adev->in_baco_reset) { +- adev->in_baco_reset = 0; ++ if (adev->in_gpu_reset && ++ (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) { + + ret = vega20_baco_apply_vdci_flush_workaround(hwmgr); + if (ret) +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4149-drm-amdgpu-soc15-add-support-for-baco-reset-with-swS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4149-drm-amdgpu-soc15-add-support-for-baco-reset-with-swS.patch new file mode 100644 index 00000000..f3fe7ccb --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4149-drm-amdgpu-soc15-add-support-for-baco-reset-with-swS.patch @@ -0,0 +1,100 @@ +From 34656170efd682732e9b3e565cb013055295dbbe Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Tue, 15 Oct 2019 14:27:01 -0400 +Subject: [PATCH 4149/4736] drm/amdgpu/soc15: add support for baco reset with + swSMU + +Add support for vega20 when the swSMU path is used. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/soc15.c | 53 ++++++++++++++++++++---------- + 1 file changed, 35 insertions(+), 18 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index 5fadb237d103..438722c0b76a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -477,15 +477,22 @@ static int soc15_asic_mode1_reset(struct amdgpu_device *adev) + + static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap) + { +- void *pp_handle = adev->powerplay.pp_handle; +- const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; ++ if (is_support_sw_smu(adev)) { ++ struct smu_context *smu = &adev->smu; + +- if (!pp_funcs || !pp_funcs->get_asic_baco_capability) { +- *cap = false; +- return -ENOENT; +- } ++ *cap = smu_baco_is_support(smu); ++ return 0; ++ } else { ++ void *pp_handle = adev->powerplay.pp_handle; ++ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; ++ ++ if (!pp_funcs || !pp_funcs->get_asic_baco_capability) { ++ *cap = false; ++ return -ENOENT; ++ } + +- return pp_funcs->get_asic_baco_capability(pp_handle, cap); ++ return pp_funcs->get_asic_baco_capability(pp_handle, cap); ++ } + } + + static int soc15_asic_baco_reset(struct amdgpu_device *adev) +@@ -494,27 +501,37 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev) + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; + struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); + +- if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state) +- return -ENOENT; +- + /* avoid NBIF got stuck when do RAS recovery in BACO reset */ + if (ras && ras->supported) + adev->nbio.funcs->enable_doorbell_interrupt(adev, false); + +- /* enter BACO state */ +- if (pp_funcs->set_asic_baco_state(pp_handle, 1)) +- return -EIO; ++ dev_info(adev->dev, "GPU BACO reset\n"); ++ ++ if (is_support_sw_smu(adev)) { ++ struct smu_context *smu = &adev->smu; ++ ++ if (smu_baco_reset(smu)) ++ return -EIO; ++ } else { ++ void *pp_handle = adev->powerplay.pp_handle; ++ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; ++ ++ if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state) ++ return -ENOENT; ++ ++ /* enter BACO state */ ++ if (pp_funcs->set_asic_baco_state(pp_handle, 1)) ++ return -EIO; + +- /* exit BACO state */ +- if (pp_funcs->set_asic_baco_state(pp_handle, 0)) +- return -EIO; ++ /* exit BACO state */ ++ if (pp_funcs->set_asic_baco_state(pp_handle, 0)) ++ return -EIO; ++ } + + /* re-enable doorbell interrupt after BACO exit */ + if (ras && ras->supported) + adev->nbio.funcs->enable_doorbell_interrupt(adev, true); + +- dev_info(adev->dev, "GPU BACO reset\n"); +- + return 0; + } + +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4150-drm-amdgpu-add-new-BIF-4.1-register-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4150-drm-amdgpu-add-new-BIF-4.1-register-for-BACO.patch new file mode 100644 index 00000000..4819597a --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4150-drm-amdgpu-add-new-BIF-4.1-register-for-BACO.patch @@ -0,0 +1,44 @@ +From c6859827ffe21a626ef9a31179f937859d553c1d Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 15 Feb 2019 14:40:26 -0500 +Subject: [PATCH 4150/4736] drm/amdgpu: add new BIF 4.1 register for BACO +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h | 1 + + drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h | 2 ++ + 2 files changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h +index a761ba07f937..fce965984e76 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h +@@ -27,6 +27,7 @@ + #define mmMM_INDEX 0x0 + #define mmMM_INDEX_HI 0x6 + #define mmMM_DATA 0x1 ++#define mmCC_BIF_BX_FUSESTRAP0 0x14D7 + #define mmBUS_CNTL 0x1508 + #define mmCONFIG_CNTL 0x1509 + #define mmCONFIG_MEMSIZE 0x150a +diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h +index 8fbfd0261d27..39cc4880beb4 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h +@@ -32,6 +32,8 @@ + #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 + #define MM_DATA__MM_DATA_MASK 0xffffffff + #define MM_DATA__MM_DATA__SHIFT 0x0 ++#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2 ++#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1 + #define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1 + #define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0 + #define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2 +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4151-drm-amdgpu-add-new-BIF-5.0-register-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4151-drm-amdgpu-add-new-BIF-5.0-register-for-BACO.patch new file mode 100644 index 00000000..bae6f731 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4151-drm-amdgpu-add-new-BIF-5.0-register-for-BACO.patch @@ -0,0 +1,44 @@ +From 58c05ba33e4ff776d63e782cf1d41af513c4732e Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Mon, 11 Feb 2019 12:28:45 -0500 +Subject: [PATCH 4151/4736] drm/amdgpu: add new BIF 5.0 register for BACO +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h | 1 + + drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h | 2 ++ + 2 files changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h +index 809759f7bb81..8d05d6ca1c8d 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h +@@ -27,6 +27,7 @@ + #define mmMM_INDEX 0x0 + #define mmMM_INDEX_HI 0x6 + #define mmMM_DATA 0x1 ++#define mmCC_BIF_BX_FUSESTRAP0 0x14D7 + #define mmCC_BIF_BX_STRAP2 0x152A + #define mmBIF_MM_INDACCESS_CNTL 0x1500 + #define mmBIF_DOORBELL_APER_EN 0x1501 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h +index adc71b01f793..73435687d049 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h +@@ -32,6 +32,8 @@ + #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 + #define MM_DATA__MM_DATA_MASK 0xffffffff + #define MM_DATA__MM_DATA__SHIFT 0x0 ++#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2 ++#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1 + #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2 + #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 + #define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x1 +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch new file mode 100644 index 00000000..3640ee54 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch @@ -0,0 +1,44 @@ +From ebcfe185bdd35b9616c29db859721ca3123c7933 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 4 Oct 2019 15:14:18 -0500 +Subject: [PATCH 4152/4736] drm/amdgpu: add new SMU 7.0.1 registers for BACO +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h | 1 + + drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h | 2 ++ + 2 files changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h +index dbc2e723f659..71169daa701a 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h +@@ -49,6 +49,7 @@ + #define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 + #define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 + #define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 ++#define ixCG_SPLL_STATUS 0xC050015C + #define ixSPLL_CNTL_MODE 0xc0500160 + #define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 + #define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h +index 6af9f0217b34..61a9a84e0c3a 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h +@@ -194,6 +194,8 @@ + #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 + #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff + #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 ++#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2 ++#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1 + #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 + #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 + #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4153-drm-amdgpu-add-new-SMU-7.1.2-registers-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4153-drm-amdgpu-add-new-SMU-7.1.2-registers-for-BACO.patch new file mode 100644 index 00000000..e4183cdc --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4153-drm-amdgpu-add-new-SMU-7.1.2-registers-for-BACO.patch @@ -0,0 +1,44 @@ +From 4e9bf31212fdf138cab1d6bc69156609822a381b Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 4 Oct 2019 15:16:43 -0500 +Subject: [PATCH 4153/4736] drm/amdgpu: add new SMU 7.1.2 registers for BACO +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h | 1 + + drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h | 2 ++ + 2 files changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h +index bd3685166779..351446754c72 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h +@@ -49,6 +49,7 @@ + #define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 + #define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 + #define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 ++#define ixCG_SPLL_STATUS 0xC050015C + #define ixSPLL_CNTL_MODE 0xc0500160 + #define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 + #define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h +index 627906674fe8..4bfd5f8ba66c 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h +@@ -194,6 +194,8 @@ + #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 + #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff + #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 ++#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2 ++#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1 + #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 + #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 + #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch new file mode 100644 index 00000000..bcb1a5c9 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch @@ -0,0 +1,44 @@ +From a991be32477d0862ec2ca93fc8c63f304570b897 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 4 Oct 2019 15:18:52 -0500 +Subject: [PATCH 4154/4736] drm/amdgpu: add new SMU 7.1.3 registers for BACO +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h | 1 + + drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h | 2 ++ + 2 files changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h +index f35aba72e640..21da61c398f5 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h +@@ -52,6 +52,7 @@ + #define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 + #define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 + #define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 ++#define ixCG_SPLL_STATUS 0xC050015C + #define ixSPLL_CNTL_MODE 0xc0500160 + #define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 + #define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h +index 481ee6560aa9..f64fe0fbcb32 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h +@@ -220,6 +220,8 @@ + #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 + #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff + #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 ++#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2 ++#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1 + #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 + #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 + #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4155-drm-amdgpu-powerplay-add-core-support-for-pre-SOC15-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4155-drm-amdgpu-powerplay-add-core-support-for-pre-SOC15-.patch new file mode 100644 index 00000000..47666b97 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4155-drm-amdgpu-powerplay-add-core-support-for-pre-SOC15-.patch @@ -0,0 +1,83 @@ +From 57a7d38e14d4b5eda2b000265b9714fc137b83df Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Sun, 10 Feb 2019 21:57:55 -0500 +Subject: [PATCH 4155/4736] drm/amdgpu/powerplay: add core support for + pre-SOC15 baco +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This adds core support for BACO on pre-vega asics. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../gpu/drm/amd/powerplay/hwmgr/common_baco.c | 19 +++++++++++++++++++ + .../gpu/drm/amd/powerplay/hwmgr/common_baco.h | 13 +++++++++++++ + 2 files changed, 32 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c +index 9c57c1f67749..1c73776bd606 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c +@@ -79,6 +79,25 @@ static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 m + return ret; + } + ++bool baco_program_registers(struct pp_hwmgr *hwmgr, ++ const struct baco_cmd_entry *entry, ++ const u32 array_size) ++{ ++ u32 i, reg = 0; ++ ++ for (i = 0; i < array_size; i++) { ++ if ((entry[i].cmd == CMD_WRITE) || ++ (entry[i].cmd == CMD_READMODIFYWRITE) || ++ (entry[i].cmd == CMD_WAITFOR)) ++ reg = entry[i].reg_offset; ++ if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask, ++ entry[i].shift, entry[i].val, entry[i].timeout)) ++ return false; ++ } ++ ++ return true; ++} ++ + bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr, + const struct soc15_baco_cmd_entry *entry, + const u32 array_size) +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h +index 95296c916f4e..8393eb62706d 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h +@@ -33,6 +33,15 @@ enum baco_cmd_type { + CMD_DELAY_US, + }; + ++struct baco_cmd_entry { ++ enum baco_cmd_type cmd; ++ uint32_t reg_offset; ++ uint32_t mask; ++ uint32_t shift; ++ uint32_t timeout; ++ uint32_t val; ++}; ++ + struct soc15_baco_cmd_entry { + enum baco_cmd_type cmd; + uint32_t hwip; +@@ -44,6 +53,10 @@ struct soc15_baco_cmd_entry { + uint32_t timeout; + uint32_t val; + }; ++ ++extern bool baco_program_registers(struct pp_hwmgr *hwmgr, ++ const struct baco_cmd_entry *entry, ++ const u32 array_size); + extern bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr, + const struct soc15_baco_cmd_entry *entry, + const u32 array_size); +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4156-drm-amdgpu-powerplay-add-support-for-BACO-on-tonga.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4156-drm-amdgpu-powerplay-add-support-for-BACO-on-tonga.patch new file mode 100644 index 00000000..3e029169 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4156-drm-amdgpu-powerplay-add-support-for-BACO-on-tonga.patch @@ -0,0 +1,302 @@ +From 718f101490fedd049c6a6a156d9af5701769cdb5 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 15 Feb 2019 17:35:50 -0500 +Subject: [PATCH 4156/4736] drm/amdgpu/powerplay: add support for BACO on tonga +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This adds BACO support for Tonga. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +- + .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.c | 221 ++++++++++++++++++ + .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.h | 32 +++ + 3 files changed, 254 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c + create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +index cc63705920dc..d66cfe5f80f9 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +@@ -36,7 +36,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \ + pp_overdriver.o smu_helper.o \ + vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \ + vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \ +- vega12_baco.o smu9_baco.o ++ vega12_baco.o smu9_baco.o tonga_baco.o + + AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c +new file mode 100644 +index 000000000000..37a41b83c913 +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c +@@ -0,0 +1,221 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#include "amdgpu.h" ++#include "tonga_baco.h" ++ ++#include "gmc/gmc_8_1_d.h" ++#include "gmc/gmc_8_1_sh_mask.h" ++ ++#include "bif/bif_5_0_d.h" ++#include "bif/bif_5_0_sh_mask.h" ++ ++#include "dce/dce_10_0_d.h" ++#include "dce/dce_10_0_sh_mask.h" ++ ++#include "smu/smu_7_1_2_d.h" ++#include "smu/smu_7_1_2_sh_mask.h" ++ ++ ++static const struct baco_cmd_entry gpio_tbl[] = ++{ ++ { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff }, ++ { CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff }, ++ { CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 }, ++ { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 } ++}; ++ ++static const struct baco_cmd_entry enable_fb_req_rej_tbl[] = ++{ ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 }, ++ { CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 } ++}; ++ ++static const struct baco_cmd_entry use_bclk_tbl[] = ++{ ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS }, ++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS }, ++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }, ++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK, MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT, 0, 0x0 } ++}; ++ ++static const struct baco_cmd_entry turn_off_plls_tbl[] = ++{ ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK, CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x2000000, 0x19, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x8000000, 0x1b, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmMPLL_CONTROL, 0, 0, 0, 0x00000006 }, ++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D0, 0, 0, 0, 0x00007740 }, ++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D1, 0, 0, 0, 0x00007740 }, ++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D0, 0, 0, 0, 0x00007740 }, ++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D1, 0, 0, 0, 0x00007740 }, ++ { CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PU_MASK, MC_SEQ_CNTL_2__DRST_PU__SHIFT, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PD_MASK, MC_SEQ_CNTL_2__DRST_PD__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 } ++}; ++ ++static const struct baco_cmd_entry enter_baco_tbl[] = ++{ ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, 0, 5, 0x40000 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 } ++}; ++ ++#define BACO_CNTL__PWRGOOD_MASK BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK ++ ++static const struct baco_cmd_entry exit_baco_tbl[] = ++{ ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 } ++}; ++ ++static const struct baco_cmd_entry clean_baco_tbl[] = ++{ ++ { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 } ++}; ++ ++int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); ++ uint32_t reg; ++ ++ *cap = false; ++ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) ++ return 0; ++ ++ reg = RREG32(mmCC_BIF_BX_FUSESTRAP0); ++ ++ if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK) ++ *cap = true; ++ ++ return 0; ++} ++ ++int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); ++ uint32_t reg; ++ ++ reg = RREG32(mmBACO_CNTL); ++ ++ if (reg & BACO_CNTL__BACO_MODE_MASK) ++ /* gfx has already entered BACO state */ ++ *state = BACO_STATE_IN; ++ else ++ *state = BACO_STATE_OUT; ++ return 0; ++} ++ ++int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) ++{ ++ enum BACO_STATE cur_state; ++ ++ tonga_baco_get_state(hwmgr, &cur_state); ++ ++ if (cur_state == state) ++ /* aisc already in the target state */ ++ return 0; ++ ++ if (state == BACO_STATE_IN) { ++ baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl)); ++ baco_program_registers(hwmgr, enable_fb_req_rej_tbl, ++ ARRAY_SIZE(enable_fb_req_rej_tbl)); ++ baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl)); ++ baco_program_registers(hwmgr, turn_off_plls_tbl, ++ ARRAY_SIZE(turn_off_plls_tbl)); ++ if (baco_program_registers(hwmgr, enter_baco_tbl, ++ ARRAY_SIZE(enter_baco_tbl))) ++ return 0; ++ ++ } else if (state == BACO_STATE_OUT) { ++ /* HW requires at least 20ms between regulator off and on */ ++ msleep(20); ++ /* Execute Hardware BACO exit sequence */ ++ if (baco_program_registers(hwmgr, exit_baco_tbl, ++ ARRAY_SIZE(exit_baco_tbl))) { ++ if (baco_program_registers(hwmgr, clean_baco_tbl, ++ ARRAY_SIZE(clean_baco_tbl))) ++ return 0; ++ } ++ } ++ ++ return -EINVAL; ++} +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h +new file mode 100644 +index 000000000000..21301b043255 +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h +@@ -0,0 +1,32 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#ifndef __TONGA_BACO_H__ ++#define __TONGA_BACO_H__ ++#include "hwmgr.h" ++#include "common_baco.h" ++ ++extern int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap); ++extern int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); ++extern int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); ++ ++#endif +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4157-drm-amdgpu-powerplay-add-support-for-BACO-on-Iceland.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4157-drm-amdgpu-powerplay-add-support-for-BACO-on-Iceland.patch new file mode 100644 index 00000000..823fb413 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4157-drm-amdgpu-powerplay-add-support-for-BACO-on-Iceland.patch @@ -0,0 +1,100 @@ +From c33a4cf13aff4cdcef3fdc3426ed18f5a3d4c9ef Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 15 Feb 2019 11:56:56 -0500 +Subject: [PATCH 4157/4736] drm/amdgpu/powerplay: add support for BACO on + Iceland +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This adds BACO support for Iceland asics. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.c | 54 ++++++++++++++++--- + 1 file changed, 48 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c +index 37a41b83c913..84b7217b7bda 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c +@@ -152,6 +152,36 @@ static const struct baco_cmd_entry clean_baco_tbl[] = + { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 } + }; + ++static const struct baco_cmd_entry gpio_tbl_iceland[] = ++{ ++ { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff } ++}; ++ ++static const struct baco_cmd_entry exit_baco_tbl_iceland[] = ++{ ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 }, ++ { CMD_DELAY_MS, 0, 0, 0, 20, 0 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 } ++}; ++ ++static const struct baco_cmd_entry clean_baco_tbl_iceland[] = ++{ ++ { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 } ++}; ++ + int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) + { + struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); +@@ -195,7 +225,10 @@ int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) + return 0; + + if (state == BACO_STATE_IN) { +- baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl)); ++ if (hwmgr->chip_id == CHIP_TOPAZ) ++ baco_program_registers(hwmgr, gpio_tbl_iceland, ARRAY_SIZE(gpio_tbl_iceland)); ++ else ++ baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl)); + baco_program_registers(hwmgr, enable_fb_req_rej_tbl, + ARRAY_SIZE(enable_fb_req_rej_tbl)); + baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl)); +@@ -209,11 +242,20 @@ int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) + /* HW requires at least 20ms between regulator off and on */ + msleep(20); + /* Execute Hardware BACO exit sequence */ +- if (baco_program_registers(hwmgr, exit_baco_tbl, +- ARRAY_SIZE(exit_baco_tbl))) { +- if (baco_program_registers(hwmgr, clean_baco_tbl, +- ARRAY_SIZE(clean_baco_tbl))) +- return 0; ++ if (hwmgr->chip_id == CHIP_TOPAZ) { ++ if (baco_program_registers(hwmgr, exit_baco_tbl_iceland, ++ ARRAY_SIZE(exit_baco_tbl_iceland))) { ++ if (baco_program_registers(hwmgr, clean_baco_tbl_iceland, ++ ARRAY_SIZE(clean_baco_tbl_iceland))) ++ return 0; ++ } ++ } else { ++ if (baco_program_registers(hwmgr, exit_baco_tbl, ++ ARRAY_SIZE(exit_baco_tbl))) { ++ if (baco_program_registers(hwmgr, clean_baco_tbl, ++ ARRAY_SIZE(clean_baco_tbl))) ++ return 0; ++ } + } + } + +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4158-drm-amdgpu-powerplay-add-support-for-BACO-on-polaris.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4158-drm-amdgpu-powerplay-add-support-for-BACO-on-polaris.patch new file mode 100644 index 00000000..6bbe9db2 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4158-drm-amdgpu-powerplay-add-support-for-BACO-on-polaris.patch @@ -0,0 +1,300 @@ +From 0f5e17c868a5dd7e9b76cee03469690ba93de246 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 15 Feb 2019 17:36:40 -0500 +Subject: [PATCH 4158/4736] drm/amdgpu/powerplay: add support for BACO on + polaris +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This adds BACO support for Polaris asics. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +- + .../drm/amd/powerplay/hwmgr/polaris_baco.c | 218 ++++++++++++++++++ + .../drm/amd/powerplay/hwmgr/polaris_baco.h | 32 +++ + 3 files changed, 251 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c + create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +index d66cfe5f80f9..a1535e1430d5 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +@@ -36,7 +36,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \ + pp_overdriver.o smu_helper.o \ + vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \ + vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \ +- vega12_baco.o smu9_baco.o tonga_baco.o ++ vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o + + AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c +new file mode 100644 +index 000000000000..d0c9de88f474 +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c +@@ -0,0 +1,218 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#include "amdgpu.h" ++#include "polaris_baco.h" ++ ++#include "gmc/gmc_8_1_d.h" ++#include "gmc/gmc_8_1_sh_mask.h" ++ ++#include "bif/bif_5_0_d.h" ++#include "bif/bif_5_0_sh_mask.h" ++ ++#include "dce/dce_11_0_d.h" ++#include "dce/dce_11_0_sh_mask.h" ++ ++#include "smu/smu_7_1_3_d.h" ++#include "smu/smu_7_1_3_sh_mask.h" ++ ++static const struct baco_cmd_entry gpio_tbl[] = ++{ ++ { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff }, ++ { CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff }, ++ { CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 }, ++ { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 } ++}; ++ ++static const struct baco_cmd_entry enable_fb_req_rej_tbl[] = ++{ ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 }, ++ { CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 } ++}; ++ ++static const struct baco_cmd_entry use_bclk_tbl[] = ++{ ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixGCK_DFS_BYPASS_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK, GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }, ++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK, MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT, 0, 0x0 } ++}; ++ ++static const struct baco_cmd_entry turn_off_plls_tbl[] = ++{ ++ { CMD_READMODIFYWRITE, mmDC_GPIO_PAD_STRENGTH_1, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT, 0, 0x1 }, ++ { CMD_DELAY_US, 0, 0, 0, 1, 0x0 }, ++ { CMD_READMODIFYWRITE, mmMC_SEQ_DRAM, MC_SEQ_DRAM__RST_CTL_MASK, MC_SEQ_DRAM__RST_CTL__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC05002B0 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 }, ++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC050032C }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 }, ++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500080 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, 0xda2, 0x40, 0x6, 0, 0x0 }, ++ { CMD_DELAY_US, 0, 0, 0, 3, 0x0 }, ++ { CMD_READMODIFYWRITE, 0xda2, 0x8, 0x3, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, 0xda2, 0x3fff00, 0x8, 0, 0x32 }, ++ { CMD_DELAY_US, 0, 0, 0, 3, 0x0 }, ++ { CMD_READMODIFYWRITE, mmMPLL_FUNC_CNTL_2, MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK, MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT, 0, 0x0 }, ++ { CMD_DELAY_US, 0, 0, 0, 5, 0x0 } ++}; ++ ++static const struct baco_cmd_entry clk_req_b_tbl[] = ++{ ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 } ++}; ++ ++static const struct baco_cmd_entry enter_baco_tbl[] = ++{ ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, 0, 5, 0x40000 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 } ++}; ++ ++#define BACO_CNTL__PWRGOOD_MASK BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK ++ ++static const struct baco_cmd_entry exit_baco_tbl[] = ++{ ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 } ++}; ++ ++static const struct baco_cmd_entry clean_baco_tbl[] = ++{ ++ { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 } ++}; ++ ++int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); ++ uint32_t reg; ++ ++ *cap = false; ++ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) ++ return 0; ++ ++ reg = RREG32(mmCC_BIF_BX_FUSESTRAP0); ++ ++ if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK) ++ *cap = true; ++ ++ return 0; ++} ++ ++int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); ++ uint32_t reg; ++ ++ reg = RREG32(mmBACO_CNTL); ++ ++ if (reg & BACO_CNTL__BACO_MODE_MASK) ++ /* gfx has already entered BACO state */ ++ *state = BACO_STATE_IN; ++ else ++ *state = BACO_STATE_OUT; ++ return 0; ++} ++ ++int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) ++{ ++ enum BACO_STATE cur_state; ++ ++ polaris_baco_get_state(hwmgr, &cur_state); ++ ++ if (cur_state == state) ++ /* aisc already in the target state */ ++ return 0; ++ ++ if (state == BACO_STATE_IN) { ++ baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl)); ++ baco_program_registers(hwmgr, enable_fb_req_rej_tbl, ++ ARRAY_SIZE(enable_fb_req_rej_tbl)); ++ baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl)); ++ baco_program_registers(hwmgr, turn_off_plls_tbl, ++ ARRAY_SIZE(turn_off_plls_tbl)); ++ baco_program_registers(hwmgr, clk_req_b_tbl, ARRAY_SIZE(clk_req_b_tbl)); ++ if (baco_program_registers(hwmgr, enter_baco_tbl, ++ ARRAY_SIZE(enter_baco_tbl))) ++ return 0; ++ ++ } else if (state == BACO_STATE_OUT) { ++ /* HW requires at least 20ms between regulator off and on */ ++ msleep(20); ++ /* Execute Hardware BACO exit sequence */ ++ if (baco_program_registers(hwmgr, exit_baco_tbl, ++ ARRAY_SIZE(exit_baco_tbl))) { ++ if (baco_program_registers(hwmgr, clean_baco_tbl, ++ ARRAY_SIZE(clean_baco_tbl))) ++ return 0; ++ } ++ } ++ ++ return -EINVAL; ++} +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h +new file mode 100644 +index 000000000000..e48bfb1c5c6a +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h +@@ -0,0 +1,32 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#ifndef __POLARIS_BACO_H__ ++#define __POLARIS_BACO_H__ ++#include "hwmgr.h" ++#include "common_baco.h" ++ ++extern int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap); ++extern int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); ++extern int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); ++ ++#endif +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4159-drm-amdgpu-powerplay-add-support-for-BACO-on-VegaM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4159-drm-amdgpu-powerplay-add-support-for-BACO-on-VegaM.patch new file mode 100644 index 00000000..0b557a14 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4159-drm-amdgpu-powerplay-add-support-for-BACO-on-VegaM.patch @@ -0,0 +1,80 @@ +From eadd75308b9e8442de6849d88575fa6788c3228b Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 14 Feb 2019 16:53:42 -0500 +Subject: [PATCH 4159/4736] drm/amdgpu/powerplay: add support for BACO on VegaM +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This adds BACO support for VegaM asics. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/powerplay/hwmgr/polaris_baco.c | 42 +++++++++++++++++-- + 1 file changed, 39 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c +index d0c9de88f474..a9abe53df475 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c +@@ -148,6 +148,36 @@ static const struct baco_cmd_entry clean_baco_tbl[] = + { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 } + }; + ++static const struct baco_cmd_entry use_bclk_tbl_vg[] = ++{ ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixGCK_DFS_BYPASS_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK, GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 } ++}; ++ ++static const struct baco_cmd_entry turn_off_plls_tbl_vg[] = ++{ ++ { CMD_READMODIFYWRITE, mmDC_GPIO_PAD_STRENGTH_1, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT, 0, 0x1 }, ++ { CMD_DELAY_US, 0, 0, 0, 1, 0x0 }, ++ { CMD_READMODIFYWRITE, mmMC_SEQ_DRAM, MC_SEQ_DRAM__RST_CTL_MASK, MC_SEQ_DRAM__RST_CTL__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC05002B0 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 }, ++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC050032C }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 }, ++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500080 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 }, ++ { CMD_DELAY_US, 0, 0, 0, 3, 0x0 }, ++ { CMD_DELAY_US, 0, 0, 0, 3, 0x0 }, ++ { CMD_DELAY_US, 0, 0, 0, 5, 0x0 } ++}; ++ + int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) + { + struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); +@@ -194,9 +224,15 @@ int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) + baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl)); + baco_program_registers(hwmgr, enable_fb_req_rej_tbl, + ARRAY_SIZE(enable_fb_req_rej_tbl)); +- baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl)); +- baco_program_registers(hwmgr, turn_off_plls_tbl, +- ARRAY_SIZE(turn_off_plls_tbl)); ++ if (hwmgr->chip_id == CHIP_VEGAM) { ++ baco_program_registers(hwmgr, use_bclk_tbl_vg, ARRAY_SIZE(use_bclk_tbl_vg)); ++ baco_program_registers(hwmgr, turn_off_plls_tbl_vg, ++ ARRAY_SIZE(turn_off_plls_tbl_vg)); ++ } else { ++ baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl)); ++ baco_program_registers(hwmgr, turn_off_plls_tbl, ++ ARRAY_SIZE(turn_off_plls_tbl)); ++ } + baco_program_registers(hwmgr, clk_req_b_tbl, ARRAY_SIZE(clk_req_b_tbl)); + if (baco_program_registers(hwmgr, enter_baco_tbl, + ARRAY_SIZE(enter_baco_tbl))) +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4160-drm-amdgpu-powerplay-add-support-for-BACO-on-Fiji.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4160-drm-amdgpu-powerplay-add-support-for-BACO-on-Fiji.patch new file mode 100644 index 00000000..349ebad6 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4160-drm-amdgpu-powerplay-add-support-for-BACO-on-Fiji.patch @@ -0,0 +1,309 @@ +From 7e1936b6ba966edb01b6826ce684c565411ee6bf Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 15 Feb 2019 17:37:46 -0500 +Subject: [PATCH 4160/4736] drm/amdgpu/powerplay: add support for BACO on Fiji +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This adds BACO support for Fiji asics. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +- + .../gpu/drm/amd/powerplay/hwmgr/fiji_baco.c | 228 ++++++++++++++++++ + .../gpu/drm/amd/powerplay/hwmgr/fiji_baco.h | 32 +++ + 3 files changed, 261 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c + create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +index a1535e1430d5..bfd22d8b0aea 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +@@ -36,7 +36,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \ + pp_overdriver.o smu_helper.o \ + vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \ + vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \ +- vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o ++ vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o + + AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c +new file mode 100644 +index 000000000000..ad01919ccb27 +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c +@@ -0,0 +1,228 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#include "amdgpu.h" ++#include "fiji_baco.h" ++ ++#include "gmc/gmc_8_1_d.h" ++#include "gmc/gmc_8_1_sh_mask.h" ++ ++#include "bif/bif_5_0_d.h" ++#include "bif/bif_5_0_sh_mask.h" ++ ++#include "dce/dce_10_0_d.h" ++#include "dce/dce_10_0_sh_mask.h" ++ ++#include "smu/smu_7_1_3_d.h" ++#include "smu/smu_7_1_3_sh_mask.h" ++ ++ ++static const struct baco_cmd_entry gpio_tbl[] = ++{ ++ { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff }, ++ { CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff }, ++ { CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 }, ++ { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 } ++}; ++ ++static const struct baco_cmd_entry enable_fb_req_rej_tbl[] = ++{ ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 }, ++ { CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 } ++}; ++ ++static const struct baco_cmd_entry use_bclk_tbl[] = ++{ ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS }, ++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS }, ++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 } ++}; ++ ++static const struct baco_cmd_entry turn_off_plls_tbl[] = ++{ ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK, CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x2000000, 0x19, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x8000000, 0x1b, 0, 0x0 } ++}; ++ ++static const struct baco_cmd_entry clk_req_b_tbl[] = ++{ ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 } ++}; ++ ++static const struct baco_cmd_entry enter_baco_tbl[] = ++{ ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, 0, 5, 0x40000 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 } ++}; ++ ++#define BACO_CNTL__PWRGOOD_MASK BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK ++ ++static const struct baco_cmd_entry exit_baco_tbl[] = ++{ ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 } ++}; ++ ++static const struct baco_cmd_entry clean_baco_tbl[] = ++{ ++ { CMD_WRITE, mmBIOS_SCRATCH_0, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_1, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_2, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_3, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_4, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_5, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_8, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_9, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_10, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_11, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_12, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_13, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_14, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmBIOS_SCRATCH_15, 0, 0, 0, 0 } ++}; ++ ++int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); ++ uint32_t reg; ++ ++ *cap = false; ++ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) ++ return 0; ++ ++ reg = RREG32(mmCC_BIF_BX_FUSESTRAP0); ++ ++ if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK) ++ *cap = true; ++ ++ return 0; ++} ++ ++int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); ++ uint32_t reg; ++ ++ reg = RREG32(mmBACO_CNTL); ++ ++ if (reg & BACO_CNTL__BACO_MODE_MASK) ++ /* gfx has already entered BACO state */ ++ *state = BACO_STATE_IN; ++ else ++ *state = BACO_STATE_OUT; ++ return 0; ++} ++ ++int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) ++{ ++ enum BACO_STATE cur_state; ++ ++ fiji_baco_get_state(hwmgr, &cur_state); ++ ++ if (cur_state == state) ++ /* aisc already in the target state */ ++ return 0; ++ ++ if (state == BACO_STATE_IN) { ++ baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl)); ++ baco_program_registers(hwmgr, enable_fb_req_rej_tbl, ++ ARRAY_SIZE(enable_fb_req_rej_tbl)); ++ baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl)); ++ baco_program_registers(hwmgr, turn_off_plls_tbl, ++ ARRAY_SIZE(turn_off_plls_tbl)); ++ baco_program_registers(hwmgr, clk_req_b_tbl, ARRAY_SIZE(clk_req_b_tbl)); ++ if (baco_program_registers(hwmgr, enter_baco_tbl, ++ ARRAY_SIZE(enter_baco_tbl))) ++ return 0; ++ ++ } else if (state == BACO_STATE_OUT) { ++ /* HW requires at least 20ms between regulator off and on */ ++ msleep(20); ++ /* Execute Hardware BACO exit sequence */ ++ if (baco_program_registers(hwmgr, exit_baco_tbl, ++ ARRAY_SIZE(exit_baco_tbl))) { ++ if (baco_program_registers(hwmgr, clean_baco_tbl, ++ ARRAY_SIZE(clean_baco_tbl))) ++ return 0; ++ } ++ } ++ ++ return -EINVAL; ++} +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h +new file mode 100644 +index 000000000000..2f7c8388667e +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h +@@ -0,0 +1,32 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#ifndef __FIJI_BACO_H__ ++#define __FIJI_BACO_H__ ++#include "hwmgr.h" ++#include "common_baco.h" ++ ++extern int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap); ++extern int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); ++extern int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); ++ ++#endif +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4161-drm-amdgpu-powerplay-add-support-for-BACO-on-CI.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4161-drm-amdgpu-powerplay-add-support-for-BACO-on-CI.patch new file mode 100644 index 00000000..362a646d --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4161-drm-amdgpu-powerplay-add-support-for-BACO-on-CI.patch @@ -0,0 +1,309 @@ +From a835596fe3e90f66093459a5708c26b690d59e8d Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 15 Feb 2019 17:38:44 -0500 +Subject: [PATCH 4161/4736] drm/amdgpu/powerplay: add support for BACO on CI +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This adds BACO support for CI asics. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 3 +- + drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c | 227 ++++++++++++++++++ + drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h | 32 +++ + 3 files changed, 261 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c + create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +index bfd22d8b0aea..5ad5893bdae1 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +@@ -36,7 +36,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o \ + pp_overdriver.o smu_helper.o \ + vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \ + vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \ +- vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o ++ vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o \ ++ ci_baco.o + + AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c +new file mode 100644 +index 000000000000..f1a8c9cc0d1f +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c +@@ -0,0 +1,227 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#include "amdgpu.h" ++#include "ci_baco.h" ++ ++#include "gmc/gmc_7_1_d.h" ++#include "gmc/gmc_7_1_sh_mask.h" ++ ++#include "bif/bif_4_1_d.h" ++#include "bif/bif_4_1_sh_mask.h" ++ ++#include "dce/dce_8_0_d.h" ++#include "dce/dce_8_0_sh_mask.h" ++ ++#include "smu/smu_7_0_1_d.h" ++#include "smu/smu_7_0_1_sh_mask.h" ++ ++#include "gca/gfx_7_2_d.h" ++#include "gca/gfx_7_2_sh_mask.h" ++ ++static const struct baco_cmd_entry gpio_tbl[] = ++{ ++ { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff }, ++ { CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 }, ++ { CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff }, ++ { CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 }, ++ { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 } ++}; ++ ++static const struct baco_cmd_entry enable_fb_req_rej_tbl[] = ++{ ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 }, ++ { CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 } ++}; ++ ++static const struct baco_cmd_entry use_bclk_tbl[] = ++{ ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS }, ++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS }, ++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }, ++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK, MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT, 0, 0x0 } ++}; ++ ++static const struct baco_cmd_entry turn_off_plls_tbl[] = ++{ ++ { CMD_READMODIFYWRITE, mmDISPPLL_BG_CNTL, DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK, DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_DC }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_DC__OSC_EN_MASK, CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK, CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_RESET_MASK, PLL_CNTL__PLL_RESET__SHIFT, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_POWER_DOWN_MASK, PLL_CNTL__PLL_POWER_DOWN__SHIFT, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_BYPASS_CAL_MASK, PLL_CNTL__PLL_BYPASS_CAL__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK, CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x2000000, 0x19, 0, 0x1 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x8000000, 0x1b, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT, 0, 0x1 }, ++ { CMD_WRITE, mmMPLL_CONTROL, 0, 0, 0, 0x00000006 }, ++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D0, 0, 0, 0, 0x00007740 }, ++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D1, 0, 0, 0, 0x00007740 }, ++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D0, 0, 0, 0, 0x00007740 }, ++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D1, 0, 0, 0, 0x00007740 }, ++ { CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PU_MASK, MC_SEQ_CNTL_2__DRST_PU__SHIFT, 0, 0x0 }, ++ { CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PD_MASK, MC_SEQ_CNTL_2__DRST_PD__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK, MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT, 0, 0x2 }, ++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x2 }, ++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x2 } ++}; ++ ++static const struct baco_cmd_entry enter_baco_tbl[] = ++{ ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 } ++}; ++ ++#define BACO_CNTL__PWRGOOD_MASK BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK ++ ++static const struct baco_cmd_entry exit_baco_tbl[] = ++{ ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 }, ++ { CMD_DELAY_MS, 0, 0, 0, 20, 0 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x20 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x10 }, ++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 }, ++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 } ++}; ++ ++static const struct baco_cmd_entry clean_baco_tbl[] = ++{ ++ { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 }, ++ { CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 } ++}; ++ ++int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); ++ uint32_t reg; ++ ++ *cap = false; ++ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) ++ return 0; ++ ++ reg = RREG32(mmCC_BIF_BX_FUSESTRAP0); ++ ++ if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK) ++ *cap = true; ++ ++ return 0; ++} ++ ++int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); ++ uint32_t reg; ++ ++ reg = RREG32(mmBACO_CNTL); ++ ++ if (reg & BACO_CNTL__BACO_MODE_MASK) ++ /* gfx has already entered BACO state */ ++ *state = BACO_STATE_IN; ++ else ++ *state = BACO_STATE_OUT; ++ return 0; ++} ++ ++int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) ++{ ++ enum BACO_STATE cur_state; ++ ++ ci_baco_get_state(hwmgr, &cur_state); ++ ++ if (cur_state == state) ++ /* aisc already in the target state */ ++ return 0; ++ ++ if (state == BACO_STATE_IN) { ++ baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl)); ++ baco_program_registers(hwmgr, enable_fb_req_rej_tbl, ++ ARRAY_SIZE(enable_fb_req_rej_tbl)); ++ baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl)); ++ baco_program_registers(hwmgr, turn_off_plls_tbl, ++ ARRAY_SIZE(turn_off_plls_tbl)); ++ if (baco_program_registers(hwmgr, enter_baco_tbl, ++ ARRAY_SIZE(enter_baco_tbl))) ++ return 0; ++ ++ } else if (state == BACO_STATE_OUT) { ++ /* HW requires at least 20ms between regulator off and on */ ++ msleep(20); ++ /* Execute Hardware BACO exit sequence */ ++ if (baco_program_registers(hwmgr, exit_baco_tbl, ++ ARRAY_SIZE(exit_baco_tbl))) { ++ if (baco_program_registers(hwmgr, clean_baco_tbl, ++ ARRAY_SIZE(clean_baco_tbl))) ++ return 0; ++ } ++ } ++ ++ return -EINVAL; ++} +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h +new file mode 100644 +index 000000000000..c9bedb51cb25 +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h +@@ -0,0 +1,32 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#ifndef __CI_BACO_H__ ++#define __CI_BACO_H__ ++#include "hwmgr.h" ++#include "common_baco.h" ++ ++extern int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap); ++extern int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); ++extern int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); ++ ++#endif +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4162-drm-amdgpu-powerplay-split-out-common-smu7-BACO-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4162-drm-amdgpu-powerplay-split-out-common-smu7-BACO-code.patch new file mode 100644 index 00000000..286aaa53 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4162-drm-amdgpu-powerplay-split-out-common-smu7-BACO-code.patch @@ -0,0 +1,446 @@ +From 398407598af75bd60cc2a23431c992283eeff37e Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 15 Feb 2019 17:39:33 -0500 +Subject: [PATCH 4162/4736] drm/amdgpu/powerplay: split out common smu7 BACO + code +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Several of the BACO functions are common across smu7-based +asics. Split the common code out. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +- + drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c | 34 +------ + drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h | 5 +- + .../gpu/drm/amd/powerplay/hwmgr/fiji_baco.c | 34 +------ + .../gpu/drm/amd/powerplay/hwmgr/fiji_baco.h | 5 +- + .../drm/amd/powerplay/hwmgr/polaris_baco.c | 34 +------ + .../drm/amd/powerplay/hwmgr/polaris_baco.h | 5 +- + .../gpu/drm/amd/powerplay/hwmgr/smu7_baco.c | 91 +++++++++++++++++++ + .../gpu/drm/amd/powerplay/hwmgr/smu7_baco.h | 32 +++++++ + .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.c | 34 +------ + .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.h | 5 +- + 11 files changed, 132 insertions(+), 149 deletions(-) + create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c + create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +index 5ad5893bdae1..2773966ae434 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +@@ -37,7 +37,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \ + vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \ + vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \ + vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o \ +- ci_baco.o ++ ci_baco.o smu7_baco.o + + AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c +index f1a8c9cc0d1f..3be40114e63d 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c +@@ -158,43 +158,11 @@ static const struct baco_cmd_entry clean_baco_tbl[] = + { CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 } + }; + +-int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) +-{ +- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); +- uint32_t reg; +- +- *cap = false; +- if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) +- return 0; +- +- reg = RREG32(mmCC_BIF_BX_FUSESTRAP0); +- +- if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK) +- *cap = true; +- +- return 0; +-} +- +-int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) +-{ +- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); +- uint32_t reg; +- +- reg = RREG32(mmBACO_CNTL); +- +- if (reg & BACO_CNTL__BACO_MODE_MASK) +- /* gfx has already entered BACO state */ +- *state = BACO_STATE_IN; +- else +- *state = BACO_STATE_OUT; +- return 0; +-} +- + int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) + { + enum BACO_STATE cur_state; + +- ci_baco_get_state(hwmgr, &cur_state); ++ smu7_baco_get_state(hwmgr, &cur_state); + + if (cur_state == state) + /* aisc already in the target state */ +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h +index c9bedb51cb25..17041f187020 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h +@@ -22,11 +22,8 @@ + */ + #ifndef __CI_BACO_H__ + #define __CI_BACO_H__ +-#include "hwmgr.h" +-#include "common_baco.h" ++#include "smu7_baco.h" + +-extern int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap); +-extern int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); + extern int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); + + #endif +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c +index ad01919ccb27..c0368f2dfb21 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c +@@ -158,43 +158,11 @@ static const struct baco_cmd_entry clean_baco_tbl[] = + { CMD_WRITE, mmBIOS_SCRATCH_15, 0, 0, 0, 0 } + }; + +-int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) +-{ +- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); +- uint32_t reg; +- +- *cap = false; +- if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) +- return 0; +- +- reg = RREG32(mmCC_BIF_BX_FUSESTRAP0); +- +- if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK) +- *cap = true; +- +- return 0; +-} +- +-int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) +-{ +- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); +- uint32_t reg; +- +- reg = RREG32(mmBACO_CNTL); +- +- if (reg & BACO_CNTL__BACO_MODE_MASK) +- /* gfx has already entered BACO state */ +- *state = BACO_STATE_IN; +- else +- *state = BACO_STATE_OUT; +- return 0; +-} +- + int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) + { + enum BACO_STATE cur_state; + +- fiji_baco_get_state(hwmgr, &cur_state); ++ smu7_baco_get_state(hwmgr, &cur_state); + + if (cur_state == state) + /* aisc already in the target state */ +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h +index 2f7c8388667e..47f402900bdb 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h +@@ -22,11 +22,8 @@ + */ + #ifndef __FIJI_BACO_H__ + #define __FIJI_BACO_H__ +-#include "hwmgr.h" +-#include "common_baco.h" ++#include "smu7_baco.h" + +-extern int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap); +-extern int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); + extern int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); + + #endif +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c +index a9abe53df475..8f8e296f2fe9 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c +@@ -178,43 +178,11 @@ static const struct baco_cmd_entry turn_off_plls_tbl_vg[] = + { CMD_DELAY_US, 0, 0, 0, 5, 0x0 } + }; + +-int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) +-{ +- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); +- uint32_t reg; +- +- *cap = false; +- if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) +- return 0; +- +- reg = RREG32(mmCC_BIF_BX_FUSESTRAP0); +- +- if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK) +- *cap = true; +- +- return 0; +-} +- +-int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) +-{ +- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); +- uint32_t reg; +- +- reg = RREG32(mmBACO_CNTL); +- +- if (reg & BACO_CNTL__BACO_MODE_MASK) +- /* gfx has already entered BACO state */ +- *state = BACO_STATE_IN; +- else +- *state = BACO_STATE_OUT; +- return 0; +-} +- + int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) + { + enum BACO_STATE cur_state; + +- polaris_baco_get_state(hwmgr, &cur_state); ++ smu7_baco_get_state(hwmgr, &cur_state); + + if (cur_state == state) + /* aisc already in the target state */ +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h +index e48bfb1c5c6a..87a5fa0a157a 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h +@@ -22,11 +22,8 @@ + */ + #ifndef __POLARIS_BACO_H__ + #define __POLARIS_BACO_H__ +-#include "hwmgr.h" +-#include "common_baco.h" ++#include "smu7_baco.h" + +-extern int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap); +-extern int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); + extern int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); + + #endif +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c +new file mode 100644 +index 000000000000..044cda005aed +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c +@@ -0,0 +1,91 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#include "amdgpu.h" ++#include "smu7_baco.h" ++#include "tonga_baco.h" ++#include "fiji_baco.h" ++#include "polaris_baco.h" ++#include "ci_baco.h" ++ ++#include "bif/bif_5_0_d.h" ++#include "bif/bif_5_0_sh_mask.h" ++ ++#include "smu/smu_7_1_2_d.h" ++#include "smu/smu_7_1_2_sh_mask.h" ++ ++int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); ++ uint32_t reg; ++ ++ *cap = false; ++ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) ++ return 0; ++ ++ reg = RREG32(mmCC_BIF_BX_FUSESTRAP0); ++ ++ if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK) ++ *cap = true; ++ ++ return 0; ++} ++ ++int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); ++ uint32_t reg; ++ ++ reg = RREG32(mmBACO_CNTL); ++ ++ if (reg & BACO_CNTL__BACO_MODE_MASK) ++ /* gfx has already entered BACO state */ ++ *state = BACO_STATE_IN; ++ else ++ *state = BACO_STATE_OUT; ++ return 0; ++} ++ ++int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); ++ ++ switch (adev->asic_type) { ++ case CHIP_TOPAZ: ++ case CHIP_TONGA: ++ return tonga_baco_set_state(hwmgr, state); ++ case CHIP_FIJI: ++ return fiji_baco_set_state(hwmgr, state); ++ case CHIP_POLARIS10: ++ case CHIP_POLARIS11: ++ case CHIP_POLARIS12: ++ case CHIP_VEGAM: ++ return polaris_baco_set_state(hwmgr, state); ++#ifdef CONFIG_DRM_AMDGPU_CIK ++ case CHIP_BONAIRE: ++ case CHIP_HAWAII: ++ return ci_baco_set_state(hwmgr, state); ++#endif ++ default: ++ return -EINVAL; ++ } ++} +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h +new file mode 100644 +index 000000000000..be0d98abb536 +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h +@@ -0,0 +1,32 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#ifndef __SMU7_BACO_H__ ++#define __SMU7_BACO_H__ ++#include "hwmgr.h" ++#include "common_baco.h" ++ ++extern int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap); ++extern int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); ++extern int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); ++ ++#endif +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c +index 84b7217b7bda..ea743bea8e29 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c +@@ -182,43 +182,11 @@ static const struct baco_cmd_entry clean_baco_tbl_iceland[] = + { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 } + }; + +-int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) +-{ +- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); +- uint32_t reg; +- +- *cap = false; +- if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) +- return 0; +- +- reg = RREG32(mmCC_BIF_BX_FUSESTRAP0); +- +- if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK) +- *cap = true; +- +- return 0; +-} +- +-int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) +-{ +- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); +- uint32_t reg; +- +- reg = RREG32(mmBACO_CNTL); +- +- if (reg & BACO_CNTL__BACO_MODE_MASK) +- /* gfx has already entered BACO state */ +- *state = BACO_STATE_IN; +- else +- *state = BACO_STATE_OUT; +- return 0; +-} +- + int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) + { + enum BACO_STATE cur_state; + +- tonga_baco_get_state(hwmgr, &cur_state); ++ smu7_baco_get_state(hwmgr, &cur_state); + + if (cur_state == state) + /* aisc already in the target state */ +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h +index 21301b043255..5dc16cc8a295 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h +@@ -22,11 +22,8 @@ + */ + #ifndef __TONGA_BACO_H__ + #define __TONGA_BACO_H__ +-#include "hwmgr.h" +-#include "common_baco.h" ++#include "smu7_baco.h" + +-extern int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap); +-extern int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); + extern int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); + + #endif +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4163-drm-amdgpu-powerplay-wire-up-BACO-to-powerplay-API-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4163-drm-amdgpu-powerplay-wire-up-BACO-to-powerplay-API-f.patch new file mode 100644 index 00000000..8bcd8982 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4163-drm-amdgpu-powerplay-wire-up-BACO-to-powerplay-API-f.patch @@ -0,0 +1,43 @@ +From 822464648a32206c3ec2e1992a6d190a14234c85 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 15 Feb 2019 18:17:24 -0500 +Subject: [PATCH 4163/4736] drm/amdgpu/powerplay: wire up BACO to powerplay API + for smu7 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Wire up the powerplay callbacks for for BACO for smu7 devices. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index 897fd494fe33..80bfdf178892 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -47,6 +47,7 @@ + #include "smu7_clockpowergating.h" + #include "processpptables.h" + #include "pp_thermal.h" ++#include "smu7_baco.h" + + #include "ivsrcid/ivsrcid_vislands30.h" + +@@ -5142,6 +5143,9 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = { + .get_power_profile_mode = smu7_get_power_profile_mode, + .set_power_profile_mode = smu7_set_power_profile_mode, + .get_performance_level = smu7_get_performance_level, ++ .get_asic_baco_capability = smu7_baco_get_capability, ++ .get_asic_baco_state = smu7_baco_get_state, ++ .set_asic_baco_state = smu7_baco_set_state, + .power_off_asic = smu7_power_off_asic, + }; + +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4164-drm-amdgpu-enable-BACO-reset-for-SMU7-based-dGPUs-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4164-drm-amdgpu-enable-BACO-reset-for-SMU7-based-dGPUs-v2.patch new file mode 100644 index 00000000..15c281cd --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4164-drm-amdgpu-enable-BACO-reset-for-SMU7-based-dGPUs-v2.patch @@ -0,0 +1,230 @@ +From 97b0504af3ca00ce13f45fbdfb17767ee4abc4c9 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Mon, 11 Mar 2019 18:05:12 -0500 +Subject: [PATCH 4164/4736] drm/amdgpu: enable BACO reset for SMU7 based dGPUs + (v2) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Use BACO to reset the GPU if supported on SMU7 based +dGPUs. + +v2: don't use baco on CI parts + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/cik.c | 48 ++++++++++++++++-- + drivers/gpu/drm/amd/amdgpu/cik.h | 3 ++ + drivers/gpu/drm/amd/amdgpu/vi.c | 84 ++++++++++++++++++++++++++++++-- + drivers/gpu/drm/amd/amdgpu/vi.h | 3 ++ + 4 files changed, 128 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c +index 7b63d7a8298a..e3c524c8926a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/cik.c ++++ b/drivers/gpu/drm/amd/amdgpu/cik.c +@@ -1269,15 +1269,15 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev) + } + + /** +- * cik_asic_reset - soft reset GPU ++ * cik_asic_pci_config_reset - soft reset GPU + * + * @adev: amdgpu_device pointer + * +- * Look up which blocks are hung and attempt +- * to reset them. ++ * Use PCI Config method to reset the GPU. ++ * + * Returns 0 for success. + */ +-static int cik_asic_reset(struct amdgpu_device *adev) ++static int cik_asic_pci_config_reset(struct amdgpu_device *adev) + { + int r; + +@@ -1293,7 +1293,45 @@ static int cik_asic_reset(struct amdgpu_device *adev) + static enum amd_reset_method + cik_asic_reset_method(struct amdgpu_device *adev) + { +- return AMD_RESET_METHOD_LEGACY; ++ bool baco_reset; ++ ++ switch (adev->asic_type) { ++ case CHIP_BONAIRE: ++ case CHIP_HAWAII: ++ /* disable baco reset until it works */ ++ /* smu7_asic_get_baco_capability(adev, &baco_reset); */ ++ baco_reset = false; ++ break; ++ default: ++ baco_reset = false; ++ break; ++ } ++ ++ if (baco_reset) ++ return AMD_RESET_METHOD_BACO; ++ else ++ return AMD_RESET_METHOD_LEGACY; ++} ++ ++/** ++ * cik_asic_reset - soft reset GPU ++ * ++ * @adev: amdgpu_device pointer ++ * ++ * Look up which blocks are hung and attempt ++ * to reset them. ++ * Returns 0 for success. ++ */ ++static int cik_asic_reset(struct amdgpu_device *adev) ++{ ++ int r; ++ ++ if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) ++ r = smu7_asic_baco_reset(adev); ++ else ++ r = cik_asic_pci_config_reset(adev); ++ ++ return r; + } + + static u32 cik_get_config_memsize(struct amdgpu_device *adev) +diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h +index 54c625a2e570..9870bf27870e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/cik.h ++++ b/drivers/gpu/drm/amd/amdgpu/cik.h +@@ -31,4 +31,7 @@ void cik_srbm_select(struct amdgpu_device *adev, + int cik_set_ip_blocks(struct amdgpu_device *adev); + + void legacy_doorbell_index_init(struct amdgpu_device *adev); ++int smu7_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap); ++int smu7_asic_baco_reset(struct amdgpu_device *adev); ++ + #endif +diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c +index 56c882b3ea3c..34a466e785cb 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vi.c ++++ b/drivers/gpu/drm/amd/amdgpu/vi.c +@@ -687,16 +687,50 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev) + return -EINVAL; + } + ++int smu7_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap) ++{ ++ void *pp_handle = adev->powerplay.pp_handle; ++ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; ++ ++ if (!pp_funcs || !pp_funcs->get_asic_baco_capability) { ++ *cap = false; ++ return -ENOENT; ++ } ++ ++ return pp_funcs->get_asic_baco_capability(pp_handle, cap); ++} ++ ++int smu7_asic_baco_reset(struct amdgpu_device *adev) ++{ ++ void *pp_handle = adev->powerplay.pp_handle; ++ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; ++ ++ if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state) ++ return -ENOENT; ++ ++ /* enter BACO state */ ++ if (pp_funcs->set_asic_baco_state(pp_handle, 1)) ++ return -EIO; ++ ++ /* exit BACO state */ ++ if (pp_funcs->set_asic_baco_state(pp_handle, 0)) ++ return -EIO; ++ ++ dev_info(adev->dev, "GPU BACO reset\n"); ++ ++ return 0; ++} ++ + /** +- * vi_asic_reset - soft reset GPU ++ * vi_asic_pci_config_reset - soft reset GPU + * + * @adev: amdgpu_device pointer + * +- * Look up which blocks are hung and attempt +- * to reset them. ++ * Use PCI Config method to reset the GPU. ++ * + * Returns 0 for success. + */ +-static int vi_asic_reset(struct amdgpu_device *adev) ++static int vi_asic_pci_config_reset(struct amdgpu_device *adev) + { + int r; + +@@ -712,7 +746,47 @@ static int vi_asic_reset(struct amdgpu_device *adev) + static enum amd_reset_method + vi_asic_reset_method(struct amdgpu_device *adev) + { +- return AMD_RESET_METHOD_LEGACY; ++ bool baco_reset; ++ ++ switch (adev->asic_type) { ++ case CHIP_FIJI: ++ case CHIP_TONGA: ++ case CHIP_POLARIS10: ++ case CHIP_POLARIS11: ++ case CHIP_POLARIS12: ++ case CHIP_TOPAZ: ++ smu7_asic_get_baco_capability(adev, &baco_reset); ++ break; ++ default: ++ baco_reset = false; ++ break; ++ } ++ ++ if (baco_reset) ++ return AMD_RESET_METHOD_BACO; ++ else ++ return AMD_RESET_METHOD_LEGACY; ++} ++ ++/** ++ * vi_asic_reset - soft reset GPU ++ * ++ * @adev: amdgpu_device pointer ++ * ++ * Look up which blocks are hung and attempt ++ * to reset them. ++ * Returns 0 for success. ++ */ ++static int vi_asic_reset(struct amdgpu_device *adev) ++{ ++ int r; ++ ++ if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) ++ r = smu7_asic_baco_reset(adev); ++ else ++ r = vi_asic_pci_config_reset(adev); ++ ++ return r; + } + + static u32 vi_get_config_memsize(struct amdgpu_device *adev) +diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h +index 8de0772f986c..40d4174913a4 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vi.h ++++ b/drivers/gpu/drm/amd/amdgpu/vi.h +@@ -31,4 +31,7 @@ void vi_srbm_select(struct amdgpu_device *adev, + int vi_set_ip_blocks(struct amdgpu_device *adev); + + void legacy_doorbell_index_init(struct amdgpu_device *adev); ++int smu7_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap); ++int smu7_asic_baco_reset(struct amdgpu_device *adev); ++ + #endif +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4165-drm-amdgpu-simplify-ATPX-detection.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4165-drm-amdgpu-simplify-ATPX-detection.patch new file mode 100644 index 00000000..c292e9ab --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4165-drm-amdgpu-simplify-ATPX-detection.patch @@ -0,0 +1,41 @@ +From e1ba8d889f2a06ace9596ac989cd48618484bf9b Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Wed, 9 Oct 2019 14:39:37 -0500 +Subject: [PATCH 4165/4736] drm/amdgpu: simplify ATPX detection + +Use the base class rather than the specific class and drop +the second loop. + +Change-Id: Ic4d4dba633a655531c5bd6ec99f903a0805e7455 +Reviewed-by: Evan Quan <evan.quan@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 12 +----------- + 1 file changed, 1 insertion(+), 11 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c +index 354c8b6106dc..7bebe128dd7b 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c +@@ -614,17 +614,7 @@ static bool amdgpu_atpx_detect(void) + bool d3_supported = false; + struct pci_dev *parent_pdev; + +- while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { +- vga_count++; +- +- has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true); +- +- parent_pdev = pci_upstream_bridge(pdev); +- d3_supported |= parent_pdev && parent_pdev->bridge_d3; +- amdgpu_atpx_get_quirks(pdev); +- } +- +- while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { ++ while ((pdev = pci_get_class(PCI_BASE_CLASS_DISPLAY << 16, pdev)) != NULL) { + vga_count++; + + has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true); +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4166-drm-amd-powerplay-bug-fix-for-memory-clock-request-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4166-drm-amd-powerplay-bug-fix-for-memory-clock-request-f.patch new file mode 100644 index 00000000..fe9f0230 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4166-drm-amd-powerplay-bug-fix-for-memory-clock-request-f.patch @@ -0,0 +1,34 @@ +From fea8cac04d037e0669ac0ac5fa54c1222cff8769 Mon Sep 17 00:00:00 2001 +From: Kenneth Feng <kenneth.feng@amd.com> +Date: Wed, 16 Oct 2019 16:20:38 +0800 +Subject: [PATCH 4166/4736] drm/amd/powerplay: bug fix for memory clock request + from display + +In some cases, display fixes memory clock frequency to a high value +rather than the natural memory clock switching. +When we comes back from s3 resume, the request from display is not reset, +this causes the bug which makes the memory clock goes into a low value. +Then due to the insuffcient memory clock, the screen flicks. + +Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> +Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> +--- + drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +index d0a25dd8fcfc..fb5a55091292 100644 +--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +@@ -1354,6 +1354,8 @@ static int smu_resume(void *handle) + if (smu->is_apu) + smu_set_gfx_cgpg(&adev->smu, true); + ++ smu->disable_uclk_switch = 0; ++ + mutex_unlock(&smu->mutex); + + pr_info("SMU is resumed successfully!\n"); +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4167-drm-amdgpu-No-need-to-check-gfxoff-status-after-enab.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4167-drm-amdgpu-No-need-to-check-gfxoff-status-after-enab.patch new file mode 100644 index 00000000..57d925e9 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4167-drm-amdgpu-No-need-to-check-gfxoff-status-after-enab.patch @@ -0,0 +1,43 @@ +From d37f0200c8aa88982cb2358aac4684195d407585 Mon Sep 17 00:00:00 2001 +From: chen gong <curry.gong@amd.com> +Date: Wed, 16 Oct 2019 18:04:02 +0800 +Subject: [PATCH 4167/4736] drm/amdgpu: No need to check gfxoff status after + enable gfxoff feature + +smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff) Just turn on a switch. + +As to when GPU get into "GFXoff" will be up to drawing load. + +So we can not sure which state GPU should be in after enable gfxoff +feature. + +Signed-off-by: chen gong <curry.gong@amd.com> +Acked-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Kevin Wang <kevin1.wang@amd.com> +--- + drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 9 --------- + 1 file changed, 9 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c +index c9691d0fb523..cac4269cf1d1 100644 +--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c ++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c +@@ -244,15 +244,6 @@ static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable) + if (enable) { + ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff); + +- /* confirm gfx is back to "off" state, timeout is 5 seconds */ +- while (!(smu_v12_0_get_gfxoff_status(smu) == 0)) { +- msleep(10); +- timeout--; +- if (timeout == 0) { +- DRM_ERROR("enable gfxoff timeout and failed!\n"); +- break; +- } +- } + } else { + ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff); + +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch new file mode 100644 index 00000000..f41a5fc7 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch @@ -0,0 +1,546 @@ +From 40d01f785cf532f60d467345b0f371059017537b Mon Sep 17 00:00:00 2001 +From: abdoulaye berthe <abdoulaye.berthe@amd.com> +Date: Tue, 13 Aug 2019 09:24:10 -0400 +Subject: [PATCH 4168/4736] drm/amd/display: update register field access + mechanism + +1-add timeout length and multiplier fields to aux_control1 register +2-update access mechanism from macro constructed name to uint32_t +defined addresses. +3-define registers and field per asic family + +Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Reviewed-by: Roman Li <Roman.Li@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 11 +- + drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 175 +++++++++++++++++- + .../amd/display/dc/dce100/dce100_resource.c | 12 +- + .../amd/display/dc/dce110/dce110_resource.c | 12 +- + .../amd/display/dc/dce112/dce112_resource.c | 12 +- + .../amd/display/dc/dce120/dce120_resource.c | 12 +- + .../drm/amd/display/dc/dce80/dce80_resource.c | 12 +- + .../drm/amd/display/dc/dcn10/dcn10_resource.c | 12 +- + .../drm/amd/display/dc/dcn20/dcn20_resource.c | 13 +- + .../drm/amd/display/dc/dcn21/dcn21_resource.c | 12 +- + 10 files changed, 271 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +index 16960ef29132..574447185f4a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +@@ -39,6 +39,10 @@ + + #include "reg_helper.h" + ++#undef FN ++#define FN(reg_name, field_name) \ ++ aux110->shift->field_name, aux110->mask->field_name ++ + #define FROM_AUX_ENGINE(ptr) \ + container_of((ptr), struct aux_engine_dce110, base) + +@@ -411,11 +415,14 @@ void dce110_engine_destroy(struct dce_aux **engine) + *engine = NULL; + + } ++ + struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110, + struct dc_context *ctx, + uint32_t inst, + uint32_t timeout_period, +- const struct dce110_aux_registers *regs) ++ const struct dce110_aux_registers *regs, ++ const struct dce110_aux_registers_mask *mask, ++ const struct dce110_aux_registers_shift *shift) + { + aux_engine110->base.ddc = NULL; + aux_engine110->base.ctx = ctx; +@@ -425,6 +432,8 @@ struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine + aux_engine110->timeout_period = timeout_period; + aux_engine110->regs = regs; + ++ aux_engine110->mask = mask; ++ aux_engine110->shift = shift; + return &aux_engine110->base; + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +index ed7fec8fe253..717378502e9d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +@@ -29,6 +29,7 @@ + #include "i2caux_interface.h" + #include "inc/hw/aux_engine.h" + ++ + #ifdef CONFIG_DRM_AMD_DC_DCN2_0 + #define AUX_COMMON_REG_LIST0(id)\ + SRI(AUX_CONTROL, DP_AUX, id), \ +@@ -36,6 +37,7 @@ + SRI(AUX_SW_DATA, DP_AUX, id), \ + SRI(AUX_SW_CONTROL, DP_AUX, id), \ + SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \ ++ SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \ + SRI(AUX_SW_STATUS, DP_AUX, id) + #endif + +@@ -55,6 +57,7 @@ struct dce110_aux_registers { + uint32_t AUX_SW_DATA; + uint32_t AUX_SW_CONTROL; + uint32_t AUX_INTERRUPT_CONTROL; ++ uint32_t AUX_DPHY_RX_CONTROL1; + uint32_t AUX_SW_STATUS; + uint32_t AUXN_IMPCAL; + uint32_t AUXP_IMPCAL; +@@ -62,6 +65,156 @@ struct dce110_aux_registers { + uint32_t AUX_RESET_MASK; + }; + ++#define DCE_AUX_REG_FIELD_LIST(type)\ ++ type AUX_EN;\ ++ type AUX_RESET;\ ++ type AUX_RESET_DONE;\ ++ type AUX_REG_RW_CNTL_STATUS;\ ++ type AUX_SW_USE_AUX_REG_REQ;\ ++ type AUX_SW_DONE_USING_AUX_REG;\ ++ type AUX_SW_AUTOINCREMENT_DISABLE;\ ++ type AUX_SW_DATA_RW;\ ++ type AUX_SW_INDEX;\ ++ type AUX_SW_GO;\ ++ type AUX_SW_DATA;\ ++ type AUX_SW_REPLY_BYTE_COUNT;\ ++ type AUX_SW_DONE;\ ++ type AUX_SW_DONE_ACK;\ ++ type AUXN_IMPCAL_ENABLE;\ ++ type AUXP_IMPCAL_ENABLE;\ ++ type AUXN_IMPCAL_OVERRIDE_ENABLE;\ ++ type AUXP_IMPCAL_OVERRIDE_ENABLE;\ ++ type AUX_RX_TIMEOUT_LEN;\ ++ type AUX_RX_TIMEOUT_LEN_MUL;\ ++ type AUXN_CALOUT_ERROR_AK;\ ++ type AUXP_CALOUT_ERROR_AK;\ ++ type AUX_SW_START_DELAY;\ ++ type AUX_SW_WR_BYTES ++ ++#define DCE10_AUX_MASK_SH_LIST(mask_sh)\ ++ AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\ ++ AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\ ++ AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\ ++ AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\ ++ AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\ ++ AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\ ++ AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\ ++ AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\ ++ AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\ ++ AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh) ++ ++#define DCE_AUX_MASK_SH_LIST(mask_sh)\ ++ AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\ ++ AUX_SF(AUX_CONTROL, AUX_RESET, mask_sh),\ ++ AUX_SF(AUX_CONTROL, AUX_RESET_DONE, mask_sh),\ ++ AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\ ++ AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\ ++ AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\ ++ AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\ ++ AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\ ++ AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\ ++ AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\ ++ AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\ ++ AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\ ++ AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh) ++ ++#define DCE12_AUX_MASK_SH_LIST(mask_sh)\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh) ++ ++/* DCN10 MASK */ ++#define DCN10_AUX_MASK_SH_LIST(mask_sh)\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\ ++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\ ++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh) ++ ++/* for all other DCN */ ++#define DCN_AUX_MASK_SH_LIST(mask_sh)\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\ ++ AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh) ++ ++#define AUX_SF(reg_name, field_name, post_fix)\ ++ .field_name = reg_name ## __ ## field_name ## post_fix ++ + enum { /* This is the timeout as defined in DP 1.2a, + * 2.3.4 "Detailed uPacket TX AUX CH State Description". + */ +@@ -97,17 +250,31 @@ struct dce_aux { + uint32_t max_defer_write_retry; + + bool acquire_reset; ++ const struct dce_aux_funcs *funcs; ++}; ++ ++struct dce110_aux_registers_mask { ++ DCE_AUX_REG_FIELD_LIST(uint32_t); + }; + ++struct dce110_aux_registers_shift { ++ DCE_AUX_REG_FIELD_LIST(uint8_t); ++}; ++ ++ + struct aux_engine_dce110 { + struct dce_aux base; + const struct dce110_aux_registers *regs; ++ const struct dce110_aux_registers_mask *mask; ++ const struct dce110_aux_registers_shift *shift; + struct { + uint32_t aux_control; + uint32_t aux_arb_control; + uint32_t aux_sw_data; + uint32_t aux_sw_control; + uint32_t aux_interrupt_control; ++ uint32_t aux_dphy_rx_control1; ++ uint32_t aux_dphy_rx_control0; + uint32_t aux_sw_status; + } addr; + uint32_t timeout_period; +@@ -120,12 +287,14 @@ struct aux_engine_dce110_init_data { + const struct dce110_aux_registers *regs; + }; + +-struct dce_aux *dce110_aux_engine_construct( +- struct aux_engine_dce110 *aux_engine110, ++struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110, + struct dc_context *ctx, + uint32_t inst, + uint32_t timeout_period, +- const struct dce110_aux_registers *regs); ++ const struct dce110_aux_registers *regs, ++ ++ const struct dce110_aux_registers_mask *mask, ++ const struct dce110_aux_registers_shift *shift); + + void dce110_engine_destroy(struct dce_aux **engine); + +diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +index 3614e516489f..fe1538ab76ba 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +@@ -534,6 +534,14 @@ static const struct dce_mem_input_mask mi_masks = { + .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCE10_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCE10_AUX_MASK_SH_LIST(_MASK) ++}; ++ + static struct mem_input *dce100_mem_input_create( + struct dc_context *ctx, + uint32_t inst) +@@ -643,7 +651,9 @@ struct dce_aux *dce100_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +index a487b75d23b6..06ecdf044ddc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +@@ -273,6 +273,14 @@ static const struct dce_stream_encoder_mask se_mask = { + SE_COMMON_MASK_SH_LIST_DCE110(_MASK) + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCE_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCE_AUX_MASK_SH_LIST(_MASK) ++}; ++ + #define opp_regs(id)\ + [id] = {\ + OPP_DCE_110_REG_LIST(id),\ +@@ -690,7 +698,9 @@ struct dce_aux *dce110_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +index ec67db9c86e8..8dc75f71240d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +@@ -170,6 +170,14 @@ static const struct dce_abm_mask abm_mask = { + ABM_MASK_SH_LIST_DCE110(_MASK) + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCE_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCE_AUX_MASK_SH_LIST(_MASK) ++}; ++ + #define ipp_regs(id)\ + [id] = {\ + IPP_DCE110_REG_LIST_DCE_BASE(id)\ +@@ -663,7 +671,9 @@ struct dce_aux *dce112_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +index b5b9a74086a0..3aac593f9b2e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +@@ -291,6 +291,14 @@ static const struct dce_stream_encoder_mask se_mask = { + SE_COMMON_MASK_SH_LIST_DCE120(_MASK) + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCE12_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCE12_AUX_MASK_SH_LIST(_MASK) ++}; ++ + #define opp_regs(id)\ + [id] = {\ + OPP_DCE_120_REG_LIST(id),\ +@@ -433,7 +441,9 @@ struct dce_aux *dce120_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +index 8e2aa0abf87c..934d8deb95fc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +@@ -286,6 +286,14 @@ static const struct dce_opp_mask opp_mask = { + OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCE10_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCE10_AUX_MASK_SH_LIST(_MASK) ++}; ++ + #define aux_engine_regs(id)\ + [id] = {\ + AUX_COMMON_REG_LIST(id), \ +@@ -520,7 +528,9 @@ struct dce_aux *dce80_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +index 4522097e8a26..82dbc00afe54 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +@@ -317,6 +317,14 @@ static const struct dcn10_link_enc_mask le_mask = { + LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCN10_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCN10_AUX_MASK_SH_LIST(_MASK) ++}; ++ + #define ipp_regs(id)\ + [id] = {\ + IPP_REG_LIST_DCN10(id),\ +@@ -662,7 +670,9 @@ struct dce_aux *dcn10_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index 968dc5fe4f1b..f2db1fa2eba9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -732,6 +732,15 @@ static const struct dcn20_vmid_mask vmid_masks = { + DCN20_VMID_MASK_SH_LIST(_MASK) + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCN_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCN_AUX_MASK_SH_LIST(_MASK) ++}; ++ ++ + #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + #define dsc_regsDCN20(id)\ + [id] = {\ +@@ -949,7 +958,9 @@ struct dce_aux *dcn20_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +index 2cc93e2e6ec0..dc5d28d002df 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +@@ -628,6 +628,14 @@ static const struct dcn10_stream_enc_registers stream_enc_regs[] = { + stream_enc_regs(4), + }; + ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCN_AUX_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCN_AUX_MASK_SH_LIST(_MASK) ++}; ++ + static const struct dcn10_stream_encoder_shift se_shift = { + SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) + }; +@@ -685,7 +693,9 @@ static struct dce_aux *dcn21_aux_engine_create( + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, +- &aux_engine_regs[inst]); ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift); + + return &aux_engine->base; + } +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4169-drm-amd-display-configurable-aux-timeout-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4169-drm-amd-display-configurable-aux-timeout-support.patch new file mode 100644 index 00000000..9f39709d --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4169-drm-amd-display-configurable-aux-timeout-support.patch @@ -0,0 +1,467 @@ +From 7a69015f1ac7aad129d6750e20eb30493409e6ec Mon Sep 17 00:00:00 2001 +From: abdoulaye berthe <abdoulaye.berthe@amd.com> +Date: Thu, 18 Jul 2019 15:58:25 -0400 +Subject: [PATCH 4169/4736] drm/amd/display: configurable aux timeout support + +[Description] +1-add configurable timeout support to aux engine. +2-add timeout support field to dc_caps +3-add reg_key to override extended timeout support + +Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Reviewed-by: Roman Li <Roman.Li@amd.com> +--- + .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 14 ++++ + drivers/gpu/drm/amd/display/dc/dc.h | 2 + + drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 73 ++++++++++++++++++- + drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 16 +++- + .../amd/display/dc/dce100/dce100_resource.c | 5 +- + .../amd/display/dc/dce110/dce110_resource.c | 4 +- + .../amd/display/dc/dce112/dce112_resource.c | 5 +- + .../amd/display/dc/dce120/dce120_resource.c | 5 +- + .../drm/amd/display/dc/dce80/dce80_resource.c | 4 +- + .../drm/amd/display/dc/dcn10/dcn10_resource.c | 5 +- + .../drm/amd/display/dc/dcn20/dcn20_resource.c | 4 +- + .../drm/amd/display/dc/dcn21/dcn21_resource.c | 4 +- + .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h | 3 + + .../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 + + .../drm/amd/display/dc/inc/hw/aux_engine.h | 3 + + 15 files changed, 132 insertions(+), 17 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c +index 588a07b525a0..580594be1de5 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c +@@ -632,6 +632,20 @@ bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc, + return dce_aux_transfer_with_retries(ddc, payload); + } + ++ ++enum dc_status dc_link_aux_configure_timeout(struct ddc_service *ddc, ++ uint32_t timeout) ++{ ++ enum dc_status status = DC_OK; ++ struct ddc *ddc_pin = ddc->ddc_pin; ++ ++ if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout == NULL) ++ return DC_ERROR_UNEXPECTED; ++ if (!ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout)) ++ status = DC_ERROR_UNEXPECTED; ++ return status; ++} ++ + /*test only function*/ + void dal_ddc_service_set_ddc_pin( + struct ddc_service *ddc_service, +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index 41e366f59f10..5967106826ca 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -111,6 +111,7 @@ struct dc_caps { + bool force_dp_tps4_for_cp2520; + bool disable_dp_clk_share; + bool psp_setup_panel_mode; ++ bool extended_aux_timeout_support; + #ifdef CONFIG_DRM_AMD_DC_DCN2_0 + bool hw_3d_lut; + #endif +@@ -220,6 +221,7 @@ struct dc_config { + bool power_down_display_on_boot; + bool edp_not_connected; + bool forced_clocks; ++ bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well + bool multi_mon_pp_mclk_switch; + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +index 574447185f4a..a68edd0c2172 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +@@ -56,6 +56,14 @@ enum { + AUX_TIMED_OUT_RETRY_COUNTER = 2, + AUX_DEFER_RETRY_COUNTER = 6 + }; ++ ++#define TIME_OUT_INCREMENT 1016 ++#define TIME_OUT_MULTIPLIER_8 8 ++#define TIME_OUT_MULTIPLIER_16 16 ++#define TIME_OUT_MULTIPLIER_32 32 ++#define TIME_OUT_MULTIPLIER_64 64 ++#define MAX_TIMEOUT_LENGTH 127 ++ + static void release_engine( + struct dce_aux *engine) + { +@@ -199,7 +207,7 @@ static void submit_channel_request( + REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1); + + REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0, +- 10, aux110->timeout_period/10); ++ 10, aux110->polling_timeout_period/10); + + /* set the delay and the number of bytes to write */ + +@@ -328,7 +336,7 @@ static enum aux_channel_operation_result get_channel_status( + + /* poll to make sure that SW_DONE is asserted */ + REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1, +- 10, aux110->timeout_period/10); ++ 10, aux110->polling_timeout_period/10); + + value = REG_READ(AUX_SW_STATUS); + /* in case HPD is LOW, exit AUX transaction */ +@@ -416,24 +424,81 @@ void dce110_engine_destroy(struct dce_aux **engine) + + } + ++static bool dce_aux_configure_timeout(struct ddc_service *ddc, ++ uint32_t timeout_in_us) ++{ ++ uint32_t multiplier = 0; ++ uint32_t length = 0; ++ uint32_t timeout = 0; ++ struct ddc *ddc_pin = ddc->ddc_pin; ++ struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; ++ struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine); ++ ++ /* 1-Update polling timeout period */ ++ aux110->polling_timeout_period = timeout_in_us * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER; ++ ++ /* 2-Update aux timeout period length and multiplier */ ++ if (timeout_in_us <= TIME_OUT_INCREMENT) { ++ multiplier = 0; ++ length = timeout_in_us/TIME_OUT_MULTIPLIER_8; ++ if (timeout_in_us % TIME_OUT_MULTIPLIER_8 != 0) ++ length++; ++ timeout = length * TIME_OUT_MULTIPLIER_8; ++ } else if (timeout_in_us <= 2 * TIME_OUT_INCREMENT) { ++ multiplier = 1; ++ length = timeout_in_us/TIME_OUT_MULTIPLIER_16; ++ if (timeout_in_us % TIME_OUT_MULTIPLIER_16 != 0) ++ length++; ++ timeout = length * TIME_OUT_MULTIPLIER_16; ++ } else if (timeout_in_us <= 4 * TIME_OUT_INCREMENT) { ++ multiplier = 2; ++ length = timeout_in_us/TIME_OUT_MULTIPLIER_32; ++ if (timeout_in_us % TIME_OUT_MULTIPLIER_32 != 0) ++ length++; ++ timeout = length * TIME_OUT_MULTIPLIER_32; ++ } else if (timeout_in_us > 4 * TIME_OUT_INCREMENT) { ++ multiplier = 3; ++ length = timeout_in_us/TIME_OUT_MULTIPLIER_64; ++ if (timeout_in_us % TIME_OUT_MULTIPLIER_64 != 0) ++ length++; ++ timeout = length * TIME_OUT_MULTIPLIER_64; ++ } ++ ++ length = (length < MAX_TIMEOUT_LENGTH) ? length : MAX_TIMEOUT_LENGTH; ++ ++ REG_UPDATE_SEQ_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, length, AUX_RX_TIMEOUT_LEN_MUL, multiplier); ++ ++ return true; ++} ++ ++static struct dce_aux_funcs aux_functions = { ++ .configure_timeout = NULL, ++ .destroy = NULL, ++}; ++ + struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110, + struct dc_context *ctx, + uint32_t inst, + uint32_t timeout_period, + const struct dce110_aux_registers *regs, + const struct dce110_aux_registers_mask *mask, +- const struct dce110_aux_registers_shift *shift) ++ const struct dce110_aux_registers_shift *shift, ++ bool is_ext_aux_timeout_configurable) + { + aux_engine110->base.ddc = NULL; + aux_engine110->base.ctx = ctx; + aux_engine110->base.delay = 0; + aux_engine110->base.max_defer_write_retry = 0; + aux_engine110->base.inst = inst; +- aux_engine110->timeout_period = timeout_period; ++ aux_engine110->polling_timeout_period = timeout_period; + aux_engine110->regs = regs; + + aux_engine110->mask = mask; + aux_engine110->shift = shift; ++ aux_engine110->base.funcs = &aux_functions; ++ if (is_ext_aux_timeout_configurable) ++ aux_engine110->base.funcs->configure_timeout = &dce_aux_configure_timeout; ++ + return &aux_engine110->base; + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +index 717378502e9d..b4b2c79a8073 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +@@ -250,7 +250,7 @@ struct dce_aux { + uint32_t max_defer_write_retry; + + bool acquire_reset; +- const struct dce_aux_funcs *funcs; ++ struct dce_aux_funcs *funcs; + }; + + struct dce110_aux_registers_mask { +@@ -277,7 +277,7 @@ struct aux_engine_dce110 { + uint32_t aux_dphy_rx_control0; + uint32_t aux_sw_status; + } addr; +- uint32_t timeout_period; ++ uint32_t polling_timeout_period; + }; + + struct aux_engine_dce110_init_data { +@@ -294,7 +294,8 @@ struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine + const struct dce110_aux_registers *regs, + + const struct dce110_aux_registers_mask *mask, +- const struct dce110_aux_registers_shift *shift); ++ const struct dce110_aux_registers_shift *shift, ++ bool is_ext_aux_timeout_configurable); + + void dce110_engine_destroy(struct dce_aux **engine); + +@@ -308,4 +309,13 @@ int dce_aux_transfer_raw(struct ddc_service *ddc, + + bool dce_aux_transfer_with_retries(struct ddc_service *ddc, + struct aux_payload *cmd); ++ ++struct dce_aux_funcs { ++ bool (*configure_timeout) ++ (struct ddc_service *ddc, ++ uint32_t timeout); ++ void (*destroy) ++ (struct aux_engine **ptr); ++}; ++ + #endif +diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +index fe1538ab76ba..8ec9b4639fe7 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +@@ -653,7 +653,8 @@ struct dce_aux *dce100_aux_engine_create( + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, + &aux_engine_regs[inst], + &aux_mask, +- &aux_shift); ++ &aux_shift, ++ ctx->dc->caps.extended_aux_timeout_support); + + return &aux_engine->base; + } +@@ -1039,6 +1040,8 @@ static bool construct( + dc->caps.max_cursor_size = 128; + dc->caps.dual_link_dvi = true; + dc->caps.disable_dp_clk_share = true; ++ dc->caps.extended_aux_timeout_support = false; ++ + for (i = 0; i < pool->base.pipe_count; i++) { + pool->base.timing_generators[i] = + dce100_timing_generator_create( +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +index 06ecdf044ddc..377fa9193ce1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +@@ -700,7 +700,8 @@ struct dce_aux *dce110_aux_engine_create( + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, + &aux_engine_regs[inst], + &aux_mask, +- &aux_shift); ++ &aux_shift, ++ ctx->dc->caps.extended_aux_timeout_support); + + return &aux_engine->base; + } +@@ -1336,6 +1337,7 @@ static bool construct( + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 128; + dc->caps.is_apu = true; ++ dc->caps.extended_aux_timeout_support = false; + + /************************************************* + * Create resources * +diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +index 8dc75f71240d..5bde6ac2fa7e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +@@ -673,7 +673,8 @@ struct dce_aux *dce112_aux_engine_create( + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, + &aux_engine_regs[inst], + &aux_mask, +- &aux_shift); ++ &aux_shift, ++ ctx->dc->caps.extended_aux_timeout_support); + + return &aux_engine->base; + } +@@ -1206,7 +1207,7 @@ static bool construct( + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 128; + dc->caps.dual_link_dvi = true; +- ++ dc->caps.extended_aux_timeout_support = false; + + /************************************************* + * Create resources * +diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +index 3aac593f9b2e..2dcc647ad27d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +@@ -443,7 +443,8 @@ struct dce_aux *dce120_aux_engine_create( + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, + &aux_engine_regs[inst], + &aux_mask, +- &aux_shift); ++ &aux_shift, ++ ctx->dc->caps.extended_aux_timeout_support); + + return &aux_engine->base; + } +@@ -1049,7 +1050,7 @@ static bool construct( + dc->caps.max_cursor_size = 128; + dc->caps.dual_link_dvi = true; + dc->caps.psp_setup_panel_mode = true; +- ++ dc->caps.extended_aux_timeout_support = true; + dc->debug = debug_defaults; + + /************************************************* +diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +index 934d8deb95fc..6a9efa3bb93e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +@@ -530,7 +530,8 @@ struct dce_aux *dce80_aux_engine_create( + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, + &aux_engine_regs[inst], + &aux_mask, +- &aux_shift); ++ &aux_shift, ++ ctx->dc->caps.extended_aux_timeout_support); + + return &aux_engine->base; + } +@@ -938,6 +939,7 @@ static bool dce80_construct( + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; + dc->caps.dual_link_dvi = true; ++ dc->caps.extended_aux_timeout_support = false; + + /************************************************* + * Create resources * +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +index 82dbc00afe54..a38c83c6aa5c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +@@ -672,7 +672,8 @@ struct dce_aux *dcn10_aux_engine_create( + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, + &aux_engine_regs[inst], + &aux_mask, +- &aux_shift); ++ &aux_shift, ++ ctx->dc->caps.extended_aux_timeout_support); + + return &aux_engine->base; + } +@@ -1342,6 +1343,8 @@ static bool construct( + dc->caps.max_slave_planes = 1; + dc->caps.is_apu = true; + dc->caps.post_blend_color_processing = false; ++ dc->caps.extended_aux_timeout_support = false; ++ + /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ + dc->caps.force_dp_tps4_for_cp2520 = true; + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index f2db1fa2eba9..2796c84db740 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -960,7 +960,8 @@ struct dce_aux *dcn20_aux_engine_create( + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, + &aux_engine_regs[inst], + &aux_mask, +- &aux_shift); ++ &aux_shift, ++ ctx->dc->caps.extended_aux_timeout_support); + + return &aux_engine->base; + } +@@ -3372,6 +3373,7 @@ static bool construct( + dc->caps.post_blend_color_processing = true; + dc->caps.force_dp_tps4_for_cp2520 = true; + dc->caps.hw_3d_lut = true; ++ dc->caps.extended_aux_timeout_support = true; + + if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) { + dc->debug = debug_defaults_drv; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +index dc5d28d002df..86005cb05c2a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +@@ -695,7 +695,8 @@ static struct dce_aux *dcn21_aux_engine_create( + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, + &aux_engine_regs[inst], + &aux_mask, +- &aux_shift); ++ &aux_shift, ++ ctx->dc->caps.extended_aux_timeout_support); + + return &aux_engine->base; + } +@@ -1539,6 +1540,7 @@ static bool construct( + dc->caps.max_slave_planes = 1; + dc->caps.post_blend_color_processing = true; + dc->caps.force_dp_tps4_for_cp2520 = true; ++ dc->caps.extended_aux_timeout_support = true; + + if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) + dc->debug = debug_defaults_drv; +diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h +index 7d35d03a2d43..14716ba35662 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h +@@ -105,6 +105,9 @@ int dc_link_aux_transfer_raw(struct ddc_service *ddc, + bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc, + struct aux_payload *payload); + ++enum dc_status dc_link_aux_configure_timeout(struct ddc_service *ddc, ++ uint32_t timeout); ++ + void dal_ddc_service_write_scdc_data( + struct ddc_service *ddc_service, + uint32_t pix_clk, +diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +index 967706e7898e..045138dbdccb 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +@@ -28,6 +28,8 @@ + + #define LINK_TRAINING_ATTEMPTS 4 + #define LINK_TRAINING_RETRY_DELAY 50 /* ms */ ++#define LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD 32000 /*us*/ ++#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 400 /*us*/ + + struct dc_link; + struct dc_stream_state; +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h b/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h +index e79cd4e92919..e77b3a76766d 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h +@@ -140,6 +140,9 @@ struct write_command_context { + + + struct aux_engine_funcs { ++ bool (*configure_timeout)( ++ struct ddc_service *ddc, ++ uint32_t timeout); + void (*destroy)( + struct aux_engine **ptr); + bool (*acquire_engine)( +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4170-drm-amd-display-disable-ext-aux-support-for-vega.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4170-drm-amd-display-disable-ext-aux-support-for-vega.patch new file mode 100644 index 00000000..51c374a0 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4170-drm-amd-display-disable-ext-aux-support-for-vega.patch @@ -0,0 +1,37 @@ +From 380cc83606e4cd2ca0b3b206955d7047d54ace0c Mon Sep 17 00:00:00 2001 +From: Roman Li <Roman.Li@amd.com> +Date: Tue, 8 Oct 2019 17:35:48 -0400 +Subject: [PATCH 4170/4736] drm/amd/display: disable ext aux support for vega + +[Why] +Earlier changes to support configurable aux timeout +caused dc init failure on vega due to missing reg defs. +Needs to be disabled until implemented for vega. + +[How] +Set extended aux timeout cap for vega to false. + +fixes: drm/amd/display: configurable aux timeout support + +Signed-off-by: Roman Li <Roman.Li@amd.com> +Reviewed-By: abdoulaye berthe <abdoulaye.berthe@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +index 2dcc647ad27d..c982fd336cae 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +@@ -1050,7 +1050,7 @@ static bool construct( + dc->caps.max_cursor_size = 128; + dc->caps.dual_link_dvi = true; + dc->caps.psp_setup_panel_mode = true; +- dc->caps.extended_aux_timeout_support = true; ++ dc->caps.extended_aux_timeout_support = false; + dc->debug = debug_defaults; + + /************************************************* +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch new file mode 100644 index 00000000..4b56b5b0 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch @@ -0,0 +1,63 @@ +From 77b8a13374bac1feff732bbbce9233abd5f65aef Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Wed, 2 Oct 2019 11:50:15 -0400 +Subject: [PATCH 4171/4736] drm/amd/display: Add DP_DPHY_INTERNAL_CTR regs + +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Reviewed-by: Roman Li <Roman.Li@amd.com> +--- + .../drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h +index be4249adb356..eddf83ec1c39 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h +@@ -9859,6 +9859,8 @@ + #define mmDP0_DP_STEER_FIFO_BASE_IDX 2 + #define mmDP0_DP_MSA_MISC 0x210e + #define mmDP0_DP_MSA_MISC_BASE_IDX 2 ++#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f ++#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 + #define mmDP0_DP_VID_TIMING 0x2110 + #define mmDP0_DP_VID_TIMING_BASE_IDX 2 + #define mmDP0_DP_VID_N 0x2111 +@@ -10187,6 +10189,8 @@ + #define mmDP1_DP_STEER_FIFO_BASE_IDX 2 + #define mmDP1_DP_MSA_MISC 0x220e + #define mmDP1_DP_MSA_MISC_BASE_IDX 2 ++#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f ++#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 + #define mmDP1_DP_VID_TIMING 0x2210 + #define mmDP1_DP_VID_TIMING_BASE_IDX 2 + #define mmDP1_DP_VID_N 0x2211 +@@ -10515,6 +10519,8 @@ + #define mmDP2_DP_STEER_FIFO_BASE_IDX 2 + #define mmDP2_DP_MSA_MISC 0x230e + #define mmDP2_DP_MSA_MISC_BASE_IDX 2 ++#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f ++#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 + #define mmDP2_DP_VID_TIMING 0x2310 + #define mmDP2_DP_VID_TIMING_BASE_IDX 2 + #define mmDP2_DP_VID_N 0x2311 +@@ -10843,6 +10849,8 @@ + #define mmDP3_DP_STEER_FIFO_BASE_IDX 2 + #define mmDP3_DP_MSA_MISC 0x240e + #define mmDP3_DP_MSA_MISC_BASE_IDX 2 ++#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f ++#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 + #define mmDP3_DP_VID_TIMING 0x2410 + #define mmDP3_DP_VID_TIMING_BASE_IDX 2 + #define mmDP3_DP_VID_N 0x2411 +@@ -11171,6 +11179,8 @@ + #define mmDP4_DP_STEER_FIFO_BASE_IDX 2 + #define mmDP4_DP_MSA_MISC 0x250e + #define mmDP4_DP_MSA_MISC_BASE_IDX 2 ++#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f ++#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 + #define mmDP4_DP_VID_TIMING 0x2510 + #define mmDP4_DP_VID_TIMING_BASE_IDX 2 + #define mmDP4_DP_VID_N 0x2511 +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch new file mode 100644 index 00000000..8374bd65 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch @@ -0,0 +1,64 @@ +From 0fcb1884fb7b2db1e44bbdca280bce9284e3b902 Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Wed, 2 Oct 2019 11:51:20 -0400 +Subject: [PATCH 4172/4736] drm/amd/display: Add DCN_BASE regs + +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Reviewed-by: Roman Li <Roman.Li@amd.com> +--- + .../gpu/drm/amd/include/renoir_ip_offset.h | 34 +++++++++++++++++++ + 1 file changed, 34 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/renoir_ip_offset.h b/drivers/gpu/drm/amd/include/renoir_ip_offset.h +index 094648cac392..07633e22e99a 100644 +--- a/drivers/gpu/drm/amd/include/renoir_ip_offset.h ++++ b/drivers/gpu/drm/amd/include/renoir_ip_offset.h +@@ -169,6 +169,11 @@ static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; ++static const struct IP_BASE DCN_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, ++ { { 0, 0, 0, 0, 0 } }, ++ { { 0, 0, 0, 0, 0 } }, ++ { { 0, 0, 0, 0, 0 } }, ++ { { 0, 0, 0, 0, 0 } } } }; + static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, +@@ -1361,4 +1366,33 @@ static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x0240300 + #define UVD0_BASE__INST6_SEG3 0 + #define UVD0_BASE__INST6_SEG4 0 + ++#define DCN_BASE__INST0_SEG0 0x00000012 ++#define DCN_BASE__INST0_SEG1 0x000000C0 ++#define DCN_BASE__INST0_SEG2 0x000034C0 ++#define DCN_BASE__INST0_SEG3 0 ++#define DCN_BASE__INST0_SEG4 0 ++ ++#define DCN_BASE__INST1_SEG0 0 ++#define DCN_BASE__INST1_SEG1 0 ++#define DCN_BASE__INST1_SEG2 0 ++#define DCN_BASE__INST1_SEG3 0 ++#define DCN_BASE__INST1_SEG4 0 ++ ++#define DCN_BASE__INST2_SEG0 0 ++#define DCN_BASE__INST2_SEG1 0 ++#define DCN_BASE__INST2_SEG2 0 ++#define DCN_BASE__INST2_SEG3 0 ++#define DCN_BASE__INST2_SEG4 0 ++ ++#define DCN_BASE__INST3_SEG0 0 ++#define DCN_BASE__INST3_SEG1 0 ++#define DCN_BASE__INST3_SEG2 0 ++#define DCN_BASE__INST3_SEG3 0 ++#define DCN_BASE__INST3_SEG4 0 ++ ++#define DCN_BASE__INST4_SEG0 0 ++#define DCN_BASE__INST4_SEG1 0 ++#define DCN_BASE__INST4_SEG2 0 ++#define DCN_BASE__INST4_SEG3 0 ++#define DCN_BASE__INST4_SEG4 0 + #endif +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4173-drm-amd-display-Add-renoir-hw_seq.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4173-drm-amd-display-Add-renoir-hw_seq.patch new file mode 100644 index 00000000..8f133525 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4173-drm-amd-display-Add-renoir-hw_seq.patch @@ -0,0 +1,449 @@ +From 8e48ee9e07fb0aa2b88f1e157660f182afafd7cc Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Wed, 2 Oct 2019 11:54:56 -0400 +Subject: [PATCH 4173/4736] drm/amd/display: Add renoir hw_seq + +This change adds renoir hw_seq, needed to do renoir +specific hw programing + +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Reviewed-by: Roman Li <Roman.Li@amd.com> +--- + .../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 1 + + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 + + drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 2 +- + .../drm/amd/display/dc/dcn21/dcn21_hwseq.c | 122 ++++++++++++++++++ + .../drm/amd/display/dc/dcn21/dcn21_hwseq.h | 33 +++++ + .../drm/amd/display/dc/dcn21/dcn21_resource.c | 118 +++++++++++++---- + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 + + 7 files changed, 255 insertions(+), 28 deletions(-) + create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c + create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +index ac04d77058f0..32d145a0d6fc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +@@ -679,6 +679,7 @@ struct dce_hwseq_registers { + HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ ++ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh), \ + HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ + HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) + #endif +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 3b55716bf63b..7c02f646feed 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -669,6 +669,10 @@ static void dcn10_bios_golden_init(struct dc *dc) + int i; + bool allow_self_fresh_force_enable = true; + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++ if (dc->hwss.s0i3_golden_init_wa && dc->hwss.s0i3_golden_init_wa(dc)) ++ return; ++#endif + if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled) + allow_self_fresh_force_enable = + dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile +index b2b39090fb57..5b8f42ae2334 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile +@@ -1,7 +1,7 @@ + # + # Makefile for DCN21. + +-DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o ++DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o + + CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4 + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c +new file mode 100644 +index 000000000000..b25215cadf85 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c +@@ -0,0 +1,122 @@ ++/* ++ * Copyright 2016 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++ ++#include "dm_services.h" ++#include "dm_helpers.h" ++#include "core_types.h" ++#include "resource.h" ++#include "dce/dce_hwseq.h" ++#include "dcn20/dcn20_hwseq.h" ++#include "vmid.h" ++#include "reg_helper.h" ++#include "hw/clk_mgr.h" ++ ++ ++#define DC_LOGGER_INIT(logger) ++ ++#define CTX \ ++ hws->ctx ++#define REG(reg)\ ++ hws->regs->reg ++ ++#undef FN ++#define FN(reg_name, field_name) \ ++ hws->shifts->field_name, hws->masks->field_name ++ ++/* Temporary read settings, future will get values from kmd directly */ ++static void mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config *config, ++ struct dce_hwseq *hws) ++{ ++ uint32_t page_table_base_hi; ++ uint32_t page_table_base_lo; ++ ++ REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, ++ PAGE_DIRECTORY_ENTRY_HI32, &page_table_base_hi); ++ REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, ++ PAGE_DIRECTORY_ENTRY_LO32, &page_table_base_lo); ++ ++ config->gart_config.page_table_base_addr = ((uint64_t)page_table_base_hi << 32) | page_table_base_lo; ++ ++} ++ ++static int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) ++{ ++ struct dcn_hubbub_phys_addr_config config; ++ ++ config.system_aperture.fb_top = pa_config->system_aperture.fb_top; ++ config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; ++ config.system_aperture.fb_base = pa_config->system_aperture.fb_base; ++ config.system_aperture.agp_top = pa_config->system_aperture.agp_top; ++ config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; ++ config.system_aperture.agp_base = pa_config->system_aperture.agp_base; ++ config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; ++ config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; ++ config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; ++ ++ mmhub_update_page_table_config(&config, hws); ++ ++ return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); ++} ++ ++// work around for Renoir s0i3, if register is programmed, bypass golden init. ++ ++static bool dcn21_s0i3_golden_init_wa(struct dc *dc) ++{ ++ struct dce_hwseq *hws = dc->hwseq; ++ uint32_t value = 0; ++ ++ value = REG_READ(MICROSECOND_TIME_BASE_DIV); ++ ++ return value != 0x00120464; ++} ++ ++void dcn21_exit_optimized_pwr_state( ++ const struct dc *dc, ++ struct dc_state *context) ++{ ++ dc->clk_mgr->funcs->update_clocks( ++ dc->clk_mgr, ++ context, ++ false); ++} ++ ++void dcn21_optimize_pwr_state( ++ const struct dc *dc, ++ struct dc_state *context) ++{ ++ dc->clk_mgr->funcs->update_clocks( ++ dc->clk_mgr, ++ context, ++ true); ++} ++ ++void dcn21_hw_sequencer_construct(struct dc *dc) ++{ ++ dcn20_hw_sequencer_construct(dc); ++ dc->hwss.init_sys_ctx = dcn21_init_sys_ctx; ++ dc->hwss.s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa; ++ dc->hwss.optimize_pwr_state = dcn21_optimize_pwr_state; ++ dc->hwss.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state; ++} +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h +new file mode 100644 +index 000000000000..be67b62e6fb1 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h +@@ -0,0 +1,33 @@ ++/* ++* Copyright 2016 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++ ++#ifndef __DC_HWSS_DCN21_H__ ++#define __DC_HWSS_DCN21_H__ ++ ++struct dc; ++ ++void dcn21_hw_sequencer_construct(struct dc *dc); ++ ++#endif /* __DC_HWSS_DCN21_H__ */ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +index 86005cb05c2a..1bac7eca5963 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +@@ -23,8 +23,6 @@ + * + */ + +-#include <linux/slab.h> +- + #include "dm_services.h" + #include "dc.h" + +@@ -42,7 +40,7 @@ + #include "irq/dcn21/irq_service_dcn21.h" + #include "dcn20/dcn20_dpp.h" + #include "dcn20/dcn20_optc.h" +-#include "dcn20/dcn20_hwseq.h" ++#include "dcn21/dcn21_hwseq.h" + #include "dce110/dce110_hw_sequencer.h" + #include "dcn20/dcn20_opp.h" + #include "dcn20/dcn20_dsc.h" +@@ -350,6 +348,30 @@ static const struct bios_registers bios_regs = { + NBIO_SR(BIOS_SCRATCH_6) + }; + ++static const struct dce_dmcu_registers dmcu_regs = { ++ DMCU_DCN10_REG_LIST() ++}; ++ ++static const struct dce_dmcu_shift dmcu_shift = { ++ DMCU_MASK_SH_LIST_DCN10(__SHIFT) ++}; ++ ++static const struct dce_dmcu_mask dmcu_mask = { ++ DMCU_MASK_SH_LIST_DCN10(_MASK) ++}; ++ ++static const struct dce_abm_registers abm_regs = { ++ ABM_DCN20_REG_LIST() ++}; ++ ++static const struct dce_abm_shift abm_shift = { ++ ABM_MASK_SH_LIST_DCN20(__SHIFT) ++}; ++ ++static const struct dce_abm_mask abm_mask = { ++ ABM_MASK_SH_LIST_DCN20(_MASK) ++}; ++ + #ifdef CONFIG_DRM_AMD_DC_DMUB + static const struct dcn21_dmcub_registers dmcub_regs = { + DMCUB_REG_LIST_DCN() +@@ -1491,6 +1513,19 @@ static struct link_encoder *dcn21_link_encoder_create( + return &enc21->enc10.base; + } + ++#define CTX ctx ++ ++#define REG(reg_name) \ ++ (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) ++ ++static uint32_t read_pipe_fuses(struct dc_context *ctx) ++{ ++ uint32_t value = REG_READ(CC_DC_PIPE_DIS); ++ /* RV1 support max 4 pipes */ ++ value = value & 0xf; ++ return value; ++} ++ + static struct resource_funcs dcn21_res_pool_funcs = { + .destroy = dcn21_destroy_resource_pool, + .link_enc_create = dcn20_link_encoder_create, +@@ -1510,9 +1545,10 @@ static bool construct( + struct dc *dc, + struct dcn21_resource_pool *pool) + { +- int i; ++ int i, j; + struct dc_context *ctx = dc->ctx; + struct irq_service_init_data init_data; ++ uint32_t pipe_fuses = read_pipe_fuses(ctx); + + ctx->dc_bios->regs = &bios_regs; + +@@ -1530,7 +1566,9 @@ static bool construct( + *************************************************/ + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; + +- pool->base.pipe_count = 4; ++ /* max pipe num for ASIC before check pipe fuses */ ++ pool->base.pipe_count = pool->base.res_cap->num_timing_generator; ++ + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 256; +@@ -1590,6 +1628,26 @@ static bool construct( + goto create_fail; + } + ++ pool->base.dmcu = dcn20_dmcu_create(ctx, ++ &dmcu_regs, ++ &dmcu_shift, ++ &dmcu_mask); ++ if (pool->base.dmcu == NULL) { ++ dm_error("DC: failed to create dmcu!\n"); ++ BREAK_TO_DEBUGGER(); ++ goto create_fail; ++ } ++ ++ pool->base.abm = dce_abm_create(ctx, ++ &abm_regs, ++ &abm_shift, ++ &abm_mask); ++ if (pool->base.abm == NULL) { ++ dm_error("DC: failed to create abm!\n"); ++ BREAK_TO_DEBUGGER(); ++ goto create_fail; ++ } ++ + #ifdef CONFIG_DRM_AMD_DC_DMUB + pool->base.dmcub = dcn21_dmcub_create(ctx, + &dmcub_regs, +@@ -1611,8 +1669,15 @@ static bool construct( + if (!pool->base.irqs) + goto create_fail; + ++ j = 0; + /* mem input -> ipp -> dpp -> opp -> TG */ + for (i = 0; i < pool->base.pipe_count; i++) { ++ /* if pipe is disabled, skip instance of HW pipe, ++ * i.e, skip ASIC register instance ++ */ ++ if ((pipe_fuses & (1 << i)) != 0) ++ continue; ++ + pool->base.hubps[i] = dcn21_hubp_create(ctx, i); + if (pool->base.hubps[i] == NULL) { + BREAK_TO_DEBUGGER(); +@@ -1636,6 +1701,23 @@ static bool construct( + "DC: failed to create dpps!\n"); + goto create_fail; + } ++ ++ pool->base.opps[i] = dcn21_opp_create(ctx, i); ++ if (pool->base.opps[i] == NULL) { ++ BREAK_TO_DEBUGGER(); ++ dm_error( ++ "DC: failed to create output pixel processor!\n"); ++ goto create_fail; ++ } ++ ++ pool->base.timing_generators[i] = dcn21_timing_generator_create( ++ ctx, i); ++ if (pool->base.timing_generators[i] == NULL) { ++ BREAK_TO_DEBUGGER(); ++ dm_error("DC: failed to create tg!\n"); ++ goto create_fail; ++ } ++ j++; + } + + for (i = 0; i < pool->base.res_cap->num_ddc; i++) { +@@ -1656,27 +1738,9 @@ static bool construct( + pool->base.sw_i2cs[i] = NULL; + } + +- for (i = 0; i < pool->base.res_cap->num_opp; i++) { +- pool->base.opps[i] = dcn21_opp_create(ctx, i); +- if (pool->base.opps[i] == NULL) { +- BREAK_TO_DEBUGGER(); +- dm_error( +- "DC: failed to create output pixel processor!\n"); +- goto create_fail; +- } +- } +- +- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { +- pool->base.timing_generators[i] = dcn21_timing_generator_create( +- ctx, i); +- if (pool->base.timing_generators[i] == NULL) { +- BREAK_TO_DEBUGGER(); +- dm_error("DC: failed to create tg!\n"); +- goto create_fail; +- } +- } +- +- pool->base.timing_generator_count = i; ++ pool->base.timing_generator_count = j; ++ pool->base.pipe_count = j; ++ pool->base.mpcc_count = j; + + pool->base.mpc = dcn21_mpc_create(ctx); + if (pool->base.mpc == NULL) { +@@ -1719,7 +1783,7 @@ static bool construct( + &res_create_funcs : &res_create_maximus_funcs))) + goto create_fail; + +- dcn20_hw_sequencer_construct(dc); ++ dcn21_hw_sequencer_construct(dc); + + dc->caps.max_planes = pool->base.pipe_count; + +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +index e775d7aa062f..d39c1e11def5 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +@@ -349,6 +349,9 @@ struct hw_sequencer_funcs { + enum dc_clock_type clock_type, + struct dc_clock_config *clock_cfg); + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_1) ++ bool (*s0i3_golden_init_wa)(struct dc *dc); ++#endif + }; + + void color_space_to_black_color( +-- +2.17.1 + diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4174-drm-amd-display-create-dcn21_link_encoder-files.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4174-drm-amd-display-create-dcn21_link_encoder-files.patch new file mode 100644 index 00000000..69b71fce --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4174-drm-amd-display-create-dcn21_link_encoder-files.patch @@ -0,0 +1,668 @@ +From eedab588549241d11646033a4667dd8851e5a97f Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Wed, 2 Oct 2019 11:55:12 -0400 +Subject: [PATCH 4174/4736] drm/amd/display: create dcn21_link_encoder files + +[Why] +DCN20 and DCN21 have different phy programming sequences. + +[How] +Create a separate dcn21_link_encoder for Renoir + +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Reviewed-by: Roman Li <Roman.Li@amd.com> +--- + .../amd/display/dc/dcn10/dcn10_link_encoder.h | 35 +- + .../amd/display/dc/dcn20/dcn20_link_encoder.h | 7 + + drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 2 +- + .../amd/display/dc/dcn21/dcn21_link_encoder.c | 379 ++++++++++++++++++ + .../amd/display/dc/dcn21/dcn21_link_encoder.h | 51 +++ + .../drm/amd/display/dc/dcn21/dcn21_resource.c | 85 +++- + 6 files changed, 555 insertions(+), 4 deletions(-) + create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c + create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h +index 0c12395cfa36..239a6c90ffb9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h +@@ -250,6 +250,10 @@ struct dcn10_link_enc_registers { + type RDPCS_EXT_REFCLK_EN;\ + type RDPCS_TX_FIFO_EN;\ + type UNIPHY_LINK_ENABLE;\ ++ type UNIPHY_CHANNEL0_XBAR_SOURCE;\ ++ type UNIPHY_CHANNEL1_XBAR_SOURCE;\ ++ type UNIPHY_CHANNEL2_XBAR_SOURCE;\ ++ type UNIPHY_CHANNEL3_XBAR_SOURCE;\ + type UNIPHY_CHANNEL0_INVERT;\ + type UNIPHY_CHANNEL1_INVERT;\ + type UNIPHY_CHANNEL2_INVERT;\ +@@ -342,12 +346,41 @@ struct dcn10_link_enc_registers { + type RDPCS_PHY_DPALT_DISABLE_ACK;\ + type RDPCS_PHY_DP_MPLLB_V2I;\ + type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\ ++ type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\ ++ type RDPCS_PHY_RX_VREF_CTRL;\ + type RDPCS_PHY_DP_MPLLB_CP_INT;\ + type RDPCS_PHY_DP_MPLLB_CP_PROP;\ + type RDPCS_PHY_RX_REF_LD_VAL;\ + type RDPCS_PHY_RX_VCO_LD_VAL;\ + type DPCSTX_DEBUG_CONFIG; \ +- type RDPCSTX_DEBUG_CONFIG ++ type RDPCSTX_DEBUG_CONFIG; \ ++ type RDPCS_PHY_DP_TX0_EQ_MAIN;\ ++ type RDPCS_PHY_DP_TX0_EQ_PRE;\ ++ type RDPCS_PHY_DP_TX0_EQ_POST;\ ++ type RDPCS_PHY_DP_TX1_EQ_MAIN;\ ++ type RDPCS_PHY_DP_TX1_EQ_PRE;\ ++ type RDPCS_PHY_DP_TX1_EQ_POST;\ ++ type RDPCS_PHY_DP_TX2_EQ_MAIN;\ ++ type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\ ++ type RDPCS_PHY_DP_TX2_EQ_PRE;\ ++ type RDPCS_PHY_DP_TX2_EQ_POST;\ ++ type RDPCS_PHY_DP_TX3_EQ_MAIN;\ ++ type RDPCS_PHY_DCO_RANGE;\ ++ type RDPCS_PHY_DCO_FINETUNE;\ ++ type RDPCS_PHY_DP_TX3_EQ_PRE;\ ++ type RDPCS_PHY_DP_TX3_EQ_POST;\ ++ type RDPCS_PHY_SUP_PRE_HP;\ ++ type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\ ++ type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\ ++ type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\ ++ type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\ ++ type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\ ++ type UNIPHYA_SOFT_RESET;\ ++ type UNIPHYB_SOFT_RESET;\ ++ type UNIPHYC_SOFT_RESET;\ ++ type UNIPHYD_SOFT_RESET;\ ++ type UNIPHYE_SOFT_RESET;\ ++ type UNIPHYF_SOFT_RESET + + #define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \ + type DIG_LANE0EN;\ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h +index 3736b5548a25..0c98a0bbbd14 1006 |