aboutsummaryrefslogtreecommitdiffstats
path: root/common/recipes-kernel/linux/files/0887-drm-amd-dal-Move-crtc-timing-definitions-to-dc_hw_ty.patch
blob: 1f554d83be8a90ff19498d3fc18d0fc72c79b661 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
From 9e513990a2e53959b0df3febe5d334ad357bec25 Mon Sep 17 00:00:00 2001
From: Jordan Lazare <Jordan.Lazare@amd.com>
Date: Tue, 8 Mar 2016 17:37:39 -0500
Subject: [PATCH 0887/1110] drm/amd/dal: Move crtc timing definitions to
 dc_hw_types header

Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/dal/dc/dc_hw_types.h | 157 ++++++++++++++++++++++++++++---
 drivers/gpu/drm/amd/dal/dc/dc_types.h    | 123 ------------------------
 2 files changed, 142 insertions(+), 138 deletions(-)

diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
index bfe9955..9a92dd7 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
@@ -344,14 +344,7 @@ struct dc_cursor_attributes {
 };
 
 /* OPP */
-enum dc_pixel_encoding {
-	PIXEL_ENCODING_UNDEFINED,
-	PIXEL_ENCODING_RGB,
-	PIXEL_ENCODING_YCBCR422,
-	PIXEL_ENCODING_YCBCR444,
-	PIXEL_ENCODING_YCBCR420,
-	PIXEL_ENCODING_COUNT
-};
+
 
 enum dc_color_space {
 	COLOR_SPACE_UNKNOWN,
@@ -365,6 +358,63 @@ enum dc_color_space {
 	COLOR_SPACE_YCBCR709_LIMITED
 };
 
+
+
+/* XFM */
+
+/* used in  struct dc_surface */
+struct scaling_taps {
+	uint32_t v_taps;
+	uint32_t h_taps;
+	uint32_t v_taps_c;
+	uint32_t h_taps_c;
+};
+
+
+enum dc_timing_standard {
+	TIMING_STANDARD_UNDEFINED,
+	TIMING_STANDARD_DMT,
+	TIMING_STANDARD_GTF,
+	TIMING_STANDARD_CVT,
+	TIMING_STANDARD_CVT_RB,
+	TIMING_STANDARD_CEA770,
+	TIMING_STANDARD_CEA861,
+	TIMING_STANDARD_HDMI,
+	TIMING_STANDARD_TV_NTSC,
+	TIMING_STANDARD_TV_NTSC_J,
+	TIMING_STANDARD_TV_PAL,
+	TIMING_STANDARD_TV_PAL_M,
+	TIMING_STANDARD_TV_PAL_CN,
+	TIMING_STANDARD_TV_SECAM,
+	TIMING_STANDARD_EXPLICIT,
+	/*!< For explicit timings from EDID, VBIOS, etc.*/
+	TIMING_STANDARD_USER_OVERRIDE,
+	/*!< For mode timing override by user*/
+	TIMING_STANDARD_MAX
+};
+
+enum dc_timing_3d_format {
+	TIMING_3D_FORMAT_NONE,
+	TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
+	TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
+	TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
+	/* for active DP-HDMI dongle*/
+	TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
+	TIMING_3D_FORMAT_HW_FRAME_PACKING,
+	TIMING_3D_FORMAT_SW_FRAME_PACKING,
+	TIMING_3D_FORMAT_ROW_INTERLEAVE,
+	TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
+	TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
+	TIMING_3D_FORMAT_SIDE_BY_SIDE,
+	TIMING_3D_FORMAT_TOP_AND_BOTTOM,
+	TIMING_3D_FORMAT_SBS_SW_PACKED,
+	/* Side-by-side, packed by application/driver into 2D frame*/
+	TIMING_3D_FORMAT_TB_SW_PACKED,
+	/* Top-and-bottom, packed by application/driver into 2D frame*/
+
+	TIMING_3D_FORMAT_MAX,
+};
+
 enum dc_color_depth {
 	COLOR_DEPTH_UNDEFINED,
 	COLOR_DEPTH_666,
@@ -376,14 +426,91 @@ enum dc_color_depth {
 	COLOR_DEPTH_COUNT
 };
 
-/* XFM */
+enum dc_pixel_encoding {
+	PIXEL_ENCODING_UNDEFINED,
+	PIXEL_ENCODING_RGB,
+	PIXEL_ENCODING_YCBCR422,
+	PIXEL_ENCODING_YCBCR444,
+	PIXEL_ENCODING_YCBCR420,
+	PIXEL_ENCODING_COUNT
+};
 
-/* used in  struct dc_surface */
-struct scaling_taps {
-	uint32_t v_taps;
-	uint32_t h_taps;
-	uint32_t v_taps_c;
-	uint32_t h_taps_c;
+enum dc_aspect_ratio {
+	ASPECT_RATIO_NO_DATA,
+	ASPECT_RATIO_4_3,
+	ASPECT_RATIO_16_9,
+	ASPECT_RATIO_64_27,
+	ASPECT_RATIO_256_135,
+	ASPECT_RATIO_FUTURE
+};
+
+enum scanning_type {
+	SCANNING_TYPE_NODATA = 0,
+	SCANNING_TYPE_OVERSCAN,
+	SCANNING_TYPE_UNDERSCAN,
+	SCANNING_TYPE_FUTURE,
+	SCANNING_TYPE_UNDEFINED
+};
+
+struct dc_crtc_timing_flags {
+	uint32_t INTERLACE :1;
+	uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
+	 it is positive polarity --reversed with dal1 or video bios define*/
+	uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
+	 it is positive polarity --reversed with dal1 or video bios define*/
+
+	uint32_t HORZ_COUNT_BY_TWO:1;
+
+	uint32_t EXCLUSIVE_3D :1; /* if this bit set,
+	 timing can be driven in 3D format only
+	 and there is no corresponding 2D timing*/
+	uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
+	 (right eye = '1', left eye = '0') */
+	uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right  images subsampled
+	 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
+	uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
+	 because corresponding 2D timing also present in the list*/
+	uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
+	 and we want to match priority of corresponding 3D timing*/
+	uint32_t Y_ONLY :1;
+
+	uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
+	uint32_t DTD_COUNTER :5; /* values 1 to 16 */
+
+	/* HDMI 2.0 - Support scrambling for TMDS character
+	 * rates less than or equal to 340Mcsc */
+	uint32_t LTE_340MCSC_SCRAMBLE:1;
+
+};
+
+struct dc_crtc_timing {
+
+	uint32_t h_total;
+	uint32_t h_border_left;
+	uint32_t h_addressable;
+	uint32_t h_border_right;
+	uint32_t h_front_porch;
+	uint32_t h_sync_width;
+
+	uint32_t v_total;
+	uint32_t v_border_top;
+	uint32_t v_addressable;
+	uint32_t v_border_bottom;
+	uint32_t v_front_porch;
+	uint32_t v_sync_width;
+
+	uint32_t pix_clk_khz;
+
+	uint32_t vic;
+	uint32_t hdmi_vic;
+	enum dc_timing_standard timing_standard;
+	enum dc_timing_3d_format timing_3d_format;
+	enum dc_color_depth display_color_depth;
+	enum dc_pixel_encoding pixel_encoding;
+	enum dc_aspect_ratio aspect_ratio;
+	enum scanning_type scan_type;
+
+	struct dc_crtc_timing_flags flags;
 };
 
 #endif /* DC_HW_TYPES_H */
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
index d3d105e..99da485 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
@@ -310,89 +310,6 @@ struct dc_mode_flags {
 	uint32_t MIRACAST_REFRESH_DIVIDER;
 };
 
-struct dc_crtc_timing_flags {
-	uint32_t INTERLACE :1;
-	uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
-	 it is positive polarity --reversed with dal1 or video bios define*/
-	uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
-	 it is positive polarity --reversed with dal1 or video bios define*/
-
-	uint32_t HORZ_COUNT_BY_TWO:1;
-
-	uint32_t EXCLUSIVE_3D :1; /* if this bit set,
-	 timing can be driven in 3D format only
-	 and there is no corresponding 2D timing*/
-	uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
-	 (right eye = '1', left eye = '0') */
-	uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right  images subsampled
-	 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
-	uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
-	 because corresponding 2D timing also present in the list*/
-	uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
-	 and we want to match priority of corresponding 3D timing*/
-	uint32_t Y_ONLY :1;
-
-	uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
-	uint32_t DTD_COUNTER :5; /* values 1 to 16 */
-
-	/* HDMI 2.0 - Support scrambling for TMDS character
-	 * rates less than or equal to 340Mcsc */
-	uint32_t LTE_340MCSC_SCRAMBLE:1;
-
-};
-
-enum dc_timing_standard {
-	TIMING_STANDARD_UNDEFINED,
-	TIMING_STANDARD_DMT,
-	TIMING_STANDARD_GTF,
-	TIMING_STANDARD_CVT,
-	TIMING_STANDARD_CVT_RB,
-	TIMING_STANDARD_CEA770,
-	TIMING_STANDARD_CEA861,
-	TIMING_STANDARD_HDMI,
-	TIMING_STANDARD_TV_NTSC,
-	TIMING_STANDARD_TV_NTSC_J,
-	TIMING_STANDARD_TV_PAL,
-	TIMING_STANDARD_TV_PAL_M,
-	TIMING_STANDARD_TV_PAL_CN,
-	TIMING_STANDARD_TV_SECAM,
-	TIMING_STANDARD_EXPLICIT,
-	/*!< For explicit timings from EDID, VBIOS, etc.*/
-	TIMING_STANDARD_USER_OVERRIDE,
-	/*!< For mode timing override by user*/
-	TIMING_STANDARD_MAX
-};
-
-enum dc_aspect_ratio {
-	ASPECT_RATIO_NO_DATA,
-	ASPECT_RATIO_4_3,
-	ASPECT_RATIO_16_9,
-	ASPECT_RATIO_64_27,
-	ASPECT_RATIO_256_135,
-	ASPECT_RATIO_FUTURE
-};
-
-enum dc_timing_3d_format {
-	TIMING_3D_FORMAT_NONE,
-	TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
-	TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
-	TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
-	/* for active DP-HDMI dongle*/
-	TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
-	TIMING_3D_FORMAT_HW_FRAME_PACKING,
-	TIMING_3D_FORMAT_SW_FRAME_PACKING,
-	TIMING_3D_FORMAT_ROW_INTERLEAVE,
-	TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
-	TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
-	TIMING_3D_FORMAT_SIDE_BY_SIDE,
-	TIMING_3D_FORMAT_TOP_AND_BOTTOM,
-	TIMING_3D_FORMAT_SBS_SW_PACKED,
-	/* Side-by-side, packed by application/driver into 2D frame*/
-	TIMING_3D_FORMAT_TB_SW_PACKED,
-	/* Top-and-bottom, packed by application/driver into 2D frame*/
-
-	TIMING_3D_FORMAT_MAX,
-};
 
 enum dc_timing_source {
 	TIMING_SOURCE_UNDEFINED,
@@ -454,46 +371,6 @@ struct dc_mode_info {
 	struct dc_mode_flags flags;
 };
 
-/* TODO: assess necessity*/
-/*scanning type*/
-enum scanning_type {
-	SCANNING_TYPE_NODATA = 0,
-	SCANNING_TYPE_OVERSCAN,
-	SCANNING_TYPE_UNDERSCAN,
-	SCANNING_TYPE_FUTURE,
-	SCANNING_TYPE_UNDEFINED
-};
-
-struct dc_crtc_timing {
-
-	uint32_t h_total;
-	uint32_t h_border_left;
-	uint32_t h_addressable;
-	uint32_t h_border_right;
-	uint32_t h_front_porch;
-	uint32_t h_sync_width;
-
-	uint32_t v_total;
-	uint32_t v_border_top;
-	uint32_t v_addressable;
-	uint32_t v_border_bottom;
-	uint32_t v_front_porch;
-	uint32_t v_sync_width;
-
-	uint32_t pix_clk_khz;
-
-	uint32_t vic;
-	uint32_t hdmi_vic;
-	enum dc_timing_standard timing_standard;
-	enum dc_timing_3d_format timing_3d_format;
-	enum dc_color_depth display_color_depth;
-	enum dc_pixel_encoding pixel_encoding;
-	enum dc_aspect_ratio aspect_ratio;
-	enum scanning_type scan_type;
-
-	struct dc_crtc_timing_flags flags;
-};
-
 struct dc_mode_timing {
 	struct dc_mode_info mode_info;
 	struct dc_crtc_timing crtc_timing;
-- 
2.7.4