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From 03e60574d37c6d9ab73d4aee14c0327224c0c3be Mon Sep 17 00:00:00 2001
From: Eric Yang <eric.yang2@amd.com>
Date: Tue, 19 Jan 2016 17:24:37 -0500
Subject: [PATCH 0710/1110] drm/amd/dal: tonga initial light up

Add Tonga support by reusing dce110, has corresponding
kernel change

Signed-off-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      |   8 ++
 .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |   4 +
 .../gpu/drm/amd/dal/dc/asic_capability/Makefile    |  12 ++
 .../amd/dal/dc/asic_capability/asic_capability.c   |  14 +-
 .../dc/asic_capability/carrizo_asic_capability.c   |   1 +
 .../dal/dc/asic_capability/tonga_asic_capability.c | 147 +++++++++++++++++++++
 .../dal/dc/asic_capability/tonga_asic_capability.h |  18 +++
 drivers/gpu/drm/amd/dal/dc/audio/audio_base.c      |   4 +
 .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c   |   6 +
 .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h   |   2 +-
 .../gpu/drm/amd/dal/dc/bios/command_table_helper.c |   6 +
 .../gpu/drm/amd/dal/dc/bios/command_table_helper.h |   2 +-
 drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c  |   4 +
 .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    |   9 ++
 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c     |  13 ++
 .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  28 +++-
 drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c       |   5 +
 drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c     |   3 +
 drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c      |   5 +-
 .../dal/dc/gpu/dce110/ext_clock_source_dce110.c    |   2 +-
 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c         |   5 +-
 drivers/gpu/drm/amd/dal/dc/irq/irq_service.c       |   4 +
 drivers/gpu/drm/amd/dal/include/dal_asic_id.h      |  11 ++
 drivers/gpu/drm/amd/dal/include/dal_types.h        |   3 +
 24 files changed, 308 insertions(+), 8 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
 create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h

diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
index 7614ac8..2cece0f 100644
--- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
@@ -1216,6 +1216,8 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 	/* Software is initialized. Now we can register interrupt handlers. */
 	switch (adev->asic_type) {
 	case CHIP_BONAIRE:
+	case CHIP_TONGA:
+	case CHIP_FIJI:
 	case CHIP_CARRIZO:
 		if (dce110_register_irq_handlers(dm->adev)) {
 			DRM_ERROR("DM: Failed to initialize IRQ\n");
@@ -1435,6 +1437,12 @@ static int dm_early_init(void *handle)
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 6;
 		break;
+	case CHIP_FIJI:
+	case CHIP_TONGA:
+		adev->mode_info.num_crtc = 6;
+		adev->mode_info.num_hpd = 6;
+		adev->mode_info.num_dig = 7;
+		break;
 	case CHIP_CARRIZO:
 		adev->mode_info.num_crtc = 3;
 		adev->mode_info.num_hpd = 6;
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index b8d6033..17a9d2c 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -677,6 +677,10 @@ static struct hw_ctx_adapter_service *create_hw_ctx(
 	}
 
 	switch (dce_version) {
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+	case DCE_VERSION_10_0:
+		return dal_adapter_service_create_hw_ctx_dce110(ctx);
+#endif
 #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
 	case DCE_VERSION_11_0:
 		return dal_adapter_service_create_hw_ctx_dce110(ctx);
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
index 5e01a86..8491b38 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
@@ -9,6 +9,18 @@ AMD_DAL_ASIC_CAPABILITY = \
 
 AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY)
 
+###############################################################################
+# DCE 10x
+###############################################################################
+ifdef CONFIG_DRM_AMD_DAL_DCE10_0
+ASIC_CAPABILITY_DCE10 = tonga_asic_capability.o
+
+AMD_DAL_ASIC_CAPABILITY_DCE10 = \
+	$(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE10))
+
+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE10)
+endif
+
 
 ###############################################################################
 # DCE 11x
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
index a532e2f..b3eb665 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
@@ -32,6 +32,9 @@
 #include "include/dal_types.h"
 #include "include/dal_asic_id.h"
 
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+#include "tonga_asic_capability.h"
+#endif
 
 #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
 #include "carrizo_asic_capability.h"
@@ -97,7 +100,16 @@ static bool construct(
 		asic_supported = true;
 #endif
 		break;
-
+ 	case FAMILY_VI:
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+		if (ASIC_REV_IS_TONGA_P(init->hw_internal_rev) ||
+				ASIC_REV_IS_FIJI_P(init->hw_internal_rev)) {
+			tonga_asic_capability_create(cap, init);
+			asic_supported = true;
+			break;
+		}
+#endif
+		break;
 	default:
 		/* unsupported "chip_family" */
 		break;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
index f57d3f7..b106ccc 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
@@ -49,6 +49,7 @@ void carrizo_asic_capability_create(struct asic_capability *cap,
 	uint32_t e_fuse_setting;
 	/* ASIC data */
 	cap->data[ASIC_DATA_CONTROLLERS_NUM] = 3;
+	cap->data[ASIC_DATA_DIGFE_NUM] = 3;
 	cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 3;
 	cap->data[ASIC_DATA_LINEBUFFER_NUM] = 3;
 	cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
new file mode 100644
index 0000000..599c47d
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dal_services.h"
+
+#include "include/asic_capability_interface.h"
+#include "include/asic_capability_types.h"
+
+#include "tonga_asic_capability.h"
+
+#include "atom.h"
+#include "dce/dce_10_0_d.h"
+#include "smu/smu_8_0_d.h"
+#include "dce/dce_10_0_sh_mask.h"
+#include "dal_asic_id.h"
+
+#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS     0xC0014074
+
+/*
+ * carrizo_asic_capability_create
+ *
+ * Create and initiate Carrizo capability.
+ */
+void tonga_asic_capability_create(struct asic_capability *cap,
+	struct hw_asic_id *init)
+{
+	uint32_t e_fuse_setting;
+	/* ASIC data */
+	cap->data[ASIC_DATA_CONTROLLERS_NUM] = 6;
+	cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 6;
+	cap->data[ASIC_DATA_DIGFE_NUM] = 6;
+	cap->data[ASIC_DATA_LINEBUFFER_NUM] = 6;
+
+	cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
+	cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
+	cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 3;
+	cap->data[ASIC_DATA_MC_LATENCY] = 5000;
+	cap->data[ASIC_DATA_STUTTERMODE] = 0x2002;
+	cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
+	cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
+	cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 3;
+	cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
+
+	cap->data[ASIC_DATA_DCE_VERSION] = 0x100; /* DCE 11 */
+
+	cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 2;
+	cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
+	cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 40;
+	cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 1;
+
+
+	/* ASIC basic capability */
+	cap->caps.IS_FUSION = true;
+	cap->caps.DP_MST_SUPPORTED = true;
+	cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
+	cap->caps.MIRABILIS_SUPPORTED = true;
+	cap->caps.NO_VCC_OFF_HPD_POLLING = true;
+	cap->caps.VCE_SUPPORTED = true;
+	cap->caps.HPD_CHECK_FOR_EDID = true;
+	cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = true;
+	cap->caps.SUPPORT_8BPP = false;
+
+	/* ASIC stereo 3d capability */
+	cap->stereo_3d_caps.DISPLAY_BASED_ON_WS = true;
+	cap->stereo_3d_caps.HDMI_FRAME_PACK = true;
+	cap->stereo_3d_caps.INTERLACE_FRAME_PACK = true;
+	cap->stereo_3d_caps.DISPLAYPORT_FRAME_PACK = true;
+	cap->stereo_3d_caps.DISPLAYPORT_FRAME_ALT = true;
+	cap->stereo_3d_caps.INTERLEAVE = true;
+
+	e_fuse_setting = dal_read_index_reg(cap->ctx, CGS_IND_REG__SMC,
+			ixVCE_HARVEST_FUSE_MACRO__ADDRESS);
+
+	/* Bits [28:27]*/
+	switch ((e_fuse_setting >> 27) & 0x3) {
+	case 0:
+		/* both VCE engine are working*/
+		cap->caps.VCE_SUPPORTED = true;
+		cap->caps.WIRELESS_TIMING_ADJUSTMENT = false;
+		/*
+		 * TODO:
+		 * cap->caps.wirelessLowVCEPerformance = false;
+		 * m_AsicCaps.vceInstance0Enabled = true;
+		 * m_AsicCaps.vceInstance1Enabled = true;
+		 */
+		cap->caps.NEED_MC_TUNING = true;
+		break;
+
+	case 1:
+		cap->caps.VCE_SUPPORTED = true;
+		cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
+		/*
+		 * TODO:
+		 * m_AsicCaps.wirelessLowVCEPerformance = false;
+		 * m_AsicCaps.vceInstance1Enabled = true;
+		 */
+		cap->caps.NEED_MC_TUNING = true;
+		break;
+
+	case 2:
+		cap->caps.VCE_SUPPORTED = true;
+		cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
+		/*
+		 * TODO:
+		 * m_AsicCaps.wirelessLowVCEPerformance = false;
+		 * m_AsicCaps.vceInstance0Enabled = true;
+		 */
+		cap->caps.NEED_MC_TUNING = true;
+		break;
+
+	case 3:
+		/*
+		 * VCE_DISABLE = 0x3  - both VCE
+		 * instances are in harvesting,
+		 * no VCE supported any more.
+		 */
+		cap->caps.VCE_SUPPORTED = false;
+		break;
+
+	default:
+		break;
+	}
+
+
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h
new file mode 100644
index 0000000..ca6d683
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h
@@ -0,0 +1,18 @@
+/*
+ * tonga_asic_capability.h
+ *
+ *  Created on: 2016-01-18
+ *      Author: qyang
+ */
+
+#ifndef TONGA_ASIC_CAPABILITY_H_
+#define TONGA_ASIC_CAPABILITY_H_
+
+/* Forward declaration */
+struct asic_capability;
+
+/* Create and initialize Carrizo data */
+void tonga_asic_capability_create(struct asic_capability *cap,
+	struct hw_asic_id *init);
+
+#endif /* TONGA_ASIC_CAPABILITY_H_ */
diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
index f553b7a..2737851 100644
--- a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
@@ -264,6 +264,10 @@ struct audio *dal_audio_create(
 
 	as = init_data->as;
 	switch (dal_adapter_service_get_dce_version(as)) {
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+	case DCE_VERSION_10_0:
+		return dal_audio_create_dce110(init_data);
+#endif
 #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
 	case DCE_VERSION_11_0:
 		return dal_audio_create_dce110(init_data);
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
index a0927cf..da559b0 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
@@ -39,6 +39,12 @@ bool dal_bios_parser_init_bios_helper(
 {
 	switch (version) {
 
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+	case DCE_VERSION_10_0:
+		bp->bios_helper = dal_bios_parser_helper_dce110_get_table();
+		return true;
+
+#endif
 #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
 	case DCE_VERSION_11_0:
 		bp->bios_helper = dal_bios_parser_helper_dce110_get_table();
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
index d0e9de9..1ad7455 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
@@ -26,7 +26,7 @@
 #ifndef __DAL_BIOS_PARSER_HELPER_H__
 #define __DAL_BIOS_PARSER_HELPER_H__
 
-#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0) || defined(CONFIG_DRM_AMD_DAL_DCE10_0)
 #include "dce110/bios_parser_helper_dce110.h"
 #endif
 
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
index 51027c5..e0407f4 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
@@ -38,6 +38,12 @@ bool dal_bios_parser_init_cmd_tbl_helper(
 {
 	switch (dce) {
 
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+	case DCE_VERSION_10_0:
+		*h = dal_cmd_tbl_helper_dce110_get_table();
+		return true;
+#endif
+
 #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
 	case DCE_VERSION_11_0:
 		*h = dal_cmd_tbl_helper_dce110_get_table();
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
index cf563ce..4646cab 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
@@ -26,7 +26,7 @@
 #ifndef __DAL_COMMAND_TABLE_HELPER_H__
 #define __DAL_COMMAND_TABLE_HELPER_H__
 
-#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0) || defined(CONFIG_DRM_AMD_DAL_DCE10_0)
 #include "dce110/command_table_helper_dce110.h"
 #endif
 
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
index b9e6ffd..2cac267 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
@@ -37,6 +37,10 @@ bool dc_construct_hw_sequencer(
 
 	switch (dce_ver)
 	{
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+	case DCE_VERSION_10_0:
+		return dce110_hw_sequencer_construct(dc);
+#endif
 #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
 	case DCE_VERSION_11_0:
 		return dce110_hw_sequencer_construct(dc);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
index 3eaced4..b4e8467 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
@@ -1126,6 +1126,15 @@ bool dce110_link_encoder_construct(
 	case TRANSMITTER_UNIPHY_C:
 		enc110->base.preferred_engine = ENGINE_ID_DIGC;
 	break;
+	case TRANSMITTER_UNIPHY_D:
+		enc110->base.preferred_engine = ENGINE_ID_DIGD;
+	break;
+	case TRANSMITTER_UNIPHY_E:
+		enc110->base.preferred_engine = ENGINE_ID_DIGE;
+	break;
+	case TRANSMITTER_UNIPHY_F:
+		enc110->base.preferred_engine = ENGINE_ID_DIGF;
+	break;
 	default:
 		ASSERT_CRITICAL(false);
 		enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
index 410b52f..3fd12eb 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
@@ -52,6 +52,19 @@ static const struct dce110_opp_reg_offsets reg_offsets[] = {
 {	.fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
 	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
 	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+},
+{
+	.fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
+	.dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
+	.dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+},
+{	.fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
+	.dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
+	.dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+},
+{	.fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
+	.dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
+	.dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
 }
 };
 
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index c43dd07..96f4423 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -61,6 +61,18 @@ static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
 	{
 		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
+	},
+	{
+		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
+		.dcp =  (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
+	},
+	{
+		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
+		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
+	},
+	{
+		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
+		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 	}
 };
 
@@ -146,10 +158,18 @@ static const struct dce110_ipp_reg_offsets dce110_ipp_reg_offsets[] = {
 },
 {
 	.dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL),
+},
+{
+	.dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL),
+},
+{
+	.dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL),
+},
+{
+	.dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL),
 }
 };
 
-
 static struct timing_generator *dce110_timing_generator_create(
 		struct adapter_service *as,
 		struct dc_context *ctx,
@@ -296,6 +316,9 @@ bool dce110_construct_resource_pool(
 	pool->stream_engines.engine.ENGINE_ID_DIGA = 1;
 	pool->stream_engines.engine.ENGINE_ID_DIGB = 1;
 	pool->stream_engines.engine.ENGINE_ID_DIGC = 1;
+	pool->stream_engines.engine.ENGINE_ID_DIGD = 1;
+	pool->stream_engines.engine.ENGINE_ID_DIGE = 1;
+	pool->stream_engines.engine.ENGINE_ID_DIGF = 1;
 
 	clk_src_init_data.as = adapter_serv;
 	clk_src_init_data.ctx = ctx;
@@ -342,7 +365,8 @@ bool dce110_construct_resource_pool(
 
 	pool->controller_count =
 		dal_adapter_service_get_func_controllers_num(adapter_serv);
-	pool->stream_enc_count = 3;
+	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(
+			adapter_serv);
 	pool->scaler_filter = dal_scaler_filter_create(ctx);
 	if (pool->scaler_filter == NULL) {
 		BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
index a01024e..7e93014 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
@@ -66,6 +66,11 @@ bool dal_hw_factory_init(
 
 	switch (dce_version) {
 
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+	case DCE_VERSION_10_0:
+		dal_hw_factory_dce110_init(factory);
+		return true;
+#endif
 #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
 	case DCE_VERSION_11_0:
 		dal_hw_factory_dce110_init(factory);
diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
index d49e952..0e768df 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
@@ -67,6 +67,9 @@ bool dal_hw_translate_init(
 	switch (dce_version) {
 
 #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+	case DCE_VERSION_10_0:
+#endif
 	case DCE_VERSION_11_0:
 		dal_hw_translate_dce110_init(translate);
 		return true;
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
index cd4a91e..a2e618e 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
@@ -34,7 +34,7 @@
 #include "clock_source.h"
 #include "pll_clock_source.h"
 
-#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0) || defined(CONFIG_DRM_AMD_DAL_DCE10_0)
 #include "dce110/ext_clock_source_dce110.h"
 #include "dce110/pll_clock_source_dce110.h"
 #include "dce110/vce_clock_source_dce110.h"
@@ -53,6 +53,9 @@ struct clock_source *dal_clock_source_create(
 
 #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
 	break;
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+	case DCE_VERSION_10_0:
+#endif
 	case DCE_VERSION_11_0:
 	{
 		switch (clk_src_id) {
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
index 80f7da7..ae70e41 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
@@ -314,7 +314,7 @@ static bool construct(
 	controllers_num = dal_adapter_service_get_controllers_num(
 			base->adapter_service);
 
-	if (controllers_num <= 0 || controllers_num > 3) {
+	if (controllers_num <= 0 || controllers_num > 6) {
 		ECS_ERROR("ECS110:Invalid number of controllers = %d!\n",
 				controllers_num);
 		return false;
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
index 6de108c..941213d 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
@@ -49,7 +49,7 @@
  * This unit
  */
 
-#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0) || defined(CONFIG_DRM_AMD_DAL_DCE10_0)
 #include "dce110/i2caux_dce110.h"
 #endif
 
@@ -84,6 +84,9 @@ struct i2caux *dal_i2caux_create(
 
 	switch (dce_version) {
 #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+	case DCE_VERSION_10_0:
+#endif
 	case DCE_VERSION_11_0:
 		return dal_i2caux_dce110_create(as, ctx);
 #endif
diff --git a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
index 0c7429c..b54e813 100644
--- a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
@@ -50,6 +50,10 @@ struct irq_service *dal_irq_service_create(
 	struct irq_service_init_data *init_data)
 {
 	switch (version) {
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+	case DCE_VERSION_10_0:
+		return dal_irq_service_dce110_create(init_data);
+#endif
 #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
 	case DCE_VERSION_11_0:
 		return dal_irq_service_dce110_create(init_data);
diff --git a/drivers/gpu/drm/amd/dal/include/dal_asic_id.h b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
index fa04f80..78f88b1 100644
--- a/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
@@ -77,6 +77,17 @@
 #define ASIC_REV_IS_GODAVARI(rev) \
 	((rev >= ML_GODAVARI_A0) && (rev < KV_UNKNOWN))
 
+/* VI Family */
+/* DCE10 */
+#define VI_TONGA_P_A0 20
+#define VI_TONGA_P_A1 21
+#define VI_FIJI_P_A0 60
+
+#define ASIC_REV_IS_TONGA_P(eChipRev) ((eChipRev >= VI_TONGA_P_A0) && \
+		(eChipRev < 40))
+#define ASIC_REV_IS_FIJI_P(eChipRev) ((eChipRev >= VI_FIJI_P_A0) && \
+		(eChipRev < 80))
+
 /* DCE11 */
 #define CZ_CARRIZO_A0 0x01
 
diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
index f756d36..8e54862 100644
--- a/drivers/gpu/drm/amd/dal/include/dal_types.h
+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
@@ -34,6 +34,9 @@ struct dc_bios;
 
 enum dce_version {
 	DCE_VERSION_UNKNOWN = (-1),
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+	DCE_VERSION_10_0,
+#endif
 #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
 	DCE_VERSION_11_0,
 #endif
-- 
2.7.4