From dd89e7c818be7eb788e95c9ceeaf44daf2a5e45b Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Wed, 30 Mar 2016 18:30:16 -0400 Subject: [PATCH 0994/1110] drm/amd/dal: Don't wait in software for double buffered registers update. It's not necessary. Signed-off-by: Andrey Grodzovsky Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c | 91 ----------------- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 96 +----------------- .../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c | 109 --------------------- .../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c | 79 --------------- 4 files changed, 1 insertion(+), 374 deletions(-) diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c index 467f322..a2a4f2a 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c @@ -118,7 +118,6 @@ static bool dce100_pipe_control_lock( { uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx); uint32_t value = dm_read_reg(ctx, addr); - bool need_to_wait = false; if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) set_reg_field_value( @@ -147,7 +146,6 @@ static bool dce100_pipe_control_lock( lock, BLND_V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK); - need_to_wait = true; } if (control_mask & PIPE_LOCK_CONTROL_MODE) @@ -159,95 +157,6 @@ static bool dce100_pipe_control_lock( dm_write_reg(ctx, addr, value); - if (!lock && need_to_wait) { - uint8_t counter = 0; - const uint8_t counter_limit = 100; - const uint16_t delay_us = 1000; - - uint8_t pipe_pending; - - addr = HW_REG_BLND(mmBLND_REG_UPDATE_STATUS, - controller_idx); - - while (counter < counter_limit) { - value = dm_read_reg(ctx, addr); - - pipe_pending = 0; - - if (control_mask & PIPE_LOCK_CONTROL_BLENDER) { - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - BLND_BLNDC_UPDATE_PENDING); - pipe_pending |= get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - BLND_BLNDO_UPDATE_PENDING); - } - - if (control_mask & PIPE_LOCK_CONTROL_SCL) { - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - SCL_BLNDC_UPDATE_PENDING); - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - SCL_BLNDO_UPDATE_PENDING); - } - if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) { - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDC_GRPH_UPDATE_PENDING); - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDO_GRPH_UPDATE_PENDING); - } - if (control_mask & PIPE_LOCK_CONTROL_SURFACE) { - pipe_pending |= get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDC_GRPH_SURF_UPDATE_PENDING); - pipe_pending |= get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDO_GRPH_SURF_UPDATE_PENDING); - } - - if (pipe_pending == 0) - break; - - counter++; - udelay(delay_us); - } - - if (counter == counter_limit) { - dal_logger_write( - ctx->logger, - LOG_MAJOR_WARNING, - LOG_MINOR_COMPONENT_CONTROLLER, - "%s: wait for update exceeded (wait %d us)\n", - __func__, - counter * delay_us); - dal_logger_write( - ctx->logger, - LOG_MAJOR_WARNING, - LOG_MINOR_COMPONENT_CONTROLLER, - "%s: control %d, remain value %x\n", - __func__, - control_mask, - value); - } else { - /* OK. */ - } - } return true; } diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c index 9ca604d..e5cb1aa 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c @@ -215,7 +215,6 @@ static bool dce110_pipe_control_lock( { uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx); uint32_t value = dm_read_reg(ctx, addr); - bool need_to_wait = false; if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) set_reg_field_value( @@ -244,7 +243,6 @@ static bool dce110_pipe_control_lock( lock, BLND_V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK); - need_to_wait = true; } if (control_mask & PIPE_LOCK_CONTROL_MODE) @@ -256,97 +254,6 @@ static bool dce110_pipe_control_lock( dm_write_reg(ctx, addr, value); - need_to_wait = false;/*todo: mpo optimization remove*/ - if (!lock && need_to_wait) { - uint8_t counter = 0; - const uint8_t counter_limit = 100; - const uint16_t delay_us = 1000; - - uint8_t pipe_pending; - - addr = HW_REG_BLND(mmBLND_REG_UPDATE_STATUS, - controller_idx); - - while (counter < counter_limit) { - value = dm_read_reg(ctx, addr); - - pipe_pending = 0; - - if (control_mask & PIPE_LOCK_CONTROL_BLENDER) { - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - BLND_BLNDC_UPDATE_PENDING); - pipe_pending |= get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - BLND_BLNDO_UPDATE_PENDING); - } - - if (control_mask & PIPE_LOCK_CONTROL_SCL) { - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - SCL_BLNDC_UPDATE_PENDING); - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - SCL_BLNDO_UPDATE_PENDING); - } - if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) { - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDC_GRPH_UPDATE_PENDING); - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDO_GRPH_UPDATE_PENDING); - } - if (control_mask & PIPE_LOCK_CONTROL_SURFACE) { - pipe_pending |= get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDC_GRPH_SURF_UPDATE_PENDING); - pipe_pending |= get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDO_GRPH_SURF_UPDATE_PENDING); - } - - if (pipe_pending == 0) - break; - - counter++; - udelay(delay_us); - } - - if (counter == counter_limit) { - dal_logger_write( - ctx->logger, - LOG_MAJOR_WARNING, - LOG_MINOR_COMPONENT_CONTROLLER, - "%s: wait for update exceeded (wait %d us)\n", - __func__, - counter * delay_us); - dal_logger_write( - ctx->logger, - LOG_MAJOR_WARNING, - LOG_MINOR_COMPONENT_CONTROLLER, - "%s: control %d, remain value %x\n", - __func__, - control_mask, - value); - } else { - /* OK. */ - } - } - if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER)) trigger_write_crtc_h_blank_start_end(ctx, controller_idx); @@ -1505,7 +1412,7 @@ static void update_plane_addrs(struct core_dc *dc, struct resource_context *res_ PIPE_LOCK_CONTROL_SURFACE, true); - pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( + pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( pipe_ctx->mi, &surface->public.address, surface->public.flip_immediate); @@ -1521,7 +1428,6 @@ static void update_plane_addrs(struct core_dc *dc, struct resource_context *res_ PIPE_LOCK_CONTROL_SURFACE, false); - if (surface->public.flip_immediate) pipe_ctx->mi->funcs->wait_for_no_surface_update_pending(pipe_ctx->mi); diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c index 0a7e82b..b887764 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c +++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c @@ -122,19 +122,6 @@ static void dce112_enable_fe_clock( dm_write_reg(ctx, addr, value); } -/* this is a workaround for hw bug - it is a trigger on r/w */ -static void trigger_write_crtc_h_blank_start_end( - struct dc_context *ctx, - uint8_t controller_id) -{ - uint32_t value; - uint32_t addr; - - addr = HW_REG_CRTC(mmCRTC_H_BLANK_START_END, controller_id); - value = dm_read_reg(ctx, addr); - dm_write_reg(ctx, addr, value); -} - static bool dce112_pipe_control_lock( struct dc_context *ctx, uint8_t controller_idx, @@ -143,7 +130,6 @@ static bool dce112_pipe_control_lock( { uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx); uint32_t value = dm_read_reg(ctx, addr); - bool need_to_wait = false; if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) set_reg_field_value( @@ -172,7 +158,6 @@ static bool dce112_pipe_control_lock( lock, BLND_V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK); - need_to_wait = true; } if (control_mask & PIPE_LOCK_CONTROL_MODE) @@ -184,100 +169,6 @@ static bool dce112_pipe_control_lock( dm_write_reg(ctx, addr, value); - need_to_wait = false;/*todo: mpo optimization remove*/ - if (!lock && need_to_wait) { - uint8_t counter = 0; - const uint8_t counter_limit = 100; - const uint16_t delay_us = 1000; - - uint8_t pipe_pending; - - addr = HW_REG_BLND(mmBLND_REG_UPDATE_STATUS, - controller_idx); - - while (counter < counter_limit) { - value = dm_read_reg(ctx, addr); - - pipe_pending = 0; - - if (control_mask & PIPE_LOCK_CONTROL_BLENDER) { - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - BLND_BLNDC_UPDATE_PENDING); - pipe_pending |= get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - BLND_BLNDO_UPDATE_PENDING); - } - - if (control_mask & PIPE_LOCK_CONTROL_SCL) { - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - SCL_BLNDC_UPDATE_PENDING); - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - SCL_BLNDO_UPDATE_PENDING); - } - if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) { - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDC_GRPH_UPDATE_PENDING); - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDO_GRPH_UPDATE_PENDING); - } - if (control_mask & PIPE_LOCK_CONTROL_SURFACE) { - pipe_pending |= get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDC_GRPH_SURF_UPDATE_PENDING); - pipe_pending |= get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDO_GRPH_SURF_UPDATE_PENDING); - } - - if (pipe_pending == 0) - break; - - counter++; - udelay(delay_us); - } - - if (counter == counter_limit) { - dal_logger_write( - ctx->logger, - LOG_MAJOR_WARNING, - LOG_MINOR_COMPONENT_CONTROLLER, - "%s: wait for update exceeded (wait %d us)\n", - __func__, - counter * delay_us); - dal_logger_write( - ctx->logger, - LOG_MAJOR_WARNING, - LOG_MINOR_COMPONENT_CONTROLLER, - "%s: control %d, remain value %x\n", - __func__, - control_mask, - value); - } else { - /* OK. */ - } - } - - if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER)) - trigger_write_crtc_h_blank_start_end(ctx, controller_idx); - return true; } diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c index 02d7508..68cf84d 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c +++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c @@ -122,7 +122,6 @@ static bool dce80_pipe_control_lock( { uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx); uint32_t value = dm_read_reg(ctx, addr); - bool need_to_wait = false; if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) set_reg_field_value( @@ -147,84 +146,6 @@ static bool dce80_pipe_control_lock( dm_write_reg(ctx, addr, value); - if (!lock && need_to_wait) { - uint8_t counter = 0; - const uint8_t counter_limit = 100; - const uint16_t delay_us = 1000; - - uint8_t pipe_pending; - - addr = HW_REG_BLND(mmBLND_REG_UPDATE_STATUS, - controller_idx); - - while (counter < counter_limit) { - value = dm_read_reg(ctx, addr); - - pipe_pending = 0; - - if (control_mask & PIPE_LOCK_CONTROL_SCL) { - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - SCL_BLNDc_UPDATE_PENDING); - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - SCL_BLNDo_UPDATE_PENDING); - } - if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) { - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDc_GRPH_UPDATE_PENDING); - pipe_pending |= - get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDo_GRPH_UPDATE_PENDING); - } - if (control_mask & PIPE_LOCK_CONTROL_SURFACE) { - pipe_pending |= get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDc_GRPH_SURF_UPDATE_PENDING); - pipe_pending |= get_reg_field_value( - value, - BLND_REG_UPDATE_STATUS, - DCP_BLNDo_GRPH_SURF_UPDATE_PENDING); - } - - if (pipe_pending == 0) - break; - - counter++; - udelay(delay_us); - } - - if (counter == counter_limit) { - dal_logger_write( - ctx->logger, - LOG_MAJOR_WARNING, - LOG_MINOR_COMPONENT_CONTROLLER, - "%s: wait for update exceeded (wait %d us)\n", - __func__, - counter * delay_us); - dal_logger_write( - ctx->logger, - LOG_MAJOR_WARNING, - LOG_MINOR_COMPONENT_CONTROLLER, - "%s: control %d, remain value %x\n", - __func__, - control_mask, - value); - } else { - /* OK. */ - } - } - return true; } -- 2.7.4