From 7e29b00f72a005621d2f8f022d282a68c08bb370 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Tue, 1 Mar 2016 17:01:30 +0800 Subject: [PATCH 0950/1110] drm/amd/powerplay: print gpu loading and uvd/vce power gate enablement for polaris10/11. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c index 5080d67..ac40599 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c @@ -3646,7 +3646,9 @@ static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr, static void polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m) { - uint32_t sclk, mclk; + uint32_t sclk, mclk, activity_percent; + uint32_t offset; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); @@ -3657,6 +3659,17 @@ polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file * mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", mclk / 100, sclk / 100); + + offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity); + activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset); + activity_percent += 0x80; + activity_percent >>= 8; + + seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent); + + seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en"); + + seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en"); } static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) -- 2.7.4