From 4f67f6f7f0a5a267d342bdf8ce7146a6ca04e0ac Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 14 Mar 2016 18:33:29 -0400 Subject: [PATCH 0949/1110] drm/amdgpu: change ELM/BAF to Polaris10/Polaris11 Adjust to preferred code names. Signed-off-by: Flora Cui Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 16 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 20 +- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 16 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 16 +- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 36 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 116 +- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 28 +- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 32 +- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/vi.c | 22 +- drivers/gpu/drm/amd/include/amd_shared.h | 4 +- drivers/gpu/drm/amd/include/atombios.h | 6 +- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 4 +- .../powerplay/hwmgr/ellesmere_clockpowergating.c | 428 - .../powerplay/hwmgr/ellesmere_clockpowergating.h | 40 - .../amd/powerplay/hwmgr/ellesmere_dyn_defaults.h | 62 - .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c | 4711 --------- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h | 354 - .../drm/amd/powerplay/hwmgr/ellesmere_powertune.c | 396 - .../drm/amd/powerplay/hwmgr/ellesmere_powertune.h | 70 - .../drm/amd/powerplay/hwmgr/ellesmere_thermal.c | 711 -- .../drm/amd/powerplay/hwmgr/ellesmere_thermal.h | 62 - drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 8 +- .../powerplay/hwmgr/polaris10_clockpowergating.c | 428 + .../powerplay/hwmgr/polaris10_clockpowergating.h | 40 + .../amd/powerplay/hwmgr/polaris10_dyn_defaults.h | 62 + .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 4844 +++++++++ .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h | 354 + .../drm/amd/powerplay/hwmgr/polaris10_powertune.c | 396 + .../drm/amd/powerplay/hwmgr/polaris10_powertune.h | 70 + .../drm/amd/powerplay/hwmgr/polaris10_thermal.c | 711 ++ .../drm/amd/powerplay/hwmgr/polaris10_thermal.h | 62 + .../gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h | 10 +- .../amd/powerplay/hwmgr/tonga_processpptables.c | 4 +- .../gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h | 401 - .../gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h | 10088 ------------------- .../gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h | 409 + .../gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h | 10088 +++++++++++++++++++ drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h | 42 + drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +- .../drm/amd/powerplay/smumgr/ellesmere_smumgr.c | 983 -- .../drm/amd/powerplay/smumgr/ellesmere_smumgr.h | 68 - .../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 983 ++ .../drm/amd/powerplay/smumgr/polaris10_smumgr.h | 68 + drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 8 +- 47 files changed, 18742 insertions(+), 18557 deletions(-) delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h delete mode 100644 drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h delete mode 100644 drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h create mode 100644 drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h create mode 100644 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h delete mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c delete mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index e066817..837cdd2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -681,8 +681,8 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type) result = AMDGPU_UCODE_ID_CP_MEC1; break; case CGS_UCODE_ID_CP_MEC_JT2: - if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_BAFFIN - || adev->asic_type == CHIP_ELLESMERE) + if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_POLARIS11 + || adev->asic_type == CHIP_POLARIS10) result = AMDGPU_UCODE_ID_CP_MEC2; else result = AMDGPU_UCODE_ID_CP_MEC1; @@ -742,17 +742,17 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, case CHIP_FIJI: strcpy(fw_name, "amdgpu/fiji_smc.bin"); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: if (type == CGS_UCODE_ID_SMU) - strcpy(fw_name, "amdgpu/baffin_smc.bin"); + strcpy(fw_name, "amdgpu/polaris11_smc.bin"); else if (type == CGS_UCODE_ID_SMU_SK) - strcpy(fw_name, "amdgpu/baffin_smc_sk.bin"); + strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin"); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: if (type == CGS_UCODE_ID_SMU) - strcpy(fw_name, "amdgpu/ellesmere_smc.bin"); + strcpy(fw_name, "amdgpu/polaris10_smc.bin"); else if (type == CGS_UCODE_ID_SMU_SK) - strcpy(fw_name, "amdgpu/ellesmere_smc_sk.bin"); + strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin"); break; default: DRM_ERROR("SMC firmware not supported\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 51703e7..b73533d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -61,8 +61,8 @@ static const char *amdgpu_asic_name[] = { "FIJI", "CARRIZO", "STONEY", - "ELLESMERE", - "BAFFIN", + "POLARIS10", + "POLARIS11", "LAST", }; @@ -1153,8 +1153,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev) case CHIP_TOPAZ: case CHIP_TONGA: case CHIP_FIJI: - case CHIP_BAFFIN: - case CHIP_ELLESMERE: + case CHIP_POLARIS11: + case CHIP_POLARIS10: case CHIP_CARRIZO: case CHIP_STONEY: if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 7cb8118..30e8c46 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -281,16 +281,16 @@ static const struct pci_device_id pciidlist[] = { {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, /* stoney */ {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, - /* Baffin */ - {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - /* Ellesmere */ - {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ELLESMERE}, - {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ELLESMERE}, + /* Polaris11 */ + {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + /* Polaris10 */ + {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, + {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, {0, 0, 0} }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c index ea2006a..f315995 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c @@ -99,10 +99,12 @@ static int amdgpu_pp_early_init(void *handle) #ifdef CONFIG_DRM_AMD_POWERPLAY switch (adev->asic_type) { + case CHIP_POLARIS11: + case CHIP_POLARIS10: + adev->pp_enabled = true; + break; case CHIP_TONGA: case CHIP_FIJI: - case CHIP_BAFFIN: - case CHIP_ELLESMERE: adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true; break; case CHIP_CARRIZO: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 239b764..b5b5ff3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -54,8 +54,8 @@ #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" -#define FIRMWARE_ELLESMERE "amdgpu/ellesmere_uvd.bin" -#define FIRMWARE_BAFFIN "amdgpu/baffin_uvd.bin" +#define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" +#define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" /** * amdgpu_uvd_cs_ctx - Command submission parser context @@ -87,8 +87,8 @@ MODULE_FIRMWARE(FIRMWARE_TONGA); MODULE_FIRMWARE(FIRMWARE_CARRIZO); MODULE_FIRMWARE(FIRMWARE_FIJI); MODULE_FIRMWARE(FIRMWARE_STONEY); -MODULE_FIRMWARE(FIRMWARE_ELLESMERE); -MODULE_FIRMWARE(FIRMWARE_BAFFIN); +MODULE_FIRMWARE(FIRMWARE_POLARIS10); +MODULE_FIRMWARE(FIRMWARE_POLARIS11); static void amdgpu_uvd_note_usage(struct amdgpu_device *adev); static void amdgpu_uvd_idle_work_handler(struct work_struct *work); @@ -135,11 +135,11 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) case CHIP_STONEY: fw_name = FIRMWARE_STONEY; break; - case CHIP_ELLESMERE: - fw_name = FIRMWARE_ELLESMERE; + case CHIP_POLARIS10: + fw_name = FIRMWARE_POLARIS10; break; - case CHIP_BAFFIN: - fw_name = FIRMWARE_BAFFIN; + case CHIP_POLARIS11: + fw_name = FIRMWARE_POLARIS11; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 2904842..199f5cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -50,8 +50,8 @@ #define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin" #define FIRMWARE_FIJI "amdgpu/fiji_vce.bin" #define FIRMWARE_STONEY "amdgpu/stoney_vce.bin" -#define FIRMWARE_ELLESMERE "amdgpu/ellesmere_vce.bin" -#define FIRMWARE_BAFFIN "amdgpu/baffin_vce.bin" +#define FIRMWARE_POLARIS10 "amdgpu/polaris10_vce.bin" +#define FIRMWARE_POLARIS11 "amdgpu/polaris11_vce.bin" #ifdef CONFIG_DRM_AMDGPU_CIK MODULE_FIRMWARE(FIRMWARE_BONAIRE); @@ -64,8 +64,8 @@ MODULE_FIRMWARE(FIRMWARE_TONGA); MODULE_FIRMWARE(FIRMWARE_CARRIZO); MODULE_FIRMWARE(FIRMWARE_FIJI); MODULE_FIRMWARE(FIRMWARE_STONEY); -MODULE_FIRMWARE(FIRMWARE_ELLESMERE); -MODULE_FIRMWARE(FIRMWARE_BAFFIN); +MODULE_FIRMWARE(FIRMWARE_POLARIS10); +MODULE_FIRMWARE(FIRMWARE_POLARIS11); static void amdgpu_vce_idle_work_handler(struct work_struct *work); @@ -117,11 +117,11 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) case CHIP_STONEY: fw_name = FIRMWARE_STONEY; break; - case CHIP_ELLESMERE: - fw_name = FIRMWARE_ELLESMERE; + case CHIP_POLARIS10: + fw_name = FIRMWARE_POLARIS10; break; - case CHIP_BAFFIN: - fw_name = FIRMWARE_BAFFIN; + case CHIP_POLARIS11: + fw_name = FIRMWARE_POLARIS11; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index bcb8626..e47b252 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -132,7 +132,7 @@ static const u32 stoney_golden_settings_a11[] = mmFBC_MISC, 0x1f311fff, 0x14302000, }; -static const u32 baffin_golden_settings_a11[] = +static const u32 polaris11_golden_settings_a11[] = { mmDCI_CLK_CNTL, 0x00000080, 0x00000000, mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, @@ -141,7 +141,7 @@ static const u32 baffin_golden_settings_a11[] = mmHDMI_CONTROL, 0x313f031f, 0x00000011, }; -static const u32 ellesmere_golden_settings_a11[] = +static const u32 polaris10_golden_settings_a11[] = { mmDCI_CLK_CNTL, 0x00000080, 0x00000000, mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, @@ -165,15 +165,15 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) stoney_golden_settings_a11, (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_program_register_sequence(adev, - baffin_golden_settings_a11, - (const u32)ARRAY_SIZE(baffin_golden_settings_a11)); + polaris11_golden_settings_a11, + (const u32)ARRAY_SIZE(polaris11_golden_settings_a11)); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, - ellesmere_golden_settings_a11, - (const u32)ARRAY_SIZE(ellesmere_golden_settings_a11)); + polaris10_golden_settings_a11, + (const u32)ARRAY_SIZE(polaris10_golden_settings_a11)); break; default: break; @@ -1610,10 +1610,10 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev) case CHIP_CARRIZO: adev->mode_info.audio.num_pins = 7; break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: adev->mode_info.audio.num_pins = 8; break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: adev->mode_info.audio.num_pins = 6; break; default: @@ -2410,8 +2410,8 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) u32 pll_in_use; int pll; - if ((adev->asic_type == CHIP_ELLESMERE) || - (adev->asic_type == CHIP_BAFFIN)) { + if ((adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) { if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) return ATOM_DP_DTO; /* use the same PPLL for all monitors with the same clock */ @@ -2811,8 +2811,8 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, if (!amdgpu_crtc->adjusted_clock) return -EINVAL; - if ((adev->asic_type == CHIP_ELLESMERE) || - (adev->asic_type == CHIP_BAFFIN)) { + if ((adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(amdgpu_crtc->encoder); int encoder_mode = @@ -2977,12 +2977,12 @@ static int dce_v11_0_early_init(void *handle) adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: adev->mode_info.num_crtc = 5; adev->mode_info.num_hpd = 5; adev->mode_info.num_dig = 5; @@ -3089,8 +3089,8 @@ static int dce_v11_0_hw_init(void *handle) /* init dig PHYs, disp eng pll */ amdgpu_atombios_crtc_powergate_init(adev); amdgpu_atombios_encoder_init_dig(adev); - if ((adev->asic_type == CHIP_ELLESMERE) || - (adev->asic_type == CHIP_BAFFIN)) { + if ((adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) { amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS); amdgpu_atombios_crtc_set_dce_clock(adev, 0, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 4cd0d19..b043dd6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -52,7 +52,7 @@ #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 -#define BAFFIN_GB_ADDR_CONFIG_GOLDEN 0x22011002 +#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) @@ -121,19 +121,19 @@ MODULE_FIRMWARE("amdgpu/fiji_mec.bin"); MODULE_FIRMWARE("amdgpu/fiji_mec2.bin"); MODULE_FIRMWARE("amdgpu/fiji_rlc.bin"); -MODULE_FIRMWARE("amdgpu/baffin_ce.bin"); -MODULE_FIRMWARE("amdgpu/baffin_pfp.bin"); -MODULE_FIRMWARE("amdgpu/baffin_me.bin"); -MODULE_FIRMWARE("amdgpu/baffin_mec.bin"); -MODULE_FIRMWARE("amdgpu/baffin_mec2.bin"); -MODULE_FIRMWARE("amdgpu/baffin_rlc.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_ce.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_me.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_mec.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_ce.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_pfp.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_me.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_mec.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_mec2.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_rlc.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_ce.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_me.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_mec.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin"); static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = { @@ -265,7 +265,7 @@ static const u32 tonga_mgcg_cgcg_init[] = mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, }; -static const u32 golden_settings_baffin_a11[] = +static const u32 golden_settings_polaris11_a11[] = { mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, mmDB_DEBUG2, 0xf00fffff, 0x00000400, @@ -281,7 +281,7 @@ static const u32 golden_settings_baffin_a11[] = mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, }; -static const u32 baffin_golden_common_all[] = +static const u32 polaris11_golden_common_all[] = { mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, @@ -293,7 +293,7 @@ static const u32 baffin_golden_common_all[] = mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, }; -static const u32 golden_settings_ellesmere_a11[] = +static const u32 golden_settings_polaris10_a11[] = { mmATC_MISC_CG, 0x000c0fc0, 0x000c0200, mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, @@ -311,7 +311,7 @@ static const u32 golden_settings_ellesmere_a11[] = mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, }; -static const u32 ellesmere_golden_common_all[] = +static const u32 polaris10_golden_common_all[] = { mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, @@ -674,21 +674,21 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) tonga_golden_common_all, (const u32)ARRAY_SIZE(tonga_golden_common_all)); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_program_register_sequence(adev, - golden_settings_baffin_a11, - (const u32)ARRAY_SIZE(golden_settings_baffin_a11)); + golden_settings_polaris11_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); amdgpu_program_register_sequence(adev, - baffin_golden_common_all, - (const u32)ARRAY_SIZE(baffin_golden_common_all)); + polaris11_golden_common_all, + (const u32)ARRAY_SIZE(polaris11_golden_common_all)); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, - golden_settings_ellesmere_a11, - (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11)); + golden_settings_polaris10_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); amdgpu_program_register_sequence(adev, - ellesmere_golden_common_all, - (const u32)ARRAY_SIZE(ellesmere_golden_common_all)); + polaris10_golden_common_all, + (const u32)ARRAY_SIZE(polaris10_golden_common_all)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, @@ -859,11 +859,11 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) case CHIP_FIJI: chip_name = "fiji"; break; - case CHIP_BAFFIN: - chip_name = "baffin"; + case CHIP_POLARIS11: + chip_name = "polaris11"; break; - case CHIP_ELLESMERE: - chip_name = "ellesmere"; + case CHIP_POLARIS10: + chip_name = "polaris10"; break; case CHIP_STONEY: chip_name = "stoney"; @@ -1092,11 +1092,11 @@ static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, PACKET3_SET_CONTEXT_REG_START); switch (adev->asic_type) { case CHIP_TONGA: - case CHIP_ELLESMERE: + case CHIP_POLARIS10: buffer[count++] = cpu_to_le32(0x16000012); buffer[count++] = cpu_to_le32(0x0000002A); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: buffer[count++] = cpu_to_le32(0x16000012); buffer[count++] = cpu_to_le32(0x00000000); break; @@ -1628,7 +1628,7 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: ret = amdgpu_atombios_get_gfx_info(adev); if (ret) return ret; @@ -1640,9 +1640,9 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) adev->gfx.config.sc_prim_fifo_size_backend = 0x100; adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; - gb_addr_config = BAFFIN_GB_ADDR_CONFIG_GOLDEN; + gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN; break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: ret = amdgpu_atombios_get_gfx_info(adev); if (ret) return ret; @@ -2551,7 +2551,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_16x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | @@ -2753,7 +2753,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | @@ -3658,7 +3658,7 @@ static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev) WREG32(mmRLC_SRM_CNTL, data); } -static void baffin_init_power_gating(struct amdgpu_device *adev) +static void polaris11_init_power_gating(struct amdgpu_device *adev) { uint32_t data; @@ -3701,8 +3701,8 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev) gfx_v8_0_init_save_restore_list(adev); gfx_v8_0_enable_save_restore_machine(adev); - if (adev->asic_type == CHIP_BAFFIN) - baffin_init_power_gating(adev); + if (adev->asic_type == CHIP_POLARIS11) + polaris11_init_power_gating(adev); } } @@ -3776,8 +3776,8 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) /* disable CG */ WREG32(mmRLC_CGCG_CGLS_CTRL, 0); - if (adev->asic_type == CHIP_BAFFIN || - adev->asic_type == CHIP_ELLESMERE) + if (adev->asic_type == CHIP_POLARIS11 || + adev->asic_type == CHIP_POLARIS10) WREG32(mmRLC_CGCG_CGLS_CTRL_3D, 0); /* disable PG */ @@ -3958,11 +3958,11 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); switch (adev->asic_type) { case CHIP_TONGA: - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_ring_write(ring, 0x16000012); amdgpu_ring_write(ring, 0x0000002A); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_ring_write(ring, 0x16000012); amdgpu_ring_write(ring, 0x00000000); break; @@ -4610,8 +4610,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) if ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_FIJI) || (adev->asic_type == CHIP_STONEY) || - (adev->asic_type == CHIP_BAFFIN) || - (adev->asic_type == CHIP_ELLESMERE)) { + (adev->asic_type == CHIP_POLARIS11) || + (adev->asic_type == CHIP_POLARIS10)) { WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ << 2); WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, @@ -4646,8 +4646,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) WREG32(mmCP_HQD_PERSISTENT_STATE, tmp); mqd->cp_hqd_persistent_state = tmp; if (adev->asic_type == CHIP_STONEY || - adev->asic_type == CHIP_BAFFIN || - adev->asic_type == CHIP_ELLESMERE) { + adev->asic_type == CHIP_POLARIS11 || + adev->asic_type == CHIP_POLARIS10) { tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL); tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1); WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp); @@ -5216,7 +5216,7 @@ static int gfx_v8_0_late_init(void *handle) return 0; } -static void baffin_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, +static void polaris11_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, bool enable) { uint32_t data, temp; @@ -5242,7 +5242,7 @@ static void baffin_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, } } -static void baffin_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, +static void polaris11_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, bool enable) { uint32_t data, temp; @@ -5263,7 +5263,7 @@ static void baffin_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev } } -static void baffin_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev, +static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev, bool enable) { uint32_t data, temp; @@ -5293,15 +5293,15 @@ static int gfx_v8_0_set_powergating_state(void *handle, return 0; switch (adev->asic_type) { - case CHIP_BAFFIN: - if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG) - baffin_enable_gfx_static_mg_power_gating(adev, + case CHIP_POLARIS11: + if (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) + polaris11_enable_gfx_static_mg_power_gating(adev, state == AMD_PG_STATE_GATE ? true : false); - else if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG) - baffin_enable_gfx_dynamic_mg_power_gating(adev, + else if (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) + polaris11_enable_gfx_dynamic_mg_power_gating(adev, state == AMD_PG_STATE_GATE ? true : false); else - baffin_enable_gfx_quick_mg_power_gating(adev, + polaris11_enable_gfx_quick_mg_power_gating(adev, state == AMD_PG_STATE_GATE ? true : false); break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 27956dd..f5efc67 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -43,8 +43,8 @@ static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); -MODULE_FIRMWARE("amdgpu/baffin_mc.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_mc.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); static const u32 golden_settings_tonga_a11[] = { @@ -75,7 +75,7 @@ static const u32 fiji_mgcg_cgcg_init[] = mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 }; -static const u32 golden_settings_baffin_a11[] = +static const u32 golden_settings_polaris11_a11[] = { mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, @@ -83,7 +83,7 @@ static const u32 golden_settings_baffin_a11[] = mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff }; -static const u32 golden_settings_ellesmere_a11[] = +static const u32 golden_settings_polaris10_a11[] = { mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, @@ -122,15 +122,15 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) golden_settings_tonga_a11, (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_program_register_sequence(adev, - golden_settings_baffin_a11, - (const u32)ARRAY_SIZE(golden_settings_baffin_a11)); + golden_settings_polaris11_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, - golden_settings_ellesmere_a11, - (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11)); + golden_settings_polaris10_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, @@ -238,11 +238,11 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) case CHIP_TONGA: chip_name = "tonga"; break; - case CHIP_BAFFIN: - chip_name = "baffin"; + case CHIP_POLARIS11: + chip_name = "polaris11"; break; - case CHIP_ELLESMERE: - chip_name = "ellesmere"; + case CHIP_POLARIS10: + chip_name = "polaris10"; break; case CHIP_FIJI: case CHIP_CARRIZO: diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 6b24a9c..72cae36 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -56,10 +56,10 @@ MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_sdma.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_sdma1.bin"); -MODULE_FIRMWARE("amdgpu/baffin_sdma.bin"); -MODULE_FIRMWARE("amdgpu/baffin_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = @@ -106,7 +106,7 @@ static const u32 fiji_mgcg_cgcg_init[] = mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 }; -static const u32 golden_settings_baffin_a11[] = +static const u32 golden_settings_polaris11_a11[] = { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, @@ -118,7 +118,7 @@ static const u32 golden_settings_baffin_a11[] = mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, }; -static const u32 golden_settings_ellesmere_a11[] = +static const u32 golden_settings_polaris10_a11[] = { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, @@ -203,15 +203,15 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) golden_settings_tonga_a11, (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_program_register_sequence(adev, - golden_settings_baffin_a11, - (const u32)ARRAY_SIZE(golden_settings_baffin_a11)); + golden_settings_polaris11_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, - golden_settings_ellesmere_a11, - (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11)); + golden_settings_polaris10_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, @@ -261,11 +261,11 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) case CHIP_FIJI: chip_name = "fiji"; break; - case CHIP_BAFFIN: - chip_name = "baffin"; + case CHIP_POLARIS11: + chip_name = "polaris11"; break; - case CHIP_ELLESMERE: - chip_name = "ellesmere"; + case CHIP_POLARIS10: + chip_name = "polaris10"; break; case CHIP_CARRIZO: chip_name = "carrizo"; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index c12fd83..5834285 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -315,11 +315,11 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) { u32 tmp; - /* Fiji, Stoney, Ellesmere, Baffin are single pipe */ + /* Fiji, Stoney, Polaris10, Polaris11 are single pipe */ if ((adev->asic_type == CHIP_FIJI) || (adev->asic_type == CHIP_STONEY) || - (adev->asic_type == CHIP_ELLESMERE) || - (adev->asic_type == CHIP_BAFFIN)) + (adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) return AMDGPU_VCE_HARVEST_VCE1; /* Tonga and CZ are dual or single pipe */ diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 8e0e014..0d61d5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -277,8 +277,8 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) stoney_mgcg_cgcg_init, (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); break; - case CHIP_BAFFIN: - case CHIP_ELLESMERE: + case CHIP_POLARIS11: + case CHIP_POLARIS10: default: break; } @@ -540,8 +540,8 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, break; case CHIP_FIJI: case CHIP_TONGA: - case CHIP_BAFFIN: - case CHIP_ELLESMERE: + case CHIP_POLARIS11: + case CHIP_POLARIS10: case CHIP_CARRIZO: case CHIP_STONEY: asic_register_table = cz_allowed_read_registers; @@ -912,7 +912,7 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] = }, }; -static const struct amdgpu_ip_block_version baffin_ip_blocks[] = +static const struct amdgpu_ip_block_version polaris11_ip_blocks[] = { /* ORDER MATTERS! */ { @@ -1311,10 +1311,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks); #endif break; - case CHIP_BAFFIN: - case CHIP_ELLESMERE: - adev->ip_blocks = baffin_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(baffin_ip_blocks); + case CHIP_POLARIS11: + case CHIP_POLARIS10: + adev->ip_blocks = polaris11_ip_blocks; + adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks); break; case CHIP_CARRIZO: case CHIP_STONEY: @@ -1427,12 +1427,12 @@ static int vi_common_early_init(void *handle) adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x14; break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: adev->cg_flags = 0; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x5A; break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: adev->cg_flags = 0; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x50; diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 72858a0..e56d8a3 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -48,8 +48,8 @@ enum amd_asic_type { CHIP_FIJI, CHIP_CARRIZO, CHIP_STONEY, - CHIP_ELLESMERE, - CHIP_BAFFIN, + CHIP_POLARIS10, + CHIP_POLARIS11, CHIP_LAST, }; diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h index 296def3..32f3e34 100644 --- a/drivers/gpu/drm/amd/include/atombios.h +++ b/drivers/gpu/drm/amd/include/atombios.h @@ -2061,7 +2061,7 @@ typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V1_1 #define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS 0x01 #define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK 0x02 -// SetDCEClockTable input parameter for DCE11.2( ELM and BF ) and above +// SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above typedef struct _SET_DCE_CLOCK_PARAMETERS_V2_1 { ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. @@ -5494,7 +5494,7 @@ typedef struct _ATOM_ASIC_PROFILING_INFO_V3_4 ULONG ulReserved[8]; // Reserved for future ASIC }ATOM_ASIC_PROFILING_INFO_V3_4; -// for Ellemser/Baffin speed EVV algorithm +// for Polaris10/Polaris11 speed EVV algorithm typedef struct _ATOM_ASIC_PROFILING_INFO_V3_5 { ATOM_COMMON_TABLE_HEADER asHeader; @@ -5549,7 +5549,7 @@ typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{ }ATOM_SCLK_FCW_RANGE_ENTRY_V1; -// SMU_InfoTable for Ellesmere/Baffin +// SMU_InfoTable for Polaris10/Polaris11 typedef struct _ATOM_SMU_INFO_V2_1 { ATOM_COMMON_TABLE_HEADER asHeader; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile index 5437ec0..f7ce4cb 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile @@ -9,8 +9,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \ tonga_hwmgr.o pppcielanes.o tonga_thermal.o\ fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \ fiji_clockpowergating.o fiji_thermal.o \ - ellesmere_hwmgr.o ellesmere_powertune.o ellesmere_thermal.o \ - ellesmere_clockpowergating.o + polaris10_hwmgr.o polaris10_powertune.o polaris10_thermal.o \ + polaris10_clockpowergating.o AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c deleted file mode 100644 index 93db824..0000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c +++ /dev/null @@ -1,428 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "ellesmere_clockpowergating.h" - -int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr) -{ - if (phm_cf_want_uvd_power_gating(hwmgr)) - return smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_UVDPowerOFF); - return 0; -} - -int ellesmere_phm_powerup_uvd(struct pp_hwmgr *hwmgr) -{ - if (phm_cf_want_uvd_power_gating(hwmgr)) { - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDDynamicPowerGating)) { - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_UVDPowerON, 1); - } else { - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_UVDPowerON, 0); - } - } - - return 0; -} - -int ellesmere_phm_powerdown_vce(struct pp_hwmgr *hwmgr) -{ - if (phm_cf_want_vce_power_gating(hwmgr)) - return smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_VCEPowerOFF); - return 0; -} - -int ellesmere_phm_powerup_vce(struct pp_hwmgr *hwmgr) -{ - if (phm_cf_want_vce_power_gating(hwmgr)) - return smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_VCEPowerON); - return 0; -} - -int ellesmere_phm_powerdown_samu(struct pp_hwmgr *hwmgr) -{ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SamuPowerGating)) - return smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_SAMPowerOFF); - return 0; -} - -int ellesmere_phm_powerup_samu(struct pp_hwmgr *hwmgr) -{ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SamuPowerGating)) - return smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_SAMPowerON); - return 0; -} - -int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - data->uvd_power_gated = false; - data->vce_power_gated = false; - data->samu_power_gated = false; - - ellesmere_phm_powerup_uvd(hwmgr); - ellesmere_phm_powerup_vce(hwmgr); - ellesmere_phm_powerup_samu(hwmgr); - - return 0; -} - -int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - if (data->uvd_power_gated == bgate) - return 0; - - data->uvd_power_gated = bgate; - - if (bgate) { - ellesmere_update_uvd_dpm(hwmgr, true); - ellesmere_phm_powerdown_uvd(hwmgr); - } else { - ellesmere_phm_powerup_uvd(hwmgr); - ellesmere_update_uvd_dpm(hwmgr, false); - } - - return 0; -} - -int ellesmere_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - if (data->vce_power_gated == bgate) - return 0; - - if (bgate) - ellesmere_phm_powerdown_vce(hwmgr); - else - ellesmere_phm_powerup_vce(hwmgr); - - return 0; -} - -int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - if (data->samu_power_gated == bgate) - return 0; - - data->samu_power_gated = bgate; - - if (bgate) { - ellesmere_update_samu_dpm(hwmgr, true); - ellesmere_phm_powerdown_samu(hwmgr); - } else { - ellesmere_phm_powerup_samu(hwmgr); - ellesmere_update_samu_dpm(hwmgr, false); - } - - return 0; -} - -int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr, - const uint32_t *msg_id) -{ - PPSMC_Msg msg; - uint32_t value; - - switch ((*msg_id & PP_GROUP_MASK) >> PP_GROUP_SHIFT) { - case PP_GROUP_GFX: - switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) { - case PP_BLOCK_GFX_CG: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_GFX_CGCG_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS - ? PPSMC_MSG_EnableClockGatingFeature - : PPSMC_MSG_DisableClockGatingFeature; - value = CG_GFX_CGLS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - break; - - case PP_BLOCK_GFX_3D: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_GFX_3DCG_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_GFX_3DLS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - break; - - case PP_BLOCK_GFX_RLC: - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_GFX_RLC_LS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - break; - - case PP_BLOCK_GFX_CP: - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_GFX_CP_LS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - break; - - case PP_BLOCK_GFX_MG: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = (CG_CPF_MGCG_MASK | CG_RLC_MGCG_MASK | - CG_GFX_OTHERS_MGCG_MASK); - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - break; - - default: - return -1; - } - break; - - case PP_GROUP_SYS: - switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) { - case PP_BLOCK_SYS_BIF: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_BIF_MGCG_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_BIF_MGLS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - break; - - case PP_BLOCK_SYS_MC: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_MC_MGCG_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_MC_MGLS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - break; - - case PP_BLOCK_SYS_DRM: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_DRM_MGCG_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_DRM_MGLS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - break; - - case PP_BLOCK_SYS_HDP: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_HDP_MGCG_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_HDP_MGLS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - break; - - case PP_BLOCK_SYS_SDMA: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_SDMA_MGCG_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - - if (PP_STATE_SUPPORT_LS & *msg_id) { - msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_SDMA_MGLS_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - break; - - case PP_BLOCK_SYS_ROM: - if (PP_STATE_SUPPORT_CG & *msg_id) { - msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? - PPSMC_MSG_EnableClockGatingFeature : - PPSMC_MSG_DisableClockGatingFeature; - value = CG_SYS_ROM_MASK; - - if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) - return -1; - } - break; - - default: - return -1; - - } - break; - - default: - return -1; - - } - - return 0; -} - -/* This function is for Baffin only for now, - * Powerplay will only control the static per CU Power Gating. - * Dynamic per CU Power Gating will be done in gfx. - */ -int ellesmere_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable) -{ - struct cgs_system_info sys_info = {0}; - uint32_t active_cus; - int result; - - sys_info.size = sizeof(struct cgs_system_info); - sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO; - - result = cgs_query_system_info(hwmgr->device, &sys_info); - - if (result) - return -EINVAL; - else - active_cus = sys_info.value; - - if (enable) - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus); - else - return smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_GFX_CU_PG_DISABLE); -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h deleted file mode 100644 index b403e11..0000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _ELLESMERE_CLOCK_POWER_GATING_H_ -#define _ELLESMERE_CLOCK_POWER_GATING_H_ - -#include "ellesmere_hwmgr.h" -#include "pp_asicblocks.h" - -int ellesmere_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate); -int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate); -int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr); -int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate); -int ellesmere_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate); -int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr); -int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr, - const uint32_t *msg_id); -int ellesmere_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable); - -#endif /* _ELLESMERE_CLOCK_POWER_GATING_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h deleted file mode 100644 index ba1187c..0000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef ELLESMERE_DYN_DEFAULTS_H -#define ELLESMERE_DYN_DEFAULTS_H - - -enum Ellesmeredpm_TrendDetection { - EllesmereAdpm_TrendDetection_AUTO, - EllesmereAdpm_TrendDetection_UP, - EllesmereAdpm_TrendDetection_DOWN -}; -typedef enum Ellesmeredpm_TrendDetection Ellesmeredpm_TrendDetection; - -/* We need to fill in the default values */ - - -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102 -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT1 0x000400 -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT2 0xC00080 -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT3 0xC00200 -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT4 0xC01680 -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT5 0xC00033 -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT6 0xC00033 -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT7 0x3FFFC000 - - -#define PPELLESMERE_THERMALPROTECTCOUNTER_DFLT 0x200 -#define PPELLESMERE_STATICSCREENTHRESHOLDUNIT_DFLT 0 -#define PPELLESMERE_STATICSCREENTHRESHOLD_DFLT 0x00C8 -#define PPELLESMERE_GFXIDLECLOCKSTOPTHRESHOLD_DFLT 0x200 -#define PPELLESMERE_REFERENCEDIVIDER_DFLT 4 - -#define PPELLESMERE_ULVVOLTAGECHANGEDELAY_DFLT 1687 - -#define PPELLESMERE_CGULVPARAMETER_DFLT 0x00040035 -#define PPELLESMERE_CGULVCONTROL_DFLT 0x00007450 -#define PPELLESMERE_TARGETACTIVITY_DFLT 50 -#define PPELLESMERE_MCLK_TARGETACTIVITY_DFLT 10 - -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c deleted file mode 100644 index 152d77d..0000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c +++ /dev/null @@ -1,4711 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include -#include -#include -#include "linux/delay.h" -#include "pp_acpi.h" -#include "hwmgr.h" -#include "ellesmere_hwmgr.h" -#include "ellesmere_powertune.h" -#include "ellesmere_dyn_defaults.h" -#include "ellesmere_smumgr.h" -#include "pp_debug.h" -#include "ppatomctrl.h" -#include "atombios.h" -#include "tonga_pptable.h" -#include "pppcielanes.h" -#include "amd_pcie_helpers.h" -#include "hardwaremanager.h" -#include "tonga_processpptables.h" -#include "cgs_common.h" -#include "smu74.h" -#include "smu_ucode_xfer_vi.h" -#include "smu74_discrete.h" -#include "smu/smu_7_1_3_d.h" -#include "smu/smu_7_1_3_sh_mask.h" -#include "gmc/gmc_8_1_d.h" -#include "gmc/gmc_8_1_sh_mask.h" -#include "oss/oss_3_0_d.h" -#include "gca/gfx_8_0_d.h" -#include "bif/bif_5_0_d.h" -#include "bif/bif_5_0_sh_mask.h" -#include "gmc/gmc_8_1_d.h" -#include "gmc/gmc_8_1_sh_mask.h" -#include "bif/bif_5_0_d.h" -#include "bif/bif_5_0_sh_mask.h" -#include "dce/dce_10_0_d.h" -#include "dce/dce_10_0_sh_mask.h" - -#include "ellesmere_thermal.h" -#include "ellesmere_clockpowergating.h" - -#define MC_CG_ARB_FREQ_F0 0x0a -#define MC_CG_ARB_FREQ_F1 0x0b -#define MC_CG_ARB_FREQ_F2 0x0c -#define MC_CG_ARB_FREQ_F3 0x0d - -#define MC_CG_SEQ_DRAMCONF_S0 0x05 -#define MC_CG_SEQ_DRAMCONF_S1 0x06 -#define MC_CG_SEQ_YCLK_SUSPEND 0x04 -#define MC_CG_SEQ_YCLK_RESUME 0x0a - - -#define SMC_RAM_END 0x40000 - -#define SMC_CG_IND_START 0xc0030000 -#define SMC_CG_IND_END 0xc0040000 - -#define VOLTAGE_SCALE 4 -#define VOLTAGE_VID_OFFSET_SCALE1 625 -#define VOLTAGE_VID_OFFSET_SCALE2 100 - -#define VDDC_VDDCI_DELTA 200 - -#define MEM_FREQ_LOW_LATENCY 25000 -#define MEM_FREQ_HIGH_LATENCY 80000 - -#define MEM_LATENCY_HIGH 45 -#define MEM_LATENCY_LOW 35 -#define MEM_LATENCY_ERR 0xFFFF - -#define MC_SEQ_MISC0_GDDR5_SHIFT 28 -#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 -#define MC_SEQ_MISC0_GDDR5_VALUE 5 - - -#define PCIE_BUS_CLK 10000 -#define TCLK (PCIE_BUS_CLK / 10) - - -uint16_t ellesmere_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0}, - {600, 1050, 6, 1} }; - -/* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */ -uint32_t ellesmere_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} }, - { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } }; - -/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */ -uint8_t ellesmere_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5}, - {0, 2, 4, 5, 6, 5} }; - -/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ -enum DPM_EVENT_SRC { - DPM_EVENT_SRC_ANALOG = 0, - DPM_EVENT_SRC_EXTERNAL = 1, - DPM_EVENT_SRC_DIGITAL = 2, - DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, - DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 -}; - -const unsigned long PhwEllesmere_Magic = (unsigned long)(PHM_VIslands_Magic); - -struct ellesmere_power_state *cast_phw_ellesmere_power_state( - struct pp_hw_power_state *hw_ps) -{ - PP_ASSERT_WITH_CODE((PhwEllesmere_Magic == hw_ps->magic), - "Invalid Powerstate Type!", - return NULL); - - return (struct ellesmere_power_state *)hw_ps; -} - -const struct ellesmere_power_state *cast_const_phw_ellesmere_power_state( - const struct pp_hw_power_state *hw_ps) -{ - PP_ASSERT_WITH_CODE((PhwEllesmere_Magic == hw_ps->magic), - "Invalid Powerstate Type!", - return NULL); - - return (const struct ellesmere_power_state *)hw_ps; -} - -static bool ellesmere_is_dpm_running(struct pp_hwmgr *hwmgr) -{ - return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, - CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) - ? true : false; -} - -/** - * Find the MC microcode version and store it in the HwMgr struct - * - * @param hwmgr the address of the powerplay hardware manager. - * @return always 0 - */ -int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr) -{ - cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); - - hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); - - return 0; -} - -uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr) -{ - uint32_t speedCntl = 0; - - /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ - speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, - ixPCIE_LC_SPEED_CNTL); - return((uint16_t)PHM_GET_FIELD(speedCntl, - PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); -} - -int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) -{ - uint32_t link_width; - - /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ - link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, - PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD); - - PP_ASSERT_WITH_CODE((7 >= link_width), - "Invalid PCIe lane width!", return 0); - - return decode_pcie_lane_width(link_width); -} - -void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)hwmgr->pptable; - struct phm_clock_voltage_dependency_table *table = - table_info->vddc_dep_on_dal_pwrl; - struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table; - enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level; - uint32_t req_vddc = 0, req_volt, i; - - if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW && - dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE)) - return; - - for (i = 0; i < table->count; i++) { - if (dal_power_level == table->entries[i].clk) { - req_vddc = table->entries[i].v; - break; - } - } - - vddc_table = table_info->vdd_dep_on_sclk; - for (i = 0; i < vddc_table->count; i++) { - if (req_vddc <= vddc_table->entries[i].vddc) { - req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE) - << VDDC_SHIFT; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_VddC_Request, req_volt); - return; - } - } - printk(KERN_ERR "DAL requested level can not" - " found a available voltage in VDDC DPM Table \n"); -} - -/** -* Enable voltage control -* -* @param pHwMgr the address of the powerplay hardware manager. -* @return always PP_Result_OK -*/ -int ellesmere_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) -{ - PP_ASSERT_WITH_CODE( - (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0), - "Failed to enable voltage DPM during DPM Start Function!", - return 1; - ); - - return 0; -} - -/** -* Checks if we want to support voltage control -* -* @param hwmgr the address of the powerplay hardware manager. -*/ -static bool ellesmere_voltage_control(const struct pp_hwmgr *hwmgr) -{ - const struct ellesmere_hwmgr *data = - (const struct ellesmere_hwmgr *)(hwmgr->backend); - - return (ELLESMERE_VOLTAGE_CONTROL_NONE != data->voltage_control); -} - -/** -* Enable voltage control -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int ellesmere_enable_voltage_control(struct pp_hwmgr *hwmgr) -{ - /* enable voltage control */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); - - return 0; -} - -/** -* Create Voltage Tables. -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int ellesmere_construct_voltage_tables(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)hwmgr->pptable; - int result; - - if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { - result = atomctrl_get_voltage_table_v3(hwmgr, - VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, - &(data->mvdd_voltage_table)); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to retrieve MVDD table.", - return result); - } else if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { - result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table), - table_info->vdd_dep_on_mclk); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to retrieve SVI2 MVDD table from dependancy table.", - return result;); - } - - if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { - result = atomctrl_get_voltage_table_v3(hwmgr, - VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, - &(data->vddci_voltage_table)); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to retrieve VDDCI table.", - return result); - } else if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { - result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table), - table_info->vdd_dep_on_mclk); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to retrieve SVI2 VDDCI table from dependancy table.", - return result); - } - - if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { - result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table), - table_info->vddc_lookup_table); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to retrieve SVI2 VDDC table from lookup table.", - return result); - } - - PP_ASSERT_WITH_CODE( - (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)), - "Too many voltage values for VDDC. Trimming to fit state table.", - phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC, - &(data->vddc_voltage_table))); - - PP_ASSERT_WITH_CODE( - (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)), - "Too many voltage values for VDDCI. Trimming to fit state table.", - phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI, - &(data->vddci_voltage_table))); - - PP_ASSERT_WITH_CODE( - (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)), - "Too many voltage values for MVDD. Trimming to fit state table.", - phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD, - &(data->mvdd_voltage_table))); - - return 0; -} - -/** -* Programs static screed detection parameters -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int ellesmere_program_static_screen_threshold_parameters( - struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - /* Set static screen threshold unit */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT, - data->static_screen_threshold_unit); - /* Set static screen threshold */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD, - data->static_screen_threshold); - - return 0; -} - -/** -* Setup display gap for glitch free memory clock switching. -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int ellesmere_enable_display_gap(struct pp_hwmgr *hwmgr) -{ - uint32_t display_gap = - cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_DISPLAY_GAP_CNTL); - - display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, - DISP_GAP, DISPLAY_GAP_IGNORE); - - display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, - DISP_GAP_MCHG, DISPLAY_GAP_VBLANK); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_DISPLAY_GAP_CNTL, display_gap); - - return 0; -} - -/** -* Programs activity state transition voting clients -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int ellesmere_program_voting_clients(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - /* Clear reset for voting clients before enabling DPM */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7); - - return 0; -} - -/** -* Get the location of various tables inside the FW image. -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int ellesmere_process_firmware_header(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(hwmgr->smumgr->backend); - uint32_t tmp; - int result; - bool error = false; - - result = ellesmere_read_smc_sram_dword(hwmgr->smumgr, - SMU7_FIRMWARE_HEADER_LOCATION + - offsetof(SMU74_Firmware_Header, DpmTable), - &tmp, data->sram_end); - - if (0 == result) - data->dpm_table_start = tmp; - - error |= (0 != result); - - result = ellesmere_read_smc_sram_dword(hwmgr->smumgr, - SMU7_FIRMWARE_HEADER_LOCATION + - offsetof(SMU74_Firmware_Header, SoftRegisters), - &tmp, data->sram_end); - - if (!result) { - data->soft_regs_start = tmp; - smu_data->soft_regs_start = tmp; - } - - error |= (0 != result); - - result = ellesmere_read_smc_sram_dword(hwmgr->smumgr, - SMU7_FIRMWARE_HEADER_LOCATION + - offsetof(SMU74_Firmware_Header, mcRegisterTable), - &tmp, data->sram_end); - - if (!result) - data->mc_reg_table_start = tmp; - - result = ellesmere_read_smc_sram_dword(hwmgr->smumgr, - SMU7_FIRMWARE_HEADER_LOCATION + - offsetof(SMU74_Firmware_Header, FanTable), - &tmp, data->sram_end); - - if (!result) - data->fan_table_start = tmp; - - error |= (0 != result); - - result = ellesmere_read_smc_sram_dword(hwmgr->smumgr, - SMU7_FIRMWARE_HEADER_LOCATION + - offsetof(SMU74_Firmware_Header, mcArbDramTimingTable), - &tmp, data->sram_end); - - if (!result) - data->arb_table_start = tmp; - - error |= (0 != result); - - result = ellesmere_read_smc_sram_dword(hwmgr->smumgr, - SMU7_FIRMWARE_HEADER_LOCATION + - offsetof(SMU74_Firmware_Header, Version), - &tmp, data->sram_end); - - if (!result) - hwmgr->microcode_version_info.SMC = tmp; - - error |= (0 != result); - - return error ? -1 : 0; -} - -/* Copy one arb setting to another and then switch the active set. - * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants. - */ -static int ellesmere_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, - uint32_t arb_src, uint32_t arb_dest) -{ - uint32_t mc_arb_dram_timing; - uint32_t mc_arb_dram_timing2; - uint32_t burst_time; - uint32_t mc_cg_config; - - switch (arb_src) { - case MC_CG_ARB_FREQ_F0: - mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); - mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); - burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); - break; - case MC_CG_ARB_FREQ_F1: - mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); - mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); - burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1); - break; - default: - return -EINVAL; - } - - switch (arb_dest) { - case MC_CG_ARB_FREQ_F0: - cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); - cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); - PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time); - break; - case MC_CG_ARB_FREQ_F1: - cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); - cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); - PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time); - break; - default: - return -EINVAL; - } - - mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); - mc_cg_config |= 0x0000000F; - cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); - PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest); - - return 0; -} - -/** -* Initial switch from ARB F0->F1 -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -* This function is to be called from the SetPowerState table. -*/ -static int ellesmere_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr) -{ - return ellesmere_copy_and_switch_arb_sets(hwmgr, - MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); -} - -static int ellesmere_setup_default_pcie_table(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; - uint32_t i, max_entry; - - PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels || - data->use_pcie_power_saving_levels), "No pcie performance levels!", - return -EINVAL); - - if (data->use_pcie_performance_levels && - !data->use_pcie_power_saving_levels) { - data->pcie_gen_power_saving = data->pcie_gen_performance; - data->pcie_lane_power_saving = data->pcie_lane_performance; - } else if (!data->use_pcie_performance_levels && - data->use_pcie_power_saving_levels) { - data->pcie_gen_performance = data->pcie_gen_power_saving; - data->pcie_lane_performance = data->pcie_lane_power_saving; - } - - phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, - SMU74_MAX_LEVELS_LINK, - MAX_REGULAR_DPM_NUMBER); - - if (pcie_table != NULL) { - /* max_entry is used to make sure we reserve one PCIE level - * for boot level (fix for A+A PSPP issue). - * If PCIE table from PPTable have ULV entry + 8 entries, - * then ignore the last entry.*/ - max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ? - SMU74_MAX_LEVELS_LINK : pcie_table->count; - for (i = 1; i < max_entry; i++) { - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, - get_pcie_gen_support(data->pcie_gen_cap, - pcie_table->entries[i].gen_speed), - get_pcie_lane_support(data->pcie_lane_cap, - pcie_table->entries[i].lane_width)); - } - data->dpm_table.pcie_speed_table.count = max_entry - 1; - - /* Setup BIF_SCLK levels */ - for (i = 0; i < max_entry; i++) - data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk; - } else { - /* Hardcode Pcie Table */ - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Min_PCIEGen), - get_pcie_lane_support(data->pcie_lane_cap, - PP_Max_PCIELane)); - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Min_PCIEGen), - get_pcie_lane_support(data->pcie_lane_cap, - PP_Max_PCIELane)); - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Max_PCIEGen), - get_pcie_lane_support(data->pcie_lane_cap, - PP_Max_PCIELane)); - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Max_PCIEGen), - get_pcie_lane_support(data->pcie_lane_cap, - PP_Max_PCIELane)); - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Max_PCIEGen), - get_pcie_lane_support(data->pcie_lane_cap, - PP_Max_PCIELane)); - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Max_PCIEGen), - get_pcie_lane_support(data->pcie_lane_cap, - PP_Max_PCIELane)); - - data->dpm_table.pcie_speed_table.count = 6; - } - /* Populate last level for boot PCIE level, but do not increment count. */ - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, - data->dpm_table.pcie_speed_table.count, - get_pcie_gen_support(data->pcie_gen_cap, - PP_Min_PCIEGen), - get_pcie_lane_support(data->pcie_lane_cap, - PP_Max_PCIELane)); - - return 0; -} - -/* - * This function is to initalize all DPM state tables - * for SMU7 based on the dependency table. - * Dynamic state patching function will then trim these - * state tables to the allowed range based - * on the power policy or external client requests, - * such as UVD request, etc. - */ -int ellesmere_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - uint32_t i; - - struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = - table_info->vdd_dep_on_sclk; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = - table_info->vdd_dep_on_mclk; - - PP_ASSERT_WITH_CODE(dep_sclk_table != NULL, - "SCLK dependency table is missing. This table is mandatory", - return -EINVAL); - PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1, - "SCLK dependency table has to have is missing." - "This table is mandatory", - return -EINVAL); - - PP_ASSERT_WITH_CODE(dep_mclk_table != NULL, - "MCLK dependency table is missing. This table is mandatory", - return -EINVAL); - PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, - "MCLK dependency table has to have is missing." - "This table is mandatory", - return -EINVAL); - - /* clear the state table to reset everything to default */ - phm_reset_single_dpm_table( - &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER); - phm_reset_single_dpm_table( - &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER); - - - /* Initialize Sclk DPM table based on allow Sclk values */ - data->dpm_table.sclk_table.count = 0; - for (i = 0; i < dep_sclk_table->count; i++) { - if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != - dep_sclk_table->entries[i].clk) { - - data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = - dep_sclk_table->entries[i].clk; - - data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = - (i == 0) ? true : false; - data->dpm_table.sclk_table.count++; - } - } - - /* Initialize Mclk DPM table based on allow Mclk values */ - data->dpm_table.mclk_table.count = 0; - for (i = 0; i < dep_mclk_table->count; i++) { - if (i == 0 || data->dpm_table.mclk_table.dpm_levels - [data->dpm_table.mclk_table.count - 1].value != - dep_mclk_table->entries[i].clk) { - data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = - dep_mclk_table->entries[i].clk; - data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = - (i == 0) ? true : false; - data->dpm_table.mclk_table.count++; - } - } - - /* setup PCIE gen speed levels */ - ellesmere_setup_default_pcie_table(hwmgr); - - /* save a copy of the default DPM table */ - memcpy(&(data->golden_dpm_table), &(data->dpm_table), - sizeof(struct ellesmere_dpm_table)); - - return 0; -} - -uint8_t convert_to_vid(uint16_t vddc) -{ - return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25); -} - -/** - * Mvdd table preparation for SMC. - * - * @param *hwmgr The address of the hardware manager. - * @param *table The SMC DPM table structure to be populated. - * @return 0 - */ -static int ellesmere_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, - SMU74_Discrete_DpmTable *table) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - uint32_t count, level; - - if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { - count = data->mvdd_voltage_table.count; - if (count > SMU_MAX_SMIO_LEVELS) - count = SMU_MAX_SMIO_LEVELS; - for (level = 0; level < count; level++) { - table->SmioTable2.Pattern[level].Voltage = - PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE); - /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/ - table->SmioTable2.Pattern[level].Smio = - (uint8_t) level; - table->Smio[level] |= - data->mvdd_voltage_table.entries[level].smio_low; - } - table->SmioMask2 = data->vddci_voltage_table.mask_low; - - table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count); - } - - return 0; -} - -static int ellesmere_populate_smc_vddci_table(struct pp_hwmgr *hwmgr, - struct SMU74_Discrete_DpmTable *table) -{ - uint32_t count, level; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - count = data->vddci_voltage_table.count; - - if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { - if (count > SMU_MAX_SMIO_LEVELS) - count = SMU_MAX_SMIO_LEVELS; - for (level = 0; level < count; ++level) { - table->SmioTable1.Pattern[level].Voltage = - PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE); - table->SmioTable1.Pattern[level].Smio = (uint8_t) level; - - table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low; - } - } - - table->SmioMask1 = data->vddci_voltage_table.mask_low; - - return 0; -} - -/** -* Preparation of vddc and vddgfx CAC tables for SMC. -* -* @param hwmgr the address of the hardware manager -* @param table the SMC DPM table structure to be populated -* @return always 0 -*/ -static int ellesmere_populate_cac_table(struct pp_hwmgr *hwmgr, - struct SMU74_Discrete_DpmTable *table) -{ - uint32_t count; - uint8_t index; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct phm_ppt_v1_voltage_lookup_table *lookup_table = - table_info->vddc_lookup_table; - /* tables is already swapped, so in order to use the value from it, - * we need to swap it back. - * We are populating vddc CAC data to BapmVddc table - * in split and merged mode - */ - for (count = 0; count < lookup_table->count; count++) { - index = phm_get_voltage_index(lookup_table, - data->vddc_voltage_table.entries[count].value); - table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low); - table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid); - table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high); - } - - return 0; -} - -/** -* Preparation of voltage tables for SMC. -* -* @param hwmgr the address of the hardware manager -* @param table the SMC DPM table structure to be populated -* @return always 0 -*/ - -int ellesmere_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, - struct SMU74_Discrete_DpmTable *table) -{ - ellesmere_populate_smc_vddci_table(hwmgr, table); - ellesmere_populate_smc_mvdd_table(hwmgr, table); - ellesmere_populate_cac_table(hwmgr, table); - - return 0; -} - -static int ellesmere_populate_ulv_level(struct pp_hwmgr *hwmgr, - struct SMU74_Discrete_Ulv *state) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - state->CcPwrDynRm = 0; - state->CcPwrDynRm1 = 0; - - state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset; - state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset * - VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); - - state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1; - - CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm); - CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1); - CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset); - - return 0; -} - -static int ellesmere_populate_ulv_state(struct pp_hwmgr *hwmgr, - struct SMU74_Discrete_DpmTable *table) -{ - return ellesmere_populate_ulv_level(hwmgr, &table->Ulv); -} - -static int ellesmere_populate_smc_link_level(struct pp_hwmgr *hwmgr, - struct SMU74_Discrete_DpmTable *table) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_dpm_table *dpm_table = &data->dpm_table; - int i; - - /* Index (dpm_table->pcie_speed_table.count) - * is reserved for PCIE boot level. */ - for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { - table->LinkLevel[i].PcieGenSpeed = - (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; - table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( - dpm_table->pcie_speed_table.dpm_levels[i].param1); - table->LinkLevel[i].EnabledForActivity = 1; - table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff); - table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5); - table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30); - } - - data->smc_state_table.LinkLevelCount = - (uint8_t)dpm_table->pcie_speed_table.count; - data->dpm_level_enable_mask.pcie_dpm_enable_mask = - phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); - - return 0; -} - -static uint32_t ellesemere_get_xclk(struct pp_hwmgr *hwmgr) -{ - uint32_t reference_clock, tmp; - struct cgs_display_info info = {0}; - struct cgs_mode_info mode_info; - - info.mode_info = &mode_info; - - tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK); - - if (tmp) - return TCLK; - - cgs_get_active_displays_info(hwmgr->device, &info); - reference_clock = mode_info.ref_clock; - - tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE); - - if (0 != tmp) - return reference_clock / 4; - - return reference_clock; -} - -/** -* Calculates the SCLK dividers using the provided engine clock -* -* @param hwmgr the address of the hardware manager -* @param clock the engine clock to use to populate the structure -* @param sclk the SMC SCLK structure to be populated -*/ -static int ellesmere_calculate_sclk_params(struct pp_hwmgr *hwmgr, - uint32_t clock, SMU_SclkSetting *sclk_setting) -{ - const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - const SMU74_Discrete_DpmTable *table = &(data->smc_state_table); - struct pp_atomctrl_clock_dividers_ai dividers; - - uint32_t ref_clock; - uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq; - uint8_t i; - int result; - uint64_t temp; - - sclk_setting->SclkFrequency = clock; - /* get the engine clock dividers for this clock value */ - result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); - if (result == 0) { - sclk_setting->Fcw_int = dividers.usSclk_fcw_int; - sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; - sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; - sclk_setting->PllRange = dividers.ucSclkPllRange; - sclk_setting->Sclk_slew_rate = 0x400; - sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; - sclk_setting->Pcc_down_slew_rate = 0xffff; - sclk_setting->SSc_En = dividers.ucSscEnable; - sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; - sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; - sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac; - return result; - } - - ref_clock = ellesemere_get_xclk(hwmgr); - - for (i = 0; i < NUM_SCLK_RANGE; i++) { - if (clock > data->range_table[i].trans_lower_frequency - && clock <= data->range_table[i].trans_upper_frequency) { - sclk_setting->PllRange = i; - break; - } - } - - sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); - temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; - temp <<= 0x10; - sclk_setting->Fcw_frac = (uint16_t)(0xFFFF & (temp / ref_clock)); - - pcc_target_percent = 10; /* Hardcode 10% for now. */ - pcc_target_freq = clock - (clock * pcc_target_percent / 100); - sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); - - ss_target_percent = 2; /* Hardcode 2% for now. */ - sclk_setting->SSc_En = 0; - if (ss_target_percent) { - sclk_setting->SSc_En = 1; - ss_target_freq = clock - (clock * ss_target_percent / 100); - sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); - temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; - temp <<= 0x10; - sclk_setting->Fcw1_frac = (uint16_t)(0xFFFF & (temp / ref_clock)); - } - - return 0; -} - -static int ellesmere_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, - struct phm_ppt_v1_clock_voltage_dependency_table *dep_table, - uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) -{ - uint32_t i; - uint16_t vddci; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - *voltage = *mvdd = 0; - - /* clock - voltage dependency table is empty table */ - if (dep_table->count == 0) - return -EINVAL; - - for (i = 0; i < dep_table->count; i++) { - /* find first sclk bigger than request */ - if (dep_table->entries[i].clk >= clock) { - *voltage |= (dep_table->entries[i].vddc * - VOLTAGE_SCALE) << VDDC_SHIFT; - if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->vddci_control) - *voltage |= (data->vbios_boot_state.vddci_bootup_value * - VOLTAGE_SCALE) << VDDCI_SHIFT; - else if (dep_table->entries[i].vddci) - *voltage |= (dep_table->entries[i].vddci * - VOLTAGE_SCALE) << VDDCI_SHIFT; - else { - vddci = phm_find_closest_vddci(&(data->vddci_voltage_table), - (dep_table->entries[i].vddc - - (uint16_t)data->vddc_vddci_delta)); - *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; - } - - if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control) - *mvdd = data->vbios_boot_state.mvdd_bootup_value * - VOLTAGE_SCALE; - else if (dep_table->entries[i].mvdd) - *mvdd = (uint32_t) dep_table->entries[i].mvdd * - VOLTAGE_SCALE; - - *voltage |= 1 << PHASES_SHIFT; - return 0; - } - } - - /* sclk is bigger than max sclk in the dependence table */ - *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; - - if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->vddci_control) - *voltage |= (data->vbios_boot_state.vddci_bootup_value * - VOLTAGE_SCALE) << VDDCI_SHIFT; - else if (dep_table->entries[i-1].vddci) { - vddci = phm_find_closest_vddci(&(data->vddci_voltage_table), - (dep_table->entries[i].vddc - - (uint16_t)data->vddc_vddci_delta)); - *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; - } - - if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control) - *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE; - else if (dep_table->entries[i].mvdd) - *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE; - - return 0; -} - -sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = { {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112}, - {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160}, - {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112}, - {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160}, - {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112}, - {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160}, - {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108}, - {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} }; - -static void ellesmere_get_sclk_range_table(struct pp_hwmgr *hwmgr) -{ - uint32_t i, ref_clk; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - SMU74_Discrete_DpmTable *table = &(data->smc_state_table); - struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } }; - - ref_clk = ellesemere_get_xclk(hwmgr); - - if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) { - for (i = 0; i < NUM_SCLK_RANGE; i++) { - table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting; - table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv; - table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc; - - table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper; - table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower; - - CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc); - CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper); - CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower); - } - return; - } - - for (i = 0; i < NUM_SCLK_RANGE; i++) { - - data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; - data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; - - table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting; - table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; - table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc; - - table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper; - table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower; - - CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc); - CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper); - CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower); - } -} - -/** -* Populates single SMC SCLK structure using the provided engine clock -* -* @param hwmgr the address of the hardware manager -* @param clock the engine clock to use to populate the structure -* @param sclk the SMC SCLK structure to be populated -*/ - -static int ellesmere_populate_single_graphic_level(struct pp_hwmgr *hwmgr, - uint32_t clock, uint16_t sclk_al_threshold, - struct SMU74_Discrete_GraphicsLevel *level) -{ - int result, i, temp; - /* PP_Clocks minClocks; */ - uint32_t mvdd; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - SMU_SclkSetting curr_sclk_setting = { 0 }; - - result = ellesmere_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting); - - /* populate graphics levels */ - result = ellesmere_get_dependency_volt_by_clk(hwmgr, - table_info->vdd_dep_on_sclk, clock, - &level->MinVoltage, &mvdd); - - PP_ASSERT_WITH_CODE((0 == result), - "can not find VDDC voltage value for " - "VDDC engine clock dependency table", - return result); - level->ActivityLevel = sclk_al_threshold; - - level->CcPwrDynRm = 0; - level->CcPwrDynRm1 = 0; - level->EnabledForActivity = 0; - level->EnabledForThrottle = 1; - level->UpHyst = 10; - level->DownHyst = 0; - level->VoltageDownHyst = 0; - level->PowerThrottle = 0; - - /* - * TODO: get minimum clocks from dal configaration - * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks); - */ - /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */ - - /* get level->DeepSleepDivId - if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) - level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR); - */ - PP_ASSERT_WITH_CODE((clock >= 2500), "Engine clock can't satisfy stutter requirement!", return 0); - for (i = ELLESMERE_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { - temp = clock / (1UL << i); - - if (temp >= 2500 || i == 0) - break; - } - - level->DeepSleepDivId = i; - - /* Default to slow, highest DPM level will be - * set to PPSMC_DISPLAY_WATERMARK_LOW later. - */ - if (data->update_up_hyst) - level->UpHyst = (uint8_t)data->up_hyst; - if (data->update_down_hyst) - level->DownHyst = (uint8_t)data->down_hyst; - - level->SclkSetting = curr_sclk_setting; - - CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage); - CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm); - CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1); - CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel); - CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency); - CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int); - CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac); - CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int); - CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate); - CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate); - CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate); - CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int); - CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac); - CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate); - return 0; -} - -/** -* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states -* -* @param hwmgr the address of the hardware manager -*/ -static int ellesmere_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_dpm_table *dpm_table = &data->dpm_table; - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; - uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count; - int result = 0; - uint32_t array = data->dpm_table_start + - offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); - uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) * - SMU74_MAX_LEVELS_GRAPHICS; - struct SMU74_Discrete_GraphicsLevel *levels = - data->smc_state_table.GraphicsLevel; - uint32_t i, max_entry; - uint8_t hightest_pcie_level_enabled = 0, - lowest_pcie_level_enabled = 0, - mid_pcie_level_enabled = 0, - count = 0; - - ellesmere_get_sclk_range_table(hwmgr); - - for (i = 0; i < dpm_table->sclk_table.count; i++) { - - result = ellesmere_populate_single_graphic_level(hwmgr, - dpm_table->sclk_table.dpm_levels[i].value, - (uint16_t)data->activity_target[i], - &(data->smc_state_table.GraphicsLevel[i])); - if (result) - return result; - - /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ - if (i > 1) - levels[i].DeepSleepDivId = 0; - } - - data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; - data->smc_state_table.GraphicsDpmLevelCount = - (uint8_t)dpm_table->sclk_table.count; - data->dpm_level_enable_mask.sclk_dpm_enable_mask = - phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); - - - if (pcie_table != NULL) { - PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt), - "There must be 1 or more PCIE levels defined in PPTable.", - return -EINVAL); - max_entry = pcie_entry_cnt - 1; - for (i = 0; i < dpm_table->sclk_table.count; i++) - levels[i].pcieDpmLevel = - (uint8_t) ((i < max_entry) ? i : max_entry); - } else { - while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && - ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & - (1 << (hightest_pcie_level_enabled + 1))) != 0)) - hightest_pcie_level_enabled++; - - while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && - ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & - (1 << lowest_pcie_level_enabled)) == 0)) - lowest_pcie_level_enabled++; - - while ((count < hightest_pcie_level_enabled) && - ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & - (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) - count++; - - mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) < - hightest_pcie_level_enabled ? - (lowest_pcie_level_enabled + 1 + count) : - hightest_pcie_level_enabled; - - /* set pcieDpmLevel to hightest_pcie_level_enabled */ - for (i = 2; i < dpm_table->sclk_table.count; i++) - levels[i].pcieDpmLevel = hightest_pcie_level_enabled; - - /* set pcieDpmLevel to lowest_pcie_level_enabled */ - levels[0].pcieDpmLevel = lowest_pcie_level_enabled; - - /* set pcieDpmLevel to mid_pcie_level_enabled */ - levels[1].pcieDpmLevel = mid_pcie_level_enabled; - } - /* level count will send to smc once at init smc table and never change */ - result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, - (uint32_t)array_size, data->sram_end); - - return result; -} - -static int ellesmere_populate_single_memory_level(struct pp_hwmgr *hwmgr, - uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - int result = 0; - struct cgs_display_info info = {0, 0, NULL}; - - cgs_get_active_displays_info(hwmgr->device, &info); - - if (table_info->vdd_dep_on_mclk) { - result = ellesmere_get_dependency_volt_by_clk(hwmgr, - table_info->vdd_dep_on_mclk, clock, - &mem_level->MinVoltage, &mem_level->MinMvdd); - PP_ASSERT_WITH_CODE((0 == result), - "can not find MinVddc voltage value from memory " - "VDDC voltage dependency table", return result); - } - - mem_level->MclkFrequency = clock; - mem_level->StutterEnable = 0; - mem_level->EnabledForThrottle = 1; - mem_level->EnabledForActivity = 0; - mem_level->UpHyst = 0; - mem_level->DownHyst = 100; - mem_level->VoltageDownHyst = 0; - mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target; - mem_level->StutterEnable = false; - - mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; - - data->display_timing.num_existing_displays = info.display_count; - - if ((data->mclk_stutter_mode_threshold) && - (clock <= data->mclk_stutter_mode_threshold) && - (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, - STUTTER_ENABLE) & 0x1)) - mem_level->StutterEnable = true; - - if (!result) { - CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd); - CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency); - CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel); - CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage); - } - return result; -} - -/** -* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states -* -* @param hwmgr the address of the hardware manager -*/ -static int ellesmere_populate_all_memory_levels(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_dpm_table *dpm_table = &data->dpm_table; - int result; - /* populate MCLK dpm table to SMU7 */ - uint32_t array = data->dpm_table_start + - offsetof(SMU74_Discrete_DpmTable, MemoryLevel); - uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) * - SMU74_MAX_LEVELS_MEMORY; - struct SMU74_Discrete_MemoryLevel *levels = - data->smc_state_table.MemoryLevel; - uint32_t i; - - for (i = 0; i < dpm_table->mclk_table.count; i++) { - PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), - "can not populate memory level as memory clock is zero", - return -EINVAL); - result = ellesmere_populate_single_memory_level(hwmgr, - dpm_table->mclk_table.dpm_levels[i].value, - &levels[i]); - if (result) - return result; - } - - /* Only enable level 0 for now. */ - levels[0].EnabledForActivity = 1; - - /* in order to prevent MC activity from stutter mode to push DPM up. - * the UVD change complements this by putting the MCLK in - * a higher state by default such that we are not effected by - * up threshold or and MCLK DPM latency. - */ - levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target; - CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel); - - data->smc_state_table.MemoryDpmLevelCount = - (uint8_t)dpm_table->mclk_table.count; - data->dpm_level_enable_mask.mclk_dpm_enable_mask = - phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); - /* set highest level watermark to high */ - levels[dpm_table->mclk_table.count - 1].DisplayWatermark = - PPSMC_DISPLAY_WATERMARK_HIGH; - - /* level count will send to smc once at init smc table and never change */ - result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, - (uint32_t)array_size, data->sram_end); - - return result; -} - -/** -* Populates the SMC MVDD structure using the provided memory clock. -* -* @param hwmgr the address of the hardware manager -* @param mclk the MCLK value to be used in the decision if MVDD should be high or low. -* @param voltage the SMC VOLTAGE structure to be populated -*/ -int ellesmere_populate_mvdd_value(struct pp_hwmgr *hwmgr, - uint32_t mclk, SMIO_Pattern *smio_pat) -{ - const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - uint32_t i = 0; - - if (ELLESMERE_VOLTAGE_CONTROL_NONE != data->mvdd_control) { - /* find mvdd value which clock is more than request */ - for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) { - if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) { - smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value; - break; - } - } - PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count, - "MVDD Voltage is outside the supported range.", - return -EINVAL); - } else - return -EINVAL; - - return 0; -} - -static int ellesmere_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, - SMU74_Discrete_DpmTable *table) -{ - int result = 0; - uint32_t sclk_frequency; - const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - SMIO_Pattern vol_level; - uint32_t mvdd; - uint16_t us_mvdd; - - table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; - - if (!data->sclk_dpm_key_disabled) { - /* Get MinVoltage and Frequency from DPM0, - * already converted to SMC_UL */ - sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value; - result = ellesmere_get_dependency_volt_by_clk(hwmgr, - table_info->vdd_dep_on_sclk, - table->ACPILevel.SclkFrequency, - &table->ACPILevel.MinVoltage, &mvdd); - PP_ASSERT_WITH_CODE((0 == result), - "Cannot find ACPI VDDC voltage value " - "in Clock Dependency Table", ); - } else { - sclk_frequency = data->vbios_boot_state.sclk_bootup_value; - table->ACPILevel.MinVoltage = - data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE; - } - - result = ellesmere_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting)); - PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result); - - table->ACPILevel.DeepSleepDivId = 0; - table->ACPILevel.CcPwrDynRm = 0; - table->ACPILevel.CcPwrDynRm1 = 0; - - CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); - CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage); - CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); - CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); - - CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency); - CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int); - CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac); - CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int); - CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate); - CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate); - CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate); - CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int); - CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac); - CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate); - - if (!data->mclk_dpm_key_disabled) { - /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */ - table->MemoryACPILevel.MclkFrequency = - data->dpm_table.mclk_table.dpm_levels[0].value; - result = ellesmere_get_dependency_volt_by_clk(hwmgr, - table_info->vdd_dep_on_mclk, - table->MemoryACPILevel.MclkFrequency, - &table->MemoryACPILevel.MinVoltage, &mvdd); - PP_ASSERT_WITH_CODE((0 == result), - "Cannot find ACPI VDDCI voltage value " - "in Clock Dependency Table", - ); - } else { - table->MemoryACPILevel.MclkFrequency = - data->vbios_boot_state.mclk_bootup_value; - table->MemoryACPILevel.MinVoltage = - data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE; - } - - us_mvdd = 0; - if ((ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control) || - (data->mclk_dpm_key_disabled)) - us_mvdd = data->vbios_boot_state.mvdd_bootup_value; - else { - if (!ellesmere_populate_mvdd_value(hwmgr, - data->dpm_table.mclk_table.dpm_levels[0].value, - &vol_level)) - us_mvdd = vol_level.Voltage; - } - - if (0 == ellesmere_populate_mvdd_value(hwmgr, 0, &vol_level)) - table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage); - else - table->MemoryACPILevel.MinMvdd = 0; - - table->MemoryACPILevel.StutterEnable = false; - - table->MemoryACPILevel.EnabledForThrottle = 0; - table->MemoryACPILevel.EnabledForActivity = 0; - table->MemoryACPILevel.UpHyst = 0; - table->MemoryACPILevel.DownHyst = 100; - table->MemoryACPILevel.VoltageDownHyst = 0; - table->MemoryACPILevel.ActivityLevel = - PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target); - - CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency); - CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage); - - return result; -} - -static int ellesmere_populate_smc_vce_level(struct pp_hwmgr *hwmgr, - SMU74_Discrete_DpmTable *table) -{ - int result = -EINVAL; - uint8_t count; - struct pp_atomctrl_clock_dividers_vi dividers; - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = - table_info->mm_dep_table; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - table->VceLevelCount = (uint8_t)(mm_table->count); - table->VceBootLevel = 0; - - for (count = 0; count < table->VceLevelCount; count++) { - table->VceLevel[count].Frequency = mm_table->entries[count].eclk; - table->VceLevel[count].MinVoltage |= - (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; - table->VceLevel[count].MinVoltage |= - ((mm_table->entries[count].vddc - data->vddc_vddci_delta) * - VOLTAGE_SCALE) << VDDCI_SHIFT; - table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT; - - /*retrieve divider value for VBIOS */ - result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, - table->VceLevel[count].Frequency, ÷rs); - PP_ASSERT_WITH_CODE((0 == result), - "can not find divide id for VCE engine clock", - return result); - - table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; - - CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); - CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage); - } - return result; -} - -static int ellesmere_populate_smc_samu_level(struct pp_hwmgr *hwmgr, - SMU74_Discrete_DpmTable *table) -{ - int result = -EINVAL; - uint8_t count; - struct pp_atomctrl_clock_dividers_vi dividers; - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = - table_info->mm_dep_table; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - table->SamuBootLevel = 0; - table->SamuLevelCount = (uint8_t)(mm_table->count); - - for (count = 0; count < table->SamuLevelCount; count++) { - /* not sure whether we need evclk or not */ - table->SamuLevel[count].Frequency = mm_table->entries[count].samclock; - table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc * - VOLTAGE_SCALE) << VDDC_SHIFT; - table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc - - data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT; - table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT; - - /* retrieve divider value for VBIOS */ - result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, - table->SamuLevel[count].Frequency, ÷rs); - PP_ASSERT_WITH_CODE((0 == result), - "can not find divide id for samu clock", return result); - - table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider; - - CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency); - CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage); - } - return result; -} - -static int ellesmere_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, - int32_t eng_clock, int32_t mem_clock, - SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs) -{ - uint32_t dram_timing; - uint32_t dram_timing2; - uint32_t burst_time; - int result; - - result = atomctrl_set_engine_dram_timings_rv770(hwmgr, - eng_clock, mem_clock); - PP_ASSERT_WITH_CODE(result == 0, - "Error calling VBIOS to set DRAM_TIMING.", return result); - - dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); - dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); - burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); - - - arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); - arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); - arb_regs->McArbBurstTime = (uint8_t)burst_time; - - return 0; -} - -static int ellesmere_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct SMU74_Discrete_MCArbDramTimingTable arb_regs; - uint32_t i, j; - int result = 0; - - for (i = 0; i < data->dpm_table.sclk_table.count; i++) { - for (j = 0; j < data->dpm_table.mclk_table.count; j++) { - result = ellesmere_populate_memory_timing_parameters(hwmgr, - data->dpm_table.sclk_table.dpm_levels[i].value, - data->dpm_table.mclk_table.dpm_levels[j].value, - &arb_regs.entries[i][j]); - if (result == 0) - result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j); - if (result != 0) - return result; - } - } - - result = ellesmere_copy_bytes_to_smc( - hwmgr->smumgr, - data->arb_table_start, - (uint8_t *)&arb_regs, - sizeof(SMU74_Discrete_MCArbDramTimingTable), - data->sram_end); - return result; -} - -static int ellesmere_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, - struct SMU74_Discrete_DpmTable *table) -{ - int result = -EINVAL; - uint8_t count; - struct pp_atomctrl_clock_dividers_vi dividers; - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = - table_info->mm_dep_table; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - table->UvdLevelCount = (uint8_t)(mm_table->count); - table->UvdBootLevel = 0; - - for (count = 0; count < table->UvdLevelCount; count++) { - table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; - table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; - table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc * - VOLTAGE_SCALE) << VDDC_SHIFT; - table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc - - data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT; - table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT; - - /* retrieve divider value for VBIOS */ - result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, - table->UvdLevel[count].VclkFrequency, ÷rs); - PP_ASSERT_WITH_CODE((0 == result), - "can not find divide id for Vclk clock", return result); - - table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; - - result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, - table->UvdLevel[count].DclkFrequency, ÷rs); - PP_ASSERT_WITH_CODE((0 == result), - "can not find divide id for Dclk clock", return result); - - table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; - - CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); - CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); - CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage); - - } - return result; -} - -static int ellesmere_populate_smc_boot_level(struct pp_hwmgr *hwmgr, - struct SMU74_Discrete_DpmTable *table) -{ - int result = 0; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - table->GraphicsBootLevel = 0; - table->MemoryBootLevel = 0; - - /* find boot level from dpm table */ - result = phm_find_boot_level(&(data->dpm_table.sclk_table), - data->vbios_boot_state.sclk_bootup_value, - (uint32_t *)&(table->GraphicsBootLevel)); - - result = phm_find_boot_level(&(data->dpm_table.mclk_table), - data->vbios_boot_state.mclk_bootup_value, - (uint32_t *)&(table->MemoryBootLevel)); - - table->BootVddc = data->vbios_boot_state.vddc_bootup_value * - VOLTAGE_SCALE; - table->BootVddci = data->vbios_boot_state.vddci_bootup_value * - VOLTAGE_SCALE; - table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value * - VOLTAGE_SCALE; - - CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc); - CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci); - CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd); - - return 0; -} - - -static int ellesmere_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - uint8_t count, level; - - count = (uint8_t)(table_info->vdd_dep_on_sclk->count); - - for (level = 0; level < count; level++) { - if (table_info->vdd_dep_on_sclk->entries[level].clk >= - data->vbios_boot_state.sclk_bootup_value) { - data->smc_state_table.GraphicsBootLevel = level; - break; - } - } - - count = (uint8_t)(table_info->vdd_dep_on_mclk->count); - for (level = 0; level < count; level++) { - if (table_info->vdd_dep_on_mclk->entries[level].clk >= - data->vbios_boot_state.mclk_bootup_value) { - data->smc_state_table.MemoryBootLevel = level; - break; - } - } - - return 0; -} - -static int ellesmere_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) -{ - uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks, - volt_with_cks, value; - uint16_t clock_freq_u16; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2, - volt_offset = 0; - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = - table_info->vdd_dep_on_sclk; - - stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount; - - /* Read SMU_Eefuse to read and calculate RO and determine - * if the part is SS or FF. if RO >= 1660MHz, part is FF. - */ - efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixSMU_EFUSE_0 + (146 * 4)); - efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixSMU_EFUSE_0 + (148 * 4)); - efuse &= 0xFF000000; - efuse = efuse >> 24; - efuse2 &= 0xF; - - if (efuse2 == 1) - ro = (2300 - 1350) * efuse / 255 + 1350; - else - ro = (2500 - 1000) * efuse / 255 + 1000; - - if (ro >= 1660) - type = 0; - else - type = 1; - - /* Populate Stretch amount */ - data->smc_state_table.ClockStretcherAmount = stretch_amount; - - /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */ - for (i = 0; i < sclk_table->count; i++) { - data->smc_state_table.Sclk_CKS_masterEn0_7 |= - sclk_table->entries[i].cks_enable << i; - volt_without_cks = (uint32_t)((14041 * - (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 / - (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000))); - volt_with_cks = (uint32_t)((13946 * - (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 / - (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000))); - if (volt_without_cks >= volt_with_cks) - volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks + - sclk_table->entries[i].cks_voffset) * 100 / 625) + 1); - data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; - } - - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, - STRETCH_ENABLE, 0x0); - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, - masterReset, 0x1); - /* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, - masterReset, 0x0); - - /* Populate CKS Lookup Table */ - if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5) - stretch_amount2 = 0; - else if (stretch_amount == 3 || stretch_amount == 4) - stretch_amount2 = 1; - else { - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ClockStretcher); - PP_ASSERT_WITH_CODE(false, - "Stretch Amount in PPTable not supported\n", - return -EINVAL); - } - - value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixPWR_CKS_CNTL); - value &= 0xFFC2FF87; - data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq = - ellesmere_clock_stretcher_lookup_table[stretch_amount2][0]; - data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq = - ellesmere_clock_stretcher_lookup_table[stretch_amount2][1]; - clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table. - GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100); - if (ellesmere_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16 - && ellesmere_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) { - /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */ - value |= (ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]) << 16; - /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */ - value |= (ellesmere_clock_stretcher_lookup_table[stretch_amount2][2]) << 18; - /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */ - value |= (ellesmere_clock_stretch_amount_conversion - [ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]] - [stretch_amount]) << 3; - } - CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq); - CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq); - data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting = - ellesmere_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F; - data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |= - (ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]) << 7; - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixPWR_CKS_CNTL, value); - - /* Populate DDT Lookup Table */ - for (i = 0; i < 4; i++) { - /* Assign the minimum and maximum VID stored - * in the last row of Clock Stretcher Voltage Table. - */ - data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID = - (uint8_t) ellesmere_clock_stretcher_ddt_table[type][i][2]; - data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID = - (uint8_t) ellesmere_clock_stretcher_ddt_table[type][i][3]; - /* Loop through each SCLK and check the frequency - * to see if it lies within the frequency for clock stretcher. - */ - for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) { - cks_setting = 0; - clock_freq = PP_SMC_TO_HOST_UL( - data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency); - /* Check the allowed frequency against the sclk level[j]. - * Sclk's endianness has already been converted, - * and it's in 10Khz unit, - * as opposed to Data table, which is in Mhz unit. - */ - if (clock_freq >= (ellesmere_clock_stretcher_ddt_table[type][i][0]) * 100) { - cks_setting |= 0x2; - if (clock_freq < (ellesmere_clock_stretcher_ddt_table[type][i][1]) * 100) - cks_setting |= 0x1; - } - data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting - |= cks_setting << (j * 2); - } - CONVERT_FROM_HOST_TO_SMC_US( - data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting); - } - - value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL); - value &= 0xFFFFFFFE; - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value); - - return 0; -} - -/** -* Populates the SMC VRConfig field in DPM table. -* -* @param hwmgr the address of the hardware manager -* @param table the SMC DPM table structure to be populated -* @return always 0 -*/ -static int ellesmere_populate_vr_config(struct pp_hwmgr *hwmgr, - struct SMU74_Discrete_DpmTable *table) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - uint16_t config; - - config = VR_MERGED_WITH_VDDC; - table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT); - - /* Set Vddc Voltage Controller */ - if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { - config = VR_SVI2_PLANE_1; - table->VRConfig |= config; - } else { - PP_ASSERT_WITH_CODE(false, - "VDDC should be on SVI2 control in merged mode!", - ); - } - /* Set Vddci Voltage Controller */ - if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { - config = VR_SVI2_PLANE_2; /* only in merged mode */ - table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); - } else if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { - config = VR_SMIO_PATTERN_1; - table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); - } else { - config = VR_STATIC_VOLTAGE; - table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); - } - /* Set Mvdd Voltage Controller */ - if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { - config = VR_SVI2_PLANE_2; - table->VRConfig |= (config << VRCONF_MVDD_SHIFT); - } else if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { - config = VR_SMIO_PATTERN_2; - table->VRConfig |= (config << VRCONF_MVDD_SHIFT); - } else { - config = VR_STATIC_VOLTAGE; - table->VRConfig |= (config << VRCONF_MVDD_SHIFT); - } - - return 0; -} - -/** -* Initializes the SMC table and uploads it -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr) -{ - int result; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table); - const struct ellesmere_ulv_parm *ulv = &(data->ulv); - uint8_t i; - struct pp_atomctrl_gpio_pin_assignment gpio_pin; - pp_atomctrl_clock_dividers_vi dividers; - - result = ellesmere_setup_default_dpm_tables(hwmgr); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to setup default DPM tables!", return result); - - if (ELLESMERE_VOLTAGE_CONTROL_NONE != data->voltage_control) - ellesmere_populate_smc_voltage_tables(hwmgr, table); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_AutomaticDCTransition)) - table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StepVddc)) - table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; - - if (data->is_memory_gddr5) - table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; - - if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) { - result = ellesmere_populate_ulv_state(hwmgr, table); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to initialize ULV state!", return result); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_ULV_PARAMETER, PPELLESMERE_CGULVPARAMETER_DFLT); - } - - result = ellesmere_populate_smc_link_level(hwmgr, table); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to initialize Link Level!", return result); - - result = ellesmere_populate_all_graphic_levels(hwmgr); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to initialize Graphics Level!", return result); - - result = ellesmere_populate_all_memory_levels(hwmgr); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to initialize Memory Level!", return result); - - result = ellesmere_populate_smc_acpi_level(hwmgr, table); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to initialize ACPI Level!", return result); - - result = ellesmere_populate_smc_vce_level(hwmgr, table); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to initialize VCE Level!", return result); - - result = ellesmere_populate_smc_samu_level(hwmgr, table); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to initialize SAMU Level!", return result); - - /* Since only the initial state is completely set up at this point - * (the other states are just copies of the boot state) we only - * need to populate the ARB settings for the initial state. - */ - result = ellesmere_program_memory_timing_parameters(hwmgr); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to Write ARB settings for the initial state.", return result); - - result = ellesmere_populate_smc_uvd_level(hwmgr, table); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to initialize UVD Level!", return result); - - result = ellesmere_populate_smc_boot_level(hwmgr, table); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to initialize Boot Level!", return result); - - result = ellesmere_populate_smc_initailial_state(hwmgr); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to initialize Boot State!", return result); - - result = ellesmere_populate_bapm_parameters_in_dpm_table(hwmgr); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to populate BAPM Parameters!", return result); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ClockStretcher)) { - result = ellesmere_populate_clock_stretcher_data_table(hwmgr); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to populate Clock Stretcher Data Table!", - return result); - } - - table->GraphicsVoltageChangeEnable = 1; - table->GraphicsThermThrottleEnable = 1; - table->GraphicsInterval = 1; - table->VoltageInterval = 1; - table->ThermalInterval = 1; - table->TemperatureLimitHigh = - table_info->cac_dtp_table->usTargetOperatingTemp * - ELLESMERE_Q88_FORMAT_CONVERSION_UNIT; - table->TemperatureLimitLow = - (table_info->cac_dtp_table->usTargetOperatingTemp - 1) * - ELLESMERE_Q88_FORMAT_CONVERSION_UNIT; - table->MemoryVoltageChangeEnable = 1; - table->MemoryInterval = 1; - table->VoltageResponseTime = 0; - table->PhaseResponseTime = 0; - table->MemoryThermThrottleEnable = 1; - table->PCIeBootLinkLevel = 0; - table->PCIeGenInterval = 1; - - result = ellesmere_populate_vr_config(hwmgr, table); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to populate VRConfig setting!", return result); - - table->ThermGpio = 17; - table->SclkStepSize = 0x4000; - - if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) { - table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift; - } else { - table->VRHotGpio = ELLESMERE_UNUSED_GPIO_PIN; - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_RegulatorHot); - } - - if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID, - &gpio_pin)) { - table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift; - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_AutomaticDCTransition); - } else { - table->AcDcGpio = ELLESMERE_UNUSED_GPIO_PIN; - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_AutomaticDCTransition); - } - - /* Thermal Output GPIO */ - if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID, - &gpio_pin)) { - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ThermalOutGPIO); - - table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift; - - /* For porlarity read GPIOPAD_A with assigned Gpio pin - * since VBIOS will program this register to set 'inactive state', - * driver can then determine 'active state' from this and - * program SMU with correct polarity - */ - table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) - & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0; - table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY; - - /* if required, combine VRHot/PCC with thermal out GPIO */ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot) - && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal)) - table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT; - } else { - table->ThermOutGpio = 17; - table->ThermOutPolarity = 1; - table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE; - } - - /* Populate BIF_SCLK levels into SMC DPM table */ - for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) { - result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], ÷rs); - PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result); - - if (i == 0) - table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider)); - else - table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider)); - } - - for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++) - table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]); - - CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); - CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig); - CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1); - CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2); - CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); - CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); - CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); - CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); - CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); - - /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ - result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, - data->dpm_table_start + - offsetof(SMU74_Discrete_DpmTable, SystemFlags), - (uint8_t *)&(table->SystemFlags), - sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController), - data->sram_end); - PP_ASSERT_WITH_CODE(0 == result, - "Failed to upload dpm data to SMC memory!", return result); - - return 0; -} - -/** -* Initialize the ARB DRAM timing table's index field. -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int ellesmere_init_arb_table_index(struct pp_hwmgr *hwmgr) -{ - const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - uint32_t tmp; - int result; - - /* This is a read-modify-write on the first byte of the ARB table. - * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure - * is the field 'current'. - * This solution is ugly, but we never write the whole table only - * individual fields in it. - * In reality this field should not be in that structure - * but in a soft register. - */ - result = ellesmere_read_smc_sram_dword(hwmgr->smumgr, - data->arb_table_start, &tmp, data->sram_end); - - if (result) - return result; - - tmp &= 0x00FFFFFF; - tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; - - return ellesmere_write_smc_sram_dword(hwmgr->smumgr, - data->arb_table_start, tmp, data->sram_end); -} - -static int ellesmere_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) -{ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_RegulatorHot)) - return smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_EnableVRHotGPIOInterrupt); - - return 0; -} - -static int ellesmere_enable_sclk_control(struct pp_hwmgr *hwmgr) -{ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, - SCLK_PWRMGT_OFF, 0); - return 0; -} - -static int ellesmere_enable_ulv(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_ulv_parm *ulv = &(data->ulv); - - if (ulv->ulv_supported) - return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV); - - return 0; -} - -static int ellesmere_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) -{ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkDeepSleep)) { - if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON)) - PP_ASSERT_WITH_CODE(false, - "Attempt to enable Master Deep Sleep switch failed!", - return -1); - } else { - if (smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_MASTER_DeepSleep_OFF)) { - PP_ASSERT_WITH_CODE(false, - "Attempt to disable Master Deep Sleep switch failed!", - return -1); - } - } - - return 0; -} - -static int ellesmere_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - /* enable SCLK dpm */ - if (!data->sclk_dpm_key_disabled) - PP_ASSERT_WITH_CODE( - (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)), - "Failed to enable SCLK DPM during DPM Start Function!", - return -1); - - /* enable MCLK dpm */ - if (0 == data->mclk_dpm_key_disabled) { - - PP_ASSERT_WITH_CODE( - (0 == smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_MCLKDPM_Enable)), - "Failed to enable MCLK DPM during DPM Start Function!", - return -1); - - - PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005); - udelay(10); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005); - } - - return 0; -} - -static int ellesmere_start_dpm(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - /*enable general power management */ - - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, - GLOBAL_PWRMGT_EN, 1); - - /* enable sclk deep sleep */ - - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, - DYNAMIC_PM_EN, 1); - - /* prepare for PCIE DPM */ - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - data->soft_regs_start + offsetof(SMU74_SoftRegisters, - VoltageChangeTimeout), 0x1000); - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, - SWRST_COMMAND_1, RESETLC, 0x0); -/* - PP_ASSERT_WITH_CODE( - (0 == smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_Voltage_Cntl_Enable)), - "Failed to enable voltage DPM during DPM Start Function!", - return -1); -*/ - - if (ellesmere_enable_sclk_mclk_dpm(hwmgr)) { - printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!"); - return -1; - } - - /* enable PCIE dpm */ - if (0 == data->pcie_dpm_key_disabled) { - PP_ASSERT_WITH_CODE( - (0 == smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_PCIeDPM_Enable)), - "Failed to enable pcie DPM during DPM Start Function!", - return -1); - } - - PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_EnableACDCGPIOInterrupt)), - "Failed to enable AC DC GPIO Interrupt!", - ); - - return 0; -} - -static void ellesmere_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources) -{ - bool protection; - enum DPM_EVENT_SRC src; - - switch (sources) { - default: - printk(KERN_ERR "Unknown throttling event sources."); - /* fall through */ - case 0: - protection = false; - /* src is unused */ - break; - case (1 << PHM_AutoThrottleSource_Thermal): - protection = true; - src = DPM_EVENT_SRC_DIGITAL; - break; - case (1 << PHM_AutoThrottleSource_External): - protection = true; - src = DPM_EVENT_SRC_EXTERNAL; - break; - case (1 << PHM_AutoThrottleSource_External) | - (1 << PHM_AutoThrottleSource_Thermal): - protection = true; - src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL; - break; - } - /* Order matters - don't enable thermal protection for the wrong source. */ - if (protection) { - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL, - DPM_EVENT_SRC, src); - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, - THERMAL_PROTECTION_DIS, - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ThermalController)); - } else - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, - THERMAL_PROTECTION_DIS, 1); -} - -static int ellesmere_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, - PHM_AutoThrottleSource source) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - if (!(data->active_auto_throttle_sources & (1 << source))) { - data->active_auto_throttle_sources |= 1 << source; - ellesmere_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); - } - return 0; -} - -static int ellesmere_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) -{ - return ellesmere_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); -} - -int ellesmere_pcie_performance_request(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - data->pcie_performance_request = true; - - return 0; -} - -int ellesmere_enable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - int tmp_result, result = 0; - tmp_result = (!ellesmere_is_dpm_running(hwmgr)) ? 0 : -1; - PP_ASSERT_WITH_CODE(result == 0, - "DPM is already running right now, no need to enable DPM!", - return 0); - - if (ellesmere_voltage_control(hwmgr)) { - tmp_result = ellesmere_enable_voltage_control(hwmgr); - PP_ASSERT_WITH_CODE(tmp_result == 0, - "Failed to enable voltage control!", - result = tmp_result); - - tmp_result = ellesmere_construct_voltage_tables(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to contruct voltage tables!", - result = tmp_result); - } - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EngineSpreadSpectrumSupport)) - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ThermalController)) - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0); - - tmp_result = ellesmere_program_static_screen_threshold_parameters(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to program static screen threshold parameters!", - result = tmp_result); - - tmp_result = ellesmere_enable_display_gap(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable display gap!", result = tmp_result); - - tmp_result = ellesmere_program_voting_clients(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to program voting clients!", result = tmp_result); - - tmp_result = ellesmere_process_firmware_header(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to process firmware header!", result = tmp_result); - - tmp_result = ellesmere_initial_switch_from_arbf0_to_f1(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to initialize switch from ArbF0 to F1!", - result = tmp_result); - - tmp_result = ellesmere_init_smc_table(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to initialize SMC table!", result = tmp_result); - - tmp_result = ellesmere_init_arb_table_index(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to initialize ARB table index!", result = tmp_result); - - tmp_result = ellesmere_populate_pm_fuses(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to populate PM fuses!", result = tmp_result); - - tmp_result = ellesmere_enable_vrhot_gpio_interrupt(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable VR hot GPIO interrupt!", result = tmp_result); - - tmp_result = ellesmere_enable_sclk_control(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable SCLK control!", result = tmp_result); - - tmp_result = ellesmere_enable_smc_voltage_controller(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable voltage control!", result = tmp_result); - - tmp_result = ellesmere_enable_ulv(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable ULV!", result = tmp_result); - - tmp_result = ellesmere_enable_deep_sleep_master_switch(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable deep sleep master switch!", result = tmp_result); - - tmp_result = ellesmere_start_dpm(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to start DPM!", result = tmp_result); - - tmp_result = ellesmere_enable_smc_cac(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable SMC CAC!", result = tmp_result); - - tmp_result = ellesmere_enable_power_containment(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable power containment!", result = tmp_result); - - tmp_result = ellesmere_power_control_set_level(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to power control set level!", result = tmp_result); - - tmp_result = ellesmere_enable_thermal_auto_throttle(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable thermal auto throttle!", result = tmp_result); - - tmp_result = ellesmere_pcie_performance_request(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable thermal auto throttle!", result = tmp_result); - - return result; -} - -int ellesmere_disable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - - return 0; -} - -int ellesmere_reset_asic_tasks(struct pp_hwmgr *hwmgr) -{ - - return 0; -} - -int ellesmere_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) -{ - return phm_hwmgr_backend_fini(hwmgr); -} - -int ellesmere_set_features_platform_caps(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkDeepSleep); - - if (data->mvdd_control == ELLESMERE_VOLTAGE_CONTROL_NONE) - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EnableMVDDControl); - - if (data->vddci_control == ELLESMERE_VOLTAGE_CONTROL_NONE) - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ControlVDDCI); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EnableSMU7ThermalManagement); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicPowerManagement); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SMC); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_NonABMSupportInPPLib); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicUVDState); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkThrottleLowNotification); - - /* power tune caps Assume disabled */ - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SQRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DBRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TDRamping); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TCPRamping); - - return 0; -} - -static void ellesmere_init_dpm_defaults(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - ellesmere_initialize_power_tune_defaults(hwmgr); - - data->pcie_gen_performance.max = PP_PCIEGen1; - data->pcie_gen_performance.min = PP_PCIEGen3; - data->pcie_gen_power_saving.max = PP_PCIEGen1; - data->pcie_gen_power_saving.min = PP_PCIEGen3; - data->pcie_lane_performance.max = 0; - data->pcie_lane_performance.min = 16; - data->pcie_lane_power_saving.max = 0; - data->pcie_lane_power_saving.min = 16; -} - -/** -* Get Leakage VDDC based on leakage ID. -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always 0 -*/ -static int ellesmere_get_evv_voltages(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - uint16_t vv_id; - uint16_t vddc = 0; - uint16_t i, j; - uint32_t sclk = 0; - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = - table_info->vdd_dep_on_sclk; - int result; - - for (i = 0; i < ELLESMERE_MAX_LEAKAGE_COUNT; i++) { - vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; - if (!phm_get_sclk_for_voltage_evv(hwmgr, - table_info->vddc_lookup_table, vv_id, &sclk)) { - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ClockStretcher)) { - for (j = 1; j < sclk_table->count; j++) { - if (sclk_table->entries[j].clk == sclk && - sclk_table->entries[j].cks_enable == 0) { - sclk += 5000; - break; - } - } - } - - - PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, - VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc), - "Error retrieving EVV voltage value!", - continue); - - - /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ - PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0), - "Invalid VDDC value", result = -EINVAL;); - - /* the voltage should not be zero nor equal to leakage ID */ - if (vddc != 0 && vddc != vv_id) { - data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100); - data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id; - data->vddc_leakage.count++; - } - } - } - - return 0; -} - -/** - * Change virtual leakage voltage to actual value. - * - * @param hwmgr the address of the powerplay hardware manager. - * @param pointer to changing voltage - * @param pointer to leakage table - */ -static void ellesmere_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, - uint16_t *voltage, struct ellesmere_leakage_voltage *leakage_table) -{ - uint32_t index; - - /* search for leakage voltage ID 0xff01 ~ 0xff08 */ - for (index = 0; index < leakage_table->count; index++) { - /* if this voltage matches a leakage voltage ID */ - /* patch with actual leakage voltage */ - if (leakage_table->leakage_id[index] == *voltage) { - *voltage = leakage_table->actual_voltage[index]; - break; - } - } - - if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) - printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n"); -} - -/** -* Patch voltage lookup table by EVV leakages. -* -* @param hwmgr the address of the powerplay hardware manager. -* @param pointer to voltage lookup table -* @param pointer to leakage table -* @return always 0 -*/ -static int ellesmere_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, - phm_ppt_v1_voltage_lookup_table *lookup_table, - struct ellesmere_leakage_voltage *leakage_table) -{ - uint32_t i; - - for (i = 0; i < lookup_table->count; i++) - ellesmere_patch_with_vdd_leakage(hwmgr, - &lookup_table->entries[i].us_vdd, leakage_table); - - return 0; -} - -static int ellesmere_patch_clock_voltage_limits_with_vddc_leakage( - struct pp_hwmgr *hwmgr, struct ellesmere_leakage_voltage *leakage_table, - uint16_t *vddc) -{ - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - ellesmere_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); - hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = - table_info->max_clock_voltage_on_dc.vddc; - return 0; -} - -static int ellesmere_patch_voltage_dependency_tables_with_lookup_table( - struct pp_hwmgr *hwmgr) -{ - uint8_t entryId; - uint8_t voltageId; - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = - table_info->vdd_dep_on_sclk; - struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = - table_info->vdd_dep_on_mclk; - struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = - table_info->mm_dep_table; - - for (entryId = 0; entryId < sclk_table->count; ++entryId) { - voltageId = sclk_table->entries[entryId].vddInd; - sclk_table->entries[entryId].vddc = - table_info->vddc_lookup_table->entries[voltageId].us_vdd; - } - - for (entryId = 0; entryId < mclk_table->count; ++entryId) { - voltageId = mclk_table->entries[entryId].vddInd; - mclk_table->entries[entryId].vddc = - table_info->vddc_lookup_table->entries[voltageId].us_vdd; - } - - for (entryId = 0; entryId < mm_table->count; ++entryId) { - voltageId = mm_table->entries[entryId].vddcInd; - mm_table->entries[entryId].vddc = - table_info->vddc_lookup_table->entries[voltageId].us_vdd; - } - - return 0; - -} - -static int ellesmere_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) -{ - /* Need to determine if we need calculated voltage. */ - return 0; -} - -static int ellesmere_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) -{ - /* Need to determine if we need calculated voltage from mm table. */ - return 0; -} - -static int ellesmere_sort_lookup_table(struct pp_hwmgr *hwmgr, - struct phm_ppt_v1_voltage_lookup_table *lookup_table) -{ - uint32_t table_size, i, j; - struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record; - table_size = lookup_table->count; - - PP_ASSERT_WITH_CODE(0 != lookup_table->count, - "Lookup table is empty", return -EINVAL); - - /* Sorting voltages */ - for (i = 0; i < table_size - 1; i++) { - for (j = i + 1; j > 0; j--) { - if (lookup_table->entries[j].us_vdd < - lookup_table->entries[j - 1].us_vdd) { - tmp_voltage_lookup_record = lookup_table->entries[j - 1]; - lookup_table->entries[j - 1] = lookup_table->entries[j]; - lookup_table->entries[j] = tmp_voltage_lookup_record; - } - } - } - - return 0; -} - -static int ellesmere_complete_dependency_tables(struct pp_hwmgr *hwmgr) -{ - int result = 0; - int tmp_result; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - tmp_result = ellesmere_patch_lookup_table_with_leakage(hwmgr, - table_info->vddc_lookup_table, &(data->vddc_leakage)); - if (tmp_result) - result = tmp_result; - - tmp_result = ellesmere_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, - &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); - if (tmp_result) - result = tmp_result; - - tmp_result = ellesmere_patch_voltage_dependency_tables_with_lookup_table(hwmgr); - if (tmp_result) - result = tmp_result; - - tmp_result = ellesmere_calc_voltage_dependency_tables(hwmgr); - if (tmp_result) - result = tmp_result; - - tmp_result = ellesmere_calc_mm_voltage_dependency_table(hwmgr); - if (tmp_result) - result = tmp_result; - - tmp_result = ellesmere_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); - if (tmp_result) - result = tmp_result; - - return result; -} - -static int ellesmere_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = - table_info->vdd_dep_on_sclk; - struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = - table_info->vdd_dep_on_mclk; - - PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, - "VDD dependency on SCLK table is missing. \ - This table is mandatory", return -EINVAL); - PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, - "VDD dependency on SCLK table has to have is missing. \ - This table is mandatory", return -EINVAL); - - PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, - "VDD dependency on MCLK table is missing. \ - This table is mandatory", return -EINVAL); - PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, - "VDD dependency on MCLK table has to have is missing. \ - This table is mandatory", return -EINVAL); - - table_info->max_clock_voltage_on_ac.sclk = - allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; - table_info->max_clock_voltage_on_ac.mclk = - allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; - table_info->max_clock_voltage_on_ac.vddc = - allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; - table_info->max_clock_voltage_on_ac.vddci = - allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; - - return 0; -} - -int ellesmere_hwmgr_backend_init(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; - uint32_t temp_reg; - int result; - - data->dll_default_on = false; - data->sram_end = SMC_RAM_END; - - data->disable_dpm_mask = 0xFF; - data->static_screen_threshold = PPELLESMERE_STATICSCREENTHRESHOLD_DFLT; - data->static_screen_threshold_unit = PPELLESMERE_STATICSCREENTHRESHOLD_DFLT; - data->activity_target[0] = PPELLESMERE_TARGETACTIVITY_DFLT; - data->activity_target[1] = PPELLESMERE_TARGETACTIVITY_DFLT; - data->activity_target[2] = PPELLESMERE_TARGETACTIVITY_DFLT; - data->activity_target[3] = PPELLESMERE_TARGETACTIVITY_DFLT; - data->activity_target[4] = PPELLESMERE_TARGETACTIVITY_DFLT; - data->activity_target[5] = PPELLESMERE_TARGETACTIVITY_DFLT; - data->activity_target[6] = PPELLESMERE_TARGETACTIVITY_DFLT; - data->activity_target[7] = PPELLESMERE_TARGETACTIVITY_DFLT; - - data->voting_rights_clients0 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT0; - data->voting_rights_clients1 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT1; - data->voting_rights_clients2 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT2; - data->voting_rights_clients3 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT3; - data->voting_rights_clients4 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT4; - data->voting_rights_clients5 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT5; - data->voting_rights_clients6 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT6; - data->voting_rights_clients7 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT7; - - data->vddc_vddci_delta = VDDC_VDDCI_DELTA; - - data->mclk_activity_target = PPELLESMERE_MCLK_TARGETACTIVITY_DFLT; - - /* need to set voltage control types before EVV patching */ - data->voltage_control = ELLESMERE_VOLTAGE_CONTROL_NONE; - data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_NONE; - data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_NONE; - - if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, - VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) - data->voltage_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2; - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicPatchPowerState); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EnableMVDDControl)) { - if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, - VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) - data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_BY_GPIO; - else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, - VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) - data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2; - } - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ControlVDDCI)) { - if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, - VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) - data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_BY_GPIO; - else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, - VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) - data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2; - } - - ellesmere_set_features_platform_caps(hwmgr); - - ellesmere_init_dpm_defaults(hwmgr); - - /* Get leakage voltage based on leakage ID. */ - result = ellesmere_get_evv_voltages(hwmgr); - - if (result) { - printk("Get EVV Voltage Failed. Abort Driver loading!\n"); - return -1; - } - - ellesmere_complete_dependency_tables(hwmgr); - ellesmere_set_private_data_based_on_pptable(hwmgr); - - /* Initalize Dynamic State Adjustment Rule Settings */ - result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr); - - if (0 == result) { - struct cgs_system_info sys_info = {0}; - - data->is_tlu_enabled = 0; - - hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = - ELLESMERE_MAX_HARDWARE_POWERLEVELS; - hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; - hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; - hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ -/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ - hwmgr->platform_descriptor.clockStep.engineClock = 500; - hwmgr->platform_descriptor.clockStep.memoryClock = 500; - - if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) { - temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL); - switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) { - case 0: - temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1); - break; - case 1: - temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2); - break; - case 2: - temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1); - break; - case 3: - temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1); - break; - case 4: - temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1); - break; - default: - PP_ASSERT_WITH_CODE(0, - "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!", - ); - break; - } - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg); - } - - sys_info.size = sizeof(struct cgs_system_info); - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO; - result = cgs_query_system_info(hwmgr->device, &sys_info); - if (result) - data->pcie_gen_cap = 0x30007; - else - data->pcie_gen_cap = (uint32_t)sys_info.value; - if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) - data->pcie_spc_cap = 20; - sys_info.size = sizeof(struct cgs_system_info); - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW; - result = cgs_query_system_info(hwmgr->device, &sys_info); - if (result) - data->pcie_lane_cap = 0x2f0000; - else - data->pcie_lane_cap = (uint32_t)sys_info.value; - } else { - /* Ignore return value in here, we are cleaning up a mess. */ - ellesmere_hwmgr_backend_fini(hwmgr); - } - - return 0; -} - -static int ellesmere_force_dpm_highest(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - uint32_t level, tmp; - - if (!data->pcie_dpm_key_disabled) { - if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { - level = 0; - tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; - while (tmp >>= 1) - level++; - - if (level) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_PCIeDPM_ForceLevel, level); - } - } - - if (!data->sclk_dpm_key_disabled) { - if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { - level = 0; - tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; - while (tmp >>= 1) - level++; - - if (level) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SCLKDPM_SetEnabledMask, - (1 << level)); - } - } - - if (!data->mclk_dpm_key_disabled) { - if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { - level = 0; - tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; - while (tmp >>= 1) - level++; - - if (level) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_MCLKDPM_SetEnabledMask, - (1 << level)); - } - } - - return 0; -} - -static int ellesmere_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - phm_apply_dal_min_voltage_request(hwmgr); - - if (!data->sclk_dpm_key_disabled) { - if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SCLKDPM_SetEnabledMask, - data->dpm_level_enable_mask.sclk_dpm_enable_mask); - } - - if (!data->mclk_dpm_key_disabled) { - if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_MCLKDPM_SetEnabledMask, - data->dpm_level_enable_mask.mclk_dpm_enable_mask); - } - - return 0; -} - -static int ellesmere_unforce_dpm_levels(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - if (!ellesmere_is_dpm_running(hwmgr)) - return -EINVAL; - - if (!data->pcie_dpm_key_disabled) { - smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_PCIeDPM_UnForceLevel); - } - - return ellesmere_upload_dpm_level_enable_mask(hwmgr); -} - -static int ellesmere_force_dpm_lowest(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = - (struct ellesmere_hwmgr *)(hwmgr->backend); - uint32_t level; - - if (!data->sclk_dpm_key_disabled) - if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { - level = phm_get_lowest_enabled_level(hwmgr, - data->dpm_level_enable_mask.sclk_dpm_enable_mask); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SCLKDPM_SetEnabledMask, - (1 << level)); - - } -/* uvd is enabled, can't set mclk low right now - if (!data->mclk_dpm_key_disabled) { - if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { - level = phm_get_lowest_enabled_level(hwmgr, - data->dpm_level_enable_mask.mclk_dpm_enable_mask); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_MCLKDPM_SetEnabledMask, - (1 << level)); - } - } -*/ - if (!data->pcie_dpm_key_disabled) { - if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { - level = phm_get_lowest_enabled_level(hwmgr, - data->dpm_level_enable_mask.pcie_dpm_enable_mask); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_PCIeDPM_ForceLevel, - (level)); - } - } - - return 0; - -} -static int ellesmere_force_dpm_level(struct pp_hwmgr *hwmgr, - enum amd_dpm_forced_level level) -{ - int ret = 0; - - switch (level) { - case AMD_DPM_FORCED_LEVEL_HIGH: - ret = ellesmere_force_dpm_highest(hwmgr); - if (ret) - return ret; - break; - case AMD_DPM_FORCED_LEVEL_LOW: - ret = ellesmere_force_dpm_lowest(hwmgr); - if (ret) - return ret; - break; - case AMD_DPM_FORCED_LEVEL_AUTO: - ret = ellesmere_unforce_dpm_levels(hwmgr); - if (ret) - return ret; - break; - default: - break; - } - - hwmgr->dpm_level = level; - - return ret; -} - -static int ellesmere_get_power_state_size(struct pp_hwmgr *hwmgr) -{ - return sizeof(struct ellesmere_power_state); -} - - -static int ellesmere_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, - struct pp_power_state *request_ps, - const struct pp_power_state *current_ps) -{ - - struct ellesmere_power_state *ellesmere_ps = - cast_phw_ellesmere_power_state(&request_ps->hardware); - uint32_t sclk; - uint32_t mclk; - struct PP_Clocks minimum_clocks = {0}; - bool disable_mclk_switching; - bool disable_mclk_switching_for_frame_lock; - struct cgs_display_info info = {0}; - const struct phm_clock_and_voltage_limits *max_limits; - uint32_t i; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - int32_t count; - int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; - - data->battery_state = (PP_StateUILabel_Battery == - request_ps->classification.ui_label); - - PP_ASSERT_WITH_CODE(ellesmere_ps->performance_level_count == 2, - "VI should always have 2 performance levels", - ); - - max_limits = (PP_PowerSource_AC == hwmgr->power_source) ? - &(hwmgr->dyn_state.max_clock_voltage_on_ac) : - &(hwmgr->dyn_state.max_clock_voltage_on_dc); - - /* Cap clock DPM tables at DC MAX if it is in DC. */ - if (PP_PowerSource_DC == hwmgr->power_source) { - for (i = 0; i < ellesmere_ps->performance_level_count; i++) { - if (ellesmere_ps->performance_levels[i].memory_clock > max_limits->mclk) - ellesmere_ps->performance_levels[i].memory_clock = max_limits->mclk; - if (ellesmere_ps->performance_levels[i].engine_clock > max_limits->sclk) - ellesmere_ps->performance_levels[i].engine_clock = max_limits->sclk; - } - } - - ellesmere_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk; - ellesmere_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk; - - cgs_get_active_displays_info(hwmgr->device, &info); - - /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ - - /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */ - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StablePState)) { - max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); - stable_pstate_sclk = (max_limits->sclk * 75) / 100; - - for (count = table_info->vdd_dep_on_sclk->count - 1; - count >= 0; count--) { - if (stable_pstate_sclk >= - table_info->vdd_dep_on_sclk->entries[count].clk) { - stable_pstate_sclk = - table_info->vdd_dep_on_sclk->entries[count].clk; - break; - } - } - - if (count < 0) - stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; - - stable_pstate_mclk = max_limits->mclk; - - minimum_clocks.engineClock = stable_pstate_sclk; - minimum_clocks.memoryClock = stable_pstate_mclk; - } - - if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk) - minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk; - - if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk) - minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk; - - ellesmere_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold; - - if (0 != hwmgr->gfx_arbiter.sclk_over_drive) { - PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= - hwmgr->platform_descriptor.overdriveLimit.engineClock), - "Overdrive sclk exceeds limit", - hwmgr->gfx_arbiter.sclk_over_drive = - hwmgr->platform_descriptor.overdriveLimit.engineClock); - - if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk) - ellesmere_ps->performance_levels[1].engine_clock = - hwmgr->gfx_arbiter.sclk_over_drive; - } - - if (0 != hwmgr->gfx_arbiter.mclk_over_drive) { - PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= - hwmgr->platform_descriptor.overdriveLimit.memoryClock), - "Overdrive mclk exceeds limit", - hwmgr->gfx_arbiter.mclk_over_drive = - hwmgr->platform_descriptor.overdriveLimit.memoryClock); - - if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk) - ellesmere_ps->performance_levels[1].memory_clock = - hwmgr->gfx_arbiter.mclk_over_drive; - } - - disable_mclk_switching_for_frame_lock = phm_cap_enabled( - hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); - - disable_mclk_switching = (1 < info.display_count) || - disable_mclk_switching_for_frame_lock; - - sclk = ellesmere_ps->performance_levels[0].engine_clock; - mclk = ellesmere_ps->performance_levels[0].memory_clock; - - if (disable_mclk_switching) - mclk = ellesmere_ps->performance_levels - [ellesmere_ps->performance_level_count - 1].memory_clock; - - if (sclk < minimum_clocks.engineClock) - sclk = (minimum_clocks.engineClock > max_limits->sclk) ? - max_limits->sclk : minimum_clocks.engineClock; - - if (mclk < minimum_clocks.memoryClock) - mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? - max_limits->mclk : minimum_clocks.memoryClock; - - ellesmere_ps->performance_levels[0].engine_clock = sclk; - ellesmere_ps->performance_levels[0].memory_clock = mclk; - - ellesmere_ps->performance_levels[1].engine_clock = - (ellesmere_ps->performance_levels[1].engine_clock >= - ellesmere_ps->performance_levels[0].engine_clock) ? - ellesmere_ps->performance_levels[1].engine_clock : - ellesmere_ps->performance_levels[0].engine_clock; - - if (disable_mclk_switching) { - if (mclk < ellesmere_ps->performance_levels[1].memory_clock) - mclk = ellesmere_ps->performance_levels[1].memory_clock; - - ellesmere_ps->performance_levels[0].memory_clock = mclk; - ellesmere_ps->performance_levels[1].memory_clock = mclk; - } else { - if (ellesmere_ps->performance_levels[1].memory_clock < - ellesmere_ps->performance_levels[0].memory_clock) - ellesmere_ps->performance_levels[1].memory_clock = - ellesmere_ps->performance_levels[0].memory_clock; - } - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StablePState)) { - for (i = 0; i < ellesmere_ps->performance_level_count; i++) { - ellesmere_ps->performance_levels[i].engine_clock = stable_pstate_sclk; - ellesmere_ps->performance_levels[i].memory_clock = stable_pstate_mclk; - ellesmere_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; - ellesmere_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; - } - } - return 0; -} - - -static int ellesmere_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) -{ - struct pp_power_state *ps; - struct ellesmere_power_state *ellesmere_ps; - - if (hwmgr == NULL) - return -EINVAL; - - ps = hwmgr->request_ps; - - if (ps == NULL) - return -EINVAL; - - ellesmere_ps = cast_phw_ellesmere_power_state(&ps->hardware); - - if (low) - return ellesmere_ps->performance_levels[0].memory_clock; - else - return ellesmere_ps->performance_levels - [ellesmere_ps->performance_level_count-1].memory_clock; -} - -static int ellesmere_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) -{ - struct pp_power_state *ps; - struct ellesmere_power_state *ellesmere_ps; - - if (hwmgr == NULL) - return -EINVAL; - - ps = hwmgr->request_ps; - - if (ps == NULL) - return -EINVAL; - - ellesmere_ps = cast_phw_ellesmere_power_state(&ps->hardware); - - if (low) - return ellesmere_ps->performance_levels[0].engine_clock; - else - return ellesmere_ps->performance_levels - [ellesmere_ps->performance_level_count-1].engine_clock; -} - -static int ellesmere_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, - struct pp_hw_power_state *hw_ps) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_power_state *ps = (struct ellesmere_power_state *)hw_ps; - ATOM_FIRMWARE_INFO_V2_2 *fw_info; - uint16_t size; - uint8_t frev, crev; - int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); - - /* First retrieve the Boot clocks and VDDC from the firmware info table. - * We assume here that fw_info is unchanged if this call fails. - */ - fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table( - hwmgr->device, index, - &size, &frev, &crev); - if (!fw_info) - /* During a test, there is no firmware info table. */ - return 0; - - /* Patch the state. */ - data->vbios_boot_state.sclk_bootup_value = - le32_to_cpu(fw_info->ulDefaultEngineClock); - data->vbios_boot_state.mclk_bootup_value = - le32_to_cpu(fw_info->ulDefaultMemoryClock); - data->vbios_boot_state.mvdd_bootup_value = - le16_to_cpu(fw_info->usBootUpMVDDCVoltage); - data->vbios_boot_state.vddc_bootup_value = - le16_to_cpu(fw_info->usBootUpVDDCVoltage); - data->vbios_boot_state.vddci_bootup_value = - le16_to_cpu(fw_info->usBootUpVDDCIVoltage); - data->vbios_boot_state.pcie_gen_bootup_value = - phm_get_current_pcie_speed(hwmgr); - - data->vbios_boot_state.pcie_lane_bootup_value = - (uint16_t)phm_get_current_pcie_lane_number(hwmgr); - - /* set boot power state */ - ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value; - ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value; - ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value; - ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value; - - return 0; -} - -static int ellesmere_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, - void *state, struct pp_power_state *power_state, - void *pp_table, uint32_t classification_flag) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_power_state *ellesmere_power_state = - (struct ellesmere_power_state *)(&(power_state->hardware)); - struct ellesmere_performance_level *performance_level; - ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state; - ATOM_Tonga_POWERPLAYTABLE *powerplay_table = - (ATOM_Tonga_POWERPLAYTABLE *)pp_table; - ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table = - (ATOM_Tonga_SCLK_Dependency_Table *) - (((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); - ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = - (ATOM_Tonga_MCLK_Dependency_Table *) - (((unsigned long)powerplay_table) + - le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); - - /* The following fields are not initialized here: id orderedList allStatesList */ - power_state->classification.ui_label = - (le16_to_cpu(state_entry->usClassification) & - ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> - ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; - power_state->classification.flags = classification_flag; - /* NOTE: There is a classification2 flag in BIOS that is not being used right now */ - - power_state->classification.temporary_state = false; - power_state->classification.to_be_deleted = false; - - power_state->validation.disallowOnDC = - (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & - ATOM_Tonga_DISALLOW_ON_DC)); - - power_state->pcie.lanes = 0; - - power_state->display.disableFrameModulation = false; - power_state->display.limitRefreshrate = false; - power_state->display.enableVariBright = - (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & - ATOM_Tonga_ENABLE_VARIBRIGHT)); - - power_state->validation.supportedPowerLevels = 0; - power_state->uvd_clocks.VCLK = 0; - power_state->uvd_clocks.DCLK = 0; - power_state->temperatures.min = 0; - power_state->temperatures.max = 0; - - performance_level = &(ellesmere_power_state->performance_levels - [ellesmere_power_state->performance_level_count++]); - - PP_ASSERT_WITH_CODE( - (ellesmere_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS), - "Performance levels exceeds SMC limit!", - return -1); - - PP_ASSERT_WITH_CODE( - (ellesmere_power_state->performance_level_count <= - hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), - "Performance levels exceeds Driver limit!", - return -1); - - /* Performance levels are arranged from low to high. */ - performance_level->memory_clock = mclk_dep_table->entries - [state_entry->ucMemoryClockIndexLow].ulMclk; - performance_level->engine_clock = sclk_dep_table->entries - [state_entry->ucEngineClockIndexLow].ulSclk; - performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, - state_entry->ucPCIEGenLow); - performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, - state_entry->ucPCIELaneHigh); - - performance_level = &(ellesmere_power_state->performance_levels - [ellesmere_power_state->performance_level_count++]); - performance_level->memory_clock = mclk_dep_table->entries - [state_entry->ucMemoryClockIndexHigh].ulMclk; - performance_level->engine_clock = sclk_dep_table->entries - [state_entry->ucEngineClockIndexHigh].ulSclk; - performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, - state_entry->ucPCIEGenHigh); - performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, - state_entry->ucPCIELaneHigh); - - return 0; -} - -static int ellesmere_get_pp_table_entry(struct pp_hwmgr *hwmgr, - unsigned long entry_index, struct pp_power_state *state) -{ - int result; - struct ellesmere_power_state *ps; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = - table_info->vdd_dep_on_mclk; - - state->hardware.magic = PHM_VIslands_Magic; - - ps = (struct ellesmere_power_state *)(&state->hardware); - - result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state, - ellesmere_get_pp_table_entry_callback_func); - - /* This is the earliest time we have all the dependency table and the VBIOS boot state - * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state - * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state - */ - if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { - if (dep_mclk_table->entries[0].clk != - data->vbios_boot_state.mclk_bootup_value) - printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table " - "does not match VBIOS boot MCLK level"); - if (dep_mclk_table->entries[0].vddci != - data->vbios_boot_state.vddci_bootup_value) - printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table " - "does not match VBIOS boot VDDCI level"); - } - - /* set DC compatible flag if this state supports DC */ - if (!state->validation.disallowOnDC) - ps->dc_compatible = true; - - if (state->classification.flags & PP_StateClassificationFlag_ACPI) - data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; - - ps->uvd_clks.vclk = state->uvd_clocks.VCLK; - ps->uvd_clks.dclk = state->uvd_clocks.DCLK; - - if (!result) { - uint32_t i; - - switch (state->classification.ui_label) { - case PP_StateUILabel_Performance: - data->use_pcie_performance_levels = true; - - for (i = 0; i < ps->performance_level_count; i++) { - if (data->pcie_gen_performance.max < - ps->performance_levels[i].pcie_gen) - data->pcie_gen_performance.max = - ps->performance_levels[i].pcie_gen; - - if (data->pcie_gen_performance.min > - ps->performance_levels[i].pcie_gen) - data->pcie_gen_performance.min = - ps->performance_levels[i].pcie_gen; - - if (data->pcie_lane_performance.max < - ps->performance_levels[i].pcie_lane) - data->pcie_lane_performance.max = - ps->performance_levels[i].pcie_lane; - - if (data->pcie_lane_performance.min > - ps->performance_levels[i].pcie_lane) - data->pcie_lane_performance.min = - ps->performance_levels[i].pcie_lane; - } - break; - case PP_StateUILabel_Battery: - data->use_pcie_power_saving_levels = true; - - for (i = 0; i < ps->performance_level_count; i++) { - if (data->pcie_gen_power_saving.max < - ps->performance_levels[i].pcie_gen) - data->pcie_gen_power_saving.max = - ps->performance_levels[i].pcie_gen; - - if (data->pcie_gen_power_saving.min > - ps->performance_levels[i].pcie_gen) - data->pcie_gen_power_saving.min = - ps->performance_levels[i].pcie_gen; - - if (data->pcie_lane_power_saving.max < - ps->performance_levels[i].pcie_lane) - data->pcie_lane_power_saving.max = - ps->performance_levels[i].pcie_lane; - - if (data->pcie_lane_power_saving.min > - ps->performance_levels[i].pcie_lane) - data->pcie_lane_power_saving.min = - ps->performance_levels[i].pcie_lane; - } - break; - default: - break; - } - } - return 0; -} - -static void -ellesmere_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m) -{ - uint32_t sclk, mclk; - - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); - - sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); - - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); - - mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); - seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", - mclk / 100, sclk / 100); -} - -static int ellesmere_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) -{ - const struct phm_set_power_state_input *states = - (const struct phm_set_power_state_input *)input; - const struct ellesmere_power_state *ellesmere_ps = - cast_const_phw_ellesmere_power_state(states->pnew_state); - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); - uint32_t sclk = ellesmere_ps->performance_levels - [ellesmere_ps->performance_level_count - 1].engine_clock; - struct ellesmere_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); - uint32_t mclk = ellesmere_ps->performance_levels - [ellesmere_ps->performance_level_count - 1].memory_clock; - struct PP_Clocks min_clocks = {0}; - uint32_t i; - struct cgs_display_info info = {0}; - - data->need_update_smu7_dpm_table = 0; - - for (i = 0; i < sclk_table->count; i++) { - if (sclk == sclk_table->dpm_levels[i].value) - break; - } - - if (i >= sclk_table->count) - data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; - else { - /* TODO: Check SCLK in DAL's minimum clocks - * in case DeepSleep divider update is required. - */ - if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR) - data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; - } - - for (i = 0; i < mclk_table->count; i++) { - if (mclk == mclk_table->dpm_levels[i].value) - break; - } - - if (i >= mclk_table->count) - data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; - - cgs_get_active_displays_info(hwmgr->device, &info); - - if (data->display_timing.num_existing_displays != info.display_count) - data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; - - return 0; -} - -static uint16_t ellesmere_get_maximum_link_speed(struct pp_hwmgr *hwmgr, - const struct ellesmere_power_state *ellesmere_ps) -{ - uint32_t i; - uint32_t sclk, max_sclk = 0; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_dpm_table *dpm_table = &data->dpm_table; - - for (i = 0; i < ellesmere_ps->performance_level_count; i++) { - sclk = ellesmere_ps->performance_levels[i].engine_clock; - if (max_sclk < sclk) - max_sclk = sclk; - } - - for (i = 0; i < dpm_table->sclk_table.count; i++) { - if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk) - return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ? - dpm_table->pcie_speed_table.dpm_levels - [dpm_table->pcie_speed_table.count - 1].value : - dpm_table->pcie_speed_table.dpm_levels[i].value); - } - - return 0; -} - -static int ellesmere_request_link_speed_change_before_state_change( - struct pp_hwmgr *hwmgr, const void *input) -{ - const struct phm_set_power_state_input *states = - (const struct phm_set_power_state_input *)input; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - const struct ellesmere_power_state *ellesmere_nps = - cast_const_phw_ellesmere_power_state(states->pnew_state); - const struct ellesmere_power_state *ellesmere_cps = - cast_const_phw_ellesmere_power_state(states->pcurrent_state); - - uint16_t target_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_nps); - uint16_t current_link_speed; - - if (data->force_pcie_gen == PP_PCIEGenInvalid) - current_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_cps); - else - current_link_speed = data->force_pcie_gen; - - data->force_pcie_gen = PP_PCIEGenInvalid; - data->pspp_notify_required = false; - - if (target_link_speed > current_link_speed) { - switch (target_link_speed) { - case PP_PCIEGen3: - if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false)) - break; - data->force_pcie_gen = PP_PCIEGen2; - if (current_link_speed == PP_PCIEGen2) - break; - case PP_PCIEGen2: - if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false)) - break; - default: - data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr); - break; - } - } else { - if (target_link_speed < current_link_speed) - data->pspp_notify_required = true; - } - - return 0; -} - -static int ellesmere_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - if (0 == data->need_update_smu7_dpm_table) - return 0; - - if ((0 == data->sclk_dpm_key_disabled) && - (data->need_update_smu7_dpm_table & - (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { - PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr), - "Trying to freeze SCLK DPM when DPM is disabled", - ); - PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_SCLKDPM_FreezeLevel), - "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", - return -1); - } - - if ((0 == data->mclk_dpm_key_disabled) && - (data->need_update_smu7_dpm_table & - DPMTABLE_OD_UPDATE_MCLK)) { - PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr), - "Trying to freeze MCLK DPM when DPM is disabled", - ); - PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_MCLKDPM_FreezeLevel), - "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", - return -1); - } - - return 0; -} - -static int ellesmere_populate_and_upload_sclk_mclk_dpm_levels( - struct pp_hwmgr *hwmgr, const void *input) -{ - int result = 0; - const struct phm_set_power_state_input *states = - (const struct phm_set_power_state_input *)input; - const struct ellesmere_power_state *ellesmere_ps = - cast_const_phw_ellesmere_power_state(states->pnew_state); - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - uint32_t sclk = ellesmere_ps->performance_levels - [ellesmere_ps->performance_level_count - 1].engine_clock; - uint32_t mclk = ellesmere_ps->performance_levels - [ellesmere_ps->performance_level_count - 1].memory_clock; - struct ellesmere_dpm_table *dpm_table = &data->dpm_table; - - struct ellesmere_dpm_table *golden_dpm_table = &data->golden_dpm_table; - uint32_t dpm_count, clock_percent; - uint32_t i; - - if (0 == data->need_update_smu7_dpm_table) - return 0; - - if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { - dpm_table->sclk_table.dpm_levels - [dpm_table->sclk_table.count - 1].value = sclk; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { - /* Need to do calculation based on the golden DPM table - * as the Heatmap GPU Clock axis is also based on the default values - */ - PP_ASSERT_WITH_CODE( - (golden_dpm_table->sclk_table.dpm_levels - [golden_dpm_table->sclk_table.count - 1].value != 0), - "Divide by 0!", - return -1); - dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2; - - for (i = dpm_count; i > 1; i--) { - if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) { - clock_percent = - ((sclk - - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value - ) * 100) - / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value; - - dpm_table->sclk_table.dpm_levels[i].value = - golden_dpm_table->sclk_table.dpm_levels[i].value + - (golden_dpm_table->sclk_table.dpm_levels[i].value * - clock_percent)/100; - - } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) { - clock_percent = - ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value - - sclk) * 100) - / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value; - - dpm_table->sclk_table.dpm_levels[i].value = - golden_dpm_table->sclk_table.dpm_levels[i].value - - (golden_dpm_table->sclk_table.dpm_levels[i].value * - clock_percent) / 100; - } else - dpm_table->sclk_table.dpm_levels[i].value = - golden_dpm_table->sclk_table.dpm_levels[i].value; - } - } - } - - if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { - dpm_table->mclk_table.dpm_levels - [dpm_table->mclk_table.count - 1].value = mclk; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { - - PP_ASSERT_WITH_CODE( - (golden_dpm_table->mclk_table.dpm_levels - [golden_dpm_table->mclk_table.count-1].value != 0), - "Divide by 0!", - return -1); - dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2; - for (i = dpm_count; i > 1; i--) { - if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) { - clock_percent = ((mclk - - golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100) - / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value; - - dpm_table->mclk_table.dpm_levels[i].value = - golden_dpm_table->mclk_table.dpm_levels[i].value + - (golden_dpm_table->mclk_table.dpm_levels[i].value * - clock_percent) / 100; - - } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) { - clock_percent = ( - (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk) - * 100) - / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value; - - dpm_table->mclk_table.dpm_levels[i].value = - golden_dpm_table->mclk_table.dpm_levels[i].value - - (golden_dpm_table->mclk_table.dpm_levels[i].value * - clock_percent) / 100; - } else - dpm_table->mclk_table.dpm_levels[i].value = - golden_dpm_table->mclk_table.dpm_levels[i].value; - } - } - } - - if (data->need_update_smu7_dpm_table & - (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) { - result = ellesmere_populate_all_graphic_levels(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", - return result); - } - - if (data->need_update_smu7_dpm_table & - (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { - /*populate MCLK dpm table to SMU7 */ - result = ellesmere_populate_all_memory_levels(hwmgr); - PP_ASSERT_WITH_CODE((0 == result), - "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", - return result); - } - - return result; -} - -static int ellesmere_trim_single_dpm_states(struct pp_hwmgr *hwmgr, - struct ellesmere_single_dpm_table *dpm_table, - uint32_t low_limit, uint32_t high_limit) -{ - uint32_t i; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - for (i = 0; i < dpm_table->count; i++) { - if ((dpm_table->dpm_levels[i].value < low_limit) - || (dpm_table->dpm_levels[i].value > high_limit)) - dpm_table->dpm_levels[i].enabled = false; - else if (((1 << i) & data->disable_dpm_mask) == 0) - dpm_table->dpm_levels[i].enabled = false; - else - dpm_table->dpm_levels[i].enabled = true; - } - - return 0; -} - -static int ellesmere_trim_dpm_states(struct pp_hwmgr *hwmgr, - const struct ellesmere_power_state *ellesmere_ps) -{ - int result = 0; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - uint32_t high_limit_count; - - PP_ASSERT_WITH_CODE((ellesmere_ps->performance_level_count >= 1), - "power state did not have any performance level", - return -1); - - high_limit_count = (1 == ellesmere_ps->performance_level_count) ? 0 : 1; - - ellesmere_trim_single_dpm_states(hwmgr, - &(data->dpm_table.sclk_table), - ellesmere_ps->performance_levels[0].engine_clock, - ellesmere_ps->performance_levels[high_limit_count].engine_clock); - - ellesmere_trim_single_dpm_states(hwmgr, - &(data->dpm_table.mclk_table), - ellesmere_ps->performance_levels[0].memory_clock, - ellesmere_ps->performance_levels[high_limit_count].memory_clock); - - return result; -} - -static int ellesmere_generate_dpm_level_enable_mask( - struct pp_hwmgr *hwmgr, const void *input) -{ - int result; - const struct phm_set_power_state_input *states = - (const struct phm_set_power_state_input *)input; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - const struct ellesmere_power_state *ellesmere_ps = - cast_const_phw_ellesmere_power_state(states->pnew_state); - - result = ellesmere_trim_dpm_states(hwmgr, ellesmere_ps); - if (result) - return result; - - data->dpm_level_enable_mask.sclk_dpm_enable_mask = - phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table); - data->dpm_level_enable_mask.mclk_dpm_enable_mask = - phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table); - data->dpm_level_enable_mask.pcie_dpm_enable_mask = - phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table); - - return 0; -} - -int ellesmere_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) -{ - return smum_send_msg_to_smc(hwmgr->smumgr, enable ? - PPSMC_MSG_UVDDPM_Enable : - PPSMC_MSG_UVDDPM_Disable); -} - -int ellesmere_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) -{ - return smum_send_msg_to_smc(hwmgr->smumgr, enable? - PPSMC_MSG_VCEDPM_Enable : - PPSMC_MSG_VCEDPM_Disable); -} - -int ellesmere_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable) -{ - return smum_send_msg_to_smc(hwmgr->smumgr, enable? - PPSMC_MSG_SAMUDPM_Enable : - PPSMC_MSG_SAMUDPM_Disable); -} - -int ellesmere_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - uint32_t mm_boot_level_offset, mm_boot_level_value; - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - if (!bgate) { - data->smc_state_table.UvdBootLevel = 0; - if (table_info->mm_dep_table->count > 0) - data->smc_state_table.UvdBootLevel = - (uint8_t) (table_info->mm_dep_table->count - 1); - mm_boot_level_offset = data->dpm_table_start + - offsetof(SMU74_Discrete_DpmTable, UvdBootLevel); - mm_boot_level_offset /= 4; - mm_boot_level_offset *= 4; - mm_boot_level_value = cgs_read_ind_register(hwmgr->device, - CGS_IND_REG__SMC, mm_boot_level_offset); - mm_boot_level_value &= 0x00FFFFFF; - mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24; - cgs_write_ind_register(hwmgr->device, - CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); - - if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDDPM) || - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StablePState)) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_UVDDPM_SetEnabledMask, - (uint32_t)(1 << data->smc_state_table.UvdBootLevel)); - } - - return ellesmere_enable_disable_uvd_dpm(hwmgr, !bgate); -} - -static int ellesmere_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) -{ - const struct phm_set_power_state_input *states = - (const struct phm_set_power_state_input *)input; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - const struct ellesmere_power_state *ellesmere_nps = - cast_const_phw_ellesmere_power_state(states->pnew_state); - const struct ellesmere_power_state *ellesmere_cps = - cast_const_phw_ellesmere_power_state(states->pcurrent_state); - - uint32_t mm_boot_level_offset, mm_boot_level_value; - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - if (ellesmere_nps->vce_clks.evclk > 0 && - (ellesmere_cps == NULL || ellesmere_cps->vce_clks.evclk == 0)) { - - data->smc_state_table.VceBootLevel = - (uint8_t) (table_info->mm_dep_table->count - 1); - - mm_boot_level_offset = data->dpm_table_start + - offsetof(SMU74_Discrete_DpmTable, VceBootLevel); - mm_boot_level_offset /= 4; - mm_boot_level_offset *= 4; - mm_boot_level_value = cgs_read_ind_register(hwmgr->device, - CGS_IND_REG__SMC, mm_boot_level_offset); - mm_boot_level_value &= 0xFF00FFFF; - mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16; - cgs_write_ind_register(hwmgr->device, - CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_VCEDPM_SetEnabledMask, - (uint32_t)1 << data->smc_state_table.VceBootLevel); - - ellesmere_enable_disable_vce_dpm(hwmgr, true); - } else if (ellesmere_nps->vce_clks.evclk == 0 && - ellesmere_cps != NULL && - ellesmere_cps->vce_clks.evclk > 0) - ellesmere_enable_disable_vce_dpm(hwmgr, false); - } - - return 0; -} - -int ellesmere_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - uint32_t mm_boot_level_offset, mm_boot_level_value; - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - if (!bgate) { - data->smc_state_table.SamuBootLevel = - (uint8_t) (table_info->mm_dep_table->count - 1); - mm_boot_level_offset = data->dpm_table_start + - offsetof(SMU74_Discrete_DpmTable, SamuBootLevel); - mm_boot_level_offset /= 4; - mm_boot_level_offset *= 4; - mm_boot_level_value = cgs_read_ind_register(hwmgr->device, - CGS_IND_REG__SMC, mm_boot_level_offset); - mm_boot_level_value &= 0xFFFFFF00; - mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0; - cgs_write_ind_register(hwmgr->device, - CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StablePState)) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SAMUDPM_SetEnabledMask, - (uint32_t)(1 << data->smc_state_table.SamuBootLevel)); - } - - return ellesmere_enable_disable_samu_dpm(hwmgr, !bgate); -} - -static int ellesmere_update_sclk_threshold(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - int result = 0; - uint32_t low_sclk_interrupt_threshold = 0; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkThrottleLowNotification) - && (hwmgr->gfx_arbiter.sclk_threshold != - data->low_sclk_interrupt_threshold)) { - data->low_sclk_interrupt_threshold = - hwmgr->gfx_arbiter.sclk_threshold; - low_sclk_interrupt_threshold = - data->low_sclk_interrupt_threshold; - - CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); - - result = ellesmere_copy_bytes_to_smc( - hwmgr->smumgr, - data->dpm_table_start + - offsetof(SMU74_Discrete_DpmTable, - LowSclkInterruptThreshold), - (uint8_t *)&low_sclk_interrupt_threshold, - sizeof(uint32_t), - data->sram_end); - } - - return result; -} - -static int ellesmere_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - if (data->need_update_smu7_dpm_table & - (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) - return ellesmere_program_memory_timing_parameters(hwmgr); - - return 0; -} - -static int ellesmere_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - if (0 == data->need_update_smu7_dpm_table) - return 0; - - if ((0 == data->sclk_dpm_key_disabled) && - (data->need_update_smu7_dpm_table & - (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { - - PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr), - "Trying to Unfreeze SCLK DPM when DPM is disabled", - ); - PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_SCLKDPM_UnfreezeLevel), - "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", - return -1); - } - - if ((0 == data->mclk_dpm_key_disabled) && - (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { - - PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr), - "Trying to Unfreeze MCLK DPM when DPM is disabled", - ); - PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_SCLKDPM_UnfreezeLevel), - "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", - return -1); - } - - data->need_update_smu7_dpm_table = 0; - - return 0; -} - -static int ellesmere_notify_link_speed_change_after_state_change( - struct pp_hwmgr *hwmgr, const void *input) -{ - const struct phm_set_power_state_input *states = - (const struct phm_set_power_state_input *)input; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - const struct ellesmere_power_state *ellesmere_ps = - cast_const_phw_ellesmere_power_state(states->pnew_state); - uint16_t target_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_ps); - uint8_t request; - - if (data->pspp_notify_required) { - if (target_link_speed == PP_PCIEGen3) - request = PCIE_PERF_REQ_GEN3; - else if (target_link_speed == PP_PCIEGen2) - request = PCIE_PERF_REQ_GEN2; - else - request = PCIE_PERF_REQ_GEN1; - - if (request == PCIE_PERF_REQ_GEN1 && - phm_get_current_pcie_speed(hwmgr) > 0) - return 0; - - if (acpi_pcie_perf_request(hwmgr->device, request, false)) { - if (PP_PCIEGen2 == target_link_speed) - printk("PSPP request to switch to Gen2 from Gen3 Failed!"); - else - printk("PSPP request to switch to Gen1 from Gen2 Failed!"); - } - } - - return 0; -} - -static int ellesmere_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) -{ - int tmp_result, result = 0; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - tmp_result = ellesmere_find_dpm_states_clocks_in_dpm_table(hwmgr, input); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to find DPM states clocks in DPM table!", - result = tmp_result); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PCIEPerformanceRequest)) { - tmp_result = - ellesmere_request_link_speed_change_before_state_change(hwmgr, input); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to request link speed change before state change!", - result = tmp_result); - } - - tmp_result = ellesmere_freeze_sclk_mclk_dpm(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to freeze SCLK MCLK DPM!", result = tmp_result); - - tmp_result = ellesmere_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to populate and upload SCLK MCLK DPM levels!", - result = tmp_result); - - tmp_result = ellesmere_generate_dpm_level_enable_mask(hwmgr, input); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to generate DPM level enabled mask!", - result = tmp_result); - - tmp_result = ellesmere_update_vce_dpm(hwmgr, input); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to update VCE DPM!", - result = tmp_result); - - tmp_result = ellesmere_update_sclk_threshold(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to update SCLK threshold!", - result = tmp_result); - - tmp_result = ellesmere_program_mem_timing_parameters(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to program memory timing parameters!", - result = tmp_result); - - tmp_result = ellesmere_unfreeze_sclk_mclk_dpm(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to unfreeze SCLK MCLK DPM!", - result = tmp_result); - - tmp_result = ellesmere_upload_dpm_level_enable_mask(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to upload DPM level enabled mask!", - result = tmp_result); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PCIEPerformanceRequest)) { - tmp_result = - ellesmere_notify_link_speed_change_after_state_change(hwmgr, input); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to notify link speed change after state change!", - result = tmp_result); - } - data->apply_optimized_settings = false; - return result; -} - -static int ellesmere_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) -{ - hwmgr->thermal_controller. - advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; - - if (phm_is_hw_access_blocked(hwmgr)) - return 0; - - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm); -} - -int ellesmere_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) -{ - PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; - - return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; -} - -int ellesmere_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) -{ - uint32_t num_active_displays = 0; - struct cgs_display_info info = {0}; - info.mode_info = NULL; - - cgs_get_active_displays_info(hwmgr->device, &info); - - num_active_displays = info.display_count; - - if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */ - ellesmere_notify_smc_display_change(hwmgr, false); - else - ellesmere_notify_smc_display_change(hwmgr, true); - - return 0; -} - -/** -* Programs the display gap -* -* @param hwmgr the address of the powerplay hardware manager. -* @return always OK -*/ -int ellesmere_program_display_gap(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - uint32_t num_active_displays = 0; - uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); - uint32_t display_gap2; - uint32_t pre_vbi_time_in_us; - uint32_t frame_time_in_us; - uint32_t ref_clock; - uint32_t refresh_rate = 0; - struct cgs_display_info info = {0}; - struct cgs_mode_info mode_info; - - info.mode_info = &mode_info; - - cgs_get_active_displays_info(hwmgr->device, &info); - num_active_displays = info.display_count; - - display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); - - ref_clock = mode_info.ref_clock; - refresh_rate = mode_info.refresh_rate; - - if (0 == refresh_rate) - refresh_rate = 60; - - frame_time_in_us = 1000000 / refresh_rate; - - pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us; - display_gap2 = pre_vbi_time_in_us * (ref_clock / 100); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); - - if (num_active_displays == 1) - ellesmere_notify_smc_display_change(hwmgr, true); - - return 0; -} - - -int ellesmere_display_configuration_changed_task(struct pp_hwmgr *hwmgr) -{ - return ellesmere_program_display_gap(hwmgr); -} - -/** -* Set maximum target operating fan output RPM -* -* @param hwmgr: the address of the powerplay hardware manager. -* @param usMaxFanRpm: max operating fan RPM value. -* @return The response that came from the SMC. -*/ -static int ellesmere_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm) -{ - hwmgr->thermal_controller. - advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; - - if (phm_is_hw_access_blocked(hwmgr)) - return 0; - - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm); -} - -int ellesmere_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, - const void *thermal_interrupt_info) -{ - return 0; -} - -bool ellesmere_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - bool is_update_required = false; - struct cgs_display_info info = {0, 0, NULL}; - - cgs_get_active_displays_info(hwmgr->device, &info); - - if (data->display_timing.num_existing_displays != info.display_count) - is_update_required = true; -/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL - if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { - cgs_get_min_clock_settings(hwmgr->device, &min_clocks); - if (min_clocks.engineClockInSR != data->display_timing.minClockInSR) - is_update_required = true; -*/ - return is_update_required; -} - -static inline bool ellesmere_are_power_levels_equal(const struct ellesmere_performance_level *pl1, - const struct ellesmere_performance_level *pl2) -{ - return ((pl1->memory_clock == pl2->memory_clock) && - (pl1->engine_clock == pl2->engine_clock) && - (pl1->pcie_gen == pl2->pcie_gen) && - (pl1->pcie_lane == pl2->pcie_lane)); -} - -int ellesmere_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) -{ - const struct ellesmere_power_state *psa = cast_const_phw_ellesmere_power_state(pstate1); - const struct ellesmere_power_state *psb = cast_const_phw_ellesmere_power_state(pstate2); - int i; - - if (pstate1 == NULL || pstate2 == NULL || equal == NULL) - return -EINVAL; - - /* If the two states don't even have the same number of performance levels they cannot be the same state. */ - if (psa->performance_level_count != psb->performance_level_count) { - *equal = false; - return 0; - } - - for (i = 0; i < psa->performance_level_count; i++) { - if (!ellesmere_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { - /* If we have found even one performance level pair that is different the states are different. */ - *equal = false; - return 0; - } - } - - /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ - *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk)); - *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk)); - *equal &= (psa->sclk_threshold == psb->sclk_threshold); - - return 0; -} - -int ellesmere_upload_mc_firmware(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - uint32_t vbios_version; - - /* Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/ - - phm_get_mc_microcode_version(hwmgr); - vbios_version = hwmgr->microcode_version_info.MC & 0xf; - /* Full version of MC ucode has already been loaded. */ - if (vbios_version == 0) { - data->need_long_memory_training = false; - return 0; - } - - data->need_long_memory_training = true; - -/* - * PPMCME_FirmwareDescriptorEntry *pfd = NULL; - pfd = &tonga_mcmeFirmware; - if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN)) - ellesmere_load_mc_microcode(hwmgr, pfd->dpmThreshold, - pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray, - pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize); -*/ - return 0; -} - -/** - * Read clock related registers. - * - * @param hwmgr the address of the powerplay hardware manager. - * @return always 0 - */ -static int ellesmere_read_clock_registers(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device, - CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL) - & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK; - - data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device, - CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2) - & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK; - - data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device, - CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4) - & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK; - - return 0; -} - -/** - * Find out if memory is GDDR5. - * - * @param hwmgr the address of the powerplay hardware manager. - * @return always 0 - */ -static int ellesmere_get_memory_type(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - uint32_t temp; - - temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0); - - data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == - ((temp & MC_SEQ_MISC0_GDDR5_MASK) >> - MC_SEQ_MISC0_GDDR5_SHIFT)); - - return 0; -} - -/** - * Enables Dynamic Power Management by SMC - * - * @param hwmgr the address of the powerplay hardware manager. - * @return always 0 - */ -static int ellesmere_enable_acpi_power_management(struct pp_hwmgr *hwmgr) -{ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - GENERAL_PWRMGT, STATIC_PM_EN, 1); - - return 0; -} - -/** - * Initialize PowerGating States for different engines - * - * @param hwmgr the address of the powerplay hardware manager. - * @return always 0 - */ -static int ellesmere_init_power_gate_state(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - data->uvd_power_gated = false; - data->vce_power_gated = false; - data->samu_power_gated = false; - - return 0; -} - -static int ellesmere_init_sclk_threshold(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - data->low_sclk_interrupt_threshold = 0; - - return 0; -} - -int ellesmere_setup_asic_task(struct pp_hwmgr *hwmgr) -{ - int tmp_result, result = 0; - - ellesmere_upload_mc_firmware(hwmgr); - - tmp_result = ellesmere_read_clock_registers(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to read clock registers!", result = tmp_result); - - tmp_result = ellesmere_get_memory_type(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to get memory type!", result = tmp_result); - - tmp_result = ellesmere_enable_acpi_power_management(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to enable ACPI power management!", result = tmp_result); - - tmp_result = ellesmere_init_power_gate_state(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to init power gate state!", result = tmp_result); - - tmp_result = phm_get_mc_microcode_version(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to get MC microcode version!", result = tmp_result); - - tmp_result = ellesmere_init_sclk_threshold(hwmgr); - PP_ASSERT_WITH_CODE((0 == tmp_result), - "Failed to init sclk threshold!", result = tmp_result); - - return result; -} - -static const struct pp_hwmgr_func ellesmere_hwmgr_funcs = { - .backend_init = &ellesmere_hwmgr_backend_init, - .backend_fini = &ellesmere_hwmgr_backend_fini, - .asic_setup = &ellesmere_setup_asic_task, - .dynamic_state_management_enable = &ellesmere_enable_dpm_tasks, - .apply_state_adjust_rules = ellesmere_apply_state_adjust_rules, - .force_dpm_level = &ellesmere_force_dpm_level, - .power_state_set = ellesmere_set_power_state_tasks, - .get_power_state_size = ellesmere_get_power_state_size, - .get_mclk = ellesmere_dpm_get_mclk, - .get_sclk = ellesmere_dpm_get_sclk, - .patch_boot_state = ellesmere_dpm_patch_boot_state, - .get_pp_table_entry = ellesmere_get_pp_table_entry, - .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries, - .print_current_perforce_level = ellesmere_print_current_perforce_level, - .powerdown_uvd = ellesmere_phm_powerdown_uvd, - .powergate_uvd = ellesmere_phm_powergate_uvd, - .powergate_vce = ellesmere_phm_powergate_vce, - .disable_clock_power_gating = ellesmere_phm_disable_clock_power_gating, - .update_clock_gatings = ellesmere_phm_update_clock_gatings, - .notify_smc_display_config_after_ps_adjustment = ellesmere_notify_smc_display_config_after_ps_adjustment, - .display_config_changed = ellesmere_display_configuration_changed_task, - .set_max_fan_pwm_output = ellesmere_set_max_fan_pwm_output, - .set_max_fan_rpm_output = ellesmere_set_max_fan_rpm_output, - .get_temperature = ellesmere_thermal_get_temperature, - .stop_thermal_controller = ellesmere_thermal_stop_thermal_controller, - .get_fan_speed_info = ellesmere_fan_ctrl_get_fan_speed_info, - .get_fan_speed_percent = ellesmere_fan_ctrl_get_fan_speed_percent, - .set_fan_speed_percent = ellesmere_fan_ctrl_set_fan_speed_percent, - .reset_fan_speed_to_default = ellesmere_fan_ctrl_reset_fan_speed_to_default, - .get_fan_speed_rpm = ellesmere_fan_ctrl_get_fan_speed_rpm, - .set_fan_speed_rpm = ellesmere_fan_ctrl_set_fan_speed_rpm, - .uninitialize_thermal_controller = ellesmere_thermal_ctrl_uninitialize_thermal_controller, - .register_internal_thermal_interrupt = ellesmere_register_internal_thermal_interrupt, - .check_smc_update_required_for_display_configuration = ellesmere_check_smc_update_required_for_display_configuration, - .check_states_equal = ellesmere_check_states_equal, - .get_pp_table = ellesmere_get_pp_table, - .set_pp_table = ellesmere_set_pp_table, - .force_clock_level = ellesmere_force_clock_level, - .print_clock_levels = ellesmere_print_clock_levels, - .enable_per_cu_power_gating = ellesmere_phm_enable_per_cu_power_gating, -}; - -int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data; - - data = kzalloc (sizeof(struct ellesmere_hwmgr), GFP_KERNEL); - if (data == NULL) - return -ENOMEM; - - hwmgr->backend = data; - hwmgr->hwmgr_func = &ellesmere_hwmgr_funcs; - hwmgr->pptable_func = &tonga_pptable_funcs; - pp_ellesmere_thermal_initialize(hwmgr); - - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h deleted file mode 100644 index dd6c60b..0000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef ELLESMERE_HWMGR_H -#define ELLESMERE_HWMGR_H - -#include "hwmgr.h" -#include "smu74.h" -#include "smu74_discrete.h" -#include "ppatomctrl.h" -#include "ellesmere_ppsmc.h" -#include "ellesmere_powertune.h" - -#define ELLESMERE_MAX_HARDWARE_POWERLEVELS 2 - -#define ELLESMERE_VOLTAGE_CONTROL_NONE 0x0 -#define ELLESMERE_VOLTAGE_CONTROL_BY_GPIO 0x1 -#define ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 0x2 -#define ELLESMERE_VOLTAGE_CONTROL_MERGED 0x3 - -#define DPMTABLE_OD_UPDATE_SCLK 0x00000001 -#define DPMTABLE_OD_UPDATE_MCLK 0x00000002 -#define DPMTABLE_UPDATE_SCLK 0x00000004 -#define DPMTABLE_UPDATE_MCLK 0x00000008 - -struct ellesmere_performance_level { - uint32_t memory_clock; - uint32_t engine_clock; - uint16_t pcie_gen; - uint16_t pcie_lane; -}; - -struct ellesmere_uvd_clocks { - uint32_t vclk; - uint32_t dclk; -}; - -struct ellesmere_vce_clocks { - uint32_t evclk; - uint32_t ecclk; -}; - -struct ellesmere_power_state { - uint32_t magic; - struct ellesmere_uvd_clocks uvd_clks; - struct ellesmere_vce_clocks vce_clks; - uint32_t sam_clk; - uint16_t performance_level_count; - bool dc_compatible; - uint32_t sclk_threshold; - struct ellesmere_performance_level performance_levels[ELLESMERE_MAX_HARDWARE_POWERLEVELS]; -}; - -struct ellesmere_dpm_level { - bool enabled; - uint32_t value; - uint32_t param1; -}; - -#define ELLESMERE_MAX_DEEPSLEEP_DIVIDER_ID 5 -#define MAX_REGULAR_DPM_NUMBER 8 -#define ELLESMERE_MINIMUM_ENGINE_CLOCK 2500 - -struct ellesmere_single_dpm_table { - uint32_t count; - struct ellesmere_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; -}; - -struct ellesmere_dpm_table { - struct ellesmere_single_dpm_table sclk_table; - struct ellesmere_single_dpm_table mclk_table; - struct ellesmere_single_dpm_table pcie_speed_table; - struct ellesmere_single_dpm_table vddc_table; - struct ellesmere_single_dpm_table vddci_table; - struct ellesmere_single_dpm_table mvdd_table; -}; - -struct ellesmere_clock_registers { - uint32_t vCG_SPLL_FUNC_CNTL; - uint32_t vCG_SPLL_FUNC_CNTL_2; - uint32_t vCG_SPLL_FUNC_CNTL_3; - uint32_t vCG_SPLL_FUNC_CNTL_4; - uint32_t vCG_SPLL_SPREAD_SPECTRUM; - uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; - uint32_t vDLL_CNTL; - uint32_t vMCLK_PWRMGT_CNTL; - uint32_t vMPLL_AD_FUNC_CNTL; - uint32_t vMPLL_DQ_FUNC_CNTL; - uint32_t vMPLL_FUNC_CNTL; - uint32_t vMPLL_FUNC_CNTL_1; - uint32_t vMPLL_FUNC_CNTL_2; - uint32_t vMPLL_SS1; - uint32_t vMPLL_SS2; -}; - -#define DISABLE_MC_LOADMICROCODE 1 -#define DISABLE_MC_CFGPROGRAMMING 2 - -struct ellesmere_voltage_smio_registers { - uint32_t vS0_VID_LOWER_SMIO_CNTL; -}; - -#define ELLESMERE_MAX_LEAKAGE_COUNT 8 - -struct ellesmere_leakage_voltage { - uint16_t count; - uint16_t leakage_id[ELLESMERE_MAX_LEAKAGE_COUNT]; - uint16_t actual_voltage[ELLESMERE_MAX_LEAKAGE_COUNT]; -}; - -struct ellesmere_vbios_boot_state { - uint16_t mvdd_bootup_value; - uint16_t vddc_bootup_value; - uint16_t vddci_bootup_value; - uint32_t sclk_bootup_value; - uint32_t mclk_bootup_value; - uint16_t pcie_gen_bootup_value; - uint16_t pcie_lane_bootup_value; -}; - -/* Ultra Low Voltage parameter structure */ -struct ellesmere_ulv_parm { - bool ulv_supported; - uint32_t cg_ulv_parameter; - uint32_t ulv_volt_change_delay; - struct ellesmere_performance_level ulv_power_level; -}; - -struct ellesmere_display_timing { - uint32_t min_clock_in_sr; - uint32_t num_existing_displays; -}; - -struct ellesmere_dpmlevel_enable_mask { - uint32_t uvd_dpm_enable_mask; - uint32_t vce_dpm_enable_mask; - uint32_t acp_dpm_enable_mask; - uint32_t samu_dpm_enable_mask; - uint32_t sclk_dpm_enable_mask; - uint32_t mclk_dpm_enable_mask; - uint32_t pcie_dpm_enable_mask; -}; - -struct ellesmere_pcie_perf_range { - uint16_t max; - uint16_t min; -}; -struct ellesmere_range_table { - uint32_t trans_lower_frequency; /* in 10khz */ - uint32_t trans_upper_frequency; -}; - -struct ellesmere_hwmgr { - struct ellesmere_dpm_table dpm_table; - struct ellesmere_dpm_table golden_dpm_table; - SMU74_Discrete_DpmTable smc_state_table; - struct SMU74_Discrete_Ulv ulv_setting; - - struct ellesmere_range_table range_table[NUM_SCLK_RANGE]; - uint32_t voting_rights_clients0; - uint32_t voting_rights_clients1; - uint32_t voting_rights_clients2; - uint32_t voting_rights_clients3; - uint32_t voting_rights_clients4; - uint32_t voting_rights_clients5; - uint32_t voting_rights_clients6; - uint32_t voting_rights_clients7; - uint32_t static_screen_threshold_unit; - uint32_t static_screen_threshold; - uint32_t voltage_control; - uint32_t vddc_vddci_delta; - - uint32_t active_auto_throttle_sources; - - struct ellesmere_clock_registers clock_registers; - struct ellesmere_voltage_smio_registers voltage_smio_registers; - - bool is_memory_gddr5; - uint16_t acpi_vddc; - bool pspp_notify_required; - uint16_t force_pcie_gen; - uint16_t acpi_pcie_gen; - uint32_t pcie_gen_cap; - uint32_t pcie_lane_cap; - uint32_t pcie_spc_cap; - struct ellesmere_leakage_voltage vddc_leakage; - struct ellesmere_leakage_voltage Vddci_leakage; - - uint32_t mvdd_control; - uint32_t vddc_mask_low; - uint32_t mvdd_mask_low; - uint16_t max_vddc_in_pptable; - uint16_t min_vddc_in_pptable; - uint16_t max_vddci_in_pptable; - uint16_t min_vddci_in_pptable; - uint32_t mclk_strobe_mode_threshold; - uint32_t mclk_stutter_mode_threshold; - uint32_t mclk_edc_enable_threshold; - uint32_t mclk_edcwr_enable_threshold; - bool is_uvd_enabled; - struct ellesmere_vbios_boot_state vbios_boot_state; - - bool pcie_performance_request; - bool battery_state; - bool is_tlu_enabled; - - /* ---- SMC SRAM Address of firmware header tables ---- */ - uint32_t sram_end; - uint32_t dpm_table_start; - uint32_t soft_regs_start; - uint32_t mc_reg_table_start; - uint32_t fan_table_start; - uint32_t arb_table_start; - - /* ---- Stuff originally coming from Evergreen ---- */ - uint32_t vddci_control; - struct pp_atomctrl_voltage_table vddc_voltage_table; - struct pp_atomctrl_voltage_table vddci_voltage_table; - struct pp_atomctrl_voltage_table mvdd_voltage_table; - - uint32_t mgcg_cgtt_local2; - uint32_t mgcg_cgtt_local3; - uint32_t gpio_debug; - uint32_t mc_micro_code_feature; - uint32_t highest_mclk; - uint16_t acpi_vddci; - uint8_t mvdd_high_index; - uint8_t mvdd_low_index; - bool dll_default_on; - bool performance_request_registered; - - /* ---- Low Power Features ---- */ - struct ellesmere_ulv_parm ulv; - - /* ---- CAC Stuff ---- */ - uint32_t cac_table_start; - bool cac_configuration_required; - bool driver_calculate_cac_leakage; - bool cac_enabled; - - /* ---- DPM2 Parameters ---- */ - uint32_t power_containment_features; - bool enable_dte_feature; - bool enable_tdc_limit_feature; - bool enable_pkg_pwr_tracking_feature; - bool disable_uvd_power_tune_feature; - struct ellesmere_pt_defaults *power_tune_defaults; - struct SMU74_Discrete_PmFuses power_tune_table; - uint32_t dte_tj_offset; - uint32_t fast_watermark_threshold; - - /* ---- Phase Shedding ---- */ - bool vddc_phase_shed_control; - - /* ---- DI/DT ---- */ - struct ellesmere_display_timing display_timing; - uint32_t bif_sclk_table[SMU74_MAX_LEVELS_LINK]; - - /* ---- Thermal Temperature Setting ---- */ - struct ellesmere_dpmlevel_enable_mask dpm_level_enable_mask; - uint32_t need_update_smu7_dpm_table; - uint32_t sclk_dpm_key_disabled; - uint32_t mclk_dpm_key_disabled; - uint32_t pcie_dpm_key_disabled; - uint32_t min_engine_clocks; - struct ellesmere_pcie_perf_range pcie_gen_performance; - struct ellesmere_pcie_perf_range pcie_lane_performance; - struct ellesmere_pcie_perf_range pcie_gen_power_saving; - struct ellesmere_pcie_perf_range pcie_lane_power_saving; - bool use_pcie_performance_levels; - bool use_pcie_power_saving_levels; - uint32_t activity_target[SMU74_MAX_LEVELS_GRAPHICS]; - uint32_t mclk_activity_target; - uint32_t mclk_dpm0_activity_target; - uint32_t low_sclk_interrupt_threshold; - uint32_t last_mclk_dpm_enable_mask; - bool uvd_enabled; - - /* ---- Power Gating States ---- */ - bool uvd_power_gated; - bool vce_power_gated; - bool samu_power_gated; - bool need_long_memory_training; - - /* Application power optimization parameters */ - bool update_up_hyst; - bool update_down_hyst; - uint32_t down_hyst; - uint32_t up_hyst; - uint32_t disable_dpm_mask; - bool apply_optimized_settings; -}; - -/* To convert to Q8.8 format for firmware */ -#define ELLESMERE_Q88_FORMAT_CONVERSION_UNIT 256 - -enum Ellesmere_I2CLineID { - Ellesmere_I2CLineID_DDC1 = 0x90, - Ellesmere_I2CLineID_DDC2 = 0x91, - Ellesmere_I2CLineID_DDC3 = 0x92, - Ellesmere_I2CLineID_DDC4 = 0x93, - Ellesmere_I2CLineID_DDC5 = 0x94, - Ellesmere_I2CLineID_DDC6 = 0x95, - Ellesmere_I2CLineID_SCLSDA = 0x96, - Ellesmere_I2CLineID_DDCVGA = 0x97 -}; - -#define ELLESMERE_I2C_DDC1DATA 0 -#define ELLESMERE_I2C_DDC1CLK 1 -#define ELLESMERE_I2C_DDC2DATA 2 -#define ELLESMERE_I2C_DDC2CLK 3 -#define ELLESMERE_I2C_DDC3DATA 4 -#define ELLESMERE_I2C_DDC3CLK 5 -#define ELLESMERE_I2C_SDA 40 -#define ELLESMERE_I2C_SCL 41 -#define ELLESMERE_I2C_DDC4DATA 65 -#define ELLESMERE_I2C_DDC4CLK 66 -#define ELLESMERE_I2C_DDC5DATA 0x48 -#define ELLESMERE_I2C_DDC5CLK 0x49 -#define ELLESMERE_I2C_DDC6DATA 0x4a -#define ELLESMERE_I2C_DDC6CLK 0x4b -#define ELLESMERE_I2C_DDCVGADATA 0x4c -#define ELLESMERE_I2C_DDCVGACLK 0x4d - -#define ELLESMERE_UNUSED_GPIO_PIN 0x7F - -int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr); - -int ellesmere_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate); -int ellesmere_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate); -int ellesmere_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); - -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c deleted file mode 100644 index ff41c41..0000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c +++ /dev/null @@ -1,396 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "hwmgr.h" -#include "smumgr.h" -#include "ellesmere_hwmgr.h" -#include "ellesmere_powertune.h" -#include "ellesmere_smumgr.h" -#include "smu74_discrete.h" -#include "pp_debug.h" - -#define VOLTAGE_SCALE 4 -#define POWERTUNE_DEFAULT_SET_MAX 1 - -struct ellesmere_pt_defaults ellesmere_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = { - /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, - * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */ - { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, - { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61}, - { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } }, -}; - -void ellesmere_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *ellesmere_hwmgr = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - - if (table_info && - table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX && - table_info->cac_dtp_table->usPowerTuneDataSetID) - ellesmere_hwmgr->power_tune_defaults = - &ellesmere_power_tune_data_set_array - [table_info->cac_dtp_table->usPowerTuneDataSetID - 1]; - else - ellesmere_hwmgr->power_tune_defaults = &ellesmere_power_tune_data_set_array[0]; - -} - -int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_pt_defaults *defaults = data->power_tune_defaults; - SMU74_Discrete_DpmTable *dpm_table = &(data->smc_state_table); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table; - int i, j, k; - uint16_t *pdef1; - uint16_t *pdef2; - - dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128)); - dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128)); - - PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255, - "Target Operating Temp is out of Range!", - ); -/* This is the same value as TemperatureLimitHigh except it is integer with no fraction bit. */ - dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp); - -/* HW request to hard code this value to 8 which is 0.5C */ - dpm_table->GpuTjHyst = 8; - - dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase; - dpm_table->DTETjOffset = (uint8_t)(data->dte_tj_offset); - dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->BAPM_TEMP_GRADIENT); - pdef1 = defaults->BAPMTI_R; - pdef2 = defaults->BAPMTI_RC; - - for (i = 0; i < SMU74_DTE_ITERATIONS; i++) { - for (j = 0; j < SMU74_DTE_SOURCES; j++) { - for (k = 0; k < SMU74_DTE_SINKS; k++) { - dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1); - dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2); - pdef1++; - pdef2++; - } - } - } - - return 0; -} - -static int ellesmere_populate_svi_load_line(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_pt_defaults *defaults = data->power_tune_defaults; - - data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn; - data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC; - data->power_tune_table.SviLoadLineTrimVddC = 3; - data->power_tune_table.SviLoadLineOffsetVddC = 0; - - return 0; -} - -static int ellesmere_populate_tdc_limit(struct pp_hwmgr *hwmgr) -{ - uint16_t tdc_limit; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct ellesmere_pt_defaults *defaults = data->power_tune_defaults; - - tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128); - data->power_tune_table.TDC_VDDC_PkgLimit = - CONVERT_FROM_HOST_TO_SMC_US(tdc_limit); - data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc = - defaults->TDC_VDDC_ThrottleReleaseLimitPerc; - data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt; - - return 0; -} - -static int ellesmere_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_pt_defaults *defaults = data->power_tune_defaults; - uint32_t temp; - - if (ellesmere_read_smc_sram_dword(hwmgr->smumgr, - fuse_table_offset + - offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl), - (uint32_t *)&temp, data->sram_end)) - PP_ASSERT_WITH_CODE(false, - "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!", - return -EINVAL); - else { - data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl; - data->power_tune_table.LPMLTemperatureMin = - (uint8_t)((temp >> 16) & 0xff); - data->power_tune_table.LPMLTemperatureMax = - (uint8_t)((temp >> 8) & 0xff); - data->power_tune_table.Reserved = (uint8_t)(temp & 0xff); - } - return 0; -} - -static int ellesmere_populate_temperature_scaler(struct pp_hwmgr *hwmgr) -{ - int i; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - /* Currently not used. Set all to zero. */ - for (i = 0; i < 16; i++) - data->power_tune_table.LPMLTemperatureScaler[i] = 0; - - return 0; -} - -static int ellesmere_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15)) - || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity) - hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = - hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity; - - data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US( - hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity); - return 0; -} - -static int ellesmere_populate_gnb_lpml(struct pp_hwmgr *hwmgr) -{ - int i; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - /* Currently not used. Set all to zero. */ - for (i = 0; i < 16; i++) - data->power_tune_table.GnbLPML[i] = 0; - - return 0; -} - -static int ellesmere_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr) -{ - return 0; -} - -static int ellesmere_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - uint16_t hi_sidd = data->power_tune_table.BapmVddCBaseLeakageHiSidd; - uint16_t lo_sidd = data->power_tune_table.BapmVddCBaseLeakageLoSidd; - struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table; - - hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256); - lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256); - - data->power_tune_table.BapmVddCBaseLeakageHiSidd = - CONVERT_FROM_HOST_TO_SMC_US(hi_sidd); - data->power_tune_table.BapmVddCBaseLeakageLoSidd = - CONVERT_FROM_HOST_TO_SMC_US(lo_sidd); - - return 0; -} - -int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - uint32_t pm_fuse_table_offset; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment)) { - if (ellesmere_read_smc_sram_dword(hwmgr->smumgr, - SMU7_FIRMWARE_HEADER_LOCATION + - offsetof(SMU74_Firmware_Header, PmFuseTable), - &pm_fuse_table_offset, data->sram_end)) - PP_ASSERT_WITH_CODE(false, - "Attempt to get pm_fuse_table_offset Failed!", - return -EINVAL); - - if (ellesmere_populate_svi_load_line(hwmgr)) - PP_ASSERT_WITH_CODE(false, - "Attempt to populate SviLoadLine Failed!", - return -EINVAL); - - if (ellesmere_populate_tdc_limit(hwmgr)) - PP_ASSERT_WITH_CODE(false, - "Attempt to populate TDCLimit Failed!", return -EINVAL); - - if (ellesmere_populate_dw8(hwmgr, pm_fuse_table_offset)) - PP_ASSERT_WITH_CODE(false, - "Attempt to populate TdcWaterfallCtl, " - "LPMLTemperature Min and Max Failed!", - return -EINVAL); - - if (0 != ellesmere_populate_temperature_scaler(hwmgr)) - PP_ASSERT_WITH_CODE(false, - "Attempt to populate LPMLTemperatureScaler Failed!", - return -EINVAL); - - if (ellesmere_populate_fuzzy_fan(hwmgr)) - PP_ASSERT_WITH_CODE(false, - "Attempt to populate Fuzzy Fan Control parameters Failed!", - return -EINVAL); - - if (ellesmere_populate_gnb_lpml(hwmgr)) - PP_ASSERT_WITH_CODE(false, - "Attempt to populate GnbLPML Failed!", - return -EINVAL); - - if (ellesmere_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr)) - PP_ASSERT_WITH_CODE(false, - "Attempt to populate GnbLPML Min and Max Vid Failed!", - return -EINVAL); - - if (ellesmere_populate_bapm_vddc_base_leakage_sidd(hwmgr)) - PP_ASSERT_WITH_CODE(false, - "Attempt to populate BapmVddCBaseLeakage Hi and Lo " - "Sidd Failed!", return -EINVAL); - - if (ellesmere_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, - (uint8_t *)&data->power_tune_table, - sizeof(struct SMU74_Discrete_PmFuses), data->sram_end)) - PP_ASSERT_WITH_CODE(false, - "Attempt to download PmFuseTable Failed!", - return -EINVAL); - } - return 0; -} - -int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - int result = 0; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC)) { - int smc_result; - smc_result = smum_send_msg_to_smc(hwmgr->smumgr, - (uint16_t)(PPSMC_MSG_EnableCac)); - PP_ASSERT_WITH_CODE((0 == smc_result), - "Failed to enable CAC in SMC.", result = -1); - - data->cac_enabled = (0 == smc_result) ? true : false; - } - return result; -} - -int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - - if (data->power_containment_features & - POWERCONTAINMENT_FEATURE_PkgPwrLimit) - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_PkgPwrSetLimit, n); - return 0; -} - -static int ellesmere_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp) -{ - return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr, - PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); -} - -int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - int smc_result; - int result = 0; - - data->power_containment_features = 0; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment)) { - if (data->enable_dte_feature) { - smc_result = smum_send_msg_to_smc(hwmgr->smumgr, - (uint16_t)(PPSMC_MSG_EnableDTE)); - PP_ASSERT_WITH_CODE((0 == smc_result), - "Failed to enable DTE in SMC.", result = -1;); - if (0 == smc_result) - data->power_containment_features |= POWERCONTAINMENT_FEATURE_DTE; - } - - if (data->enable_tdc_limit_feature) { - smc_result = smum_send_msg_to_smc(hwmgr->smumgr, - (uint16_t)(PPSMC_MSG_TDCLimitEnable)); - PP_ASSERT_WITH_CODE((0 == smc_result), - "Failed to enable TDCLimit in SMC.", result = -1;); - if (0 == smc_result) - data->power_containment_features |= - POWERCONTAINMENT_FEATURE_TDCLimit; - } - - if (data->enable_pkg_pwr_tracking_feature) { - smc_result = smum_send_msg_to_smc(hwmgr->smumgr, - (uint16_t)(PPSMC_MSG_PkgPwrLimitEnable)); - PP_ASSERT_WITH_CODE((0 == smc_result), - "Failed to enable PkgPwrTracking in SMC.", result = -1;); - if (0 == smc_result) { - struct phm_cac_tdp_table *cac_table = - table_info->cac_dtp_table; - uint32_t default_limit = - (uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256); - - data->power_containment_features |= - POWERCONTAINMENT_FEATURE_PkgPwrLimit; - - if (ellesmere_set_power_limit(hwmgr, default_limit)) - printk(KERN_ERR "Failed to set Default Power Limit in SMC!"); - } - } - } - return result; -} - -int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr) -{ - struct phm_ppt_v1_information *table_info = - (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table; - int adjust_percent, target_tdp; - int result = 0; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment)) { - /* adjustment percentage has already been validated */ - adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ? - hwmgr->platform_descriptor.TDPAdjustment : - (-1 * hwmgr->platform_descriptor.TDPAdjustment); - /* SMC requested that target_tdp to be 7 bit fraction in DPM table - * but message to be 8 bit fraction for messages - */ - target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100; - result = ellesmere_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp); - } - - return result; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h deleted file mode 100644 index 5772bf9..0000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef ELLESMERE_POWERTUNE_H -#define ELLESMERE_POWERTUNE_H - -enum ellesmere_pt_config_reg_type { - ELLESMERE_CONFIGREG_MMR = 0, - ELLESMERE_CONFIGREG_SMC_IND, - ELLESMERE_CONFIGREG_DIDT_IND, - ELLESMERE_CONFIGREG_CACHE, - ELLESMERE_CONFIGREG_MAX -}; - -/* PowerContainment Features */ -#define POWERCONTAINMENT_FEATURE_DTE 0x00000001 -#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002 -#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004 - -struct ellesmere_pt_config_reg { - uint32_t offset; - uint32_t mask; - uint32_t shift; - uint32_t value; - enum ellesmere_pt_config_reg_type type; -}; - -struct ellesmere_pt_defaults { - uint8_t SviLoadLineEn; - uint8_t SviLoadLineVddC; - uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; - uint8_t TDC_MAWt; - uint8_t TdcWaterfallCtl; - uint8_t DTEAmbientTempBase; - - uint32_t DisplayCac; - uint32_t BAPM_TEMP_GRADIENT; - uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS]; - uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS]; -}; - -void ellesmere_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr); -int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr); -int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr); -int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr); -int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr); -int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); -int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr); - -#endif /* ELLESMERE_POWERTUNE_H */ - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c deleted file mode 100644 index 08be400..0000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c +++ /dev/null @@ -1,711 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "ellesmere_thermal.h" -#include "ellesmere_hwmgr.h" -#include "ellesmere_smumgr.h" -#include "ellesmere_ppsmc.h" -#include "smu/smu_7_1_3_d.h" -#include "smu/smu_7_1_3_sh_mask.h" - -int ellesmere_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, - struct phm_fan_speed_info *fan_speed_info) -{ - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return 0; - - fan_speed_info->supports_percent_read = true; - fan_speed_info->supports_percent_write = true; - fan_speed_info->min_percent = 0; - fan_speed_info->max_percent = 100; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_FanSpeedInTableIsRPM) && - hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { - fan_speed_info->supports_rpm_read = true; - fan_speed_info->supports_rpm_write = true; - fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM; - fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM; - } else { - fan_speed_info->min_rpm = 0; - fan_speed_info->max_rpm = 0; - } - - return 0; -} - -int ellesmere_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, - uint32_t *speed) -{ - uint32_t duty100; - uint32_t duty; - uint64_t tmp64; - - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return 0; - - duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL1, FMAX_DUTY100); - duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_STATUS, FDO_PWM_DUTY); - - if (duty100 == 0) - return -EINVAL; - - - tmp64 = (uint64_t)duty * 100; - do_div(tmp64, duty100); - *speed = (uint32_t)tmp64; - - if (*speed > 100) - *speed = 100; - - return 0; -} - -int ellesmere_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) -{ - uint32_t tach_period; - uint32_t crystal_clock_freq; - - if (hwmgr->thermal_controller.fanInfo.bNoFan || - (hwmgr->thermal_controller.fanInfo. - ucTachometerPulsesPerRevolution == 0)) - return 0; - - tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_TACH_STATUS, TACH_PERIOD); - - if (tach_period == 0) - return -EINVAL; - - crystal_clock_freq = tonga_get_xclk(hwmgr); - - *speed = 60 * crystal_clock_freq * 10000 / tach_period; - - return 0; -} - -/** -* Set Fan Speed Control to static mode, so that the user can decide what speed to use. -* @param hwmgr the address of the powerplay hardware manager. -* mode the fan control mode, 0 default, 1 by percent, 5, by RPM -* @exception Should always succeed. -*/ -int ellesmere_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) -{ - - if (hwmgr->fan_ctrl_is_in_default_mode) { - hwmgr->fan_ctrl_default_mode = - PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL2, FDO_PWM_MODE); - hwmgr->tmin = - PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL2, TMIN); - hwmgr->fan_ctrl_is_in_default_mode = false; - } - - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL2, TMIN, 0); - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL2, FDO_PWM_MODE, mode); - - return 0; -} - -/** -* Reset Fan Speed Control to default mode. -* @param hwmgr the address of the powerplay hardware manager. -* @exception Should always succeed. -*/ -int ellesmere_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) -{ - if (!hwmgr->fan_ctrl_is_in_default_mode) { - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode); - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL2, TMIN, hwmgr->tmin); - hwmgr->fan_ctrl_is_in_default_mode = true; - } - - return 0; -} - -int ellesmere_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) -{ - int result; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODFuzzyFanControlSupport)) { - cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY); - result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_FanSpeedInTableIsRPM)) - hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr, - hwmgr->thermal_controller. - advanceFanControlParameters.usMaxFanRPM); - else - hwmgr->hwmgr_func->set_max_fan_pwm_output(hwmgr, - hwmgr->thermal_controller. - advanceFanControlParameters.usMaxFanPWM); - - } else { - cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE); - result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl); - } - - if (!result && hwmgr->thermal_controller. - advanceFanControlParameters.ucTargetTemperature) - result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SetFanTemperatureTarget, - hwmgr->thermal_controller. - advanceFanControlParameters.ucTargetTemperature); - - return result; -} - - -int ellesmere_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) -{ - return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl); -} - -/** -* Set Fan Speed in percent. -* @param hwmgr the address of the powerplay hardware manager. -* @param speed is the percentage value (0% - 100%) to be set. -* @exception Fails is the 100% setting appears to be 0. -*/ -int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, - uint32_t speed) -{ - uint32_t duty100; - uint32_t duty; - uint64_t tmp64; - - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return 0; - - if (speed > 100) - speed = 100; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) - ellesmere_fan_ctrl_stop_smc_fan_control(hwmgr); - - duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL1, FMAX_DUTY100); - - if (duty100 == 0) - return -EINVAL; - - tmp64 = (uint64_t)speed * 100; - do_div(tmp64, duty100); - duty = (uint32_t)tmp64; - - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL0, FDO_STATIC_DUTY, duty); - - return ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); -} - -/** -* Reset Fan Speed to default. -* @param hwmgr the address of the powerplay hardware manager. -* @exception Always succeeds. -*/ -int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) -{ - int result; - - if (hwmgr->thermal_controller.fanInfo.bNoFan) - return 0; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) { - result = ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); - if (!result) - result = ellesmere_fan_ctrl_start_smc_fan_control(hwmgr); - } else - result = ellesmere_fan_ctrl_set_default_mode(hwmgr); - - return result; -} - -/** -* Set Fan Speed in RPM. -* @param hwmgr the address of the powerplay hardware manager. -* @param speed is the percentage value (min - max) to be set. -* @exception Fails is the speed not lie between min and max. -*/ -int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) -{ - uint32_t tach_period; - uint32_t crystal_clock_freq; - - if (hwmgr->thermal_controller.fanInfo.bNoFan || - (hwmgr->thermal_controller.fanInfo. - ucTachometerPulsesPerRevolution == 0) || - (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || - (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM)) - return 0; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) - ellesmere_fan_ctrl_stop_smc_fan_control(hwmgr); - - crystal_clock_freq = tonga_get_xclk(hwmgr); - - tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); - - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_TACH_STATUS, TACH_PERIOD, tach_period); - - return ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); -} - -/** -* Reads the remote temperature from the SIslands thermal controller. -* -* @param hwmgr The address of the hardware manager. -*/ -int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr) -{ - int temp; - - temp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_MULT_THERMAL_STATUS, CTF_TEMP); - - /* Bit 9 means the reading is lower than the lowest usable value. */ - if (temp & 0x200) - temp = ELLESMERE_THERMAL_MAXIMUM_TEMP_READING; - else - temp = temp & 0x1ff; - - temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - - return temp; -} - -/** -* Set the requested temperature range for high and low alert signals -* -* @param hwmgr The address of the hardware manager. -* @param range Temperature range to be programmed for high and low alert signals -* @exception PP_Result_BadInput if the input data is not valid. -*/ -static int ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, - uint32_t low_temp, uint32_t high_temp) -{ - uint32_t low = ELLESMERE_THERMAL_MINIMUM_ALERT_TEMP * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - uint32_t high = ELLESMERE_THERMAL_MAXIMUM_ALERT_TEMP * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - - if (low < low_temp) - low = low_temp; - if (high > high_temp) - high = high_temp; - - if (low > high) - return -EINVAL; - - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_INT, DIG_THERM_INTH, - (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_INT, DIG_THERM_INTL, - (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_CTRL, DIG_THERM_DPM, - (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); - - return 0; -} - -/** -* Programs thermal controller one-time setting registers -* -* @param hwmgr The address of the hardware manager. -*/ -static int ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr) -{ - if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_TACH_CTRL, EDGE_PER_REV, - hwmgr->thermal_controller.fanInfo. - ucTachometerPulsesPerRevolution - 1); - - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28); - - return 0; -} - -/** -* Enable thermal alerts on the RV770 thermal controller. -* -* @param hwmgr The address of the hardware manager. -*/ -static int ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr) -{ - uint32_t alert; - - alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_INT, THERM_INT_MASK); - alert &= ~(ELLESMERE_THERMAL_HIGH_ALERT_MASK | ELLESMERE_THERMAL_LOW_ALERT_MASK); - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_INT, THERM_INT_MASK, alert); - - /* send message to SMU to enable internal thermal interrupts */ - return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable); -} - -/** -* Disable thermal alerts on the RV770 thermal controller. -* @param hwmgr The address of the hardware manager. -*/ -static int ellesmere_thermal_disable_alert(struct pp_hwmgr *hwmgr) -{ - uint32_t alert; - - alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_INT, THERM_INT_MASK); - alert |= (ELLESMERE_THERMAL_HIGH_ALERT_MASK | ELLESMERE_THERMAL_LOW_ALERT_MASK); - PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_THERMAL_INT, THERM_INT_MASK, alert); - - /* send message to SMU to disable internal thermal interrupts */ - return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable); -} - -/** -* Uninitialize the thermal controller. -* Currently just disables alerts. -* @param hwmgr The address of the hardware manager. -*/ -int ellesmere_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) -{ - int result = ellesmere_thermal_disable_alert(hwmgr); - - if (!hwmgr->thermal_controller.fanInfo.bNoFan) - ellesmere_fan_ctrl_set_default_mode(hwmgr); - - return result; -} - -/** -* Set up the fan table to control the fan using the SMC. -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from set temperature range routine -*/ -int tf_ellesmere_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) -{ - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; - uint32_t duty100; - uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; - uint16_t fdo_min, slope1, slope2; - uint32_t reference_clock; - int res; - uint64_t tmp64; - - if (data->fan_table_start == 0) { - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl); - return 0; - } - - duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_FDO_CTRL1, FMAX_DUTY100); - - if (duty100 == 0) { - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl); - return 0; - } - - tmp64 = hwmgr->thermal_controller.advanceFanControlParameters. - usPWMMin * duty100; - do_div(tmp64, 10000); - fdo_min = (uint16_t)tmp64; - - t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - - hwmgr->thermal_controller.advanceFanControlParameters.usTMin; - t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - - hwmgr->thermal_controller.advanceFanControlParameters.usTMed; - - pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin; - pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed; - - slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); - slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); - - fan_table.TempMin = cpu_to_be16((50 + hwmgr-> - thermal_controller.advanceFanControlParameters.usTMin) / 100); - fan_table.TempMed = cpu_to_be16((50 + hwmgr-> - thermal_controller.advanceFanControlParameters.usTMed) / 100); - fan_table.TempMax = cpu_to_be16((50 + hwmgr-> - thermal_controller.advanceFanControlParameters.usTMax) / 100); - - fan_table.Slope1 = cpu_to_be16(slope1); - fan_table.Slope2 = cpu_to_be16(slope2); - - fan_table.FdoMin = cpu_to_be16(fdo_min); - - fan_table.HystDown = cpu_to_be16(hwmgr-> - thermal_controller.advanceFanControlParameters.ucTHyst); - - fan_table.HystUp = cpu_to_be16(1); - - fan_table.HystSlope = cpu_to_be16(1); - - fan_table.TempRespLim = cpu_to_be16(5); - - reference_clock = tonga_get_xclk(hwmgr); - - fan_table.RefreshPeriod = cpu_to_be32((hwmgr-> - thermal_controller.advanceFanControlParameters.ulCycleDelay * - reference_clock) / 1600); - - fan_table.FdoMax = cpu_to_be16((uint16_t)duty100); - - fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD( - hwmgr->device, CGS_IND_REG__SMC, - CG_MULT_THERMAL_CTRL, TEMP_SEL); - - res = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, data->fan_table_start, - (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), - data->sram_end); - - if (!res && hwmgr->thermal_controller. - advanceFanControlParameters.ucMinimumPWMLimit) - res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SetFanMinPwm, - hwmgr->thermal_controller. - advanceFanControlParameters.ucMinimumPWMLimit); - - if (!res && hwmgr->thermal_controller. - advanceFanControlParameters.ulMinFanSCLKAcousticLimit) - res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SetFanSclkTarget, - hwmgr->thermal_controller. - advanceFanControlParameters.ulMinFanSCLKAcousticLimit); - - if (res) - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl); - - return 0; -} - -/** -* Start the fan control on the SMC. -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from set temperature range routine -*/ -int tf_ellesmere_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) -{ -/* If the fantable setup has failed we could have disabled - * PHM_PlatformCaps_MicrocodeFanControl even after - * this function was included in the table. - * Make sure that we still think controlling the fan is OK. -*/ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) { - ellesmere_fan_ctrl_start_smc_fan_control(hwmgr); - ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); - } - - return 0; -} - -/** -* Set temperature range for high and low alerts -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from set temperature range routine -*/ -int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) -{ - struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input; - - if (range == NULL) - return -EINVAL; - - return ellesmere_thermal_set_temperature_range(hwmgr, range->min, range->max); -} - -/** -* Programs one-time setting registers -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from initialize thermal controller routine -*/ -int tf_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) -{ - return ellesmere_thermal_initialize(hwmgr); -} - -/** -* Enable high and low alerts -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from enable alert routine -*/ -int tf_ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) -{ - return ellesmere_thermal_enable_alert(hwmgr); -} - -/** -* Disable high and low alerts -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from disable alert routine -*/ -static int tf_ellesmere_thermal_disable_alert(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) -{ - return ellesmere_thermal_disable_alert(hwmgr); -} - -static int tf_ellesmere_thermal_avfs_enable(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) -{ - int ret; - struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr); - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); - - if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS) - return 0; - - ret = (smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs) == 0) ? - 0 : -1; - - if (!ret) - /* If this param is not changed, this function could fire unnecessarily */ - smu_data->avfs.avfs_btc_status = AVFS_BTC_COMPLETED_PREVIOUSLY; - - return ret; -} - -static struct phm_master_table_item -ellesmere_thermal_start_thermal_controller_master_list[] = { - {NULL, tf_ellesmere_thermal_initialize}, - {NULL, tf_ellesmere_thermal_set_temperature_range}, - {NULL, tf_ellesmere_thermal_enable_alert}, - {NULL, tf_ellesmere_thermal_avfs_enable}, -/* We should restrict performance levels to low before we halt the SMC. - * On the other hand we are still in boot state when we do this - * so it would be pointless. - * If this assumption changes we have to revisit this table. - */ - {NULL, tf_ellesmere_thermal_setup_fan_table}, - {NULL, tf_ellesmere_thermal_start_smc_fan_control}, - {NULL, NULL} -}; - -static struct phm_master_table_header -ellesmere_thermal_start_thermal_controller_master = { - 0, - PHM_MasterTableFlag_None, - ellesmere_thermal_start_thermal_controller_master_list -}; - -static struct phm_master_table_item -ellesmere_thermal_set_temperature_range_master_list[] = { - {NULL, tf_ellesmere_thermal_disable_alert}, - {NULL, tf_ellesmere_thermal_set_temperature_range}, - {NULL, tf_ellesmere_thermal_enable_alert}, - {NULL, NULL} -}; - -struct phm_master_table_header -ellesmere_thermal_set_temperature_range_master = { - 0, - PHM_MasterTableFlag_None, - ellesmere_thermal_set_temperature_range_master_list -}; - -int ellesmere_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr) -{ - if (!hwmgr->thermal_controller.fanInfo.bNoFan) - ellesmere_fan_ctrl_set_default_mode(hwmgr); - return 0; -} - -/** -* Initializes the thermal controller related functions in the Hardware Manager structure. -* @param hwmgr The address of the hardware manager. -* @exception Any error code from the low-level communication. -*/ -int pp_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr) -{ - int result; - - result = phm_construct_table(hwmgr, - &ellesmere_thermal_set_temperature_range_master, - &(hwmgr->set_temperature_range)); - - if (!result) { - result = phm_construct_table(hwmgr, - &ellesmere_thermal_start_thermal_controller_master, - &(hwmgr->start_thermal_controller)); - if (result) - phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range)); - } - - if (!result) - hwmgr->fan_ctrl_is_in_default_mode = true; - return result; -} - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h deleted file mode 100644 index 4263e9b..0000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _ELLESMERE_THERMAL_H_ -#define _ELLESMERE_THERMAL_H_ - -#include "hwmgr.h" - -#define ELLESMERE_THERMAL_HIGH_ALERT_MASK 0x1 -#define ELLESMERE_THERMAL_LOW_ALERT_MASK 0x2 - -#define ELLESMERE_THERMAL_MINIMUM_TEMP_READING -256 -#define ELLESMERE_THERMAL_MAXIMUM_TEMP_READING 255 - -#define ELLESMERE_THERMAL_MINIMUM_ALERT_TEMP 0 -#define ELLESMERE_THERMAL_MAXIMUM_ALERT_TEMP 255 - -#define FDO_PWM_MODE_STATIC 1 -#define FDO_PWM_MODE_STATIC_RPM 5 - - -extern int tf_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); -extern int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); -extern int tf_ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); - -extern int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr); -extern int ellesmere_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr); -extern int ellesmere_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info); -extern int ellesmere_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed); -extern int ellesmere_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr); -extern int ellesmere_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode); -extern int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed); -extern int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr); -extern int pp_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr); -extern int ellesmere_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr); -extern int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed); -extern int ellesmere_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed); -extern int ellesmere_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr); -extern uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr); - -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index 2c68199..7d69ed6 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c @@ -34,7 +34,7 @@ extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr); extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr); extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr); -extern int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr); +extern int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr); int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle) { @@ -68,9 +68,9 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle) case CHIP_FIJI: fiji_hwmgr_init(hwmgr); break; - case CHIP_BAFFIN: - case CHIP_ELLESMERE: - ellesemere_hwmgr_init(hwmgr); + case CHIP_POLARIS11: + case CHIP_POLARIS10: + polaris10_hwmgr_init(hwmgr); break; default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c new file mode 100644 index 0000000..e362ddb --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c @@ -0,0 +1,428 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "polaris10_clockpowergating.h" + +int polaris10_phm_powerdown_uvd(struct pp_hwmgr *hwmgr) +{ + if (phm_cf_want_uvd_power_gating(hwmgr)) + return smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_UVDPowerOFF); + return 0; +} + +int polaris10_phm_powerup_uvd(struct pp_hwmgr *hwmgr) +{ + if (phm_cf_want_uvd_power_gating(hwmgr)) { + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_UVDDynamicPowerGating)) { + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_UVDPowerON, 1); + } else { + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_UVDPowerON, 0); + } + } + + return 0; +} + +int polaris10_phm_powerdown_vce(struct pp_hwmgr *hwmgr) +{ + if (phm_cf_want_vce_power_gating(hwmgr)) + return smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_VCEPowerOFF); + return 0; +} + +int polaris10_phm_powerup_vce(struct pp_hwmgr *hwmgr) +{ + if (phm_cf_want_vce_power_gating(hwmgr)) + return smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_VCEPowerON); + return 0; +} + +int polaris10_phm_powerdown_samu(struct pp_hwmgr *hwmgr) +{ + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SamuPowerGating)) + return smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_SAMPowerOFF); + return 0; +} + +int polaris10_phm_powerup_samu(struct pp_hwmgr *hwmgr) +{ + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SamuPowerGating)) + return smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_SAMPowerON); + return 0; +} + +int polaris10_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + data->uvd_power_gated = false; + data->vce_power_gated = false; + data->samu_power_gated = false; + + polaris10_phm_powerup_uvd(hwmgr); + polaris10_phm_powerup_vce(hwmgr); + polaris10_phm_powerup_samu(hwmgr); + + return 0; +} + +int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (data->uvd_power_gated == bgate) + return 0; + + data->uvd_power_gated = bgate; + + if (bgate) { + polaris10_update_uvd_dpm(hwmgr, true); + polaris10_phm_powerdown_uvd(hwmgr); + } else { + polaris10_phm_powerup_uvd(hwmgr); + polaris10_update_uvd_dpm(hwmgr, false); + } + + return 0; +} + +int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (data->vce_power_gated == bgate) + return 0; + + if (bgate) + polaris10_phm_powerdown_vce(hwmgr); + else + polaris10_phm_powerup_vce(hwmgr); + + return 0; +} + +int polaris10_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (data->samu_power_gated == bgate) + return 0; + + data->samu_power_gated = bgate; + + if (bgate) { + polaris10_update_samu_dpm(hwmgr, true); + polaris10_phm_powerdown_samu(hwmgr); + } else { + polaris10_phm_powerup_samu(hwmgr); + polaris10_update_samu_dpm(hwmgr, false); + } + + return 0; +} + +int polaris10_phm_update_clock_gatings(struct pp_hwmgr *hwmgr, + const uint32_t *msg_id) +{ + PPSMC_Msg msg; + uint32_t value; + + switch ((*msg_id & PP_GROUP_MASK) >> PP_GROUP_SHIFT) { + case PP_GROUP_GFX: + switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) { + case PP_BLOCK_GFX_CG: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_GFX_CGCG_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS + ? PPSMC_MSG_EnableClockGatingFeature + : PPSMC_MSG_DisableClockGatingFeature; + value = CG_GFX_CGLS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_GFX_3D: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_GFX_3DCG_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_GFX_3DLS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_GFX_RLC: + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_GFX_RLC_LS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_GFX_CP: + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_GFX_CP_LS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_GFX_MG: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = (CG_CPF_MGCG_MASK | CG_RLC_MGCG_MASK | + CG_GFX_OTHERS_MGCG_MASK); + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + default: + return -1; + } + break; + + case PP_GROUP_SYS: + switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) { + case PP_BLOCK_SYS_BIF: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_BIF_MGCG_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_BIF_MGLS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_SYS_MC: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_MC_MGCG_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_MC_MGLS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_SYS_DRM: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_DRM_MGCG_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_DRM_MGLS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_SYS_HDP: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_HDP_MGCG_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_HDP_MGLS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_SYS_SDMA: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_SDMA_MGCG_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + + if (PP_STATE_SUPPORT_LS & *msg_id) { + msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_SDMA_MGLS_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + case PP_BLOCK_SYS_ROM: + if (PP_STATE_SUPPORT_CG & *msg_id) { + msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? + PPSMC_MSG_EnableClockGatingFeature : + PPSMC_MSG_DisableClockGatingFeature; + value = CG_SYS_ROM_MASK; + + if (smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, msg, value)) + return -1; + } + break; + + default: + return -1; + + } + break; + + default: + return -1; + + } + + return 0; +} + +/* This function is for Polaris11 only for now, + * Powerplay will only control the static per CU Power Gating. + * Dynamic per CU Power Gating will be done in gfx. + */ +int polaris10_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable) +{ + struct cgs_system_info sys_info = {0}; + uint32_t active_cus; + int result; + + sys_info.size = sizeof(struct cgs_system_info); + sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO; + + result = cgs_query_system_info(hwmgr->device, &sys_info); + + if (result) + return -EINVAL; + else + active_cus = sys_info.value; + + if (enable) + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus); + else + return smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_GFX_CU_PG_DISABLE); +} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h new file mode 100644 index 0000000..88d68cb --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h @@ -0,0 +1,40 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _POLARIS10_CLOCK_POWER_GATING_H_ +#define _POLARIS10_CLOCK_POWER_GATING_H_ + +#include "polaris10_hwmgr.h" +#include "pp_asicblocks.h" + +int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_phm_powerdown_uvd(struct pp_hwmgr *hwmgr); +int polaris10_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr); +int polaris10_phm_update_clock_gatings(struct pp_hwmgr *hwmgr, + const uint32_t *msg_id); +int polaris10_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable); + +#endif /* _POLARIS10_CLOCK_POWER_GATING_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h new file mode 100644 index 0000000..f78ffd9 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h @@ -0,0 +1,62 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef POLARIS10_DYN_DEFAULTS_H +#define POLARIS10_DYN_DEFAULTS_H + + +enum Polaris10dpm_TrendDetection { + Polaris10Adpm_TrendDetection_AUTO, + Polaris10Adpm_TrendDetection_UP, + Polaris10Adpm_TrendDetection_DOWN +}; +typedef enum Polaris10dpm_TrendDetection Polaris10dpm_TrendDetection; + +/* We need to fill in the default values */ + + +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1 0x000400 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2 0xC00080 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3 0xC00200 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4 0xC01680 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5 0xC00033 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6 0xC00033 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7 0x3FFFC000 + + +#define PPPOLARIS10_THERMALPROTECTCOUNTER_DFLT 0x200 +#define PPPOLARIS10_STATICSCREENTHRESHOLDUNIT_DFLT 0 +#define PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT 0x00C8 +#define PPPOLARIS10_GFXIDLECLOCKSTOPTHRESHOLD_DFLT 0x200 +#define PPPOLARIS10_REFERENCEDIVIDER_DFLT 4 + +#define PPPOLARIS10_ULVVOLTAGECHANGEDELAY_DFLT 1687 + +#define PPPOLARIS10_CGULVPARAMETER_DFLT 0x00040035 +#define PPPOLARIS10_CGULVCONTROL_DFLT 0x00007450 +#define PPPOLARIS10_TARGETACTIVITY_DFLT 50 +#define PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT 10 + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c new file mode 100644 index 0000000..5080d67 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c @@ -0,0 +1,4844 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include +#include +#include +#include "linux/delay.h" +#include "pp_acpi.h" +#include "hwmgr.h" +#include "polaris10_hwmgr.h" +#include "polaris10_powertune.h" +#include "polaris10_dyn_defaults.h" +#include "polaris10_smumgr.h" +#include "pp_debug.h" +#include "ppatomctrl.h" +#include "atombios.h" +#include "tonga_pptable.h" +#include "pppcielanes.h" +#include "amd_pcie_helpers.h" +#include "hardwaremanager.h" +#include "tonga_processpptables.h" +#include "cgs_common.h" +#include "smu74.h" +#include "smu_ucode_xfer_vi.h" +#include "smu74_discrete.h" +#include "smu/smu_7_1_3_d.h" +#include "smu/smu_7_1_3_sh_mask.h" +#include "gmc/gmc_8_1_d.h" +#include "gmc/gmc_8_1_sh_mask.h" +#include "oss/oss_3_0_d.h" +#include "gca/gfx_8_0_d.h" +#include "bif/bif_5_0_d.h" +#include "bif/bif_5_0_sh_mask.h" +#include "gmc/gmc_8_1_d.h" +#include "gmc/gmc_8_1_sh_mask.h" +#include "bif/bif_5_0_d.h" +#include "bif/bif_5_0_sh_mask.h" +#include "dce/dce_10_0_d.h" +#include "dce/dce_10_0_sh_mask.h" + +#include "polaris10_thermal.h" +#include "polaris10_clockpowergating.h" + +#define MC_CG_ARB_FREQ_F0 0x0a +#define MC_CG_ARB_FREQ_F1 0x0b +#define MC_CG_ARB_FREQ_F2 0x0c +#define MC_CG_ARB_FREQ_F3 0x0d + +#define MC_CG_SEQ_DRAMCONF_S0 0x05 +#define MC_CG_SEQ_DRAMCONF_S1 0x06 +#define MC_CG_SEQ_YCLK_SUSPEND 0x04 +#define MC_CG_SEQ_YCLK_RESUME 0x0a + + +#define SMC_RAM_END 0x40000 + +#define SMC_CG_IND_START 0xc0030000 +#define SMC_CG_IND_END 0xc0040000 + +#define VOLTAGE_SCALE 4 +#define VOLTAGE_VID_OFFSET_SCALE1 625 +#define VOLTAGE_VID_OFFSET_SCALE2 100 + +#define VDDC_VDDCI_DELTA 200 + +#define MEM_FREQ_LOW_LATENCY 25000 +#define MEM_FREQ_HIGH_LATENCY 80000 + +#define MEM_LATENCY_HIGH 45 +#define MEM_LATENCY_LOW 35 +#define MEM_LATENCY_ERR 0xFFFF + +#define MC_SEQ_MISC0_GDDR5_SHIFT 28 +#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 +#define MC_SEQ_MISC0_GDDR5_VALUE 5 + + +#define PCIE_BUS_CLK 10000 +#define TCLK (PCIE_BUS_CLK / 10) + + +uint16_t polaris10_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0}, + {600, 1050, 6, 1} }; + +/* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */ +uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} }, + { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } }; + +/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */ +uint8_t polaris10_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5}, + {0, 2, 4, 5, 6, 5} }; + +/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ +enum DPM_EVENT_SRC { + DPM_EVENT_SRC_ANALOG = 0, + DPM_EVENT_SRC_EXTERNAL = 1, + DPM_EVENT_SRC_DIGITAL = 2, + DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, + DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 +}; + +const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic); + +struct polaris10_power_state *cast_phw_polaris10_power_state( + struct pp_hw_power_state *hw_ps) +{ + PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic), + "Invalid Powerstate Type!", + return NULL); + + return (struct polaris10_power_state *)hw_ps; +} + +const struct polaris10_power_state *cast_const_phw_polaris10_power_state( + const struct pp_hw_power_state *hw_ps) +{ + PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic), + "Invalid Powerstate Type!", + return NULL); + + return (const struct polaris10_power_state *)hw_ps; +} + +static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr) +{ + return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, + CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) + ? true : false; +} + +/** + * Find the MC microcode version and store it in the HwMgr struct + * + * @param hwmgr the address of the powerplay hardware manager. + * @return always 0 + */ +int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr) +{ + cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); + + hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); + + return 0; +} + +uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr) +{ + uint32_t speedCntl = 0; + + /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ + speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, + ixPCIE_LC_SPEED_CNTL); + return((uint16_t)PHM_GET_FIELD(speedCntl, + PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); +} + +int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) +{ + uint32_t link_width; + + /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ + link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, + PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD); + + PP_ASSERT_WITH_CODE((7 >= link_width), + "Invalid PCIe lane width!", return 0); + + return decode_pcie_lane_width(link_width); +} + +void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr) +{ + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)hwmgr->pptable; + struct phm_clock_voltage_dependency_table *table = + table_info->vddc_dep_on_dal_pwrl; + struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table; + enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level; + uint32_t req_vddc = 0, req_volt, i; + + if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW && + dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE)) + return; + + for (i = 0; i < table->count; i++) { + if (dal_power_level == table->entries[i].clk) { + req_vddc = table->entries[i].v; + break; + } + } + + vddc_table = table_info->vdd_dep_on_sclk; + for (i = 0; i < vddc_table->count; i++) { + if (req_vddc <= vddc_table->entries[i].vddc) { + req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE) + << VDDC_SHIFT; + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_VddC_Request, req_volt); + return; + } + } + printk(KERN_ERR "DAL requested level can not" + " found a available voltage in VDDC DPM Table \n"); +} + +/** +* Enable voltage control +* +* @param pHwMgr the address of the powerplay hardware manager. +* @return always PP_Result_OK +*/ +int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) +{ + PP_ASSERT_WITH_CODE( + (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0), + "Failed to enable voltage DPM during DPM Start Function!", + return 1; + ); + + return 0; +} + +/** +* Checks if we want to support voltage control +* +* @param hwmgr the address of the powerplay hardware manager. +*/ +static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr) +{ + const struct polaris10_hwmgr *data = + (const struct polaris10_hwmgr *)(hwmgr->backend); + + return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control); +} + +/** +* Enable voltage control +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr) +{ + /* enable voltage control */ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); + + return 0; +} + +/** +* Create Voltage Tables. +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)hwmgr->pptable; + int result; + + if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { + result = atomctrl_get_voltage_table_v3(hwmgr, + VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, + &(data->mvdd_voltage_table)); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to retrieve MVDD table.", + return result); + } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { + result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table), + table_info->vdd_dep_on_mclk); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to retrieve SVI2 MVDD table from dependancy table.", + return result;); + } + + if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { + result = atomctrl_get_voltage_table_v3(hwmgr, + VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, + &(data->vddci_voltage_table)); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to retrieve VDDCI table.", + return result); + } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { + result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table), + table_info->vdd_dep_on_mclk); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to retrieve SVI2 VDDCI table from dependancy table.", + return result); + } + + if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { + result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table), + table_info->vddc_lookup_table); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to retrieve SVI2 VDDC table from lookup table.", + return result); + } + + PP_ASSERT_WITH_CODE( + (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)), + "Too many voltage values for VDDC. Trimming to fit state table.", + phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC, + &(data->vddc_voltage_table))); + + PP_ASSERT_WITH_CODE( + (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)), + "Too many voltage values for VDDCI. Trimming to fit state table.", + phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI, + &(data->vddci_voltage_table))); + + PP_ASSERT_WITH_CODE( + (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)), + "Too many voltage values for MVDD. Trimming to fit state table.", + phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD, + &(data->mvdd_voltage_table))); + + return 0; +} + +/** +* Programs static screed detection parameters +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_program_static_screen_threshold_parameters( + struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + /* Set static screen threshold unit */ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT, + data->static_screen_threshold_unit); + /* Set static screen threshold */ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD, + data->static_screen_threshold); + + return 0; +} + +/** +* Setup display gap for glitch free memory clock switching. +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr) +{ + uint32_t display_gap = + cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_DISPLAY_GAP_CNTL); + + display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, + DISP_GAP, DISPLAY_GAP_IGNORE); + + display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, + DISP_GAP_MCHG, DISPLAY_GAP_VBLANK); + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_DISPLAY_GAP_CNTL, display_gap); + + return 0; +} + +/** +* Programs activity state transition voting clients +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + /* Clear reset for voting clients before enabling DPM */ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7); + + return 0; +} + +/** +* Get the location of various tables inside the FW image. +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + uint32_t tmp; + int result; + bool error = false; + + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU74_Firmware_Header, DpmTable), + &tmp, data->sram_end); + + if (0 == result) + data->dpm_table_start = tmp; + + error |= (0 != result); + + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU74_Firmware_Header, SoftRegisters), + &tmp, data->sram_end); + + if (!result) { + data->soft_regs_start = tmp; + smu_data->soft_regs_start = tmp; + } + + error |= (0 != result); + + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU74_Firmware_Header, mcRegisterTable), + &tmp, data->sram_end); + + if (!result) + data->mc_reg_table_start = tmp; + + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU74_Firmware_Header, FanTable), + &tmp, data->sram_end); + + if (!result) + data->fan_table_start = tmp; + + error |= (0 != result); + + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU74_Firmware_Header, mcArbDramTimingTable), + &tmp, data->sram_end); + + if (!result) + data->arb_table_start = tmp; + + error |= (0 != result); + + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU74_Firmware_Header, Version), + &tmp, data->sram_end); + + if (!result) + hwmgr->microcode_version_info.SMC = tmp; + + error |= (0 != result); + + return error ? -1 : 0; +} + +/* Copy one arb setting to another and then switch the active set. + * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants. + */ +static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, + uint32_t arb_src, uint32_t arb_dest) +{ + uint32_t mc_arb_dram_timing; + uint32_t mc_arb_dram_timing2; + uint32_t burst_time; + uint32_t mc_cg_config; + + switch (arb_src) { + case MC_CG_ARB_FREQ_F0: + mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); + mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); + burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); + break; + case MC_CG_ARB_FREQ_F1: + mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); + mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); + burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1); + break; + default: + return -EINVAL; + } + + switch (arb_dest) { + case MC_CG_ARB_FREQ_F0: + cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); + cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); + PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time); + break; + case MC_CG_ARB_FREQ_F1: + cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); + cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); + PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time); + break; + default: + return -EINVAL; + } + + mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); + mc_cg_config |= 0x0000000F; + cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); + PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest); + + return 0; +} + +/** +* Initial switch from ARB F0->F1 +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +* This function is to be called from the SetPowerState table. +*/ +static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr) +{ + return polaris10_copy_and_switch_arb_sets(hwmgr, + MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); +} + +static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; + uint32_t i, max_entry; + + PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels || + data->use_pcie_power_saving_levels), "No pcie performance levels!", + return -EINVAL); + + if (data->use_pcie_performance_levels && + !data->use_pcie_power_saving_levels) { + data->pcie_gen_power_saving = data->pcie_gen_performance; + data->pcie_lane_power_saving = data->pcie_lane_performance; + } else if (!data->use_pcie_performance_levels && + data->use_pcie_power_saving_levels) { + data->pcie_gen_performance = data->pcie_gen_power_saving; + data->pcie_lane_performance = data->pcie_lane_power_saving; + } + + phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, + SMU74_MAX_LEVELS_LINK, + MAX_REGULAR_DPM_NUMBER); + + if (pcie_table != NULL) { + /* max_entry is used to make sure we reserve one PCIE level + * for boot level (fix for A+A PSPP issue). + * If PCIE table from PPTable have ULV entry + 8 entries, + * then ignore the last entry.*/ + max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ? + SMU74_MAX_LEVELS_LINK : pcie_table->count; + for (i = 1; i < max_entry; i++) { + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, + get_pcie_gen_support(data->pcie_gen_cap, + pcie_table->entries[i].gen_speed), + get_pcie_lane_support(data->pcie_lane_cap, + pcie_table->entries[i].lane_width)); + } + data->dpm_table.pcie_speed_table.count = max_entry - 1; + + /* Setup BIF_SCLK levels */ + for (i = 0; i < max_entry; i++) + data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk; + } else { + /* Hardcode Pcie Table */ + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Min_PCIEGen), + get_pcie_lane_support(data->pcie_lane_cap, + PP_Max_PCIELane)); + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Min_PCIEGen), + get_pcie_lane_support(data->pcie_lane_cap, + PP_Max_PCIELane)); + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Max_PCIEGen), + get_pcie_lane_support(data->pcie_lane_cap, + PP_Max_PCIELane)); + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Max_PCIEGen), + get_pcie_lane_support(data->pcie_lane_cap, + PP_Max_PCIELane)); + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Max_PCIEGen), + get_pcie_lane_support(data->pcie_lane_cap, + PP_Max_PCIELane)); + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Max_PCIEGen), + get_pcie_lane_support(data->pcie_lane_cap, + PP_Max_PCIELane)); + + data->dpm_table.pcie_speed_table.count = 6; + } + /* Populate last level for boot PCIE level, but do not increment count. */ + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, + data->dpm_table.pcie_speed_table.count, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Min_PCIEGen), + get_pcie_lane_support(data->pcie_lane_cap, + PP_Max_PCIELane)); + + return 0; +} + +/* + * This function is to initalize all DPM state tables + * for SMU7 based on the dependency table. + * Dynamic state patching function will then trim these + * state tables to the allowed range based + * on the power policy or external client requests, + * such as UVD request, etc. + */ +int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + uint32_t i; + + struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = + table_info->vdd_dep_on_sclk; + struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = + table_info->vdd_dep_on_mclk; + + PP_ASSERT_WITH_CODE(dep_sclk_table != NULL, + "SCLK dependency table is missing. This table is mandatory", + return -EINVAL); + PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1, + "SCLK dependency table has to have is missing." + "This table is mandatory", + return -EINVAL); + + PP_ASSERT_WITH_CODE(dep_mclk_table != NULL, + "MCLK dependency table is missing. This table is mandatory", + return -EINVAL); + PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, + "MCLK dependency table has to have is missing." + "This table is mandatory", + return -EINVAL); + + /* clear the state table to reset everything to default */ + phm_reset_single_dpm_table( + &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER); + phm_reset_single_dpm_table( + &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER); + + + /* Initialize Sclk DPM table based on allow Sclk values */ + data->dpm_table.sclk_table.count = 0; + for (i = 0; i < dep_sclk_table->count; i++) { + if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != + dep_sclk_table->entries[i].clk) { + + data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = + dep_sclk_table->entries[i].clk; + + data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = + (i == 0) ? true : false; + data->dpm_table.sclk_table.count++; + } + } + + /* Initialize Mclk DPM table based on allow Mclk values */ + data->dpm_table.mclk_table.count = 0; + for (i = 0; i < dep_mclk_table->count; i++) { + if (i == 0 || data->dpm_table.mclk_table.dpm_levels + [data->dpm_table.mclk_table.count - 1].value != + dep_mclk_table->entries[i].clk) { + data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = + dep_mclk_table->entries[i].clk; + data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = + (i == 0) ? true : false; + data->dpm_table.mclk_table.count++; + } + } + + /* setup PCIE gen speed levels */ + polaris10_setup_default_pcie_table(hwmgr); + + /* save a copy of the default DPM table */ + memcpy(&(data->golden_dpm_table), &(data->dpm_table), + sizeof(struct polaris10_dpm_table)); + + return 0; +} + +uint8_t convert_to_vid(uint16_t vddc) +{ + return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25); +} + +/** + * Mvdd table preparation for SMC. + * + * @param *hwmgr The address of the hardware manager. + * @param *table The SMC DPM table structure to be populated. + * @return 0 + */ +static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, + SMU74_Discrete_DpmTable *table) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t count, level; + + if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { + count = data->mvdd_voltage_table.count; + if (count > SMU_MAX_SMIO_LEVELS) + count = SMU_MAX_SMIO_LEVELS; + for (level = 0; level < count; level++) { + table->SmioTable2.Pattern[level].Voltage = + PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE); + /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/ + table->SmioTable2.Pattern[level].Smio = + (uint8_t) level; + table->Smio[level] |= + data->mvdd_voltage_table.entries[level].smio_low; + } + table->SmioMask2 = data->vddci_voltage_table.mask_low; + + table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count); + } + + return 0; +} + +static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + uint32_t count, level; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + count = data->vddci_voltage_table.count; + + if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { + if (count > SMU_MAX_SMIO_LEVELS) + count = SMU_MAX_SMIO_LEVELS; + for (level = 0; level < count; ++level) { + table->SmioTable1.Pattern[level].Voltage = + PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE); + table->SmioTable1.Pattern[level].Smio = (uint8_t) level; + + table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low; + } + } + + table->SmioMask1 = data->vddci_voltage_table.mask_low; + + return 0; +} + +/** +* Preparation of vddc and vddgfx CAC tables for SMC. +* +* @param hwmgr the address of the hardware manager +* @param table the SMC DPM table structure to be populated +* @return always 0 +*/ +static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + uint32_t count; + uint8_t index; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_voltage_lookup_table *lookup_table = + table_info->vddc_lookup_table; + /* tables is already swapped, so in order to use the value from it, + * we need to swap it back. + * We are populating vddc CAC data to BapmVddc table + * in split and merged mode + */ + for (count = 0; count < lookup_table->count; count++) { + index = phm_get_voltage_index(lookup_table, + data->vddc_voltage_table.entries[count].value); + table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low); + table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid); + table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high); + } + + return 0; +} + +/** +* Preparation of voltage tables for SMC. +* +* @param hwmgr the address of the hardware manager +* @param table the SMC DPM table structure to be populated +* @return always 0 +*/ + +int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + polaris10_populate_smc_vddci_table(hwmgr, table); + polaris10_populate_smc_mvdd_table(hwmgr, table); + polaris10_populate_cac_table(hwmgr, table); + + return 0; +} + +static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_Ulv *state) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + state->CcPwrDynRm = 0; + state->CcPwrDynRm1 = 0; + + state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset; + state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset * + VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); + + state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1; + + CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm); + CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1); + CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset); + + return 0; +} + +static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + return polaris10_populate_ulv_level(hwmgr, &table->Ulv); +} + +static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_dpm_table *dpm_table = &data->dpm_table; + int i; + + /* Index (dpm_table->pcie_speed_table.count) + * is reserved for PCIE boot level. */ + for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { + table->LinkLevel[i].PcieGenSpeed = + (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; + table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( + dpm_table->pcie_speed_table.dpm_levels[i].param1); + table->LinkLevel[i].EnabledForActivity = 1; + table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff); + table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5); + table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30); + } + + data->smc_state_table.LinkLevelCount = + (uint8_t)dpm_table->pcie_speed_table.count; + data->dpm_level_enable_mask.pcie_dpm_enable_mask = + phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); + + return 0; +} + +static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr) +{ + uint32_t reference_clock, tmp; + struct cgs_display_info info = {0}; + struct cgs_mode_info mode_info; + + info.mode_info = &mode_info; + + tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK); + + if (tmp) + return TCLK; + + cgs_get_active_displays_info(hwmgr->device, &info); + reference_clock = mode_info.ref_clock; + + tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE); + + if (0 != tmp) + return reference_clock / 4; + + return reference_clock; +} + +/** +* Calculates the SCLK dividers using the provided engine clock +* +* @param hwmgr the address of the hardware manager +* @param clock the engine clock to use to populate the structure +* @param sclk the SMC SCLK structure to be populated +*/ +static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr, + uint32_t clock, SMU_SclkSetting *sclk_setting) +{ + const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const SMU74_Discrete_DpmTable *table = &(data->smc_state_table); + struct pp_atomctrl_clock_dividers_ai dividers; + + uint32_t ref_clock; + uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq; + uint8_t i; + int result; + uint64_t temp; + + sclk_setting->SclkFrequency = clock; + /* get the engine clock dividers for this clock value */ + result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); + if (result == 0) { + sclk_setting->Fcw_int = dividers.usSclk_fcw_int; + sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; + sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; + sclk_setting->PllRange = dividers.ucSclkPllRange; + sclk_setting->Sclk_slew_rate = 0x400; + sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; + sclk_setting->Pcc_down_slew_rate = 0xffff; + sclk_setting->SSc_En = dividers.ucSscEnable; + sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; + sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; + sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac; + return result; + } + + ref_clock = polaris10_get_xclk(hwmgr); + + for (i = 0; i < NUM_SCLK_RANGE; i++) { + if (clock > data->range_table[i].trans_lower_frequency + && clock <= data->range_table[i].trans_upper_frequency) { + sclk_setting->PllRange = i; + break; + } + } + + sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); + temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; + temp <<= 0x10; + sclk_setting->Fcw_frac = (uint16_t)(0xFFFF & (temp / ref_clock)); + + pcc_target_percent = 10; /* Hardcode 10% for now. */ + pcc_target_freq = clock - (clock * pcc_target_percent / 100); + sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); + + ss_target_percent = 2; /* Hardcode 2% for now. */ + sclk_setting->SSc_En = 0; + if (ss_target_percent) { + sclk_setting->SSc_En = 1; + ss_target_freq = clock - (clock * ss_target_percent / 100); + sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); + temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; + temp <<= 0x10; + sclk_setting->Fcw1_frac = (uint16_t)(0xFFFF & (temp / ref_clock)); + } + + return 0; +} + +static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, + struct phm_ppt_v1_clock_voltage_dependency_table *dep_table, + uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) +{ + uint32_t i; + uint16_t vddci; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + *voltage = *mvdd = 0; + + /* clock - voltage dependency table is empty table */ + if (dep_table->count == 0) + return -EINVAL; + + for (i = 0; i < dep_table->count; i++) { + /* find first sclk bigger than request */ + if (dep_table->entries[i].clk >= clock) { + *voltage |= (dep_table->entries[i].vddc * + VOLTAGE_SCALE) << VDDC_SHIFT; + if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control) + *voltage |= (data->vbios_boot_state.vddci_bootup_value * + VOLTAGE_SCALE) << VDDCI_SHIFT; + else if (dep_table->entries[i].vddci) + *voltage |= (dep_table->entries[i].vddci * + VOLTAGE_SCALE) << VDDCI_SHIFT; + else { + vddci = phm_find_closest_vddci(&(data->vddci_voltage_table), + (dep_table->entries[i].vddc - + (uint16_t)data->vddc_vddci_delta)); + *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; + } + + if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) + *mvdd = data->vbios_boot_state.mvdd_bootup_value * + VOLTAGE_SCALE; + else if (dep_table->entries[i].mvdd) + *mvdd = (uint32_t) dep_table->entries[i].mvdd * + VOLTAGE_SCALE; + + *voltage |= 1 << PHASES_SHIFT; + return 0; + } + } + + /* sclk is bigger than max sclk in the dependence table */ + *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; + + if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control) + *voltage |= (data->vbios_boot_state.vddci_bootup_value * + VOLTAGE_SCALE) << VDDCI_SHIFT; + else if (dep_table->entries[i-1].vddci) { + vddci = phm_find_closest_vddci(&(data->vddci_voltage_table), + (dep_table->entries[i].vddc - + (uint16_t)data->vddc_vddci_delta)); + *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; + } + + if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) + *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE; + else if (dep_table->entries[i].mvdd) + *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE; + + return 0; +} + +sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = { {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112}, + {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160}, + {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112}, + {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160}, + {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112}, + {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160}, + {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108}, + {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} }; + +static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr) +{ + uint32_t i, ref_clk; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + SMU74_Discrete_DpmTable *table = &(data->smc_state_table); + struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } }; + + ref_clk = polaris10_get_xclk(hwmgr); + + if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) { + for (i = 0; i < NUM_SCLK_RANGE; i++) { + table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting; + table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv; + table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc; + + table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper; + table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower; + + CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc); + CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper); + CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower); + } + return; + } + + for (i = 0; i < NUM_SCLK_RANGE; i++) { + + data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; + data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; + + table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting; + table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; + table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc; + + table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper; + table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower; + + CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc); + CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper); + CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower); + } +} + +/** +* Populates single SMC SCLK structure using the provided engine clock +* +* @param hwmgr the address of the hardware manager +* @param clock the engine clock to use to populate the structure +* @param sclk the SMC SCLK structure to be populated +*/ + +static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr, + uint32_t clock, uint16_t sclk_al_threshold, + struct SMU74_Discrete_GraphicsLevel *level) +{ + int result, i, temp; + /* PP_Clocks minClocks; */ + uint32_t mvdd; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + SMU_SclkSetting curr_sclk_setting = { 0 }; + + result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting); + + /* populate graphics levels */ + result = polaris10_get_dependency_volt_by_clk(hwmgr, + table_info->vdd_dep_on_sclk, clock, + &level->MinVoltage, &mvdd); + + PP_ASSERT_WITH_CODE((0 == result), + "can not find VDDC voltage value for " + "VDDC engine clock dependency table", + return result); + level->ActivityLevel = sclk_al_threshold; + + level->CcPwrDynRm = 0; + level->CcPwrDynRm1 = 0; + level->EnabledForActivity = 0; + level->EnabledForThrottle = 1; + level->UpHyst = 10; + level->DownHyst = 0; + level->VoltageDownHyst = 0; + level->PowerThrottle = 0; + + /* + * TODO: get minimum clocks from dal configaration + * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks); + */ + /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */ + + /* get level->DeepSleepDivId + if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) + level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR); + */ + PP_ASSERT_WITH_CODE((clock >= 2500), "Engine clock can't satisfy stutter requirement!", return 0); + for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { + temp = clock / (1UL << i); + + if (temp >= 2500 || i == 0) + break; + } + + level->DeepSleepDivId = i; + + /* Default to slow, highest DPM level will be + * set to PPSMC_DISPLAY_WATERMARK_LOW later. + */ + if (data->update_up_hyst) + level->UpHyst = (uint8_t)data->up_hyst; + if (data->update_down_hyst) + level->DownHyst = (uint8_t)data->down_hyst; + + level->SclkSetting = curr_sclk_setting; + + CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage); + CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm); + CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1); + CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel); + CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac); + CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate); + return 0; +} + +/** +* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states +* +* @param hwmgr the address of the hardware manager +*/ +static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_dpm_table *dpm_table = &data->dpm_table; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; + uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count; + int result = 0; + uint32_t array = data->dpm_table_start + + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); + uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) * + SMU74_MAX_LEVELS_GRAPHICS; + struct SMU74_Discrete_GraphicsLevel *levels = + data->smc_state_table.GraphicsLevel; + uint32_t i, max_entry; + uint8_t hightest_pcie_level_enabled = 0, + lowest_pcie_level_enabled = 0, + mid_pcie_level_enabled = 0, + count = 0; + + polaris10_get_sclk_range_table(hwmgr); + + for (i = 0; i < dpm_table->sclk_table.count; i++) { + + result = polaris10_populate_single_graphic_level(hwmgr, + dpm_table->sclk_table.dpm_levels[i].value, + (uint16_t)data->activity_target[i], + &(data->smc_state_table.GraphicsLevel[i])); + if (result) + return result; + + /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ + if (i > 1) + levels[i].DeepSleepDivId = 0; + } + + data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; + data->smc_state_table.GraphicsDpmLevelCount = + (uint8_t)dpm_table->sclk_table.count; + data->dpm_level_enable_mask.sclk_dpm_enable_mask = + phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); + + + if (pcie_table != NULL) { + PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt), + "There must be 1 or more PCIE levels defined in PPTable.", + return -EINVAL); + max_entry = pcie_entry_cnt - 1; + for (i = 0; i < dpm_table->sclk_table.count; i++) + levels[i].pcieDpmLevel = + (uint8_t) ((i < max_entry) ? i : max_entry); + } else { + while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && + ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & + (1 << (hightest_pcie_level_enabled + 1))) != 0)) + hightest_pcie_level_enabled++; + + while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && + ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & + (1 << lowest_pcie_level_enabled)) == 0)) + lowest_pcie_level_enabled++; + + while ((count < hightest_pcie_level_enabled) && + ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & + (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) + count++; + + mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) < + hightest_pcie_level_enabled ? + (lowest_pcie_level_enabled + 1 + count) : + hightest_pcie_level_enabled; + + /* set pcieDpmLevel to hightest_pcie_level_enabled */ + for (i = 2; i < dpm_table->sclk_table.count; i++) + levels[i].pcieDpmLevel = hightest_pcie_level_enabled; + + /* set pcieDpmLevel to lowest_pcie_level_enabled */ + levels[0].pcieDpmLevel = lowest_pcie_level_enabled; + + /* set pcieDpmLevel to mid_pcie_level_enabled */ + levels[1].pcieDpmLevel = mid_pcie_level_enabled; + } + /* level count will send to smc once at init smc table and never change */ + result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, + (uint32_t)array_size, data->sram_end); + + return result; +} + +static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr, + uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + int result = 0; + struct cgs_display_info info = {0, 0, NULL}; + + cgs_get_active_displays_info(hwmgr->device, &info); + + if (table_info->vdd_dep_on_mclk) { + result = polaris10_get_dependency_volt_by_clk(hwmgr, + table_info->vdd_dep_on_mclk, clock, + &mem_level->MinVoltage, &mem_level->MinMvdd); + PP_ASSERT_WITH_CODE((0 == result), + "can not find MinVddc voltage value from memory " + "VDDC voltage dependency table", return result); + } + + mem_level->MclkFrequency = clock; + mem_level->StutterEnable = 0; + mem_level->EnabledForThrottle = 1; + mem_level->EnabledForActivity = 0; + mem_level->UpHyst = 0; + mem_level->DownHyst = 100; + mem_level->VoltageDownHyst = 0; + mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target; + mem_level->StutterEnable = false; + + mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; + + data->display_timing.num_existing_displays = info.display_count; + + if ((data->mclk_stutter_mode_threshold) && + (clock <= data->mclk_stutter_mode_threshold) && + (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, + STUTTER_ENABLE) & 0x1)) + mem_level->StutterEnable = true; + + if (!result) { + CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd); + CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency); + CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel); + CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage); + } + return result; +} + +/** +* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states +* +* @param hwmgr the address of the hardware manager +*/ +static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_dpm_table *dpm_table = &data->dpm_table; + int result; + /* populate MCLK dpm table to SMU7 */ + uint32_t array = data->dpm_table_start + + offsetof(SMU74_Discrete_DpmTable, MemoryLevel); + uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) * + SMU74_MAX_LEVELS_MEMORY; + struct SMU74_Discrete_MemoryLevel *levels = + data->smc_state_table.MemoryLevel; + uint32_t i; + + for (i = 0; i < dpm_table->mclk_table.count; i++) { + PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), + "can not populate memory level as memory clock is zero", + return -EINVAL); + result = polaris10_populate_single_memory_level(hwmgr, + dpm_table->mclk_table.dpm_levels[i].value, + &levels[i]); + if (result) + return result; + } + + /* Only enable level 0 for now. */ + levels[0].EnabledForActivity = 1; + + /* in order to prevent MC activity from stutter mode to push DPM up. + * the UVD change complements this by putting the MCLK in + * a higher state by default such that we are not effected by + * up threshold or and MCLK DPM latency. + */ + levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target; + CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel); + + data->smc_state_table.MemoryDpmLevelCount = + (uint8_t)dpm_table->mclk_table.count; + data->dpm_level_enable_mask.mclk_dpm_enable_mask = + phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); + /* set highest level watermark to high */ + levels[dpm_table->mclk_table.count - 1].DisplayWatermark = + PPSMC_DISPLAY_WATERMARK_HIGH; + + /* level count will send to smc once at init smc table and never change */ + result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, + (uint32_t)array_size, data->sram_end); + + return result; +} + +/** +* Populates the SMC MVDD structure using the provided memory clock. +* +* @param hwmgr the address of the hardware manager +* @param mclk the MCLK value to be used in the decision if MVDD should be high or low. +* @param voltage the SMC VOLTAGE structure to be populated +*/ +int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr, + uint32_t mclk, SMIO_Pattern *smio_pat) +{ + const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + uint32_t i = 0; + + if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) { + /* find mvdd value which clock is more than request */ + for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) { + if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) { + smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value; + break; + } + } + PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count, + "MVDD Voltage is outside the supported range.", + return -EINVAL); + } else + return -EINVAL; + + return 0; +} + +static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, + SMU74_Discrete_DpmTable *table) +{ + int result = 0; + uint32_t sclk_frequency; + const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + SMIO_Pattern vol_level; + uint32_t mvdd; + uint16_t us_mvdd; + + table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; + + if (!data->sclk_dpm_key_disabled) { + /* Get MinVoltage and Frequency from DPM0, + * already converted to SMC_UL */ + sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value; + result = polaris10_get_dependency_volt_by_clk(hwmgr, + table_info->vdd_dep_on_sclk, + table->ACPILevel.SclkFrequency, + &table->ACPILevel.MinVoltage, &mvdd); + PP_ASSERT_WITH_CODE((0 == result), + "Cannot find ACPI VDDC voltage value " + "in Clock Dependency Table", ); + } else { + sclk_frequency = data->vbios_boot_state.sclk_bootup_value; + table->ACPILevel.MinVoltage = + data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE; + } + + result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting)); + PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result); + + table->ACPILevel.DeepSleepDivId = 0; + table->ACPILevel.CcPwrDynRm = 0; + table->ACPILevel.CcPwrDynRm1 = 0; + + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage); + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); + + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac); + CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate); + + if (!data->mclk_dpm_key_disabled) { + /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */ + table->MemoryACPILevel.MclkFrequency = + data->dpm_table.mclk_table.dpm_levels[0].value; + result = polaris10_get_dependency_volt_by_clk(hwmgr, + table_info->vdd_dep_on_mclk, + table->MemoryACPILevel.MclkFrequency, + &table->MemoryACPILevel.MinVoltage, &mvdd); + PP_ASSERT_WITH_CODE((0 == result), + "Cannot find ACPI VDDCI voltage value " + "in Clock Dependency Table", + ); + } else { + table->MemoryACPILevel.MclkFrequency = + data->vbios_boot_state.mclk_bootup_value; + table->MemoryACPILevel.MinVoltage = + data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE; + } + + us_mvdd = 0; + if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) || + (data->mclk_dpm_key_disabled)) + us_mvdd = data->vbios_boot_state.mvdd_bootup_value; + else { + if (!polaris10_populate_mvdd_value(hwmgr, + data->dpm_table.mclk_table.dpm_levels[0].value, + &vol_level)) + us_mvdd = vol_level.Voltage; + } + + if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level)) + table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage); + else + table->MemoryACPILevel.MinMvdd = 0; + + table->MemoryACPILevel.StutterEnable = false; + + table->MemoryACPILevel.EnabledForThrottle = 0; + table->MemoryACPILevel.EnabledForActivity = 0; + table->MemoryACPILevel.UpHyst = 0; + table->MemoryACPILevel.DownHyst = 100; + table->MemoryACPILevel.VoltageDownHyst = 0; + table->MemoryACPILevel.ActivityLevel = + PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target); + + CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency); + CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage); + + return result; +} + +static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr, + SMU74_Discrete_DpmTable *table) +{ + int result = -EINVAL; + uint8_t count; + struct pp_atomctrl_clock_dividers_vi dividers; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = + table_info->mm_dep_table; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + table->VceLevelCount = (uint8_t)(mm_table->count); + table->VceBootLevel = 0; + + for (count = 0; count < table->VceLevelCount; count++) { + table->VceLevel[count].Frequency = mm_table->entries[count].eclk; + table->VceLevel[count].MinVoltage |= + (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; + table->VceLevel[count].MinVoltage |= + ((mm_table->entries[count].vddc - data->vddc_vddci_delta) * + VOLTAGE_SCALE) << VDDCI_SHIFT; + table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT; + + /*retrieve divider value for VBIOS */ + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, + table->VceLevel[count].Frequency, ÷rs); + PP_ASSERT_WITH_CODE((0 == result), + "can not find divide id for VCE engine clock", + return result); + + table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; + + CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); + CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage); + } + return result; +} + +static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr, + SMU74_Discrete_DpmTable *table) +{ + int result = -EINVAL; + uint8_t count; + struct pp_atomctrl_clock_dividers_vi dividers; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = + table_info->mm_dep_table; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + table->SamuBootLevel = 0; + table->SamuLevelCount = (uint8_t)(mm_table->count); + + for (count = 0; count < table->SamuLevelCount; count++) { + /* not sure whether we need evclk or not */ + table->SamuLevel[count].Frequency = mm_table->entries[count].samclock; + table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc * + VOLTAGE_SCALE) << VDDC_SHIFT; + table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc - + data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT; + table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT; + + /* retrieve divider value for VBIOS */ + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, + table->SamuLevel[count].Frequency, ÷rs); + PP_ASSERT_WITH_CODE((0 == result), + "can not find divide id for samu clock", return result); + + table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider; + + CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency); + CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage); + } + return result; +} + +static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, + int32_t eng_clock, int32_t mem_clock, + SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs) +{ + uint32_t dram_timing; + uint32_t dram_timing2; + uint32_t burst_time; + int result; + + result = atomctrl_set_engine_dram_timings_rv770(hwmgr, + eng_clock, mem_clock); + PP_ASSERT_WITH_CODE(result == 0, + "Error calling VBIOS to set DRAM_TIMING.", return result); + + dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); + dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); + burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); + + + arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); + arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); + arb_regs->McArbBurstTime = (uint8_t)burst_time; + + return 0; +} + +static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct SMU74_Discrete_MCArbDramTimingTable arb_regs; + uint32_t i, j; + int result = 0; + + for (i = 0; i < data->dpm_table.sclk_table.count; i++) { + for (j = 0; j < data->dpm_table.mclk_table.count; j++) { + result = polaris10_populate_memory_timing_parameters(hwmgr, + data->dpm_table.sclk_table.dpm_levels[i].value, + data->dpm_table.mclk_table.dpm_levels[j].value, + &arb_regs.entries[i][j]); + if (result == 0) + result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j); + if (result != 0) + return result; + } + } + + result = polaris10_copy_bytes_to_smc( + hwmgr->smumgr, + data->arb_table_start, + (uint8_t *)&arb_regs, + sizeof(SMU74_Discrete_MCArbDramTimingTable), + data->sram_end); + return result; +} + +static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + int result = -EINVAL; + uint8_t count; + struct pp_atomctrl_clock_dividers_vi dividers; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = + table_info->mm_dep_table; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + table->UvdLevelCount = (uint8_t)(mm_table->count); + table->UvdBootLevel = 0; + + for (count = 0; count < table->UvdLevelCount; count++) { + table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; + table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; + table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc * + VOLTAGE_SCALE) << VDDC_SHIFT; + table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc - + data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT; + table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT; + + /* retrieve divider value for VBIOS */ + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, + table->UvdLevel[count].VclkFrequency, ÷rs); + PP_ASSERT_WITH_CODE((0 == result), + "can not find divide id for Vclk clock", return result); + + table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; + + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, + table->UvdLevel[count].DclkFrequency, ÷rs); + PP_ASSERT_WITH_CODE((0 == result), + "can not find divide id for Dclk clock", return result); + + table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; + + CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); + CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); + CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage); + + } + return result; +} + +static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + int result = 0; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + table->GraphicsBootLevel = 0; + table->MemoryBootLevel = 0; + + /* find boot level from dpm table */ + result = phm_find_boot_level(&(data->dpm_table.sclk_table), + data->vbios_boot_state.sclk_bootup_value, + (uint32_t *)&(table->GraphicsBootLevel)); + + result = phm_find_boot_level(&(data->dpm_table.mclk_table), + data->vbios_boot_state.mclk_bootup_value, + (uint32_t *)&(table->MemoryBootLevel)); + + table->BootVddc = data->vbios_boot_state.vddc_bootup_value * + VOLTAGE_SCALE; + table->BootVddci = data->vbios_boot_state.vddci_bootup_value * + VOLTAGE_SCALE; + table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value * + VOLTAGE_SCALE; + + CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc); + CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci); + CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd); + + return 0; +} + + +static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + uint8_t count, level; + + count = (uint8_t)(table_info->vdd_dep_on_sclk->count); + + for (level = 0; level < count; level++) { + if (table_info->vdd_dep_on_sclk->entries[level].clk >= + data->vbios_boot_state.sclk_bootup_value) { + data->smc_state_table.GraphicsBootLevel = level; + break; + } + } + + count = (uint8_t)(table_info->vdd_dep_on_mclk->count); + for (level = 0; level < count; level++) { + if (table_info->vdd_dep_on_mclk->entries[level].clk >= + data->vbios_boot_state.mclk_bootup_value) { + data->smc_state_table.MemoryBootLevel = level; + break; + } + } + + return 0; +} + +static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) +{ + uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks, + volt_with_cks, value; + uint16_t clock_freq_u16; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2, + volt_offset = 0; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = + table_info->vdd_dep_on_sclk; + + stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount; + + /* Read SMU_Eefuse to read and calculate RO and determine + * if the part is SS or FF. if RO >= 1660MHz, part is FF. + */ + efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixSMU_EFUSE_0 + (146 * 4)); + efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixSMU_EFUSE_0 + (148 * 4)); + efuse &= 0xFF000000; + efuse = efuse >> 24; + efuse2 &= 0xF; + + if (efuse2 == 1) + ro = (2300 - 1350) * efuse / 255 + 1350; + else + ro = (2500 - 1000) * efuse / 255 + 1000; + + if (ro >= 1660) + type = 0; + else + type = 1; + + /* Populate Stretch amount */ + data->smc_state_table.ClockStretcherAmount = stretch_amount; + + /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */ + for (i = 0; i < sclk_table->count; i++) { + data->smc_state_table.Sclk_CKS_masterEn0_7 |= + sclk_table->entries[i].cks_enable << i; + volt_without_cks = (uint32_t)((14041 * + (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 / + (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000))); + volt_with_cks = (uint32_t)((13946 * + (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 / + (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000))); + if (volt_without_cks >= volt_with_cks) + volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks + + sclk_table->entries[i].cks_voffset) * 100 / 625) + 1); + data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; + } + + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, + STRETCH_ENABLE, 0x0); + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, + masterReset, 0x1); + /* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, + masterReset, 0x0); + + /* Populate CKS Lookup Table */ + if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5) + stretch_amount2 = 0; + else if (stretch_amount == 3 || stretch_amount == 4) + stretch_amount2 = 1; + else { + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ClockStretcher); + PP_ASSERT_WITH_CODE(false, + "Stretch Amount in PPTable not supported\n", + return -EINVAL); + } + + value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixPWR_CKS_CNTL); + value &= 0xFFC2FF87; + data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq = + polaris10_clock_stretcher_lookup_table[stretch_amount2][0]; + data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq = + polaris10_clock_stretcher_lookup_table[stretch_amount2][1]; + clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table. + GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100); + if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16 + && polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) { + /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */ + value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16; + /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */ + value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18; + /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */ + value |= (polaris10_clock_stretch_amount_conversion + [polaris10_clock_stretcher_lookup_table[stretch_amount2][3]] + [stretch_amount]) << 3; + } + CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq); + CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq); + data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting = + polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F; + data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |= + (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7; + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixPWR_CKS_CNTL, value); + + /* Populate DDT Lookup Table */ + for (i = 0; i < 4; i++) { + /* Assign the minimum and maximum VID stored + * in the last row of Clock Stretcher Voltage Table. + */ + data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID = + (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2]; + data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID = + (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3]; + /* Loop through each SCLK and check the frequency + * to see if it lies within the frequency for clock stretcher. + */ + for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) { + cks_setting = 0; + clock_freq = PP_SMC_TO_HOST_UL( + data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency); + /* Check the allowed frequency against the sclk level[j]. + * Sclk's endianness has already been converted, + * and it's in 10Khz unit, + * as opposed to Data table, which is in Mhz unit. + */ + if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) { + cks_setting |= 0x2; + if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100) + cks_setting |= 0x1; + } + data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting + |= cks_setting << (j * 2); + } + CONVERT_FROM_HOST_TO_SMC_US( + data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting); + } + + value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL); + value &= 0xFFFFFFFE; + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value); + + return 0; +} + +/** +* Populates the SMC VRConfig field in DPM table. +* +* @param hwmgr the address of the hardware manager +* @param table the SMC DPM table structure to be populated +* @return always 0 +*/ +static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr, + struct SMU74_Discrete_DpmTable *table) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint16_t config; + + config = VR_MERGED_WITH_VDDC; + table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT); + + /* Set Vddc Voltage Controller */ + if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { + config = VR_SVI2_PLANE_1; + table->VRConfig |= config; + } else { + PP_ASSERT_WITH_CODE(false, + "VDDC should be on SVI2 control in merged mode!", + ); + } + /* Set Vddci Voltage Controller */ + if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { + config = VR_SVI2_PLANE_2; /* only in merged mode */ + table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); + } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { + config = VR_SMIO_PATTERN_1; + table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); + } else { + config = VR_STATIC_VOLTAGE; + table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); + } + /* Set Mvdd Voltage Controller */ + if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { + config = VR_SVI2_PLANE_2; + table->VRConfig |= (config << VRCONF_MVDD_SHIFT); + } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { + config = VR_SMIO_PATTERN_2; + table->VRConfig |= (config << VRCONF_MVDD_SHIFT); + } else { + config = VR_STATIC_VOLTAGE; + table->VRConfig |= (config << VRCONF_MVDD_SHIFT); + } + + return 0; +} + +/** +* Initializes the SMC table and uploads it +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr) +{ + int result; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table); + const struct polaris10_ulv_parm *ulv = &(data->ulv); + uint8_t i; + struct pp_atomctrl_gpio_pin_assignment gpio_pin; + pp_atomctrl_clock_dividers_vi dividers; + + result = polaris10_setup_default_dpm_tables(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to setup default DPM tables!", return result); + + if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control) + polaris10_populate_smc_voltage_tables(hwmgr, table); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_AutomaticDCTransition)) + table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_StepVddc)) + table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; + + if (data->is_memory_gddr5) + table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; + + if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) { + result = polaris10_populate_ulv_state(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize ULV state!", return result); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT); + } + + result = polaris10_populate_smc_link_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize Link Level!", return result); + + result = polaris10_populate_all_graphic_levels(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize Graphics Level!", return result); + + result = polaris10_populate_all_memory_levels(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize Memory Level!", return result); + + result = polaris10_populate_smc_acpi_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize ACPI Level!", return result); + + result = polaris10_populate_smc_vce_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize VCE Level!", return result); + + result = polaris10_populate_smc_samu_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize SAMU Level!", return result); + + /* Since only the initial state is completely set up at this point + * (the other states are just copies of the boot state) we only + * need to populate the ARB settings for the initial state. + */ + result = polaris10_program_memory_timing_parameters(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to Write ARB settings for the initial state.", return result); + + result = polaris10_populate_smc_uvd_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize UVD Level!", return result); + + result = polaris10_populate_smc_boot_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize Boot Level!", return result); + + result = polaris10_populate_smc_initailial_state(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize Boot State!", return result); + + result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to populate BAPM Parameters!", return result); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ClockStretcher)) { + result = polaris10_populate_clock_stretcher_data_table(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to populate Clock Stretcher Data Table!", + return result); + } + + table->GraphicsVoltageChangeEnable = 1; + table->GraphicsThermThrottleEnable = 1; + table->GraphicsInterval = 1; + table->VoltageInterval = 1; + table->ThermalInterval = 1; + table->TemperatureLimitHigh = + table_info->cac_dtp_table->usTargetOperatingTemp * + POLARIS10_Q88_FORMAT_CONVERSION_UNIT; + table->TemperatureLimitLow = + (table_info->cac_dtp_table->usTargetOperatingTemp - 1) * + POLARIS10_Q88_FORMAT_CONVERSION_UNIT; + table->MemoryVoltageChangeEnable = 1; + table->MemoryInterval = 1; + table->VoltageResponseTime = 0; + table->PhaseResponseTime = 0; + table->MemoryThermThrottleEnable = 1; + table->PCIeBootLinkLevel = 0; + table->PCIeGenInterval = 1; + + result = polaris10_populate_vr_config(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to populate VRConfig setting!", return result); + + table->ThermGpio = 17; + table->SclkStepSize = 0x4000; + + if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) { + table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift; + } else { + table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN; + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_RegulatorHot); + } + + if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID, + &gpio_pin)) { + table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift; + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_AutomaticDCTransition); + } else { + table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN; + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_AutomaticDCTransition); + } + + /* Thermal Output GPIO */ + if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID, + &gpio_pin)) { + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ThermalOutGPIO); + + table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift; + + /* For porlarity read GPIOPAD_A with assigned Gpio pin + * since VBIOS will program this register to set 'inactive state', + * driver can then determine 'active state' from this and + * program SMU with correct polarity + */ + table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) + & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0; + table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY; + + /* if required, combine VRHot/PCC with thermal out GPIO */ + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot) + && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal)) + table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT; + } else { + table->ThermOutGpio = 17; + table->ThermOutPolarity = 1; + table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE; + } + + /* Populate BIF_SCLK levels into SMC DPM table */ + for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) { + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], ÷rs); + PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result); + + if (i == 0) + table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider)); + else + table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider)); + } + + for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++) + table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]); + + CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); + CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig); + CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1); + CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2); + CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); + CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); + CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); + CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); + CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); + + /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ + result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, + data->dpm_table_start + + offsetof(SMU74_Discrete_DpmTable, SystemFlags), + (uint8_t *)&(table->SystemFlags), + sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController), + data->sram_end); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to upload dpm data to SMC memory!", return result); + + return 0; +} + +/** +* Initialize the ARB DRAM timing table's index field. +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr) +{ + const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t tmp; + int result; + + /* This is a read-modify-write on the first byte of the ARB table. + * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure + * is the field 'current'. + * This solution is ugly, but we never write the whole table only + * individual fields in it. + * In reality this field should not be in that structure + * but in a soft register. + */ + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, + data->arb_table_start, &tmp, data->sram_end); + + if (result) + return result; + + tmp &= 0x00FFFFFF; + tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; + + return polaris10_write_smc_sram_dword(hwmgr->smumgr, + data->arb_table_start, tmp, data->sram_end); +} + +static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) +{ + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_RegulatorHot)) + return smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_EnableVRHotGPIOInterrupt); + + return 0; +} + +static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr) +{ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, + SCLK_PWRMGT_OFF, 0); + return 0; +} + +static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_ulv_parm *ulv = &(data->ulv); + + if (ulv->ulv_supported) + return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV); + + return 0; +} + +static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) +{ + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkDeepSleep)) { + if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON)) + PP_ASSERT_WITH_CODE(false, + "Attempt to enable Master Deep Sleep switch failed!", + return -1); + } else { + if (smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_MASTER_DeepSleep_OFF)) { + PP_ASSERT_WITH_CODE(false, + "Attempt to disable Master Deep Sleep switch failed!", + return -1); + } + } + + return 0; +} + +static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + /* enable SCLK dpm */ + if (!data->sclk_dpm_key_disabled) + PP_ASSERT_WITH_CODE( + (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)), + "Failed to enable SCLK DPM during DPM Start Function!", + return -1); + + /* enable MCLK dpm */ + if (0 == data->mclk_dpm_key_disabled) { + + PP_ASSERT_WITH_CODE( + (0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_MCLKDPM_Enable)), + "Failed to enable MCLK DPM during DPM Start Function!", + return -1); + + + PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005); + udelay(10); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005); + } + + return 0; +} + +static int polaris10_start_dpm(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + /*enable general power management */ + + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, + GLOBAL_PWRMGT_EN, 1); + + /* enable sclk deep sleep */ + + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, + DYNAMIC_PM_EN, 1); + + /* prepare for PCIE DPM */ + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + data->soft_regs_start + offsetof(SMU74_SoftRegisters, + VoltageChangeTimeout), 0x1000); + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, + SWRST_COMMAND_1, RESETLC, 0x0); +/* + PP_ASSERT_WITH_CODE( + (0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_Voltage_Cntl_Enable)), + "Failed to enable voltage DPM during DPM Start Function!", + return -1); +*/ + + if (polaris10_enable_sclk_mclk_dpm(hwmgr)) { + printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!"); + return -1; + } + + /* enable PCIE dpm */ + if (0 == data->pcie_dpm_key_disabled) { + PP_ASSERT_WITH_CODE( + (0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_PCIeDPM_Enable)), + "Failed to enable pcie DPM during DPM Start Function!", + return -1); + } + + PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_EnableACDCGPIOInterrupt)), + "Failed to enable AC DC GPIO Interrupt!", + ); + + return 0; +} + +static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources) +{ + bool protection; + enum DPM_EVENT_SRC src; + + switch (sources) { + default: + printk(KERN_ERR "Unknown throttling event sources."); + /* fall through */ + case 0: + protection = false; + /* src is unused */ + break; + case (1 << PHM_AutoThrottleSource_Thermal): + protection = true; + src = DPM_EVENT_SRC_DIGITAL; + break; + case (1 << PHM_AutoThrottleSource_External): + protection = true; + src = DPM_EVENT_SRC_EXTERNAL; + break; + case (1 << PHM_AutoThrottleSource_External) | + (1 << PHM_AutoThrottleSource_Thermal): + protection = true; + src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL; + break; + } + /* Order matters - don't enable thermal protection for the wrong source. */ + if (protection) { + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL, + DPM_EVENT_SRC, src); + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, + THERMAL_PROTECTION_DIS, + phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ThermalController)); + } else + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, + THERMAL_PROTECTION_DIS, 1); +} + +static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, + PHM_AutoThrottleSource source) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (!(data->active_auto_throttle_sources & (1 << source))) { + data->active_auto_throttle_sources |= 1 << source; + polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); + } + return 0; +} + +static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) +{ + return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); +} + +int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + data->pcie_performance_request = true; + + return 0; +} + +int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) +{ + int tmp_result, result = 0; + tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1; + PP_ASSERT_WITH_CODE(result == 0, + "DPM is already running right now, no need to enable DPM!", + return 0); + + if (polaris10_voltage_control(hwmgr)) { + tmp_result = polaris10_enable_voltage_control(hwmgr); + PP_ASSERT_WITH_CODE(tmp_result == 0, + "Failed to enable voltage control!", + result = tmp_result); + + tmp_result = polaris10_construct_voltage_tables(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to contruct voltage tables!", + result = tmp_result); + } + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EngineSpreadSpectrumSupport)) + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ThermalController)) + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0); + + tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to program static screen threshold parameters!", + result = tmp_result); + + tmp_result = polaris10_enable_display_gap(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable display gap!", result = tmp_result); + + tmp_result = polaris10_program_voting_clients(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to program voting clients!", result = tmp_result); + + tmp_result = polaris10_process_firmware_header(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to process firmware header!", result = tmp_result); + + tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to initialize switch from ArbF0 to F1!", + result = tmp_result); + + tmp_result = polaris10_init_smc_table(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to initialize SMC table!", result = tmp_result); + + tmp_result = polaris10_init_arb_table_index(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to initialize ARB table index!", result = tmp_result); + + tmp_result = polaris10_populate_pm_fuses(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to populate PM fuses!", result = tmp_result); + + tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable VR hot GPIO interrupt!", result = tmp_result); + + tmp_result = polaris10_enable_sclk_control(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable SCLK control!", result = tmp_result); + + tmp_result = polaris10_enable_smc_voltage_controller(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable voltage control!", result = tmp_result); + + tmp_result = polaris10_enable_ulv(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable ULV!", result = tmp_result); + + tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable deep sleep master switch!", result = tmp_result); + + tmp_result = polaris10_start_dpm(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to start DPM!", result = tmp_result); + + tmp_result = polaris10_enable_smc_cac(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable SMC CAC!", result = tmp_result); + + tmp_result = polaris10_enable_power_containment(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable power containment!", result = tmp_result); + + tmp_result = polaris10_power_control_set_level(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to power control set level!", result = tmp_result); + + tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable thermal auto throttle!", result = tmp_result); + + tmp_result = polaris10_pcie_performance_request(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable thermal auto throttle!", result = tmp_result); + + return result; +} + +int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) +{ + + return 0; +} + +int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr) +{ + + return 0; +} + +int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) +{ + return phm_hwmgr_backend_fini(hwmgr); +} + +int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkDeepSleep); + + if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE) + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EnableMVDDControl); + + if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE) + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ControlVDDCI); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_TablelessHardwareInterface); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EnableSMU7ThermalManagement); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DynamicPowerManagement); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_TablelessHardwareInterface); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SMC); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_NonABMSupportInPPLib); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DynamicUVDState); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkThrottleLowNotification); + + /* power tune caps Assume disabled */ + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PowerContainment); + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_CAC); + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SQRamping); + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DBRamping); + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_TDRamping); + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_TCPRamping); + + return 0; +} + +static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + polaris10_initialize_power_tune_defaults(hwmgr); + + data->pcie_gen_performance.max = PP_PCIEGen1; + data->pcie_gen_performance.min = PP_PCIEGen3; + data->pcie_gen_power_saving.max = PP_PCIEGen1; + data->pcie_gen_power_saving.min = PP_PCIEGen3; + data->pcie_lane_performance.max = 0; + data->pcie_lane_performance.min = 16; + data->pcie_lane_power_saving.max = 0; + data->pcie_lane_power_saving.min = 16; +} + +/** +* Get Leakage VDDC based on leakage ID. +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always 0 +*/ +static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint16_t vv_id; + uint16_t vddc = 0; + uint16_t i, j; + uint32_t sclk = 0; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)hwmgr->pptable; + struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = + table_info->vdd_dep_on_sclk; + int result; + + for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) { + vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; + if (!phm_get_sclk_for_voltage_evv(hwmgr, + table_info->vddc_lookup_table, vv_id, &sclk)) { + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ClockStretcher)) { + for (j = 1; j < sclk_table->count; j++) { + if (sclk_table->entries[j].clk == sclk && + sclk_table->entries[j].cks_enable == 0) { + sclk += 5000; + break; + } + } + } + + + PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, + VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc), + "Error retrieving EVV voltage value!", + continue); + + + /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ + PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0), + "Invalid VDDC value", result = -EINVAL;); + + /* the voltage should not be zero nor equal to leakage ID */ + if (vddc != 0 && vddc != vv_id) { + data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100); + data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id; + data->vddc_leakage.count++; + } + } + } + + return 0; +} + +/** + * Change virtual leakage voltage to actual value. + * + * @param hwmgr the address of the powerplay hardware manager. + * @param pointer to changing voltage + * @param pointer to leakage table + */ +static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, + uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table) +{ + uint32_t index; + + /* search for leakage voltage ID 0xff01 ~ 0xff08 */ + for (index = 0; index < leakage_table->count; index++) { + /* if this voltage matches a leakage voltage ID */ + /* patch with actual leakage voltage */ + if (leakage_table->leakage_id[index] == *voltage) { + *voltage = leakage_table->actual_voltage[index]; + break; + } + } + + if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) + printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n"); +} + +/** +* Patch voltage lookup table by EVV leakages. +* +* @param hwmgr the address of the powerplay hardware manager. +* @param pointer to voltage lookup table +* @param pointer to leakage table +* @return always 0 +*/ +static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, + phm_ppt_v1_voltage_lookup_table *lookup_table, + struct polaris10_leakage_voltage *leakage_table) +{ + uint32_t i; + + for (i = 0; i < lookup_table->count; i++) + polaris10_patch_with_vdd_leakage(hwmgr, + &lookup_table->entries[i].us_vdd, leakage_table); + + return 0; +} + +static int polaris10_patch_clock_voltage_limits_with_vddc_leakage( + struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table, + uint16_t *vddc) +{ + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); + hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = + table_info->max_clock_voltage_on_dc.vddc; + return 0; +} + +static int polaris10_patch_voltage_dependency_tables_with_lookup_table( + struct pp_hwmgr *hwmgr) +{ + uint8_t entryId; + uint8_t voltageId; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = + table_info->vdd_dep_on_sclk; + struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = + table_info->vdd_dep_on_mclk; + struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = + table_info->mm_dep_table; + + for (entryId = 0; entryId < sclk_table->count; ++entryId) { + voltageId = sclk_table->entries[entryId].vddInd; + sclk_table->entries[entryId].vddc = + table_info->vddc_lookup_table->entries[voltageId].us_vdd; + } + + for (entryId = 0; entryId < mclk_table->count; ++entryId) { + voltageId = mclk_table->entries[entryId].vddInd; + mclk_table->entries[entryId].vddc = + table_info->vddc_lookup_table->entries[voltageId].us_vdd; + } + + for (entryId = 0; entryId < mm_table->count; ++entryId) { + voltageId = mm_table->entries[entryId].vddcInd; + mm_table->entries[entryId].vddc = + table_info->vddc_lookup_table->entries[voltageId].us_vdd; + } + + return 0; + +} + +static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) +{ + /* Need to determine if we need calculated voltage. */ + return 0; +} + +static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) +{ + /* Need to determine if we need calculated voltage from mm table. */ + return 0; +} + +static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr, + struct phm_ppt_v1_voltage_lookup_table *lookup_table) +{ + uint32_t table_size, i, j; + struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record; + table_size = lookup_table->count; + + PP_ASSERT_WITH_CODE(0 != lookup_table->count, + "Lookup table is empty", return -EINVAL); + + /* Sorting voltages */ + for (i = 0; i < table_size - 1; i++) { + for (j = i + 1; j > 0; j--) { + if (lookup_table->entries[j].us_vdd < + lookup_table->entries[j - 1].us_vdd) { + tmp_voltage_lookup_record = lookup_table->entries[j - 1]; + lookup_table->entries[j - 1] = lookup_table->entries[j]; + lookup_table->entries[j] = tmp_voltage_lookup_record; + } + } + } + + return 0; +} + +static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr) +{ + int result = 0; + int tmp_result; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr, + table_info->vddc_lookup_table, &(data->vddc_leakage)); + if (tmp_result) + result = tmp_result; + + tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, + &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); + if (tmp_result) + result = tmp_result; + + tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr); + if (tmp_result) + result = tmp_result; + + tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr); + if (tmp_result) + result = tmp_result; + + tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr); + if (tmp_result) + result = tmp_result; + + tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); + if (tmp_result) + result = tmp_result; + + return result; +} + +static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) +{ + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = + table_info->vdd_dep_on_sclk; + struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = + table_info->vdd_dep_on_mclk; + + PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, + "VDD dependency on SCLK table is missing. \ + This table is mandatory", return -EINVAL); + PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, + "VDD dependency on SCLK table has to have is missing. \ + This table is mandatory", return -EINVAL); + + PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, + "VDD dependency on MCLK table is missing. \ + This table is mandatory", return -EINVAL); + PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, + "VDD dependency on MCLK table has to have is missing. \ + This table is mandatory", return -EINVAL); + + table_info->max_clock_voltage_on_ac.sclk = + allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; + table_info->max_clock_voltage_on_ac.mclk = + allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; + table_info->max_clock_voltage_on_ac.vddc = + allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; + table_info->max_clock_voltage_on_ac.vddci = + allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; + + return 0; +} + +int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; + uint32_t temp_reg; + int result; + + data->dll_default_on = false; + data->sram_end = SMC_RAM_END; + + data->disable_dpm_mask = 0xFF; + data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT; + data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT; + data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT; + + data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0; + data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1; + data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2; + data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3; + data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4; + data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5; + data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6; + data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7; + + data->vddc_vddci_delta = VDDC_VDDCI_DELTA; + + data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT; + + /* need to set voltage control types before EVV patching */ + data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE; + data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE; + data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE; + + if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) + data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2; + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DynamicPatchPowerState); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EnableMVDDControl)) { + if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) + data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO; + else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) + data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2; + } + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ControlVDDCI)) { + if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) + data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO; + else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) + data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2; + } + + polaris10_set_features_platform_caps(hwmgr); + + polaris10_init_dpm_defaults(hwmgr); + + /* Get leakage voltage based on leakage ID. */ + result = polaris10_get_evv_voltages(hwmgr); + + if (result) { + printk("Get EVV Voltage Failed. Abort Driver loading!\n"); + return -1; + } + + polaris10_complete_dependency_tables(hwmgr); + polaris10_set_private_data_based_on_pptable(hwmgr); + + /* Initalize Dynamic State Adjustment Rule Settings */ + result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr); + + if (0 == result) { + struct cgs_system_info sys_info = {0}; + + data->is_tlu_enabled = 0; + + hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = + POLARIS10_MAX_HARDWARE_POWERLEVELS; + hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; + hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; + hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ +/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ + hwmgr->platform_descriptor.clockStep.engineClock = 500; + hwmgr->platform_descriptor.clockStep.memoryClock = 500; + + if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) { + temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL); + switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) { + case 0: + temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1); + break; + case 1: + temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2); + break; + case 2: + temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1); + break; + case 3: + temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1); + break; + case 4: + temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1); + break; + default: + PP_ASSERT_WITH_CODE(0, + "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!", + ); + break; + } + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg); + } + + sys_info.size = sizeof(struct cgs_system_info); + sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO; + result = cgs_query_system_info(hwmgr->device, &sys_info); + if (result) + data->pcie_gen_cap = 0x30007; + else + data->pcie_gen_cap = (uint32_t)sys_info.value; + if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) + data->pcie_spc_cap = 20; + sys_info.size = sizeof(struct cgs_system_info); + sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW; + result = cgs_query_system_info(hwmgr->device, &sys_info); + if (result) + data->pcie_lane_cap = 0x2f0000; + else + data->pcie_lane_cap = (uint32_t)sys_info.value; + } else { + /* Ignore return value in here, we are cleaning up a mess. */ + polaris10_hwmgr_backend_fini(hwmgr); + } + + return 0; +} + +static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t level, tmp; + + if (!data->pcie_dpm_key_disabled) { + if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { + level = 0; + tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; + while (tmp >>= 1) + level++; + + if (level) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_PCIeDPM_ForceLevel, level); + } + } + + if (!data->sclk_dpm_key_disabled) { + if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { + level = 0; + tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; + while (tmp >>= 1) + level++; + + if (level) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_SetEnabledMask, + (1 << level)); + } + } + + if (!data->mclk_dpm_key_disabled) { + if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { + level = 0; + tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; + while (tmp >>= 1) + level++; + + if (level) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_MCLKDPM_SetEnabledMask, + (1 << level)); + } + } + + return 0; +} + +static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + phm_apply_dal_min_voltage_request(hwmgr); + + if (!data->sclk_dpm_key_disabled) { + if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_SetEnabledMask, + data->dpm_level_enable_mask.sclk_dpm_enable_mask); + } + + if (!data->mclk_dpm_key_disabled) { + if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_MCLKDPM_SetEnabledMask, + data->dpm_level_enable_mask.mclk_dpm_enable_mask); + } + + return 0; +} + +static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (!polaris10_is_dpm_running(hwmgr)) + return -EINVAL; + + if (!data->pcie_dpm_key_disabled) { + smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_PCIeDPM_UnForceLevel); + } + + return polaris10_upload_dpm_level_enable_mask(hwmgr); +} + +static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = + (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t level; + + if (!data->sclk_dpm_key_disabled) + if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { + level = phm_get_lowest_enabled_level(hwmgr, + data->dpm_level_enable_mask.sclk_dpm_enable_mask); + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_SetEnabledMask, + (1 << level)); + + } +/* uvd is enabled, can't set mclk low right now + if (!data->mclk_dpm_key_disabled) { + if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { + level = phm_get_lowest_enabled_level(hwmgr, + data->dpm_level_enable_mask.mclk_dpm_enable_mask); + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_MCLKDPM_SetEnabledMask, + (1 << level)); + } + } +*/ + if (!data->pcie_dpm_key_disabled) { + if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { + level = phm_get_lowest_enabled_level(hwmgr, + data->dpm_level_enable_mask.pcie_dpm_enable_mask); + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_PCIeDPM_ForceLevel, + (level)); + } + } + + return 0; + +} +static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr, + enum amd_dpm_forced_level level) +{ + int ret = 0; + + switch (level) { + case AMD_DPM_FORCED_LEVEL_HIGH: + ret = polaris10_force_dpm_highest(hwmgr); + if (ret) + return ret; + break; + case AMD_DPM_FORCED_LEVEL_LOW: + ret = polaris10_force_dpm_lowest(hwmgr); + if (ret) + return ret; + break; + case AMD_DPM_FORCED_LEVEL_AUTO: + ret = polaris10_unforce_dpm_levels(hwmgr); + if (ret) + return ret; + break; + default: + break; + } + + hwmgr->dpm_level = level; + + return ret; +} + +static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr) +{ + return sizeof(struct polaris10_power_state); +} + + +static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + struct pp_power_state *request_ps, + const struct pp_power_state *current_ps) +{ + + struct polaris10_power_state *polaris10_ps = + cast_phw_polaris10_power_state(&request_ps->hardware); + uint32_t sclk; + uint32_t mclk; + struct PP_Clocks minimum_clocks = {0}; + bool disable_mclk_switching; + bool disable_mclk_switching_for_frame_lock; + struct cgs_display_info info = {0}; + const struct phm_clock_and_voltage_limits *max_limits; + uint32_t i; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + int32_t count; + int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; + + data->battery_state = (PP_StateUILabel_Battery == + request_ps->classification.ui_label); + + PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2, + "VI should always have 2 performance levels", + ); + + max_limits = (PP_PowerSource_AC == hwmgr->power_source) ? + &(hwmgr->dyn_state.max_clock_voltage_on_ac) : + &(hwmgr->dyn_state.max_clock_voltage_on_dc); + + /* Cap clock DPM tables at DC MAX if it is in DC. */ + if (PP_PowerSource_DC == hwmgr->power_source) { + for (i = 0; i < polaris10_ps->performance_level_count; i++) { + if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk) + polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk; + if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk) + polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk; + } + } + + polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk; + polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk; + + cgs_get_active_displays_info(hwmgr->device, &info); + + /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ + + /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */ + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_StablePState)) { + max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); + stable_pstate_sclk = (max_limits->sclk * 75) / 100; + + for (count = table_info->vdd_dep_on_sclk->count - 1; + count >= 0; count--) { + if (stable_pstate_sclk >= + table_info->vdd_dep_on_sclk->entries[count].clk) { + stable_pstate_sclk = + table_info->vdd_dep_on_sclk->entries[count].clk; + break; + } + } + + if (count < 0) + stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; + + stable_pstate_mclk = max_limits->mclk; + + minimum_clocks.engineClock = stable_pstate_sclk; + minimum_clocks.memoryClock = stable_pstate_mclk; + } + + if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk) + minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk; + + if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk) + minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk; + + polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold; + + if (0 != hwmgr->gfx_arbiter.sclk_over_drive) { + PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= + hwmgr->platform_descriptor.overdriveLimit.engineClock), + "Overdrive sclk exceeds limit", + hwmgr->gfx_arbiter.sclk_over_drive = + hwmgr->platform_descriptor.overdriveLimit.engineClock); + + if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk) + polaris10_ps->performance_levels[1].engine_clock = + hwmgr->gfx_arbiter.sclk_over_drive; + } + + if (0 != hwmgr->gfx_arbiter.mclk_over_drive) { + PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= + hwmgr->platform_descriptor.overdriveLimit.memoryClock), + "Overdrive mclk exceeds limit", + hwmgr->gfx_arbiter.mclk_over_drive = + hwmgr->platform_descriptor.overdriveLimit.memoryClock); + + if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk) + polaris10_ps->performance_levels[1].memory_clock = + hwmgr->gfx_arbiter.mclk_over_drive; + } + + disable_mclk_switching_for_frame_lock = phm_cap_enabled( + hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); + + disable_mclk_switching = (1 < info.display_count) || + disable_mclk_switching_for_frame_lock; + + sclk = polaris10_ps->performance_levels[0].engine_clock; + mclk = polaris10_ps->performance_levels[0].memory_clock; + + if (disable_mclk_switching) + mclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].memory_clock; + + if (sclk < minimum_clocks.engineClock) + sclk = (minimum_clocks.engineClock > max_limits->sclk) ? + max_limits->sclk : minimum_clocks.engineClock; + + if (mclk < minimum_clocks.memoryClock) + mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? + max_limits->mclk : minimum_clocks.memoryClock; + + polaris10_ps->performance_levels[0].engine_clock = sclk; + polaris10_ps->performance_levels[0].memory_clock = mclk; + + polaris10_ps->performance_levels[1].engine_clock = + (polaris10_ps->performance_levels[1].engine_clock >= + polaris10_ps->performance_levels[0].engine_clock) ? + polaris10_ps->performance_levels[1].engine_clock : + polaris10_ps->performance_levels[0].engine_clock; + + if (disable_mclk_switching) { + if (mclk < polaris10_ps->performance_levels[1].memory_clock) + mclk = polaris10_ps->performance_levels[1].memory_clock; + + polaris10_ps->performance_levels[0].memory_clock = mclk; + polaris10_ps->performance_levels[1].memory_clock = mclk; + } else { + if (polaris10_ps->performance_levels[1].memory_clock < + polaris10_ps->performance_levels[0].memory_clock) + polaris10_ps->performance_levels[1].memory_clock = + polaris10_ps->performance_levels[0].memory_clock; + } + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_StablePState)) { + for (i = 0; i < polaris10_ps->performance_level_count; i++) { + polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk; + polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk; + polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; + polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; + } + } + return 0; +} + + +static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) +{ + struct pp_power_state *ps; + struct polaris10_power_state *polaris10_ps; + + if (hwmgr == NULL) + return -EINVAL; + + ps = hwmgr->request_ps; + + if (ps == NULL) + return -EINVAL; + + polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware); + + if (low) + return polaris10_ps->performance_levels[0].memory_clock; + else + return polaris10_ps->performance_levels + [polaris10_ps->performance_level_count-1].memory_clock; +} + +static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) +{ + struct pp_power_state *ps; + struct polaris10_power_state *polaris10_ps; + + if (hwmgr == NULL) + return -EINVAL; + + ps = hwmgr->request_ps; + + if (ps == NULL) + return -EINVAL; + + polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware); + + if (low) + return polaris10_ps->performance_levels[0].engine_clock; + else + return polaris10_ps->performance_levels + [polaris10_ps->performance_level_count-1].engine_clock; +} + +static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, + struct pp_hw_power_state *hw_ps) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps; + ATOM_FIRMWARE_INFO_V2_2 *fw_info; + uint16_t size; + uint8_t frev, crev; + int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); + + /* First retrieve the Boot clocks and VDDC from the firmware info table. + * We assume here that fw_info is unchanged if this call fails. + */ + fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table( + hwmgr->device, index, + &size, &frev, &crev); + if (!fw_info) + /* During a test, there is no firmware info table. */ + return 0; + + /* Patch the state. */ + data->vbios_boot_state.sclk_bootup_value = + le32_to_cpu(fw_info->ulDefaultEngineClock); + data->vbios_boot_state.mclk_bootup_value = + le32_to_cpu(fw_info->ulDefaultMemoryClock); + data->vbios_boot_state.mvdd_bootup_value = + le16_to_cpu(fw_info->usBootUpMVDDCVoltage); + data->vbios_boot_state.vddc_bootup_value = + le16_to_cpu(fw_info->usBootUpVDDCVoltage); + data->vbios_boot_state.vddci_bootup_value = + le16_to_cpu(fw_info->usBootUpVDDCIVoltage); + data->vbios_boot_state.pcie_gen_bootup_value = + phm_get_current_pcie_speed(hwmgr); + + data->vbios_boot_state.pcie_lane_bootup_value = + (uint16_t)phm_get_current_pcie_lane_number(hwmgr); + + /* set boot power state */ + ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value; + ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value; + ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value; + ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value; + + return 0; +} + +static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, + void *state, struct pp_power_state *power_state, + void *pp_table, uint32_t classification_flag) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_power_state *polaris10_power_state = + (struct polaris10_power_state *)(&(power_state->hardware)); + struct polaris10_performance_level *performance_level; + ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state; + ATOM_Tonga_POWERPLAYTABLE *powerplay_table = + (ATOM_Tonga_POWERPLAYTABLE *)pp_table; + ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table = + (ATOM_Tonga_SCLK_Dependency_Table *) + (((unsigned long)powerplay_table) + + le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); + ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = + (ATOM_Tonga_MCLK_Dependency_Table *) + (((unsigned long)powerplay_table) + + le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); + + /* The following fields are not initialized here: id orderedList allStatesList */ + power_state->classification.ui_label = + (le16_to_cpu(state_entry->usClassification) & + ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> + ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; + power_state->classification.flags = classification_flag; + /* NOTE: There is a classification2 flag in BIOS that is not being used right now */ + + power_state->classification.temporary_state = false; + power_state->classification.to_be_deleted = false; + + power_state->validation.disallowOnDC = + (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & + ATOM_Tonga_DISALLOW_ON_DC)); + + power_state->pcie.lanes = 0; + + power_state->display.disableFrameModulation = false; + power_state->display.limitRefreshrate = false; + power_state->display.enableVariBright = + (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & + ATOM_Tonga_ENABLE_VARIBRIGHT)); + + power_state->validation.supportedPowerLevels = 0; + power_state->uvd_clocks.VCLK = 0; + power_state->uvd_clocks.DCLK = 0; + power_state->temperatures.min = 0; + power_state->temperatures.max = 0; + + performance_level = &(polaris10_power_state->performance_levels + [polaris10_power_state->performance_level_count++]); + + PP_ASSERT_WITH_CODE( + (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS), + "Performance levels exceeds SMC limit!", + return -1); + + PP_ASSERT_WITH_CODE( + (polaris10_power_state->performance_level_count <= + hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), + "Performance levels exceeds Driver limit!", + return -1); + + /* Performance levels are arranged from low to high. */ + performance_level->memory_clock = mclk_dep_table->entries + [state_entry->ucMemoryClockIndexLow].ulMclk; + performance_level->engine_clock = sclk_dep_table->entries + [state_entry->ucEngineClockIndexLow].ulSclk; + performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, + state_entry->ucPCIEGenLow); + performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, + state_entry->ucPCIELaneHigh); + + performance_level = &(polaris10_power_state->performance_levels + [polaris10_power_state->performance_level_count++]); + performance_level->memory_clock = mclk_dep_table->entries + [state_entry->ucMemoryClockIndexHigh].ulMclk; + performance_level->engine_clock = sclk_dep_table->entries + [state_entry->ucEngineClockIndexHigh].ulSclk; + performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, + state_entry->ucPCIEGenHigh); + performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, + state_entry->ucPCIELaneHigh); + + return 0; +} + +static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr, + unsigned long entry_index, struct pp_power_state *state) +{ + int result; + struct polaris10_power_state *ps; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = + table_info->vdd_dep_on_mclk; + + state->hardware.magic = PHM_VIslands_Magic; + + ps = (struct polaris10_power_state *)(&state->hardware); + + result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state, + polaris10_get_pp_table_entry_callback_func); + + /* This is the earliest time we have all the dependency table and the VBIOS boot state + * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state + * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state + */ + if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { + if (dep_mclk_table->entries[0].clk != + data->vbios_boot_state.mclk_bootup_value) + printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table " + "does not match VBIOS boot MCLK level"); + if (dep_mclk_table->entries[0].vddci != + data->vbios_boot_state.vddci_bootup_value) + printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table " + "does not match VBIOS boot VDDCI level"); + } + + /* set DC compatible flag if this state supports DC */ + if (!state->validation.disallowOnDC) + ps->dc_compatible = true; + + if (state->classification.flags & PP_StateClassificationFlag_ACPI) + data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; + + ps->uvd_clks.vclk = state->uvd_clocks.VCLK; + ps->uvd_clks.dclk = state->uvd_clocks.DCLK; + + if (!result) { + uint32_t i; + + switch (state->classification.ui_label) { + case PP_StateUILabel_Performance: + data->use_pcie_performance_levels = true; + + for (i = 0; i < ps->performance_level_count; i++) { + if (data->pcie_gen_performance.max < + ps->performance_levels[i].pcie_gen) + data->pcie_gen_performance.max = + ps->performance_levels[i].pcie_gen; + + if (data->pcie_gen_performance.min > + ps->performance_levels[i].pcie_gen) + data->pcie_gen_performance.min = + ps->performance_levels[i].pcie_gen; + + if (data->pcie_lane_performance.max < + ps->performance_levels[i].pcie_lane) + data->pcie_lane_performance.max = + ps->performance_levels[i].pcie_lane; + + if (data->pcie_lane_performance.min > + ps->performance_levels[i].pcie_lane) + data->pcie_lane_performance.min = + ps->performance_levels[i].pcie_lane; + } + break; + case PP_StateUILabel_Battery: + data->use_pcie_power_saving_levels = true; + + for (i = 0; i < ps->performance_level_count; i++) { + if (data->pcie_gen_power_saving.max < + ps->performance_levels[i].pcie_gen) + data->pcie_gen_power_saving.max = + ps->performance_levels[i].pcie_gen; + + if (data->pcie_gen_power_saving.min > + ps->performance_levels[i].pcie_gen) + data->pcie_gen_power_saving.min = + ps->performance_levels[i].pcie_gen; + + if (data->pcie_lane_power_saving.max < + ps->performance_levels[i].pcie_lane) + data->pcie_lane_power_saving.max = + ps->performance_levels[i].pcie_lane; + + if (data->pcie_lane_power_saving.min > + ps->performance_levels[i].pcie_lane) + data->pcie_lane_power_saving.min = + ps->performance_levels[i].pcie_lane; + } + break; + default: + break; + } + } + return 0; +} + +static void +polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m) +{ + uint32_t sclk, mclk; + + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); + + sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); + + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); + + mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); + seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", + mclk / 100, sclk / 100); +} + +static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) +{ + const struct phm_set_power_state_input *states = + (const struct phm_set_power_state_input *)input; + const struct polaris10_power_state *polaris10_ps = + cast_const_phw_polaris10_power_state(states->pnew_state); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); + uint32_t sclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].engine_clock; + struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); + uint32_t mclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].memory_clock; + struct PP_Clocks min_clocks = {0}; + uint32_t i; + struct cgs_display_info info = {0}; + + data->need_update_smu7_dpm_table = 0; + + for (i = 0; i < sclk_table->count; i++) { + if (sclk == sclk_table->dpm_levels[i].value) + break; + } + + if (i >= sclk_table->count) + data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; + else { + /* TODO: Check SCLK in DAL's minimum clocks + * in case DeepSleep divider update is required. + */ + if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR && + (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK || + data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK)) + data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; + } + + for (i = 0; i < mclk_table->count; i++) { + if (mclk == mclk_table->dpm_levels[i].value) + break; + } + + if (i >= mclk_table->count) + data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; + + cgs_get_active_displays_info(hwmgr->device, &info); + + if (data->display_timing.num_existing_displays != info.display_count) + data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; + + return 0; +} + +static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr, + const struct polaris10_power_state *polaris10_ps) +{ + uint32_t i; + uint32_t sclk, max_sclk = 0; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_dpm_table *dpm_table = &data->dpm_table; + + for (i = 0; i < polaris10_ps->performance_level_count; i++) { + sclk = polaris10_ps->performance_levels[i].engine_clock; + if (max_sclk < sclk) + max_sclk = sclk; + } + + for (i = 0; i < dpm_table->sclk_table.count; i++) { + if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk) + return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ? + dpm_table->pcie_speed_table.dpm_levels + [dpm_table->pcie_speed_table.count - 1].value : + dpm_table->pcie_speed_table.dpm_levels[i].value); + } + + return 0; +} + +static int polaris10_request_link_speed_change_before_state_change( + struct pp_hwmgr *hwmgr, const void *input) +{ + const struct phm_set_power_state_input *states = + (const struct phm_set_power_state_input *)input; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_power_state *polaris10_nps = + cast_const_phw_polaris10_power_state(states->pnew_state); + const struct polaris10_power_state *polaris10_cps = + cast_const_phw_polaris10_power_state(states->pcurrent_state); + + uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps); + uint16_t current_link_speed; + + if (data->force_pcie_gen == PP_PCIEGenInvalid) + current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps); + else + current_link_speed = data->force_pcie_gen; + + data->force_pcie_gen = PP_PCIEGenInvalid; + data->pspp_notify_required = false; + + if (target_link_speed > current_link_speed) { + switch (target_link_speed) { + case PP_PCIEGen3: + if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false)) + break; + data->force_pcie_gen = PP_PCIEGen2; + if (current_link_speed == PP_PCIEGen2) + break; + case PP_PCIEGen2: + if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false)) + break; + default: + data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr); + break; + } + } else { + if (target_link_speed < current_link_speed) + data->pspp_notify_required = true; + } + + return 0; +} + +static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (0 == data->need_update_smu7_dpm_table) + return 0; + + if ((0 == data->sclk_dpm_key_disabled) && + (data->need_update_smu7_dpm_table & + (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { + PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), + "Trying to freeze SCLK DPM when DPM is disabled", + ); + PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_FreezeLevel), + "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", + return -1); + } + + if ((0 == data->mclk_dpm_key_disabled) && + (data->need_update_smu7_dpm_table & + DPMTABLE_OD_UPDATE_MCLK)) { + PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), + "Trying to freeze MCLK DPM when DPM is disabled", + ); + PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_MCLKDPM_FreezeLevel), + "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", + return -1); + } + + return 0; +} + +static int polaris10_populate_and_upload_sclk_mclk_dpm_levels( + struct pp_hwmgr *hwmgr, const void *input) +{ + int result = 0; + const struct phm_set_power_state_input *states = + (const struct phm_set_power_state_input *)input; + const struct polaris10_power_state *polaris10_ps = + cast_const_phw_polaris10_power_state(states->pnew_state); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t sclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].engine_clock; + uint32_t mclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].memory_clock; + struct polaris10_dpm_table *dpm_table = &data->dpm_table; + + struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table; + uint32_t dpm_count, clock_percent; + uint32_t i; + + if (0 == data->need_update_smu7_dpm_table) + return 0; + + if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { + dpm_table->sclk_table.dpm_levels + [dpm_table->sclk_table.count - 1].value = sclk; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || + phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { + /* Need to do calculation based on the golden DPM table + * as the Heatmap GPU Clock axis is also based on the default values + */ + PP_ASSERT_WITH_CODE( + (golden_dpm_table->sclk_table.dpm_levels + [golden_dpm_table->sclk_table.count - 1].value != 0), + "Divide by 0!", + return -1); + dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2; + + for (i = dpm_count; i > 1; i--) { + if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) { + clock_percent = + ((sclk + - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value + ) * 100) + / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value; + + dpm_table->sclk_table.dpm_levels[i].value = + golden_dpm_table->sclk_table.dpm_levels[i].value + + (golden_dpm_table->sclk_table.dpm_levels[i].value * + clock_percent)/100; + + } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) { + clock_percent = + ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value + - sclk) * 100) + / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value; + + dpm_table->sclk_table.dpm_levels[i].value = + golden_dpm_table->sclk_table.dpm_levels[i].value - + (golden_dpm_table->sclk_table.dpm_levels[i].value * + clock_percent) / 100; + } else + dpm_table->sclk_table.dpm_levels[i].value = + golden_dpm_table->sclk_table.dpm_levels[i].value; + } + } + } + + if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { + dpm_table->mclk_table.dpm_levels + [dpm_table->mclk_table.count - 1].value = mclk; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || + phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { + + PP_ASSERT_WITH_CODE( + (golden_dpm_table->mclk_table.dpm_levels + [golden_dpm_table->mclk_table.count-1].value != 0), + "Divide by 0!", + return -1); + dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2; + for (i = dpm_count; i > 1; i--) { + if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) { + clock_percent = ((mclk - + golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100) + / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value; + + dpm_table->mclk_table.dpm_levels[i].value = + golden_dpm_table->mclk_table.dpm_levels[i].value + + (golden_dpm_table->mclk_table.dpm_levels[i].value * + clock_percent) / 100; + + } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) { + clock_percent = ( + (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk) + * 100) + / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value; + + dpm_table->mclk_table.dpm_levels[i].value = + golden_dpm_table->mclk_table.dpm_levels[i].value - + (golden_dpm_table->mclk_table.dpm_levels[i].value * + clock_percent) / 100; + } else + dpm_table->mclk_table.dpm_levels[i].value = + golden_dpm_table->mclk_table.dpm_levels[i].value; + } + } + } + + if (data->need_update_smu7_dpm_table & + (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) { + result = polaris10_populate_all_graphic_levels(hwmgr); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", + return result); + } + + if (data->need_update_smu7_dpm_table & + (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { + /*populate MCLK dpm table to SMU7 */ + result = polaris10_populate_all_memory_levels(hwmgr); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", + return result); + } + + return result; +} + +static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr, + struct polaris10_single_dpm_table *dpm_table, + uint32_t low_limit, uint32_t high_limit) +{ + uint32_t i; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + for (i = 0; i < dpm_table->count; i++) { + if ((dpm_table->dpm_levels[i].value < low_limit) + || (dpm_table->dpm_levels[i].value > high_limit)) + dpm_table->dpm_levels[i].enabled = false; + else if (((1 << i) & data->disable_dpm_mask) == 0) + dpm_table->dpm_levels[i].enabled = false; + else + dpm_table->dpm_levels[i].enabled = true; + } + + return 0; +} + +static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr, + const struct polaris10_power_state *polaris10_ps) +{ + int result = 0; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t high_limit_count; + + PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1), + "power state did not have any performance level", + return -1); + + high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1; + + polaris10_trim_single_dpm_states(hwmgr, + &(data->dpm_table.sclk_table), + polaris10_ps->performance_levels[0].engine_clock, + polaris10_ps->performance_levels[high_limit_count].engine_clock); + + polaris10_trim_single_dpm_states(hwmgr, + &(data->dpm_table.mclk_table), + polaris10_ps->performance_levels[0].memory_clock, + polaris10_ps->performance_levels[high_limit_count].memory_clock); + + return result; +} + +static int polaris10_generate_dpm_level_enable_mask( + struct pp_hwmgr *hwmgr, const void *input) +{ + int result; + const struct phm_set_power_state_input *states = + (const struct phm_set_power_state_input *)input; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_power_state *polaris10_ps = + cast_const_phw_polaris10_power_state(states->pnew_state); + + result = polaris10_trim_dpm_states(hwmgr, polaris10_ps); + if (result) + return result; + + data->dpm_level_enable_mask.sclk_dpm_enable_mask = + phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table); + data->dpm_level_enable_mask.mclk_dpm_enable_mask = + phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table); + data->dpm_level_enable_mask.pcie_dpm_enable_mask = + phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table); + + return 0; +} + +int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) +{ + return smum_send_msg_to_smc(hwmgr->smumgr, enable ? + PPSMC_MSG_UVDDPM_Enable : + PPSMC_MSG_UVDDPM_Disable); +} + +int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) +{ + return smum_send_msg_to_smc(hwmgr->smumgr, enable? + PPSMC_MSG_VCEDPM_Enable : + PPSMC_MSG_VCEDPM_Disable); +} + +int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable) +{ + return smum_send_msg_to_smc(hwmgr->smumgr, enable? + PPSMC_MSG_SAMUDPM_Enable : + PPSMC_MSG_SAMUDPM_Disable); +} + +int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t mm_boot_level_offset, mm_boot_level_value; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + if (!bgate) { + data->smc_state_table.UvdBootLevel = 0; + if (table_info->mm_dep_table->count > 0) + data->smc_state_table.UvdBootLevel = + (uint8_t) (table_info->mm_dep_table->count - 1); + mm_boot_level_offset = data->dpm_table_start + + offsetof(SMU74_Discrete_DpmTable, UvdBootLevel); + mm_boot_level_offset /= 4; + mm_boot_level_offset *= 4; + mm_boot_level_value = cgs_read_ind_register(hwmgr->device, + CGS_IND_REG__SMC, mm_boot_level_offset); + mm_boot_level_value &= 0x00FFFFFF; + mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24; + cgs_write_ind_register(hwmgr->device, + CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); + + if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_UVDDPM) || + phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_StablePState)) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_UVDDPM_SetEnabledMask, + (uint32_t)(1 << data->smc_state_table.UvdBootLevel)); + } + + return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate); +} + +static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) +{ + const struct phm_set_power_state_input *states = + (const struct phm_set_power_state_input *)input; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_power_state *polaris10_nps = + cast_const_phw_polaris10_power_state(states->pnew_state); + const struct polaris10_power_state *polaris10_cps = + cast_const_phw_polaris10_power_state(states->pcurrent_state); + + uint32_t mm_boot_level_offset, mm_boot_level_value; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + if (polaris10_nps->vce_clks.evclk > 0 && + (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) { + + data->smc_state_table.VceBootLevel = + (uint8_t) (table_info->mm_dep_table->count - 1); + + mm_boot_level_offset = data->dpm_table_start + + offsetof(SMU74_Discrete_DpmTable, VceBootLevel); + mm_boot_level_offset /= 4; + mm_boot_level_offset *= 4; + mm_boot_level_value = cgs_read_ind_register(hwmgr->device, + CGS_IND_REG__SMC, mm_boot_level_offset); + mm_boot_level_value &= 0xFF00FFFF; + mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16; + cgs_write_ind_register(hwmgr->device, + CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_VCEDPM_SetEnabledMask, + (uint32_t)1 << data->smc_state_table.VceBootLevel); + + polaris10_enable_disable_vce_dpm(hwmgr, true); + } else if (polaris10_nps->vce_clks.evclk == 0 && + polaris10_cps != NULL && + polaris10_cps->vce_clks.evclk > 0) + polaris10_enable_disable_vce_dpm(hwmgr, false); + } + + return 0; +} + +int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t mm_boot_level_offset, mm_boot_level_value; + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + if (!bgate) { + data->smc_state_table.SamuBootLevel = + (uint8_t) (table_info->mm_dep_table->count - 1); + mm_boot_level_offset = data->dpm_table_start + + offsetof(SMU74_Discrete_DpmTable, SamuBootLevel); + mm_boot_level_offset /= 4; + mm_boot_level_offset *= 4; + mm_boot_level_value = cgs_read_ind_register(hwmgr->device, + CGS_IND_REG__SMC, mm_boot_level_offset); + mm_boot_level_value &= 0xFFFFFF00; + mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0; + cgs_write_ind_register(hwmgr->device, + CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_StablePState)) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SAMUDPM_SetEnabledMask, + (uint32_t)(1 << data->smc_state_table.SamuBootLevel)); + } + + return polaris10_enable_disable_samu_dpm(hwmgr, !bgate); +} + +static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + int result = 0; + uint32_t low_sclk_interrupt_threshold = 0; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkThrottleLowNotification) + && (hwmgr->gfx_arbiter.sclk_threshold != + data->low_sclk_interrupt_threshold)) { + data->low_sclk_interrupt_threshold = + hwmgr->gfx_arbiter.sclk_threshold; + low_sclk_interrupt_threshold = + data->low_sclk_interrupt_threshold; + + CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); + + result = polaris10_copy_bytes_to_smc( + hwmgr->smumgr, + data->dpm_table_start + + offsetof(SMU74_Discrete_DpmTable, + LowSclkInterruptThreshold), + (uint8_t *)&low_sclk_interrupt_threshold, + sizeof(uint32_t), + data->sram_end); + } + + return result; +} + +static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (data->need_update_smu7_dpm_table & + (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) + return polaris10_program_memory_timing_parameters(hwmgr); + + return 0; +} + +static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (0 == data->need_update_smu7_dpm_table) + return 0; + + if ((0 == data->sclk_dpm_key_disabled) && + (data->need_update_smu7_dpm_table & + (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { + + PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), + "Trying to Unfreeze SCLK DPM when DPM is disabled", + ); + PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_UnfreezeLevel), + "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", + return -1); + } + + if ((0 == data->mclk_dpm_key_disabled) && + (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { + + PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), + "Trying to Unfreeze MCLK DPM when DPM is disabled", + ); + PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_UnfreezeLevel), + "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", + return -1); + } + + data->need_update_smu7_dpm_table = 0; + + return 0; +} + +static int polaris10_notify_link_speed_change_after_state_change( + struct pp_hwmgr *hwmgr, const void *input) +{ + const struct phm_set_power_state_input *states = + (const struct phm_set_power_state_input *)input; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_power_state *polaris10_ps = + cast_const_phw_polaris10_power_state(states->pnew_state); + uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps); + uint8_t request; + + if (data->pspp_notify_required) { + if (target_link_speed == PP_PCIEGen3) + request = PCIE_PERF_REQ_GEN3; + else if (target_link_speed == PP_PCIEGen2) + request = PCIE_PERF_REQ_GEN2; + else + request = PCIE_PERF_REQ_GEN1; + + if (request == PCIE_PERF_REQ_GEN1 && + phm_get_current_pcie_speed(hwmgr) > 0) + return 0; + + if (acpi_pcie_perf_request(hwmgr->device, request, false)) { + if (PP_PCIEGen2 == target_link_speed) + printk("PSPP request to switch to Gen2 from Gen3 Failed!"); + else + printk("PSPP request to switch to Gen1 from Gen2 Failed!"); + } + } + + return 0; +} + +static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) +{ + int tmp_result, result = 0; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to find DPM states clocks in DPM table!", + result = tmp_result); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PCIEPerformanceRequest)) { + tmp_result = + polaris10_request_link_speed_change_before_state_change(hwmgr, input); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to request link speed change before state change!", + result = tmp_result); + } + + tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to freeze SCLK MCLK DPM!", result = tmp_result); + + tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to populate and upload SCLK MCLK DPM levels!", + result = tmp_result); + + tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to generate DPM level enabled mask!", + result = tmp_result); + + tmp_result = polaris10_update_vce_dpm(hwmgr, input); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to update VCE DPM!", + result = tmp_result); + + tmp_result = polaris10_update_sclk_threshold(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to update SCLK threshold!", + result = tmp_result); + + tmp_result = polaris10_program_mem_timing_parameters(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to program memory timing parameters!", + result = tmp_result); + + tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to unfreeze SCLK MCLK DPM!", + result = tmp_result); + + tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to upload DPM level enabled mask!", + result = tmp_result); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PCIEPerformanceRequest)) { + tmp_result = + polaris10_notify_link_speed_change_after_state_change(hwmgr, input); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to notify link speed change after state change!", + result = tmp_result); + } + data->apply_optimized_settings = false; + return result; +} + +static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) +{ + hwmgr->thermal_controller. + advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; + + if (phm_is_hw_access_blocked(hwmgr)) + return 0; + + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm); +} + +int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) +{ + PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; + + return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; +} + +int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) +{ + uint32_t num_active_displays = 0; + struct cgs_display_info info = {0}; + info.mode_info = NULL; + + cgs_get_active_displays_info(hwmgr->device, &info); + + num_active_displays = info.display_count; + + if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */ + polaris10_notify_smc_display_change(hwmgr, false); + else + polaris10_notify_smc_display_change(hwmgr, true); + + return 0; +} + +/** +* Programs the display gap +* +* @param hwmgr the address of the powerplay hardware manager. +* @return always OK +*/ +int polaris10_program_display_gap(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t num_active_displays = 0; + uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); + uint32_t display_gap2; + uint32_t pre_vbi_time_in_us; + uint32_t frame_time_in_us; + uint32_t ref_clock; + uint32_t refresh_rate = 0; + struct cgs_display_info info = {0}; + struct cgs_mode_info mode_info; + + info.mode_info = &mode_info; + + cgs_get_active_displays_info(hwmgr->device, &info); + num_active_displays = info.display_count; + + display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); + + ref_clock = mode_info.ref_clock; + refresh_rate = mode_info.refresh_rate; + + if (0 == refresh_rate) + refresh_rate = 60; + + frame_time_in_us = 1000000 / refresh_rate; + + pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us; + display_gap2 = pre_vbi_time_in_us * (ref_clock / 100); + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64); + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); + + polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0); + + return 0; +} + + +int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) +{ + return polaris10_program_display_gap(hwmgr); +} + +/** +* Set maximum target operating fan output RPM +* +* @param hwmgr: the address of the powerplay hardware manager. +* @param usMaxFanRpm: max operating fan RPM value. +* @return The response that came from the SMC. +*/ +static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm) +{ + hwmgr->thermal_controller. + advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; + + if (phm_is_hw_access_blocked(hwmgr)) + return 0; + + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm); +} + +int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, + const void *thermal_interrupt_info) +{ + return 0; +} + +bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + bool is_update_required = false; + struct cgs_display_info info = {0, 0, NULL}; + + cgs_get_active_displays_info(hwmgr->device, &info); + + if (data->display_timing.num_existing_displays != info.display_count) + is_update_required = true; +/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL + if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { + cgs_get_min_clock_settings(hwmgr->device, &min_clocks); + if (min_clocks.engineClockInSR != data->display_timing.minClockInSR && + (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK || + data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK)) + is_update_required = true; +*/ + return is_update_required; +} + +static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1, + const struct polaris10_performance_level *pl2) +{ + return ((pl1->memory_clock == pl2->memory_clock) && + (pl1->engine_clock == pl2->engine_clock) && + (pl1->pcie_gen == pl2->pcie_gen) && + (pl1->pcie_lane == pl2->pcie_lane)); +} + +int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) +{ + const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1); + const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2); + int i; + + if (pstate1 == NULL || pstate2 == NULL || equal == NULL) + return -EINVAL; + + /* If the two states don't even have the same number of performance levels they cannot be the same state. */ + if (psa->performance_level_count != psb->performance_level_count) { + *equal = false; + return 0; + } + + for (i = 0; i < psa->performance_level_count; i++) { + if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { + /* If we have found even one performance level pair that is different the states are different. */ + *equal = false; + return 0; + } + } + + /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ + *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk)); + *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk)); + *equal &= (psa->sclk_threshold == psb->sclk_threshold); + + return 0; +} + +int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + uint32_t vbios_version; + + /* Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/ + + phm_get_mc_microcode_version(hwmgr); + vbios_version = hwmgr->microcode_version_info.MC & 0xf; + /* Full version of MC ucode has already been loaded. */ + if (vbios_version == 0) { + data->need_long_memory_training = false; + return 0; + } + + data->need_long_memory_training = true; + +/* + * PPMCME_FirmwareDescriptorEntry *pfd = NULL; + pfd = &tonga_mcmeFirmware; + if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN)) + polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold, + pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray, + pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize); +*/ + return 0; +} + +/** + * Read clock related registers. + * + * @param hwmgr the address of the powerplay hardware manager. + * @return always 0 + */ +static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device, + CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL) + & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK; + + data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device, + CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2) + & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK; + + data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device, + CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4) + & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK; + + return 0; +} + +/** + * Find out if memory is GDDR5. + * + * @param hwmgr the address of the powerplay hardware manager. + * @return always 0 + */ +static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t temp; + + temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0); + + data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == + ((temp & MC_SEQ_MISC0_GDDR5_MASK) >> + MC_SEQ_MISC0_GDDR5_SHIFT)); + + return 0; +} + +/** + * Enables Dynamic Power Management by SMC + * + * @param hwmgr the address of the powerplay hardware manager. + * @return always 0 + */ +static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr) +{ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + GENERAL_PWRMGT, STATIC_PM_EN, 1); + + return 0; +} + +/** + * Initialize PowerGating States for different engines + * + * @param hwmgr the address of the powerplay hardware manager. + * @return always 0 + */ +static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + data->uvd_power_gated = false; + data->vce_power_gated = false; + data->samu_power_gated = false; + + return 0; +} + +static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + data->low_sclk_interrupt_threshold = 0; + + return 0; +} + +int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr) +{ + int tmp_result, result = 0; + + polaris10_upload_mc_firmware(hwmgr); + + tmp_result = polaris10_read_clock_registers(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to read clock registers!", result = tmp_result); + + tmp_result = polaris10_get_memory_type(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to get memory type!", result = tmp_result); + + tmp_result = polaris10_enable_acpi_power_management(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to enable ACPI power management!", result = tmp_result); + + tmp_result = polaris10_init_power_gate_state(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to init power gate state!", result = tmp_result); + + tmp_result = phm_get_mc_microcode_version(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to get MC microcode version!", result = tmp_result); + + tmp_result = polaris10_init_sclk_threshold(hwmgr); + PP_ASSERT_WITH_CODE((0 == tmp_result), + "Failed to init sclk threshold!", result = tmp_result); + + return result; +} + +static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + *table = (char *)&data->smc_state_table; + + return sizeof(struct SMU74_Discrete_DpmTable); +} + +static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + void *table = (void *)&data->smc_state_table; + + memcpy(table, buf, size); + + return 0; +} + +static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, int level) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) + return -EINVAL; + + switch (type) { + case PP_SCLK: + if (!data->sclk_dpm_key_disabled) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_SetEnabledMask, + (1 << level)); + break; + case PP_MCLK: + if (!data->mclk_dpm_key_disabled) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_MCLKDPM_SetEnabledMask, + (1 << level)); + break; + case PP_PCIE: + if (!data->pcie_dpm_key_disabled) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_PCIeDPM_ForceLevel, + (1 << level)); + break; + default: + break; + } + + return 0; +} + +static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr) +{ + uint32_t speedCntl = 0; + + /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ + speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, + ixPCIE_LC_SPEED_CNTL); + return((uint16_t)PHM_GET_FIELD(speedCntl, + PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); +} + +static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, char *buf) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); + struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); + struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table); + int i, now, size = 0; + uint32_t clock, pcie_speed; + + switch (type) { + case PP_SCLK: + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); + clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); + + for (i = 0; i < sclk_table->count; i++) { + if (clock > sclk_table->dpm_levels[i].value) + continue; + break; + } + now = i; + + for (i = 0; i < sclk_table->count; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", + i, sclk_table->dpm_levels[i].value / 100, + (i == now) ? "*" : ""); + break; + case PP_MCLK: + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); + clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); + + for (i = 0; i < mclk_table->count; i++) { + if (clock > mclk_table->dpm_levels[i].value) + continue; + break; + } + now = i; + + for (i = 0; i < mclk_table->count; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", + i, mclk_table->dpm_levels[i].value / 100, + (i == now) ? "*" : ""); + break; + case PP_PCIE: + pcie_speed = polaris10_get_current_pcie_speed(hwmgr); + for (i = 0; i < pcie_table->count; i++) { + if (pcie_speed != pcie_table->dpm_levels[i].value) + continue; + break; + } + now = i; + + for (i = 0; i < pcie_table->count; i++) + size += sprintf(buf + size, "%d: %s %s\n", i, + (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" : + (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" : + (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "", + (i == now) ? "*" : ""); + break; + default: + break; + } + return size; +} + +static const struct pp_hwmgr_func polaris10_hwmgr_funcs = { + .backend_init = &polaris10_hwmgr_backend_init, + .backend_fini = &polaris10_hwmgr_backend_fini, + .asic_setup = &polaris10_setup_asic_task, + .dynamic_state_management_enable = &polaris10_enable_dpm_tasks, + .apply_state_adjust_rules = polaris10_apply_state_adjust_rules, + .force_dpm_level = &polaris10_force_dpm_level, + .power_state_set = polaris10_set_power_state_tasks, + .get_power_state_size = polaris10_get_power_state_size, + .get_mclk = polaris10_dpm_get_mclk, + .get_sclk = polaris10_dpm_get_sclk, + .patch_boot_state = polaris10_dpm_patch_boot_state, + .get_pp_table_entry = polaris10_get_pp_table_entry, + .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries, + .print_current_perforce_level = polaris10_print_current_perforce_level, + .powerdown_uvd = polaris10_phm_powerdown_uvd, + .powergate_uvd = polaris10_phm_powergate_uvd, + .powergate_vce = polaris10_phm_powergate_vce, + .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating, + .update_clock_gatings = polaris10_phm_update_clock_gatings, + .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment, + .display_config_changed = polaris10_display_configuration_changed_task, + .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output, + .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output, + .get_temperature = polaris10_thermal_get_temperature, + .stop_thermal_controller = polaris10_thermal_stop_thermal_controller, + .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info, + .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent, + .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent, + .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default, + .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm, + .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm, + .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller, + .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt, + .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration, + .check_states_equal = polaris10_check_states_equal, + .get_pp_table = polaris10_get_pp_table, + .set_pp_table = polaris10_set_pp_table, + .force_clock_level = polaris10_force_clock_level, + .print_clock_levels = polaris10_print_clock_levels, + .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating, +}; + +int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data; + + data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + + hwmgr->backend = data; + hwmgr->hwmgr_func = &polaris10_hwmgr_funcs; + hwmgr->pptable_func = &tonga_pptable_funcs; + pp_polaris10_thermal_initialize(hwmgr); + + return 0; +} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h new file mode 100644 index 0000000..2507404 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h @@ -0,0 +1,354 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef POLARIS10_HWMGR_H +#define POLARIS10_HWMGR_H + +#include "hwmgr.h" +#include "smu74.h" +#include "smu74_discrete.h" +#include "ppatomctrl.h" +#include "polaris10_ppsmc.h" +#include "polaris10_powertune.h" + +#define POLARIS10_MAX_HARDWARE_POWERLEVELS 2 + +#define POLARIS10_VOLTAGE_CONTROL_NONE 0x0 +#define POLARIS10_VOLTAGE_CONTROL_BY_GPIO 0x1 +#define POLARIS10_VOLTAGE_CONTROL_BY_SVID2 0x2 +#define POLARIS10_VOLTAGE_CONTROL_MERGED 0x3 + +#define DPMTABLE_OD_UPDATE_SCLK 0x00000001 +#define DPMTABLE_OD_UPDATE_MCLK 0x00000002 +#define DPMTABLE_UPDATE_SCLK 0x00000004 +#define DPMTABLE_UPDATE_MCLK 0x00000008 + +struct polaris10_performance_level { + uint32_t memory_clock; + uint32_t engine_clock; + uint16_t pcie_gen; + uint16_t pcie_lane; +}; + +struct polaris10_uvd_clocks { + uint32_t vclk; + uint32_t dclk; +}; + +struct polaris10_vce_clocks { + uint32_t evclk; + uint32_t ecclk; +}; + +struct polaris10_power_state { + uint32_t magic; + struct polaris10_uvd_clocks uvd_clks; + struct polaris10_vce_clocks vce_clks; + uint32_t sam_clk; + uint16_t performance_level_count; + bool dc_compatible; + uint32_t sclk_threshold; + struct polaris10_performance_level performance_levels[POLARIS10_MAX_HARDWARE_POWERLEVELS]; +}; + +struct polaris10_dpm_level { + bool enabled; + uint32_t value; + uint32_t param1; +}; + +#define POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID 5 +#define MAX_REGULAR_DPM_NUMBER 8 +#define POLARIS10_MINIMUM_ENGINE_CLOCK 2500 + +struct polaris10_single_dpm_table { + uint32_t count; + struct polaris10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; +}; + +struct polaris10_dpm_table { + struct polaris10_single_dpm_table sclk_table; + struct polaris10_single_dpm_table mclk_table; + struct polaris10_single_dpm_table pcie_speed_table; + struct polaris10_single_dpm_table vddc_table; + struct polaris10_single_dpm_table vddci_table; + struct polaris10_single_dpm_table mvdd_table; +}; + +struct polaris10_clock_registers { + uint32_t vCG_SPLL_FUNC_CNTL; + uint32_t vCG_SPLL_FUNC_CNTL_2; + uint32_t vCG_SPLL_FUNC_CNTL_3; + uint32_t vCG_SPLL_FUNC_CNTL_4; + uint32_t vCG_SPLL_SPREAD_SPECTRUM; + uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; + uint32_t vDLL_CNTL; + uint32_t vMCLK_PWRMGT_CNTL; + uint32_t vMPLL_AD_FUNC_CNTL; + uint32_t vMPLL_DQ_FUNC_CNTL; + uint32_t vMPLL_FUNC_CNTL; + uint32_t vMPLL_FUNC_CNTL_1; + uint32_t vMPLL_FUNC_CNTL_2; + uint32_t vMPLL_SS1; + uint32_t vMPLL_SS2; +}; + +#define DISABLE_MC_LOADMICROCODE 1 +#define DISABLE_MC_CFGPROGRAMMING 2 + +struct polaris10_voltage_smio_registers { + uint32_t vS0_VID_LOWER_SMIO_CNTL; +}; + +#define POLARIS10_MAX_LEAKAGE_COUNT 8 + +struct polaris10_leakage_voltage { + uint16_t count; + uint16_t leakage_id[POLARIS10_MAX_LEAKAGE_COUNT]; + uint16_t actual_voltage[POLARIS10_MAX_LEAKAGE_COUNT]; +}; + +struct polaris10_vbios_boot_state { + uint16_t mvdd_bootup_value; + uint16_t vddc_bootup_value; + uint16_t vddci_bootup_value; + uint32_t sclk_bootup_value; + uint32_t mclk_bootup_value; + uint16_t pcie_gen_bootup_value; + uint16_t pcie_lane_bootup_value; +}; + +/* Ultra Low Voltage parameter structure */ +struct polaris10_ulv_parm { + bool ulv_supported; + uint32_t cg_ulv_parameter; + uint32_t ulv_volt_change_delay; + struct polaris10_performance_level ulv_power_level; +}; + +struct polaris10_display_timing { + uint32_t min_clock_in_sr; + uint32_t num_existing_displays; +}; + +struct polaris10_dpmlevel_enable_mask { + uint32_t uvd_dpm_enable_mask; + uint32_t vce_dpm_enable_mask; + uint32_t acp_dpm_enable_mask; + uint32_t samu_dpm_enable_mask; + uint32_t sclk_dpm_enable_mask; + uint32_t mclk_dpm_enable_mask; + uint32_t pcie_dpm_enable_mask; +}; + +struct polaris10_pcie_perf_range { + uint16_t max; + uint16_t min; +}; +struct polaris10_range_table { + uint32_t trans_lower_frequency; /* in 10khz */ + uint32_t trans_upper_frequency; +}; + +struct polaris10_hwmgr { + struct polaris10_dpm_table dpm_table; + struct polaris10_dpm_table golden_dpm_table; + SMU74_Discrete_DpmTable smc_state_table; + struct SMU74_Discrete_Ulv ulv_setting; + + struct polaris10_range_table range_table[NUM_SCLK_RANGE]; + uint32_t voting_rights_clients0; + uint32_t voting_rights_clients1; + uint32_t voting_rights_clients2; + uint32_t voting_rights_clients3; + uint32_t voting_rights_clients4; + uint32_t voting_rights_clients5; + uint32_t voting_rights_clients6; + uint32_t voting_rights_clients7; + uint32_t static_screen_threshold_unit; + uint32_t static_screen_threshold; + uint32_t voltage_control; + uint32_t vddc_vddci_delta; + + uint32_t active_auto_throttle_sources; + + struct polaris10_clock_registers clock_registers; + struct polaris10_voltage_smio_registers voltage_smio_registers; + + bool is_memory_gddr5; + uint16_t acpi_vddc; + bool pspp_notify_required; + uint16_t force_pcie_gen; + uint16_t acpi_pcie_gen; + uint32_t pcie_gen_cap; + uint32_t pcie_lane_cap; + uint32_t pcie_spc_cap; + struct polaris10_leakage_voltage vddc_leakage; + struct polaris10_leakage_voltage Vddci_leakage; + + uint32_t mvdd_control; + uint32_t vddc_mask_low; + uint32_t mvdd_mask_low; + uint16_t max_vddc_in_pptable; + uint16_t min_vddc_in_pptable; + uint16_t max_vddci_in_pptable; + uint16_t min_vddci_in_pptable; + uint32_t mclk_strobe_mode_threshold; + uint32_t mclk_stutter_mode_threshold; + uint32_t mclk_edc_enable_threshold; + uint32_t mclk_edcwr_enable_threshold; + bool is_uvd_enabled; + struct polaris10_vbios_boot_state vbios_boot_state; + + bool pcie_performance_request; + bool battery_state; + bool is_tlu_enabled; + + /* ---- SMC SRAM Address of firmware header tables ---- */ + uint32_t sram_end; + uint32_t dpm_table_start; + uint32_t soft_regs_start; + uint32_t mc_reg_table_start; + uint32_t fan_table_start; + uint32_t arb_table_start; + + /* ---- Stuff originally coming from Evergreen ---- */ + uint32_t vddci_control; + struct pp_atomctrl_voltage_table vddc_voltage_table; + struct pp_atomctrl_voltage_table vddci_voltage_table; + struct pp_atomctrl_voltage_table mvdd_voltage_table; + + uint32_t mgcg_cgtt_local2; + uint32_t mgcg_cgtt_local3; + uint32_t gpio_debug; + uint32_t mc_micro_code_feature; + uint32_t highest_mclk; + uint16_t acpi_vddci; + uint8_t mvdd_high_index; + uint8_t mvdd_low_index; + bool dll_default_on; + bool performance_request_registered; + + /* ---- Low Power Features ---- */ + struct polaris10_ulv_parm ulv; + + /* ---- CAC Stuff ---- */ + uint32_t cac_table_start; + bool cac_configuration_required; + bool driver_calculate_cac_leakage; + bool cac_enabled; + + /* ---- DPM2 Parameters ---- */ + uint32_t power_containment_features; + bool enable_dte_feature; + bool enable_tdc_limit_feature; + bool enable_pkg_pwr_tracking_feature; + bool disable_uvd_power_tune_feature; + struct polaris10_pt_defaults *power_tune_defaults; + struct SMU74_Discrete_PmFuses power_tune_table; + uint32_t dte_tj_offset; + uint32_t fast_watermark_threshold; + + /* ---- Phase Shedding ---- */ + bool vddc_phase_shed_control; + + /* ---- DI/DT ---- */ + struct polaris10_display_timing display_timing; + uint32_t bif_sclk_table[SMU74_MAX_LEVELS_LINK]; + + /* ---- Thermal Temperature Setting ---- */ + struct polaris10_dpmlevel_enable_mask dpm_level_enable_mask; + uint32_t need_update_smu7_dpm_table; + uint32_t sclk_dpm_key_disabled; + uint32_t mclk_dpm_key_disabled; + uint32_t pcie_dpm_key_disabled; + uint32_t min_engine_clocks; + struct polaris10_pcie_perf_range pcie_gen_performance; + struct polaris10_pcie_perf_range pcie_lane_performance; + struct polaris10_pcie_perf_range pcie_gen_power_saving; + struct polaris10_pcie_perf_range pcie_lane_power_saving; + bool use_pcie_performance_levels; + bool use_pcie_power_saving_levels; + uint32_t activity_target[SMU74_MAX_LEVELS_GRAPHICS]; + uint32_t mclk_activity_target; + uint32_t mclk_dpm0_activity_target; + uint32_t low_sclk_interrupt_threshold; + uint32_t last_mclk_dpm_enable_mask; + bool uvd_enabled; + + /* ---- Power Gating States ---- */ + bool uvd_power_gated; + bool vce_power_gated; + bool samu_power_gated; + bool need_long_memory_training; + + /* Application power optimization parameters */ + bool update_up_hyst; + bool update_down_hyst; + uint32_t down_hyst; + uint32_t up_hyst; + uint32_t disable_dpm_mask; + bool apply_optimized_settings; +}; + +/* To convert to Q8.8 format for firmware */ +#define POLARIS10_Q88_FORMAT_CONVERSION_UNIT 256 + +enum Polaris10_I2CLineID { + Polaris10_I2CLineID_DDC1 = 0x90, + Polaris10_I2CLineID_DDC2 = 0x91, + Polaris10_I2CLineID_DDC3 = 0x92, + Polaris10_I2CLineID_DDC4 = 0x93, + Polaris10_I2CLineID_DDC5 = 0x94, + Polaris10_I2CLineID_DDC6 = 0x95, + Polaris10_I2CLineID_SCLSDA = 0x96, + Polaris10_I2CLineID_DDCVGA = 0x97 +}; + +#define POLARIS10_I2C_DDC1DATA 0 +#define POLARIS10_I2C_DDC1CLK 1 +#define POLARIS10_I2C_DDC2DATA 2 +#define POLARIS10_I2C_DDC2CLK 3 +#define POLARIS10_I2C_DDC3DATA 4 +#define POLARIS10_I2C_DDC3CLK 5 +#define POLARIS10_I2C_SDA 40 +#define POLARIS10_I2C_SCL 41 +#define POLARIS10_I2C_DDC4DATA 65 +#define POLARIS10_I2C_DDC4CLK 66 +#define POLARIS10_I2C_DDC5DATA 0x48 +#define POLARIS10_I2C_DDC5CLK 0x49 +#define POLARIS10_I2C_DDC6DATA 0x4a +#define POLARIS10_I2C_DDC6CLK 0x4b +#define POLARIS10_I2C_DDCVGADATA 0x4c +#define POLARIS10_I2C_DDCVGACLK 0x4d + +#define POLARIS10_UNUSED_GPIO_PIN 0x7F + +int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr); + +int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c new file mode 100644 index 0000000..4d97326 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c @@ -0,0 +1,396 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "hwmgr.h" +#include "smumgr.h" +#include "polaris10_hwmgr.h" +#include "polaris10_powertune.h" +#include "polaris10_smumgr.h" +#include "smu74_discrete.h" +#include "pp_debug.h" + +#define VOLTAGE_SCALE 4 +#define POWERTUNE_DEFAULT_SET_MAX 1 + +struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = { + /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, + * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */ + { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, + { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61}, + { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } }, +}; + +void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *polaris10_hwmgr = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + + if (table_info && + table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX && + table_info->cac_dtp_table->usPowerTuneDataSetID) + polaris10_hwmgr->power_tune_defaults = + &polaris10_power_tune_data_set_array + [table_info->cac_dtp_table->usPowerTuneDataSetID - 1]; + else + polaris10_hwmgr->power_tune_defaults = &polaris10_power_tune_data_set_array[0]; + +} + +int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_pt_defaults *defaults = data->power_tune_defaults; + SMU74_Discrete_DpmTable *dpm_table = &(data->smc_state_table); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table; + int i, j, k; + uint16_t *pdef1; + uint16_t *pdef2; + + dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128)); + dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128)); + + PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255, + "Target Operating Temp is out of Range!", + ); +/* This is the same value as TemperatureLimitHigh except it is integer with no fraction bit. */ + dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp); + +/* HW request to hard code this value to 8 which is 0.5C */ + dpm_table->GpuTjHyst = 8; + + dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase; + dpm_table->DTETjOffset = (uint8_t)(data->dte_tj_offset); + dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->BAPM_TEMP_GRADIENT); + pdef1 = defaults->BAPMTI_R; + pdef2 = defaults->BAPMTI_RC; + + for (i = 0; i < SMU74_DTE_ITERATIONS; i++) { + for (j = 0; j < SMU74_DTE_SOURCES; j++) { + for (k = 0; k < SMU74_DTE_SINKS; k++) { + dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1); + dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2); + pdef1++; + pdef2++; + } + } + } + + return 0; +} + +static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_pt_defaults *defaults = data->power_tune_defaults; + + data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn; + data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC; + data->power_tune_table.SviLoadLineTrimVddC = 3; + data->power_tune_table.SviLoadLineOffsetVddC = 0; + + return 0; +} + +static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr) +{ + uint16_t tdc_limit; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct polaris10_pt_defaults *defaults = data->power_tune_defaults; + + tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128); + data->power_tune_table.TDC_VDDC_PkgLimit = + CONVERT_FROM_HOST_TO_SMC_US(tdc_limit); + data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc = + defaults->TDC_VDDC_ThrottleReleaseLimitPerc; + data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt; + + return 0; +} + +static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_pt_defaults *defaults = data->power_tune_defaults; + uint32_t temp; + + if (polaris10_read_smc_sram_dword(hwmgr->smumgr, + fuse_table_offset + + offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl), + (uint32_t *)&temp, data->sram_end)) + PP_ASSERT_WITH_CODE(false, + "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!", + return -EINVAL); + else { + data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl; + data->power_tune_table.LPMLTemperatureMin = + (uint8_t)((temp >> 16) & 0xff); + data->power_tune_table.LPMLTemperatureMax = + (uint8_t)((temp >> 8) & 0xff); + data->power_tune_table.Reserved = (uint8_t)(temp & 0xff); + } + return 0; +} + +static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr) +{ + int i; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + /* Currently not used. Set all to zero. */ + for (i = 0; i < 16; i++) + data->power_tune_table.LPMLTemperatureScaler[i] = 0; + + return 0; +} + +static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15)) + || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity) + hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = + hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity; + + data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US( + hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity); + return 0; +} + +static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr) +{ + int i; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + /* Currently not used. Set all to zero. */ + for (i = 0; i < 16; i++) + data->power_tune_table.GnbLPML[i] = 0; + + return 0; +} + +static int polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr) +{ + return 0; +} + +static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + uint16_t hi_sidd = data->power_tune_table.BapmVddCBaseLeakageHiSidd; + uint16_t lo_sidd = data->power_tune_table.BapmVddCBaseLeakageLoSidd; + struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table; + + hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256); + lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256); + + data->power_tune_table.BapmVddCBaseLeakageHiSidd = + CONVERT_FROM_HOST_TO_SMC_US(hi_sidd); + data->power_tune_table.BapmVddCBaseLeakageLoSidd = + CONVERT_FROM_HOST_TO_SMC_US(lo_sidd); + + return 0; +} + +int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t pm_fuse_table_offset; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PowerContainment)) { + if (polaris10_read_smc_sram_dword(hwmgr->smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU74_Firmware_Header, PmFuseTable), + &pm_fuse_table_offset, data->sram_end)) + PP_ASSERT_WITH_CODE(false, + "Attempt to get pm_fuse_table_offset Failed!", + return -EINVAL); + + if (polaris10_populate_svi_load_line(hwmgr)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate SviLoadLine Failed!", + return -EINVAL); + + if (polaris10_populate_tdc_limit(hwmgr)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate TDCLimit Failed!", return -EINVAL); + + if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate TdcWaterfallCtl, " + "LPMLTemperature Min and Max Failed!", + return -EINVAL); + + if (0 != polaris10_populate_temperature_scaler(hwmgr)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate LPMLTemperatureScaler Failed!", + return -EINVAL); + + if (polaris10_populate_fuzzy_fan(hwmgr)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate Fuzzy Fan Control parameters Failed!", + return -EINVAL); + + if (polaris10_populate_gnb_lpml(hwmgr)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate GnbLPML Failed!", + return -EINVAL); + + if (polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate GnbLPML Min and Max Vid Failed!", + return -EINVAL); + + if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr)) + PP_ASSERT_WITH_CODE(false, + "Attempt to populate BapmVddCBaseLeakage Hi and Lo " + "Sidd Failed!", return -EINVAL); + + if (polaris10_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, + (uint8_t *)&data->power_tune_table, + sizeof(struct SMU74_Discrete_PmFuses), data->sram_end)) + PP_ASSERT_WITH_CODE(false, + "Attempt to download PmFuseTable Failed!", + return -EINVAL); + } + return 0; +} + +int polaris10_enable_smc_cac(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + int result = 0; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_CAC)) { + int smc_result; + smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + (uint16_t)(PPSMC_MSG_EnableCac)); + PP_ASSERT_WITH_CODE((0 == smc_result), + "Failed to enable CAC in SMC.", result = -1); + + data->cac_enabled = (0 == smc_result) ? true : false; + } + return result; +} + +int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (data->power_containment_features & + POWERCONTAINMENT_FEATURE_PkgPwrLimit) + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_PkgPwrSetLimit, n); + return 0; +} + +static int polaris10_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp) +{ + return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr, + PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); +} + +int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + int smc_result; + int result = 0; + + data->power_containment_features = 0; + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PowerContainment)) { + if (data->enable_dte_feature) { + smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + (uint16_t)(PPSMC_MSG_EnableDTE)); + PP_ASSERT_WITH_CODE((0 == smc_result), + "Failed to enable DTE in SMC.", result = -1;); + if (0 == smc_result) + data->power_containment_features |= POWERCONTAINMENT_FEATURE_DTE; + } + + if (data->enable_tdc_limit_feature) { + smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + (uint16_t)(PPSMC_MSG_TDCLimitEnable)); + PP_ASSERT_WITH_CODE((0 == smc_result), + "Failed to enable TDCLimit in SMC.", result = -1;); + if (0 == smc_result) + data->power_containment_features |= + POWERCONTAINMENT_FEATURE_TDCLimit; + } + + if (data->enable_pkg_pwr_tracking_feature) { + smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + (uint16_t)(PPSMC_MSG_PkgPwrLimitEnable)); + PP_ASSERT_WITH_CODE((0 == smc_result), + "Failed to enable PkgPwrTracking in SMC.", result = -1;); + if (0 == smc_result) { + struct phm_cac_tdp_table *cac_table = + table_info->cac_dtp_table; + uint32_t default_limit = + (uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256); + + data->power_containment_features |= + POWERCONTAINMENT_FEATURE_PkgPwrLimit; + + if (polaris10_set_power_limit(hwmgr, default_limit)) + printk(KERN_ERR "Failed to set Default Power Limit in SMC!"); + } + } + } + return result; +} + +int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr) +{ + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table; + int adjust_percent, target_tdp; + int result = 0; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PowerContainment)) { + /* adjustment percentage has already been validated */ + adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ? + hwmgr->platform_descriptor.TDPAdjustment : + (-1 * hwmgr->platform_descriptor.TDPAdjustment); + /* SMC requested that target_tdp to be 7 bit fraction in DPM table + * but message to be 8 bit fraction for messages + */ + target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100; + result = polaris10_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp); + } + + return result; +} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h new file mode 100644 index 0000000..68bc1cb --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h @@ -0,0 +1,70 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef POLARIS10_POWERTUNE_H +#define POLARIS10_POWERTUNE_H + +enum polaris10_pt_config_reg_type { + POLARIS10_CONFIGREG_MMR = 0, + POLARIS10_CONFIGREG_SMC_IND, + POLARIS10_CONFIGREG_DIDT_IND, + POLARIS10_CONFIGREG_CACHE, + POLARIS10_CONFIGREG_MAX +}; + +/* PowerContainment Features */ +#define POWERCONTAINMENT_FEATURE_DTE 0x00000001 +#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002 +#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004 + +struct polaris10_pt_config_reg { + uint32_t offset; + uint32_t mask; + uint32_t shift; + uint32_t value; + enum polaris10_pt_config_reg_type type; +}; + +struct polaris10_pt_defaults { + uint8_t SviLoadLineEn; + uint8_t SviLoadLineVddC; + uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; + uint8_t TDC_MAWt; + uint8_t TdcWaterfallCtl; + uint8_t DTEAmbientTempBase; + + uint32_t DisplayCac; + uint32_t BAPM_TEMP_GRADIENT; + uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS]; + uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS]; +}; + +void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr); +int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr); +int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr); +int polaris10_enable_smc_cac(struct pp_hwmgr *hwmgr); +int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr); +int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); +int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr); + +#endif /* POLARIS10_POWERTUNE_H */ + diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c new file mode 100644 index 0000000..d2f553d --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c @@ -0,0 +1,711 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "polaris10_thermal.h" +#include "polaris10_hwmgr.h" +#include "polaris10_smumgr.h" +#include "polaris10_ppsmc.h" +#include "smu/smu_7_1_3_d.h" +#include "smu/smu_7_1_3_sh_mask.h" + +int polaris10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, + struct phm_fan_speed_info *fan_speed_info) +{ + if (hwmgr->thermal_controller.fanInfo.bNoFan) + return 0; + + fan_speed_info->supports_percent_read = true; + fan_speed_info->supports_percent_write = true; + fan_speed_info->min_percent = 0; + fan_speed_info->max_percent = 100; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_FanSpeedInTableIsRPM) && + hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { + fan_speed_info->supports_rpm_read = true; + fan_speed_info->supports_rpm_write = true; + fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM; + fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM; + } else { + fan_speed_info->min_rpm = 0; + fan_speed_info->max_rpm = 0; + } + + return 0; +} + +int polaris10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, + uint32_t *speed) +{ + uint32_t duty100; + uint32_t duty; + uint64_t tmp64; + + if (hwmgr->thermal_controller.fanInfo.bNoFan) + return 0; + + duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL1, FMAX_DUTY100); + duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_STATUS, FDO_PWM_DUTY); + + if (duty100 == 0) + return -EINVAL; + + + tmp64 = (uint64_t)duty * 100; + do_div(tmp64, duty100); + *speed = (uint32_t)tmp64; + + if (*speed > 100) + *speed = 100; + + return 0; +} + +int polaris10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) +{ + uint32_t tach_period; + uint32_t crystal_clock_freq; + + if (hwmgr->thermal_controller.fanInfo.bNoFan || + (hwmgr->thermal_controller.fanInfo. + ucTachometerPulsesPerRevolution == 0)) + return 0; + + tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_TACH_STATUS, TACH_PERIOD); + + if (tach_period == 0) + return -EINVAL; + + crystal_clock_freq = tonga_get_xclk(hwmgr); + + *speed = 60 * crystal_clock_freq * 10000 / tach_period; + + return 0; +} + +/** +* Set Fan Speed Control to static mode, so that the user can decide what speed to use. +* @param hwmgr the address of the powerplay hardware manager. +* mode the fan control mode, 0 default, 1 by percent, 5, by RPM +* @exception Should always succeed. +*/ +int polaris10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) +{ + + if (hwmgr->fan_ctrl_is_in_default_mode) { + hwmgr->fan_ctrl_default_mode = + PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, FDO_PWM_MODE); + hwmgr->tmin = + PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, TMIN); + hwmgr->fan_ctrl_is_in_default_mode = false; + } + + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, TMIN, 0); + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, FDO_PWM_MODE, mode); + + return 0; +} + +/** +* Reset Fan Speed Control to default mode. +* @param hwmgr the address of the powerplay hardware manager. +* @exception Should always succeed. +*/ +int polaris10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) +{ + if (!hwmgr->fan_ctrl_is_in_default_mode) { + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode); + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, TMIN, hwmgr->tmin); + hwmgr->fan_ctrl_is_in_default_mode = true; + } + + return 0; +} + +int polaris10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) +{ + int result; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ODFuzzyFanControlSupport)) { + cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY); + result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_FanSpeedInTableIsRPM)) + hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr, + hwmgr->thermal_controller. + advanceFanControlParameters.usMaxFanRPM); + else + hwmgr->hwmgr_func->set_max_fan_pwm_output(hwmgr, + hwmgr->thermal_controller. + advanceFanControlParameters.usMaxFanPWM); + + } else { + cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE); + result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl); + } + + if (!result && hwmgr->thermal_controller. + advanceFanControlParameters.ucTargetTemperature) + result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetFanTemperatureTarget, + hwmgr->thermal_controller. + advanceFanControlParameters.ucTargetTemperature); + + return result; +} + + +int polaris10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) +{ + return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl); +} + +/** +* Set Fan Speed in percent. +* @param hwmgr the address of the powerplay hardware manager. +* @param speed is the percentage value (0% - 100%) to be set. +* @exception Fails is the 100% setting appears to be 0. +*/ +int polaris10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, + uint32_t speed) +{ + uint32_t duty100; + uint32_t duty; + uint64_t tmp64; + + if (hwmgr->thermal_controller.fanInfo.bNoFan) + return 0; + + if (speed > 100) + speed = 100; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl)) + polaris10_fan_ctrl_stop_smc_fan_control(hwmgr); + + duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL1, FMAX_DUTY100); + + if (duty100 == 0) + return -EINVAL; + + tmp64 = (uint64_t)speed * 100; + do_div(tmp64, duty100); + duty = (uint32_t)tmp64; + + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL0, FDO_STATIC_DUTY, duty); + + return polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); +} + +/** +* Reset Fan Speed to default. +* @param hwmgr the address of the powerplay hardware manager. +* @exception Always succeeds. +*/ +int polaris10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) +{ + int result; + + if (hwmgr->thermal_controller.fanInfo.bNoFan) + return 0; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl)) { + result = polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); + if (!result) + result = polaris10_fan_ctrl_start_smc_fan_control(hwmgr); + } else + result = polaris10_fan_ctrl_set_default_mode(hwmgr); + + return result; +} + +/** +* Set Fan Speed in RPM. +* @param hwmgr the address of the powerplay hardware manager. +* @param speed is the percentage value (min - max) to be set. +* @exception Fails is the speed not lie between min and max. +*/ +int polaris10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) +{ + uint32_t tach_period; + uint32_t crystal_clock_freq; + + if (hwmgr->thermal_controller.fanInfo.bNoFan || + (hwmgr->thermal_controller.fanInfo. + ucTachometerPulsesPerRevolution == 0) || + (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || + (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM)) + return 0; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl)) + polaris10_fan_ctrl_stop_smc_fan_control(hwmgr); + + crystal_clock_freq = tonga_get_xclk(hwmgr); + + tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); + + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_TACH_STATUS, TACH_PERIOD, tach_period); + + return polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); +} + +/** +* Reads the remote temperature from the SIslands thermal controller. +* +* @param hwmgr The address of the hardware manager. +*/ +int polaris10_thermal_get_temperature(struct pp_hwmgr *hwmgr) +{ + int temp; + + temp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_MULT_THERMAL_STATUS, CTF_TEMP); + + /* Bit 9 means the reading is lower than the lowest usable value. */ + if (temp & 0x200) + temp = POLARIS10_THERMAL_MAXIMUM_TEMP_READING; + else + temp = temp & 0x1ff; + + temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + + return temp; +} + +/** +* Set the requested temperature range for high and low alert signals +* +* @param hwmgr The address of the hardware manager. +* @param range Temperature range to be programmed for high and low alert signals +* @exception PP_Result_BadInput if the input data is not valid. +*/ +static int polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, + uint32_t low_temp, uint32_t high_temp) +{ + uint32_t low = POLARIS10_THERMAL_MINIMUM_ALERT_TEMP * + PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + uint32_t high = POLARIS10_THERMAL_MAXIMUM_ALERT_TEMP * + PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + + if (low < low_temp) + low = low_temp; + if (high > high_temp) + high = high_temp; + + if (low > high) + return -EINVAL; + + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_INT, DIG_THERM_INTH, + (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_INT, DIG_THERM_INTL, + (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_CTRL, DIG_THERM_DPM, + (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); + + return 0; +} + +/** +* Programs thermal controller one-time setting registers +* +* @param hwmgr The address of the hardware manager. +*/ +static int polaris10_thermal_initialize(struct pp_hwmgr *hwmgr) +{ + if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_TACH_CTRL, EDGE_PER_REV, + hwmgr->thermal_controller.fanInfo. + ucTachometerPulsesPerRevolution - 1); + + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28); + + return 0; +} + +/** +* Enable thermal alerts on the RV770 thermal controller. +* +* @param hwmgr The address of the hardware manager. +*/ +static int polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr) +{ + uint32_t alert; + + alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_INT, THERM_INT_MASK); + alert &= ~(POLARIS10_THERMAL_HIGH_ALERT_MASK | POLARIS10_THERMAL_LOW_ALERT_MASK); + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_INT, THERM_INT_MASK, alert); + + /* send message to SMU to enable internal thermal interrupts */ + return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable); +} + +/** +* Disable thermal alerts on the RV770 thermal controller. +* @param hwmgr The address of the hardware manager. +*/ +static int polaris10_thermal_disable_alert(struct pp_hwmgr *hwmgr) +{ + uint32_t alert; + + alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_INT, THERM_INT_MASK); + alert |= (POLARIS10_THERMAL_HIGH_ALERT_MASK | POLARIS10_THERMAL_LOW_ALERT_MASK); + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_THERMAL_INT, THERM_INT_MASK, alert); + + /* send message to SMU to disable internal thermal interrupts */ + return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable); +} + +/** +* Uninitialize the thermal controller. +* Currently just disables alerts. +* @param hwmgr The address of the hardware manager. +*/ +int polaris10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) +{ + int result = polaris10_thermal_disable_alert(hwmgr); + + if (!hwmgr->thermal_controller.fanInfo.bNoFan) + polaris10_fan_ctrl_set_default_mode(hwmgr); + + return result; +} + +/** +* Set up the fan table to control the fan using the SMC. +* @param hwmgr the address of the powerplay hardware manager. +* @param pInput the pointer to input data +* @param pOutput the pointer to output data +* @param pStorage the pointer to temporary storage +* @param Result the last failure code +* @return result from set temperature range routine +*/ +int tf_polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; + uint32_t duty100; + uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; + uint16_t fdo_min, slope1, slope2; + uint32_t reference_clock; + int res; + uint64_t tmp64; + + if (data->fan_table_start == 0) { + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl); + return 0; + } + + duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, + CG_FDO_CTRL1, FMAX_DUTY100); + + if (duty100 == 0) { + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl); + return 0; + } + + tmp64 = hwmgr->thermal_controller.advanceFanControlParameters. + usPWMMin * duty100; + do_div(tmp64, 10000); + fdo_min = (uint16_t)tmp64; + + t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - + hwmgr->thermal_controller.advanceFanControlParameters.usTMin; + t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - + hwmgr->thermal_controller.advanceFanControlParameters.usTMed; + + pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - + hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin; + pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - + hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed; + + slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); + slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); + + fan_table.TempMin = cpu_to_be16((50 + hwmgr-> + thermal_controller.advanceFanControlParameters.usTMin) / 100); + fan_table.TempMed = cpu_to_be16((50 + hwmgr-> + thermal_controller.advanceFanControlParameters.usTMed) / 100); + fan_table.TempMax = cpu_to_be16((50 + hwmgr-> + thermal_controller.advanceFanControlParameters.usTMax) / 100); + + fan_table.Slope1 = cpu_to_be16(slope1); + fan_table.Slope2 = cpu_to_be16(slope2); + + fan_table.FdoMin = cpu_to_be16(fdo_min); + + fan_table.HystDown = cpu_to_be16(hwmgr-> + thermal_controller.advanceFanControlParameters.ucTHyst); + + fan_table.HystUp = cpu_to_be16(1); + + fan_table.HystSlope = cpu_to_be16(1); + + fan_table.TempRespLim = cpu_to_be16(5); + + reference_clock = tonga_get_xclk(hwmgr); + + fan_table.RefreshPeriod = cpu_to_be32((hwmgr-> + thermal_controller.advanceFanControlParameters.ulCycleDelay * + reference_clock) / 1600); + + fan_table.FdoMax = cpu_to_be16((uint16_t)duty100); + + fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD( + hwmgr->device, CGS_IND_REG__SMC, + CG_MULT_THERMAL_CTRL, TEMP_SEL); + + res = polaris10_copy_bytes_to_smc(hwmgr->smumgr, data->fan_table_start, + (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), + data->sram_end); + + if (!res && hwmgr->thermal_controller. + advanceFanControlParameters.ucMinimumPWMLimit) + res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetFanMinPwm, + hwmgr->thermal_controller. + advanceFanControlParameters.ucMinimumPWMLimit); + + if (!res && hwmgr->thermal_controller. + advanceFanControlParameters.ulMinFanSCLKAcousticLimit) + res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetFanSclkTarget, + hwmgr->thermal_controller. + advanceFanControlParameters.ulMinFanSCLKAcousticLimit); + + if (res) + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl); + + return 0; +} + +/** +* Start the fan control on the SMC. +* @param hwmgr the address of the powerplay hardware manager. +* @param pInput the pointer to input data +* @param pOutput the pointer to output data +* @param pStorage the pointer to temporary storage +* @param Result the last failure code +* @return result from set temperature range routine +*/ +int tf_polaris10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) +{ +/* If the fantable setup has failed we could have disabled + * PHM_PlatformCaps_MicrocodeFanControl even after + * this function was included in the table. + * Make sure that we still think controlling the fan is OK. +*/ + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl)) { + polaris10_fan_ctrl_start_smc_fan_control(hwmgr); + polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); + } + + return 0; +} + +/** +* Set temperature range for high and low alerts +* @param hwmgr the address of the powerplay hardware manager. +* @param pInput the pointer to input data +* @param pOutput the pointer to output data +* @param pStorage the pointer to temporary storage +* @param Result the last failure code +* @return result from set temperature range routine +*/ +int tf_polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) +{ + struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input; + + if (range == NULL) + return -EINVAL; + + return polaris10_thermal_set_temperature_range(hwmgr, range->min, range->max); +} + +/** +* Programs one-time setting registers +* @param hwmgr the address of the powerplay hardware manager. +* @param pInput the pointer to input data +* @param pOutput the pointer to output data +* @param pStorage the pointer to temporary storage +* @param Result the last failure code +* @return result from initialize thermal controller routine +*/ +int tf_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) +{ + return polaris10_thermal_initialize(hwmgr); +} + +/** +* Enable high and low alerts +* @param hwmgr the address of the powerplay hardware manager. +* @param pInput the pointer to input data +* @param pOutput the pointer to output data +* @param pStorage the pointer to temporary storage +* @param Result the last failure code +* @return result from enable alert routine +*/ +int tf_polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) +{ + return polaris10_thermal_enable_alert(hwmgr); +} + +/** +* Disable high and low alerts +* @param hwmgr the address of the powerplay hardware manager. +* @param pInput the pointer to input data +* @param pOutput the pointer to output data +* @param pStorage the pointer to temporary storage +* @param Result the last failure code +* @return result from disable alert routine +*/ +static int tf_polaris10_thermal_disable_alert(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) +{ + return polaris10_thermal_disable_alert(hwmgr); +} + +static int tf_polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) +{ + int ret; + struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + + if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS) + return 0; + + ret = (smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs) == 0) ? + 0 : -1; + + if (!ret) + /* If this param is not changed, this function could fire unnecessarily */ + smu_data->avfs.avfs_btc_status = AVFS_BTC_COMPLETED_PREVIOUSLY; + + return ret; +} + +static struct phm_master_table_item +polaris10_thermal_start_thermal_controller_master_list[] = { + {NULL, tf_polaris10_thermal_initialize}, + {NULL, tf_polaris10_thermal_set_temperature_range}, + {NULL, tf_polaris10_thermal_enable_alert}, + {NULL, tf_polaris10_thermal_avfs_enable}, +/* We should restrict performance levels to low before we halt the SMC. + * On the other hand we are still in boot state when we do this + * so it would be pointless. + * If this assumption changes we have to revisit this table. + */ + {NULL, tf_polaris10_thermal_setup_fan_table}, + {NULL, tf_polaris10_thermal_start_smc_fan_control}, + {NULL, NULL} +}; + +static struct phm_master_table_header +polaris10_thermal_start_thermal_controller_master = { + 0, + PHM_MasterTableFlag_None, + polaris10_thermal_start_thermal_controller_master_list +}; + +static struct phm_master_table_item +polaris10_thermal_set_temperature_range_master_list[] = { + {NULL, tf_polaris10_thermal_disable_alert}, + {NULL, tf_polaris10_thermal_set_temperature_range}, + {NULL, tf_polaris10_thermal_enable_alert}, + {NULL, NULL} +}; + +struct phm_master_table_header +polaris10_thermal_set_temperature_range_master = { + 0, + PHM_MasterTableFlag_None, + polaris10_thermal_set_temperature_range_master_list +}; + +int polaris10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr) +{ + if (!hwmgr->thermal_controller.fanInfo.bNoFan) + polaris10_fan_ctrl_set_default_mode(hwmgr); + return 0; +} + +/** +* Initializes the thermal controller related functions in the Hardware Manager structure. +* @param hwmgr The address of the hardware manager. +* @exception Any error code from the low-level communication. +*/ +int pp_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr) +{ + int result; + + result = phm_construct_table(hwmgr, + &polaris10_thermal_set_temperature_range_master, + &(hwmgr->set_temperature_range)); + + if (!result) { + result = phm_construct_table(hwmgr, + &polaris10_thermal_start_thermal_controller_master, + &(hwmgr->start_thermal_controller)); + if (result) + phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range)); + } + + if (!result) + hwmgr->fan_ctrl_is_in_default_mode = true; + return result; +} + diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h new file mode 100644 index 0000000..62f8cbc --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h @@ -0,0 +1,62 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _POLARIS10_THERMAL_H_ +#define _POLARIS10_THERMAL_H_ + +#include "hwmgr.h" + +#define POLARIS10_THERMAL_HIGH_ALERT_MASK 0x1 +#define POLARIS10_THERMAL_LOW_ALERT_MASK 0x2 + +#define POLARIS10_THERMAL_MINIMUM_TEMP_READING -256 +#define POLARIS10_THERMAL_MAXIMUM_TEMP_READING 255 + +#define POLARIS10_THERMAL_MINIMUM_ALERT_TEMP 0 +#define POLARIS10_THERMAL_MAXIMUM_ALERT_TEMP 255 + +#define FDO_PWM_MODE_STATIC 1 +#define FDO_PWM_MODE_STATIC_RPM 5 + + +extern int tf_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); +extern int tf_polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); +extern int tf_polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); + +extern int polaris10_thermal_get_temperature(struct pp_hwmgr *hwmgr); +extern int polaris10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr); +extern int polaris10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info); +extern int polaris10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed); +extern int polaris10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr); +extern int polaris10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode); +extern int polaris10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed); +extern int polaris10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr); +extern int pp_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr); +extern int polaris10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr); +extern int polaris10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed); +extern int polaris10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed); +extern int polaris10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr); +extern uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr); + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h index a2c87ae..1b44f4e 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h @@ -209,18 +209,18 @@ typedef struct _ATOM_Tonga_PCIE_Table { ATOM_Tonga_PCIE_Record entries[1]; /* Dynamically allocate entries. */ } ATOM_Tonga_PCIE_Table; -typedef struct _ATOM_Ellesmere_PCIE_Record { +typedef struct _ATOM_Polaris10_PCIE_Record { UCHAR ucPCIEGenSpeed; UCHAR usPCIELaneWidth; UCHAR ucReserved[2]; ULONG ulPCIE_Sclk; -} ATOM_Ellesmere_PCIE_Record; +} ATOM_Polaris10_PCIE_Record; -typedef struct _ATOM_Ellesmere_PCIE_Table { +typedef struct _ATOM_Polaris10_PCIE_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Ellesmere_PCIE_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Ellesmere_PCIE_Table; + ATOM_Polaris10_PCIE_Record entries[1]; /* Dynamically allocate entries. */ +} ATOM_Polaris10_PCIE_Table; typedef struct _ATOM_Tonga_MM_Dependency_Record { diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c index ecbc43f..96a2787 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c @@ -493,8 +493,8 @@ static int get_pcie_table( *pp_tonga_pcie_table = pcie_table; } else { - /* Ellesmere/Baffin and newer. */ - const ATOM_Ellesmere_PCIE_Table *atom_pcie_table = (ATOM_Ellesmere_PCIE_Table *)pTable; + /* Polaris10/Polaris11 and newer. */ + const ATOM_Polaris10_PCIE_Table *atom_pcie_table = (ATOM_Polaris10_PCIE_Table *)pTable; PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0), "Invalid PowerPlay Table!", return -1); diff --git a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h deleted file mode 100644 index 18fe230..0000000 --- a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h +++ /dev/null @@ -1,401 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef ELLESMERE_PP_SMC_H -#define ELLESMERE_PP_SMC_H - - -#pragma pack(push, 1) - - -#define PPSMC_SWSTATE_FLAG_DC 0x01 -#define PPSMC_SWSTATE_FLAG_UVD 0x02 -#define PPSMC_SWSTATE_FLAG_VCE 0x04 - -#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 -#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 -#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff - -#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 -#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 -#define PPSMC_SYSTEMFLAG_GDDR5 0x04 - -#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 - -#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 -#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 - -#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 -#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 - -#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 -#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 - - -#define PPSMC_DPM2FLAGS_TDPCLMP 0x01 -#define PPSMC_DPM2FLAGS_PWRSHFT 0x02 -#define PPSMC_DPM2FLAGS_OCP 0x04 - - -#define PPSMC_DISPLAY_WATERMARK_LOW 0 -#define PPSMC_DISPLAY_WATERMARK_HIGH 1 - - -#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 -#define PPSMC_STATEFLAG_POWERBOOST 0x02 -#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04 -#define PPSMC_STATEFLAG_POWERSHIFT 0x08 -#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10 -#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 -#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 - - -#define FDO_MODE_HARDWARE 0 -#define FDO_MODE_PIECE_WISE_LINEAR 1 - -enum FAN_CONTROL { - FAN_CONTROL_FUZZY, - FAN_CONTROL_TABLE -}; - - -#define PPSMC_Result_OK ((uint16_t)0x01) -#define PPSMC_Result_NoMore ((uint16_t)0x02) - -#define PPSMC_Result_NotNow ((uint16_t)0x03) -#define PPSMC_Result_Failed ((uint16_t)0xFF) -#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE) -#define PPSMC_Result_UnknownVT ((uint16_t)0xFD) - -typedef uint16_t PPSMC_Result; - -#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x)) - - -#define PPSMC_MSG_Halt ((uint16_t)0x10) -#define PPSMC_MSG_Resume ((uint16_t)0x11) -#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12) -#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13) -#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14) -#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15) -#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16) -#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17) -#define PPSMC_MSG_LevelUp ((uint16_t)0x18) -#define PPSMC_MSG_LevelDown ((uint16_t)0x19) -#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a) -#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20) -#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f) -#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40) -#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41) -#define PPSMC_MSG_ForceHigh ((uint16_t)0x42) -#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43) -#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51) -#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52) -#define PPSMC_MSG_EnableCac ((uint16_t)0x53) -#define PPSMC_MSG_DisableCac ((uint16_t)0x54) -#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55) -#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56) -#define PPSMC_CACHistoryStart ((uint16_t)0x57) -#define PPSMC_CACHistoryStop ((uint16_t)0x58) -#define PPSMC_TDPClampingActive ((uint16_t)0x59) -#define PPSMC_TDPClampingInactive ((uint16_t)0x5A) -#define PPSMC_StartFanControl ((uint16_t)0x5B) -#define PPSMC_StopFanControl ((uint16_t)0x5C) -#define PPSMC_NoDisplay ((uint16_t)0x5D) -#define PPSMC_HasDisplay ((uint16_t)0x5E) -#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60) -#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61) -#define PPSMC_MSG_EnableULV ((uint16_t)0x62) -#define PPSMC_MSG_DisableULV ((uint16_t)0x63) -#define PPSMC_MSG_EnterULV ((uint16_t)0x64) -#define PPSMC_MSG_ExitULV ((uint16_t)0x65) -#define PPSMC_PowerShiftActive ((uint16_t)0x6A) -#define PPSMC_PowerShiftInactive ((uint16_t)0x6B) -#define PPSMC_OCPActive ((uint16_t)0x6C) -#define PPSMC_OCPInactive ((uint16_t)0x6D) -#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E) -#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F) -#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70) -#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71) -#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72) -#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73) -#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74) -#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75) -#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76) -#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77) -#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78) -#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79) -#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A) -#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B) -#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C) -#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D) - -#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E) -#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F) -#define PPSMC_FlushDataCache ((uint16_t)0x80) -#define PPSMC_FlushInstrCache ((uint16_t)0x81) - -#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82) -#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83) - -#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84) - -#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85) -#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86) -#define PPSMC_MSG_EnableDTE ((uint16_t)0x87) -#define PPSMC_MSG_DisableDTE ((uint16_t)0x88) - -#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89) -#define PPSM_MSG_SmcSpaceWriteDWordInc ((uint16_t)0x8A) -#define PPSM_MSG_SmcSpaceWriteWordInc ((uint16_t)0x8B) -#define PPSM_MSG_SmcSpaceWriteByteInc ((uint16_t)0x8C) - -#define PPSMC_MSG_BREAK ((uint16_t)0xF8) - -#define PPSMC_MSG_Test ((uint16_t) 0x100) -#define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101) -#define PPSMC_MSG_DPM_Config ((uint16_t) 0x102) -#define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103) -#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104) -#define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105) -#define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106) -#define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107) -#define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108) -#define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109) -#define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a) -#define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b) -#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e) -#define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f) -#define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110) -#define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111) -#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112) -#define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113) -#define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114) -#define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117) -#define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118) -#define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119) -#define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a) -#define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b) -#define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c) -#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d) -#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e) -#define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f) -#define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120) -#define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121) -#define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122) -#define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123) -#define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124) -#define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125) -#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126) -#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127) -#define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128) - -#define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129) -#define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A) -#define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B) -#define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C) -#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) -#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) -#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) -#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) -#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) -#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) -#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) -#define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134) -#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) -#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) -#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) -#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) -#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) -#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) -#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b) -#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c) -#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) -#define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e) -#define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f) -#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) -#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) -#define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142) -#define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143) -#define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144) -#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) -#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) -#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) -#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) -#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149) -#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) -#define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b) -#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c) -#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d) - -#define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e) -#define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f) -#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150) -#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151) -#define PPSMC_MSG_LCLKDPM_Enable ((uint16_t) 0x152) -#define PPSMC_MSG_LCLKDPM_Disable ((uint16_t) 0x153) -#define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154) -#define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155) -#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156) -#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157) -#define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158) -#define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159) -#define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a) -#define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b) -#define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t) 0x15c) -#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d) -#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e) -#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) -#define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160) -#define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161) -#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) -#define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163) -#define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164) -#define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165) -#define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166) -#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) -#define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168) -#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) -#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) -#define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b) -#define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t) 0x16c) -#define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t) 0x16d) -#define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t) 0x16e) -#define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t) 0x16f) -#define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170) -#define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171) -#define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172) -#define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173) -#define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174) -#define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175) -#define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176) -#define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177) -#define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178) -#define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179) -#define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a) -#define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b) -#define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c) -#define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d) -#define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e) -#define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f) -#define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180) -#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181) -#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182) -#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184) -#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) -#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) -#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) -#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) -#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) -#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) -#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) -#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) -#define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D) -#define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E) -#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) -#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) -#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) -#define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192) -#define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193) -#define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194) -#define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195) -#define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207) -#define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196) -#define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208) -#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197) -#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198) -#define PPSMC_MSG_SetTjMax ((uint16_t) 0x199) -#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) -#define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B) -#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) -#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) - -#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) -#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) -#define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202) -#define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203) -#define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204) -#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205) -#define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206) -#define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209) -#define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A) - -#define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240) -#define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241) -#define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242) -#define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243) -#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244) -#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245) -#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246) - -#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250) -#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251) -#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252) -#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253) -#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254) -#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255) -#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256) -#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257) -#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258) -#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259) -#define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A) -#define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B) -#define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C) -#define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D) -#define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260) -#define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261) -#define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262) -#define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263) -#define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264) -#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265) -#define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266) -#define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267) -#define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268) -#define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269) -#define PPSMC_MSG_EnableAvfs ((uint16_t) 0x26A) -#define PPSMC_MSG_DisableAvfs ((uint16_t) 0x26B) - -#define PPSMC_MSG_PerformBtc ((uint16_t) 0x26C) -#define PPSMC_MSG_VftTableIsValid ((uint16_t) 0x275) -#define PPSMC_MSG_UseNewGPIOScheme ((uint16_t) 0x277) -#define PPSMC_MSG_GetEnabledPsm ((uint16_t) 0x400) -#define PPSMC_MSG_AgmStartPsm ((uint16_t) 0x401) -#define PPSMC_MSG_AgmReadPsm ((uint16_t) 0x402) -#define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403) -#define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404) - -#define PPSMC_MSG_GFX_CU_PG_ENABLE ((uint16_t) 0x280) -#define PPSMC_MSG_GFX_CU_PG_DISABLE ((uint16_t) 0x281) - -#define PPSMC_MSG_SetGpuPllDfsForSclk ((uint16_t) 0x300) - -typedef uint16_t PPSMC_Msg; - -#define PPSMC_EVENT_STATUS_THERMAL 0x00000001 -#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002 -#define PPSMC_EVENT_STATUS_DC 0x00000004 - -#pragma pack(pop) - -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h deleted file mode 100644 index 997811c..0000000 --- a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h +++ /dev/null @@ -1,10088 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef _ELLESMERE_PWRVIRUS_H -#define _ELLESMERE_PWRVIRUS_H - -#define mmSMC_IND_INDEX_11 0x01AC -#define mmSMC_IND_DATA_11 0x01AD -#define mmCP_HYP_MEC1_UCODE_ADDR 0xf81a -#define mmCP_HYP_MEC1_UCODE_DATA 0xf81b -#define mmCP_HYP_MEC2_UCODE_ADDR 0xf81c -#define mmCP_HYP_MEC2_UCODE_DATA 0xf81d - -enum PWR_Command { - PwrCmdNull = 0, - PwrCmdWrite, - PwrCmdEnd, - PwrCmdMax -}; - -typedef enum PWR_Command PWR_Command; - -struct PWR_Command_Table { - PWR_Command command; - uint32_t data; - uint32_t reg; -}; - -typedef struct PWR_Command_Table PWR_Command_Table; - - -#define PWR_VIRUS_TABLE_SIZE 10031 - -static PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = { - { PwrCmdWrite, 0x00000000, mmRLC_CNTL }, - { PwrCmdWrite, 0x00000002, mmRLC_SRM_CNTL }, - { PwrCmdWrite, 0x15000000, mmCP_ME_CNTL }, - { PwrCmdWrite, 0x50000000, mmCP_MEC_CNTL }, - { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, - { PwrCmdWrite, 0x0840800a, mmCP_RB0_CNTL }, - { PwrCmdWrite, 0xf30fff0f, mmTCC_CTRL }, - { PwrCmdWrite, 0x00000002, mmTCC_EXE_DISABLE }, - { PwrCmdWrite, 0x000000ff, mmTCP_ADDR_CONFIG }, - { PwrCmdWrite, 0x540ff000, mmCP_CPC_IC_BASE_LO }, - { PwrCmdWrite, 0x000000b4, mmCP_CPC_IC_BASE_HI }, - { PwrCmdWrite, 0x00010000, mmCP_HYP_MEC1_UCODE_ADDR }, - { PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00221408, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00591260, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00621387, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, - { PwrCmdWrite, 0x00010000, mmCP_HYP_MEC2_UCODE_ADDR }, - { PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00221408, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00591260, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00621387, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, - { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, - { PwrCmdWrite, 0x540fe800, mmCP_DFY_ADDR_LO }, - { PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e020201, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e040204, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e060205, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x54106f00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000400b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00004000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00804fac, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, - { PwrCmdWrite, 0x540fef00, mmCP_DFY_ADDR_LO }, - { PwrCmdWrite, 0xc0031502, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00001e00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, - { PwrCmdWrite, 0x540ff000, mmCP_DFY_ADDR_LO }, - { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000145, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94800001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4080061, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24ccffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3cd08000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9500fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1cd0ffcf, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d018001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x050c0019, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x84c00000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000023, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000067, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000006a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000006d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000079, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000084, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000008f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000099, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800000a0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800000af, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x388c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x08880002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98800003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000002d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc000004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d808001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc800005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24cc0700, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x10cc0014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d0d000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000005d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14d00011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c01b10, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00e0080, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00e0800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x280c0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x280c0010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x280c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ca88004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc800079, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc00006f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28180080, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97400001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd4c0380, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdcc0388, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55dc0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdcc038c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce0c0390, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce0c0394, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce4c0398, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56640020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce4c039c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce8c03a0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56a80020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce8c03a4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcecc03a8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcecc03ac, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf0c03b0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x57300020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf0c03b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf4c03b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x57740020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf4c03bc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf8c03c0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x57b80020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf8c03c4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfcc03c8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x57fc0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfcc03cc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9000033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25dc0010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05dc002f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc12009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d200a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc012009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9000034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25e01c00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12200013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25e40300, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12640008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25e800c0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a80002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25ec003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e25c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7eae400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31100006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9500007b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc1c200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4df0388, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4d7038c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d5dc01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4e30390, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4d70394, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d62001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4e70398, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4d7039c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d66401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4eb03a0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4d703a4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d6a801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4ef03a8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4d703ac, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d6ec01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4f303b0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4d703b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d73001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4f703b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4d703bc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d77401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4fb03c0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4d703c4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d7b801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4ff03c8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4d703cc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d7fc01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4d70380, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0083, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc0e0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c0000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0085, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18cc006a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9900fffa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400051, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04180018, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1aac0027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80080, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00017, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04080002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080250, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080228, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000367, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9880fff3, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04080010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd80c0309, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd80c0319, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9880fffc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00e0100, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d0003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24d4001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24d80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x155c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05e80180, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc410001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000031, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9900091a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05280196, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d4fe04, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800001b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000032b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000350, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000352, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000035f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000701, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000047c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000019f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc419325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1d98001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd81325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0044, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27fc0003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c00006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9400036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15540008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd40005b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd40005d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd840006d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11540015, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1998003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1af0007d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15dc000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d65400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300018, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a38003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dd5c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7df1c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800045, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411326a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc415326b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc419326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d326d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425326e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4293279, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800077, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd000056, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800058, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00059, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x259c8000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce40005a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29988000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd000073, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17300019, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25140fff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800003a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4153279, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400077, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd00005f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26f00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15100010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd000035, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000035, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1af07fe8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43dc031, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04343000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf413267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dd1c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45dc0160, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc810001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b4c0057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f4f400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55180020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1af4007d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33740003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26d80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1ae8003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9680000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96800009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2a640002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce413277, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce413348, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x958000d8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000315, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04303000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96800041, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1714000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25540800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x459801b0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d77400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x199c01e2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3e5c0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400015, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a640002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1334e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01334f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd413350, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813351, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd881334d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193273, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3275, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113270, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4153274, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cdcc011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05900008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd00006a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc0006b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d594002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc12e23, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd012e24, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc12e25, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15540002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b340057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b280213, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980198, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd40000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd40000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x20cc003c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdd430000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc01e0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29dc0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2d540002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x078c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001239, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04f80000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dd5c005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd840007c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400069, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c018a6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4412e22, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800007c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c018a2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0019, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd4c005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24cc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9680fffc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd0c002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9680fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd013275, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9540188f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc013cfff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd0c009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x38d00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99000006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04cc0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdcc30000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c01882, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000304, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x49980198, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x459801a0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000329, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16ec001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1998003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00031, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce00000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a18003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94800015, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c0000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24dc00ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31e00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580fff0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95801827, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14dc0011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800006d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a0000ad, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04200032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04080000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27fc0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1af4003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9740004d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4080060, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ca88005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24880001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f4b4009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97400046, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313274, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d33400c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97400009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1eecffdd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf013273, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf013275, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800003c3, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc429326f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1aa80030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96800006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28240001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e6a8004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800035, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25cc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19e80042, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25dc0006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e8e800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de9c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4293270, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ce8c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd30011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11e80007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd300001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b30003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33300000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4240059, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1660001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e320009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0328000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e72400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0430000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc02ac000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d310002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17300002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa87600, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd0c011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd0c00025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280222, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4280058, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x22ec003d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce813275, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800007b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8380018, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x57b00020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04343108, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc429325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2374007e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32a80003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94800003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800003e7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04200022, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04200010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980104, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x49980104, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800003f2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380081, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf813279, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf41326e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01326d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c0000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x254c0700, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a641fe8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0726, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2a640200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1237b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8813260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4240033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4280034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9000036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce40000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c01755, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9680000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce80000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xde830000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce80000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c0174c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2bb80040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100044, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19180024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x551c003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000043d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00c8000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd840006c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28200000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000043f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x282000f0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000053, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x195c00e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc5e124dc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e624001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3255, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980158, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x49980158, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980170, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16200010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc429324f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x195400e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1154000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18dc00e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05e80488, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18f807f0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e40077, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18ec0199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000048e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000494, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800004de, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000685, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000686, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800006ac, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1ccc001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4293254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1264000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d79400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e7a400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52a8001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15180001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1aec0028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d325c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800004cc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc419324e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26e8003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d324d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d324f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d290004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f8f4001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f52800f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50e00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800004d1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d0dc002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e5e401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f534002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800004d7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3257, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4213259, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52200002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x259c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15980004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05e804e3, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800004e7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800004f0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000505, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9640fff4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26edf000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05a80507, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000050c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000528, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000057d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800005c2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800005f3, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c0000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99000008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1be00fe4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce413260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000066, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400068, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c0000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99000009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c0060, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ed6c005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113271, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4153270, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193272, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3273, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280022, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d51401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4213275, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253276, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1400061, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2730000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7db1800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800060, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05dc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00062, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd000063, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000064, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400065, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b700057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b680213, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x46ec0188, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26e01000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9c131fc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x192007ec, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x69dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de20014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x561c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce013344, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc13345, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800068, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2010007d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100060, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2010003d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9540000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013344, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013345, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180050, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c0052, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280042, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813273, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc13275, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9000068, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00124f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x46ec0190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4153249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2154003d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bd800e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc420004d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc0010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd413249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce01326f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f598004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1be800e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce80005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801327a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800005f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800007f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424004c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41326e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41325e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xda000068, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9540002d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1be000e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc63124dc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fc14001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000697, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25100007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31100005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9900008e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a9feff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d30b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00ac006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00e0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28880700, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c0006de, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x30d4000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41530b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19980028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800006c8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8380023, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fa38011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd3800025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x202400d0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28240006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd81a2a4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c0000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000712, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05e80714, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000071c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000720, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000747, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000071d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800007c4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000732, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000745, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000744, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c00006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c0000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2a64008c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce413265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b301fe8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c0fff1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000723, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41f02f1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000743, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c0ffde, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x041c3000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25dc8000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c004a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x195800e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418004c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd81326e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc0005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25dd7fff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e1a001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x46200200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04283247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1af80057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1af40213, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f6f400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc6990000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x329c325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x329c3269, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c00006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x329c3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc01defff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d9d8009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000078a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25980000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00fff2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc03e7ff0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f3f0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf013249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc03e4000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc13254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b300028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9900000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d30b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bf0003a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b000b80, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x203c003a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300700, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf0130b7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc130b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x46200008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x259c0003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc800010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31980002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19580066, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0120001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11980003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da18001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d24db, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd0c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40fff8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580137b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00ee000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113269, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19080070, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x190c00e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2510003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2518000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05a80809, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000080e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000080f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000898, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000946, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800009e1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04a80811, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000815, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000834, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3045, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1c091, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b000241, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b000003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc02f0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4252087, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x5668001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a80005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00021d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x040c0005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001a41, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43b02f1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec80278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56f00020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf080280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31100011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x950001fa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aec0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc01c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0180001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11a40006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de6000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x10e40008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e2e000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2110003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1d10ff9e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801325e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0245301, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801325f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0121fff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29108eff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0127ff0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0131fff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801326d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801326e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013279, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0100010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dd2400c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0180003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dd1c002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04a8089a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000089e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800008fa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31300022, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x964012a4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc02620c0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01c082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41c083, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0260400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000903, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31240022, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ec30011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32f80000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x67180001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0bfc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x57300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd981325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000915, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9c1325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc0fff6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f818001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001606, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d838001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94800010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3259, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16240014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12640014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a2801f0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a80010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013259, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00075e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4af0228, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1330000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13f40014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07fc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33e80010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9680ffec, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04a80948, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000094c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000099b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9740002c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x964011fe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0260010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01c080, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41c081, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0260800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dda801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e838011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001802, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x469c0390, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4280011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c0011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c0014df, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31280014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce8802ef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a800062, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31280034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a800060, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04a809e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800009ec, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000a45, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b30258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e72401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x66740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97400041, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04383000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4393267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b38007e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x4598001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf4002eb, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf4002ec, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf4002ed, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf4002ee, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001715, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0ffbc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94800005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000a55, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x233c0032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc130b6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf0130b6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc49302ef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x5198001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193269, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2598000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013268, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x53b8001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7db9801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000a5e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c01106, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c010fd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50640020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ce4c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc80c0072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x58e801fc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a80009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18dc01e2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3e5c0003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9540000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x44cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55900020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4140011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x44cc0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd812e01, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd012e02, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd412e03, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc410001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4140028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95000005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1e64001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14d00010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ab1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc420001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a0010ac, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd880003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c0003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d403f7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41b0367, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d85800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d001fc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05280adc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000af1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000adf, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ae7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd8d2000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c00010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d803f7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11940014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29544001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29544003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000af4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd44d2000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd44dc000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d0003c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95000006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd8d2c00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000b0a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd44d2c00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28148004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24d800ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00019, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4593240, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c0105e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d324f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313255, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef3400c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14e80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a8000af, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c01043, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18a01fe8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3620005c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a00000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2464003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc6290ce7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16ac001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26ac003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ee6c00d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a00fff8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000367, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9640102e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x199c0037, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19a00035, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c0005d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16f8001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9780000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc035f0ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e764009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19b401f8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce413248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1ae4003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000b7c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19a4003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bfc01e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13fc0018, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dbd800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1d98ff15, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x592c00fc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd80000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12e00016, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x592c007e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12e00015, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11a0000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1264001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1620000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12e4001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x5924007e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12640017, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12640018, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd013257, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd413258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00fdb, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9780f5ca, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07740003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x269c003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e5e4004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f67000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f674002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1ab8c006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000bec, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000b47, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc03a8004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc415325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18580037, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x262001ef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d15400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1d54001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd280200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd680208, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcda80210, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b400014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800017, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc6930200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc6970208, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc69b0210, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd900003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd940003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9000040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9400040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14fc0011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24f800ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33b80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d83c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94800020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00016, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800015, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24e000ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x321c0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580ffee, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c00014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000c30, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9480000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800f29, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800f23, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800f1a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x041c0003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9600f502, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c0f500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000f05, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16e4001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9640f4f4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc434000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33740002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b40f4f1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12780001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2bb80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00ac005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00e0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc8000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28884900, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ff3, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400ee1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41c40a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41c40c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41c40d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24d0007f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15580010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x255400ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01c411, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd81c40f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd41c40e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41c410, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e80033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18ec0034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41c414, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41c415, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd81c413, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18dc0032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c030011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c038011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431c417, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc435c416, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439c419, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43dc418, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf413261, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf013262, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc13263, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf813264, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18dc0030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00017, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d77000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51b80020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f97801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f37001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f3b000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc0000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000018, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ca7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18dc0031, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc435c40b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9740fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4280032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000cf4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc032800b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d42011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24cc007f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96800e6c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x596001fc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ce0c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x505c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc0001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd140001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1c00020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e5e800c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b000024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x122c0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000d1f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96800005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000d57, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0328009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04143000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e51001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d2d0011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19640057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19580213, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19600199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da6400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e26400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1000025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04142000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99400001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d80034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05280d83, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000d8a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000db1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000dbc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e010001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d75400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580f3d8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x526c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e2ec01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x5ae0073a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9940000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580f3c6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc3a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80fffb, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980fff5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16200002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce01c405, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd441c406, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580f3b1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29540002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580f3a5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00da7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x5aac007e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12d80017, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d9d800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56a00020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e82400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e58c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19d4003d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x20880188, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x54ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x20240090, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28240004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf80003a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd901a2a4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd841325f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc429325f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26ac0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26ac0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b301ff0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b300300, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400039, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c0001a2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a80014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2220003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18fc0034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24e8000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80e71, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000edd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ea1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000eaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000e7c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000e87, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000e8f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d9e001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4213262, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253261, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4213264, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253263, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e82005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da1801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1800072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8180072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x59a001fc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd81c400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc421c401, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400041, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425c401, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ede, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3db09001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3db09011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc5a10000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc5a50000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05280eea, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000f11, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000f2e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000f1f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0f26f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7daec01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x5af8073a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7eba800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0f25c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd81c405, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce01c406, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41c406, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0f24e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40f247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0f240, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ef2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3db09002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3db09012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc434000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b780001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf80001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c034001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c038001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01c080, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd41c081, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000f88, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51640020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e52401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01c081, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1334000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24e02000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f63400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc1c083, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000f9d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51e40020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e5a401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13380016, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e00039, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12200019, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1220001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf81c078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc1c084, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31140005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31140006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05280fb7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28140002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000fc2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000fd1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e80039, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52a8003b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c0017, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd140004b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9500000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x159c0011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x259800ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31a00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31a40001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e25800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c0fff5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580fff4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000fef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1d100010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01326f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97400003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0340008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000ffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x208801a8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000102f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1cccfe08, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00b33, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4200025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da2400f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da28002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e1ac002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d2ac002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3ef40010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b40f11d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf81325e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xde410000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xde010000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c024001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8100086, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x5510003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001075, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9900000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100081, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d15800f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d15c002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d520002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cde0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3e20001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x040c0030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1325e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001071, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00b01, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc200000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc40003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4080029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18a400e5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12500009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x248c0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x200c006d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x200c0228, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc410002b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18881fe8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d4072c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18cc00d1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3094000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x38d80000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x311c0003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x30940007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1620001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9940001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000023, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800010c4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c00019, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00041, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418002c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9940000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x259c007f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19a00030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400022, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x199c0fe8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000022, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000023, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000aac, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07a810d8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000104c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc400040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x200c007d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28240007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x192400fd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06681110, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19180070, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19100078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18f40058, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001117, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001118, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000112d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001130, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001133, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc81c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc02a0200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e8e8009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x22a8003d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x22a80074, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2774001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13740014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7eb6800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25ecffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55700020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15f40010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13740002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x275c001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15dc0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x39e00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dc1c01e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e62000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001165, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e1a0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e0d000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95000007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e02401e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06640008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05d80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dc2401e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05e00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da2000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9600ffe6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17640002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4200006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2a200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce00001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce81c078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1c080, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd41c082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12640002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x22640435, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0528117e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x312c0003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001185, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc03a0400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d81c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc130b7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c0049, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19a000e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29a80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de2c00c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc420007d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce40003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800011a3, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d654001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd41326d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c020001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4240081, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800011b6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253279, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2730003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3b380006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3f38000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0430000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb10004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e57000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e578002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d67c002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0be40001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d3a4002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x202c002c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3e640010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce81325e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07a811cf, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00feb8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x954009a7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1c07c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41c07d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41c08c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41c079, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01c07e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18f0012f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18f40612, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18cc00c1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cf7400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x39600004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0140004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18fc003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400041, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800011ee, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a6c003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c00006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04200002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800011e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428002c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96800010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26ac007f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1ab00030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1aac0fe8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001205, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0fffa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc03a2800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc03a0800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc03a4000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x30d00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99000052, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9640090f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19180038, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x30dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c0000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1ab0c006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000127f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d3258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313257, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1ab0c012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a0003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f67800f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c0012e1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x964008d7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9800036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b300677, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800012aa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc03a8002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7edec00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4140032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1858003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d0cc00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d407f0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9900000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d324f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2598003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d5d4001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d52000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d514002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193259, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d958001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dd5c002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813259, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc1325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1ccc001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b000004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b40000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd980003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9c0003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9800040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd9c00040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97800051, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4353249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b74003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50700020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04e81324, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d71401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x596401fc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12640009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b74008d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2a640000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000132c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000133b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001344, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42530b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a68003a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2024003a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25980700, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11980014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d19000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce4130b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80ffea, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8240011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80ffe0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf81a2a4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c007eb, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d0d001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x591c01fc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45140210, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x595801fc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11980009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29dc0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc0001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400069, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce013249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a307fe8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x23304076, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18cc00e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x10cc0015, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x4514020c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce013248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a2001e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2a204001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a64003c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15dc000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dcdc00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e5dc00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45140248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce013257, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce013258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0434000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdb000024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45540008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce013259, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0337fff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f220009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55300020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d01c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c01d0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06ec0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f01c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8240072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd240001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19682011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x5a6c01fc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7eeac00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfa0000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4380007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17b80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d40038, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9540073d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18c80066, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x30880001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d410001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x4220000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc000078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24e80007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24ec0010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac00006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc5310000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001465, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18f02011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x5aec01fc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96800012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a8146a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f1f0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f1b400c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f1b400d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f334002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97400014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000147b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b400012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc0001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e024001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000144a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fbfc00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94800007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800014a9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0328007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc03a0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dd9c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45dc0390, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c428001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c430001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a0800fd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x109c000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce080228, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9880000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0ec75, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26180001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52a80020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x041c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x66580001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc80260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec80288, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf080290, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec80298, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf0802a0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf4802a8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc802b0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd80802b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x178c000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27b8003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cf8c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf8802c0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc802c8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf8802d0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf8802d8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25b8ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24cc000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd2800c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc5230309, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e3a400c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001539, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd880353, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc49b0353, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc48f0228, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd14005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000154f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd080238, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3d200008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd900309, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd910ce7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4190ce6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d918005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d918004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd810ce6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdd1054f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000156e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x090c0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdcd050e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x110c0014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc4001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41230a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41230b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41230c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc41230d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc480329, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc48032a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc4802e0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09940001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x44100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580002c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x69100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000157f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4970290, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc49b0288, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc49b02a0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc49f0298, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x041c0040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dcdc002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d924019, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d26400c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c0fffa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001579, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d010021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d914019, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd480298, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd8802a0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x10d40010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12180016, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc51f0309, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d95800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d62000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdd00309, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce113320, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc49b02b0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18dc01e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dd9400e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c0001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800015aa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4a302b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12240004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4ab02a8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce4c0319, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d9d8002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ea14005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800015bc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d25000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c0fff4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd0d3330, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce0802b8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd8802b0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4ab02e0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1aa807f0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc48f02d0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc49702d8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc49b02c8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc49f02c0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96800028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d4e000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9600000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d964002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cde4002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de94001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd64002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e6a000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800015cd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d698002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd4802d8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x129c0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc50f0319, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11a0000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11140001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1198000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd953300, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e0e000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a8000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce953301, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce100319, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b70280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f73800a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x536c0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9780eb68, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c0003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001609, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x30b40000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b400011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b70258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b30250, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x53780020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb3801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7faf8019, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x67b40001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x57b80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00fffb, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4bb0260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fab8001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf880260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x66f40001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97400005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4353247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f7f4009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b40fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00fff7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x269c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a00018, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12200003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a00060, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06200020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x269c0018, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a00007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a40060, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11dc0006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12200006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b70228, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f514005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001644, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b30248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd080240, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f130005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001688, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f130004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01051e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42d051f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ed2c005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96c0fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01051f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc5170309, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x195c07f0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x196007f6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04340001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x53740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x6b740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001665, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4a702a0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4ab0298, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f634014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8113320, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce480298, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce8802a0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc5170319, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b702b0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x255c000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f5f4001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8113330, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf4802b0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11340001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x195c07e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x196007ee, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8353300, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e1e4001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8353301, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce4802d0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8100309, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc48f0250, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd4c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x64d80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x54cc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580005c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dd2000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3255, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7df5c00c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25980040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800016f1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a7003e6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a700064, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800016df, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800016f2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18fc0064, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00042, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dd9801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc0001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4bf0258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x53fc0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e7e401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x667c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7eebc00c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0fff8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x43300007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x53300002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7db30011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd3000025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc03ec005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2bfca200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x203c003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc13256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c0017f5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18fc01e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc13248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00185b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b40ffd5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0ea24, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14d4001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d52400e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc49f0258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4a30250, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de1801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400017, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d534002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4af0270, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dae4005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000174f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00178a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b40fff3, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4ab0268, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7daa4005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32a0001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001765, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8013256, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c0017f2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b3034b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f13000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf013248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001855, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32a4001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd080260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce880268, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9940ffc0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ec28001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9640005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253255, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431324f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e72400c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a80040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9680fff7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1aa4003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400049, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1aa400e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32680003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a800046, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9640000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4293260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1aa400e4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32640004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800017e2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc027ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2e6400ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e6a4009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a800ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4240009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26640008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19e403e6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26680003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12a80004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26640003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12640003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19e400e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19e40064, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06640003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a640003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800017d0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12640005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ea64002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4292083, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ea68005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a80ffdf, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26a400ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40ffca, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2024007b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800017e3, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4a70280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4ab0278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7eae8014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce480278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce880280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43b02eb, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42302ec, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf813245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce013246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fa3801a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x47b8020c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x15e00008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1220000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2a206032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x513c001e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e3e001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000180f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b3c0077, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ff3000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b300032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd200000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd3800002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400018, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000018, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dc30001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04380032, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf80000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc413248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3269, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27fc000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33fc0003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c00011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0bfc0021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd441326a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x173c0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b300303, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f3f0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ff3c004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc13084, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001842, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x23fc003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc1326d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0bb80026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd441326e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1fb8ffc6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xddc30000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc0000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001852, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc0000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc49f02e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c00018, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c0012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41f02ed, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42302ee, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e2a0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce013084, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x313c0bcc, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x393c051f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3d3c050e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc0000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x393c0560, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3d3c054f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c00007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x393c1538, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3d3c1537, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b740800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e8007c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a8189a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800018c5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800018f2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d0007e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09240002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc42130b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a24002c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14cc0004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7cd8c00a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc130b7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce0130b5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2bb80002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf800024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9600e8a8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9640e8a5, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800018a9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dad800c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c0ffd2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580fff9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x442c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9940fff1, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26240007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9940fff7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc023007f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19e4003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7de1c009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dee000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96000007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x261c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99c0fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9940fff0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18e00064, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06281911, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24cc0003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001915, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x800019af, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001a2b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc48032b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc480333, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc48033b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc480343, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98800011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b3c0057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e3e000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04180000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f438001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00068, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4213254, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a1c003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00065, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e1e0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97800062, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x43bc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fcbc001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc7df032b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e1fc00c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0fffa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c0101, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c0102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001994, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001982, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00ffcb, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001995, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98800009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x41bc0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x53fc0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e7fc011, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd3c00025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x653c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dbd8001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9940ff8f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d91800c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580fff8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9580005d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400058, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95c00053, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e41c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a70003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33240003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a400046, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1a7000e4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001a21, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f270009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x266400ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27240003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06640002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001a0f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e730002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4252083, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e724005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a40ffdf, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x267000ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001a22, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9940ff9f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001a31, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b180057, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e1a000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x30f00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04200005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95800056, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001aa2, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001a90, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf00325b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001aa3, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99800005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd2400025, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x4664001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99800008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2b300008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf000013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x244c00ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc4c0200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc44f0200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc410000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc414000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d158010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x059cc000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccdd0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0037, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc000049, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c003a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9500e69a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d0003b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d40021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd840004a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c003c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x14cc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c00028, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0120840, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x282c0040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001ae8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0121841, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x282c001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01c07c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9ac0fffb, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9940e66b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800004a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0036, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9900fffe, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18cc0021, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc00047, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc000046, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0039, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c003d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24d003ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d47fea, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x18d87ff4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd00004c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd40004e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd80004d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd41c405, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01c406, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x295c0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcdc0001a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11980002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x4110000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0160800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7d15000a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0164010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd41c078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c080, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01c084, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400048, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c003b, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801c40a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd901c40d, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801c410, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801c40e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd801c40f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc40c0040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9940ffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04140096, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1c400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc411c401, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9500fffa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424003e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04d00001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x11100002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd01c40c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0180034, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd81c411, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd841c414, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0a540001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x2468000f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc419c416, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x41980003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc41c003f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7dda0001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x12200002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x10cc0002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xccc1c40c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd901c411, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce41c412, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xce292e40, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc120000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x31144000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xcc3c000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x9780e601, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x188cfff0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x04e40002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x96400003, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80001b74, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, - { PwrCmdWrite, 0x54106500, mmCP_DFY_ADDR_LO }, - { PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e020204, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc00a0505, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xbf8c007f, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xb8900904, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xb8911a04, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xb8920304, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xb8930b44, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x921c0d0c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x921c1c13, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x921d0c12, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x811c1d1c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x811c111c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x921cff1c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000400, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x921dff10, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000100, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x81181d1c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e040218, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, - { PwrCmdWrite, 0x54106900, mmCP_DFY_ADDR_LO }, - { PwrCmdWrite, 0x7e080200, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x7e100204, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xbefc00ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00010000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x24200087, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x262200ff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000001f0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x20222282, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x28182111, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, - { PwrCmdWrite, 0x54116f00, mmCP_DFY_ADDR_LO }, - { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xb4540fe8, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000041, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000000c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x54116f00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xb454105e, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000000c0, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x54117300, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xb4541065, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000500, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000001c, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x54117700, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xb4541069, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000444, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x0000008a, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x54117b00, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, - { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL }, - { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x54116f00, mmCP_MQD_BASE_ADDR }, - { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, - { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, - { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, - { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, - { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, - { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, - { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, - { PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x54117300, mmCP_MQD_BASE_ADDR }, - { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, - { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, - { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, - { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, - { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, - { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, - { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, - { PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x54117700, mmCP_MQD_BASE_ADDR }, - { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, - { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, - { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, - { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, - { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, - { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, - { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, - { PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x54117b00, mmCP_MQD_BASE_ADDR }, - { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, - { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, - { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, - { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, - { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, - { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, - { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, - { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000104, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000204, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000304, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000404, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000504, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000604, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000704, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000105, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000205, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000305, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000405, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000505, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000605, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000705, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000106, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000206, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000306, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000406, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000506, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000606, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000706, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000107, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000207, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000307, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000407, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000507, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000607, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000707, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000008, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000108, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000208, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000308, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000408, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000508, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000608, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000708, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000009, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000109, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000209, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000309, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000409, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000509, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000609, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000709, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, - { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, - { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, - { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL }, - { PwrCmdWrite, 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1 }, - { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, - { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, - { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, - { PwrCmdEnd, 0x00000000, 0x00000000 }, -}; - - -#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h new file mode 100644 index 0000000..0c6a413 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h @@ -0,0 +1,409 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef POLARIS10_PP_SMC_H +#define POLARIS10_PP_SMC_H + + +#pragma pack(push, 1) + + +#define PPSMC_SWSTATE_FLAG_DC 0x01 +#define PPSMC_SWSTATE_FLAG_UVD 0x02 +#define PPSMC_SWSTATE_FLAG_VCE 0x04 + +#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 +#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 +#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff + +#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 +#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 +#define PPSMC_SYSTEMFLAG_GDDR5 0x04 + +#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 + +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 + +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 +#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 + +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 + + +#define PPSMC_DPM2FLAGS_TDPCLMP 0x01 +#define PPSMC_DPM2FLAGS_PWRSHFT 0x02 +#define PPSMC_DPM2FLAGS_OCP 0x04 + + +#define PPSMC_DISPLAY_WATERMARK_LOW 0 +#define PPSMC_DISPLAY_WATERMARK_HIGH 1 + + +#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 +#define PPSMC_STATEFLAG_POWERBOOST 0x02 +#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04 +#define PPSMC_STATEFLAG_POWERSHIFT 0x08 +#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10 +#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 +#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 + + +#define FDO_MODE_HARDWARE 0 +#define FDO_MODE_PIECE_WISE_LINEAR 1 + +enum FAN_CONTROL { + FAN_CONTROL_FUZZY, + FAN_CONTROL_TABLE +}; + + +#define PPSMC_Result_OK ((uint16_t)0x01) +#define PPSMC_Result_NoMore ((uint16_t)0x02) + +#define PPSMC_Result_NotNow ((uint16_t)0x03) +#define PPSMC_Result_Failed ((uint16_t)0xFF) +#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE) +#define PPSMC_Result_UnknownVT ((uint16_t)0xFD) + +typedef uint16_t PPSMC_Result; + +#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x)) + + +#define PPSMC_MSG_Halt ((uint16_t)0x10) +#define PPSMC_MSG_Resume ((uint16_t)0x11) +#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12) +#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13) +#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14) +#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15) +#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16) +#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17) +#define PPSMC_MSG_LevelUp ((uint16_t)0x18) +#define PPSMC_MSG_LevelDown ((uint16_t)0x19) +#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a) +#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20) +#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f) +#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40) +#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41) +#define PPSMC_MSG_ForceHigh ((uint16_t)0x42) +#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43) +#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51) +#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52) +#define PPSMC_MSG_EnableCac ((uint16_t)0x53) +#define PPSMC_MSG_DisableCac ((uint16_t)0x54) +#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55) +#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56) +#define PPSMC_CACHistoryStart ((uint16_t)0x57) +#define PPSMC_CACHistoryStop ((uint16_t)0x58) +#define PPSMC_TDPClampingActive ((uint16_t)0x59) +#define PPSMC_TDPClampingInactive ((uint16_t)0x5A) +#define PPSMC_StartFanControl ((uint16_t)0x5B) +#define PPSMC_StopFanControl ((uint16_t)0x5C) +#define PPSMC_NoDisplay ((uint16_t)0x5D) +#define PPSMC_HasDisplay ((uint16_t)0x5E) +#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60) +#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61) +#define PPSMC_MSG_EnableULV ((uint16_t)0x62) +#define PPSMC_MSG_DisableULV ((uint16_t)0x63) +#define PPSMC_MSG_EnterULV ((uint16_t)0x64) +#define PPSMC_MSG_ExitULV ((uint16_t)0x65) +#define PPSMC_PowerShiftActive ((uint16_t)0x6A) +#define PPSMC_PowerShiftInactive ((uint16_t)0x6B) +#define PPSMC_OCPActive ((uint16_t)0x6C) +#define PPSMC_OCPInactive ((uint16_t)0x6D) +#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E) +#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F) +#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70) +#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71) +#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72) +#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73) +#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74) +#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75) +#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76) +#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77) +#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78) +#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79) +#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A) +#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B) +#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C) +#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D) + +#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E) +#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F) +#define PPSMC_FlushDataCache ((uint16_t)0x80) +#define PPSMC_FlushInstrCache ((uint16_t)0x81) + +#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82) +#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83) + +#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84) + +#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85) +#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86) +#define PPSMC_MSG_EnableDTE ((uint16_t)0x87) +#define PPSMC_MSG_DisableDTE ((uint16_t)0x88) + +#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89) +#define PPSM_MSG_SmcSpaceWriteDWordInc ((uint16_t)0x8A) +#define PPSM_MSG_SmcSpaceWriteWordInc ((uint16_t)0x8B) +#define PPSM_MSG_SmcSpaceWriteByteInc ((uint16_t)0x8C) + +#define PPSMC_MSG_BREAK ((uint16_t)0xF8) + +#define PPSMC_MSG_Test ((uint16_t) 0x100) +#define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101) +#define PPSMC_MSG_DPM_Config ((uint16_t) 0x102) +#define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103) +#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104) +#define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105) +#define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106) +#define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107) +#define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108) +#define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109) +#define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a) +#define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b) +#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e) +#define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f) +#define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110) +#define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111) +#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112) +#define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113) +#define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114) +#define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117) +#define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118) +#define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119) +#define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a) +#define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b) +#define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c) +#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d) +#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e) +#define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f) +#define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120) +#define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121) +#define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122) +#define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123) +#define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124) +#define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125) +#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126) +#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127) +#define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128) + +#define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129) +#define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A) +#define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B) +#define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C) +#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) +#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) +#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) +#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) +#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) +#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) +#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) +#define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134) +#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) +#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) +#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) +#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) +#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) +#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) +#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b) +#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c) +#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) +#define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e) +#define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f) +#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) +#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) +#define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142) +#define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143) +#define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144) +#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) +#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) +#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) +#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) +#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149) +#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) +#define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b) +#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c) +#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d) + +#define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e) +#define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f) +#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150) +#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151) +#define PPSMC_MSG_LCLKDPM_Enable ((uint16_t) 0x152) +#define PPSMC_MSG_LCLKDPM_Disable ((uint16_t) 0x153) +#define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154) +#define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155) +#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156) +#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157) +#define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158) +#define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159) +#define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a) +#define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b) +#define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t) 0x15c) +#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d) +#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e) +#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) +#define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160) +#define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161) +#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) +#define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163) +#define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164) +#define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165) +#define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166) +#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) +#define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168) +#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) +#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) +#define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b) +#define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t) 0x16c) +#define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t) 0x16d) +#define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t) 0x16e) +#define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t) 0x16f) +#define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170) +#define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171) +#define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172) +#define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173) +#define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174) +#define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175) +#define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176) +#define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177) +#define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178) +#define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179) +#define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a) +#define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b) +#define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c) +#define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d) +#define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e) +#define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f) +#define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180) +#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181) +#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182) +#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184) +#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) +#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) +#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) +#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) +#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) +#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) +#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) +#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) +#define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D) +#define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E) +#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) +#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) +#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) +#define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192) +#define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193) +#define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194) +#define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195) +#define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207) +#define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196) +#define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208) +#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197) +#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198) +#define PPSMC_MSG_SetTjMax ((uint16_t) 0x199) +#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) +#define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B) +#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) +#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) + +#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) +#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) +#define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202) +#define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203) +#define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204) +#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205) +#define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206) +#define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209) +#define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A) + +#define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240) +#define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241) +#define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242) +#define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243) +#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244) +#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245) +#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246) + +#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250) +#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251) +#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252) +#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253) +#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254) +#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255) +#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256) +#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257) +#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258) +#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259) +#define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A) +#define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B) +#define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C) +#define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D) +#define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260) +#define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261) +#define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262) +#define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263) +#define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264) +#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265) +#define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266) +#define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267) +#define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268) +#define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269) +#define PPSMC_MSG_EnableAvfs ((uint16_t) 0x26A) +#define PPSMC_MSG_DisableAvfs ((uint16_t) 0x26B) + +#define PPSMC_MSG_PerformBtc ((uint16_t) 0x26C) +#define PPSMC_MSG_VftTableIsValid ((uint16_t) 0x275) +#define PPSMC_MSG_UseNewGPIOScheme ((uint16_t) 0x277) +#define PPSMC_MSG_GetEnabledPsm ((uint16_t) 0x400) +#define PPSMC_MSG_AgmStartPsm ((uint16_t) 0x401) +#define PPSMC_MSG_AgmReadPsm ((uint16_t) 0x402) +#define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403) +#define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404) + +#define PPSMC_MSG_GFX_CU_PG_ENABLE ((uint16_t) 0x280) +#define PPSMC_MSG_GFX_CU_PG_DISABLE ((uint16_t) 0x281) +#define PPSMC_MSG_GetCurrPkgPwr ((uint16_t) 0x282) + +#define PPSMC_MSG_SetGpuPllDfsForSclk ((uint16_t) 0x300) +#define PPSMC_MSG_Didt_Block_Function ((uint16_t) 0x301) + +#define PPSMC_MSG_SecureSRBMWrite ((uint16_t) 0x600) +#define PPSMC_MSG_SecureSRBMRead ((uint16_t) 0x601) +#define PPSMC_MSG_SetAddress ((uint16_t) 0x800) +#define PPSMC_MSG_GetData ((uint16_t) 0x801) +#define PPSMC_MSG_SetData ((uint16_t) 0x802) + +typedef uint16_t PPSMC_Msg; + +#define PPSMC_EVENT_STATUS_THERMAL 0x00000001 +#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002 +#define PPSMC_EVENT_STATUS_DC 0x00000004 + +#pragma pack(pop) + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h new file mode 100644 index 0000000..933103e --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h @@ -0,0 +1,10088 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _POLARIS10_PWRVIRUS_H +#define _POLARIS10_PWRVIRUS_H + +#define mmSMC_IND_INDEX_11 0x01AC +#define mmSMC_IND_DATA_11 0x01AD +#define mmCP_HYP_MEC1_UCODE_ADDR 0xf81a +#define mmCP_HYP_MEC1_UCODE_DATA 0xf81b +#define mmCP_HYP_MEC2_UCODE_ADDR 0xf81c +#define mmCP_HYP_MEC2_UCODE_DATA 0xf81d + +enum PWR_Command { + PwrCmdNull = 0, + PwrCmdWrite, + PwrCmdEnd, + PwrCmdMax +}; + +typedef enum PWR_Command PWR_Command; + +struct PWR_Command_Table { + PWR_Command command; + uint32_t data; + uint32_t reg; +}; + +typedef struct PWR_Command_Table PWR_Command_Table; + + +#define PWR_VIRUS_TABLE_SIZE 10031 + +static PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = { + { PwrCmdWrite, 0x00000000, mmRLC_CNTL }, + { PwrCmdWrite, 0x00000002, mmRLC_SRM_CNTL }, + { PwrCmdWrite, 0x15000000, mmCP_ME_CNTL }, + { PwrCmdWrite, 0x50000000, mmCP_MEC_CNTL }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x0840800a, mmCP_RB0_CNTL }, + { PwrCmdWrite, 0xf30fff0f, mmTCC_CTRL }, + { PwrCmdWrite, 0x00000002, mmTCC_EXE_DISABLE }, + { PwrCmdWrite, 0x000000ff, mmTCP_ADDR_CONFIG }, + { PwrCmdWrite, 0x540ff000, mmCP_CPC_IC_BASE_LO }, + { PwrCmdWrite, 0x000000b4, mmCP_CPC_IC_BASE_HI }, + { PwrCmdWrite, 0x00010000, mmCP_HYP_MEC1_UCODE_ADDR }, + { PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00221408, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00591260, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00621387, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00010000, mmCP_HYP_MEC2_UCODE_ADDR }, + { PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00221408, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00591260, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00621387, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x540fe800, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e020201, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e040204, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e060205, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54106f00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000400b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00004000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00804fac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x540fef00, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0xc0031502, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00001e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x540ff000, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000145, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080061, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24ccffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3cd08000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1cd0ffcf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x050c0019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x84c00000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000067, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000006a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000006d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000008f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000099, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800000a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800000af, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x388c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08880002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98800003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000002d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d808001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc0700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0d000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000005d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d00011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01b10, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x280c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x280c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x280c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca88004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc00006f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28180080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd4c0380, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdcc0388, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55dc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdcc038c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce0c0390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce0c0394, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4c0398, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4c039c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce8c03a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56a80020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce8c03a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcecc03a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcecc03ac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0c03b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0c03b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4c03b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4c03bc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8c03c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57b80020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8c03c4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfcc03c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57fc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfcc03cc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05dc002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc12009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d200a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc012009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25e01c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25e40300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25e800c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25ec003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e25c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31100006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4df0388, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d7038c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d5dc01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4e30390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d70394, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d62001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4e70398, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d7039c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d66401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4eb03a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d6a801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ef03a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703ac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d6ec01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4f303b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d73001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4f703b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703bc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d77401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4fb03c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703c4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d7b801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ff03c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703cc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d7fc01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d70380, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0e0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0085, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc006a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400051, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04180018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aac0027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04080002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000367, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9880fff3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04080010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80c0309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80c0319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9880fffc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d4001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x155c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e80180, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900091a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280196, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d4fe04, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800001b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000032b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000350, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000352, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000035f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000047c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000019f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d98001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0044, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9400036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840006d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11540015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1998003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af0007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15dc000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d65400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a38003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd5c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7df1c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800045, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411326a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc415326b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000056, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00059, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c8000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40005a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29988000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000073, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00005f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26f00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15100010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af07fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04343000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf413267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd1c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0160, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc810001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b4c0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f4f400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55180020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af4007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33740003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ae8003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413348, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x958000d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000315, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04303000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1714000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25540800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x459801b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d77400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c01e2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e5c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1334e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01334f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413350, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813351, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd881334d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153274, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cdcc011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05900008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00006a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0006b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d594002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc12e23, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd012e24, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc12e25, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b340057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b280213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980198, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20cc003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01e0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2d540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x078c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001239, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04f80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd5c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840007c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c018a6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e22, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800007c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c018a2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd4c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680fffc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540188f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc013cfff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x38d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdcc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01882, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000304, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x49980198, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x459801a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000329, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16ec001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1998003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce00000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a18003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24dc00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31e00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95801827, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14dc0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800006d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a0000ad, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af4003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca88005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24880001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f4b4009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313274, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d33400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1eecffdd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800003c3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa80030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a8004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e80042, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e8e800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de9c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce8c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd30011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11e80007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd300001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240059, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1660001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e320009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0328000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e72400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0430000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02ac000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d310002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa87600, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280222, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4280058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x22ec003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8380018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57b00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04343108, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2374007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32a80003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800003e7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980104, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x49980104, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800003f2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf41326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x254c0700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a641fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0726, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a640200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1237b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8813260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4280034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01755, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde830000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0174c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bb80040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100044, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19180024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x551c003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000043d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c8000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840006c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28200000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000043f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282000f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195c00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5e124dc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e624001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980158, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x49980158, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980170, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16200010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1154000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e80488, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f807f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e40077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ec0199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000048e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000494, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000685, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000686, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800006ac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ccc001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1264000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d79400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e7a400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52a8001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec0028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004cc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419324e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26e8003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d324d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d290004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f8f4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f52800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50e00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004d1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0dc002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f534002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004d7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3257, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e804e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004e7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000505, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640fff4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26edf000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05a80507, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000050c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000528, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000057d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800005c2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800005f3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1be00fe4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000066, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ed6c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113271, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193272, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d51401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253276, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400061, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2730000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7db1800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00062, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000063, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400065, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b680213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46ec0188, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26e01000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c131fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x192007ec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x69dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de20014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x561c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013344, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13345, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2010007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2010003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013344, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013345, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280042, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00124f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46ec0190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2154003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bd800e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f598004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1be800e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801327a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800005f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xda000068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540002d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1be000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc63124dc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fc14001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000697, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25100007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31100005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900008e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a9feff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d30b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00ac006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28880700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0006de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30d4000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41530b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19980028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800006c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8380023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa38011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd3800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202400d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000712, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e80714, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000071c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000720, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000747, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000071d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800007c4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000732, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000745, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000744, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a64008c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0fff1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000723, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41f02f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000743, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffde, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc8000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195800e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dd7fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1a001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46200200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04283247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af80057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af40213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6f400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc6990000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x329c325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x329c3269, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x329c3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01defff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d8009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000078a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fff2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03e7ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3f0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03e4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d30b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bf0003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000b80, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x203c003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46200008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31980002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19580066, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0120001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11980003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da18001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d24db, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580137b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00ee000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113269, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19080070, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x190c00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2518000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05a80809, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000080e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000080f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000898, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000946, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800009e1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04a80811, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000815, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000834, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3045, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c091, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000241, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02f0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4252087, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5668001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00021d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001a41, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43b02f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56f00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x950001fa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aec0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a40006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de6000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10e40008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2110003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10ff9e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0245301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0121fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29108eff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0127ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0131fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0100010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd2400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0180003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd1c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04a8089a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000089e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800008fa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31300022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x964012a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02620c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000903, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31240022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ec30011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32f80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x67180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bfc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd981325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000915, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c1325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0fff6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f818001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001606, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d838001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16240014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a2801f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00075e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f40014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33e80010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680ffec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04a80948, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000094c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000099b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x964011fe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dda801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e838011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001802, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x469c0390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4280011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0014df, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31280014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce8802ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800062, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31280034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04a809e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800009ec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a45, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e72401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04383000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b38007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4598001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4002eb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4002ec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4002ed, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4002ee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001715, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffbc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a55, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x233c0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49302ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5198001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193269, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53b8001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7db9801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01106, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c010fd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce4c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc80c0072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x58e801fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc01e2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e5c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x44cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55900020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x44cc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd812e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd012e02, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd412e03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1e64001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ab1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a0010ac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd880003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d403f7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41b0367, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d85800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280adc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000af1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000adf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ae7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd8d2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d803f7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11940014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29544001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29544003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000af4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd44d2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd44dc000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd8d2c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000b0a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd44d2c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28148004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4593240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0105e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef3400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14e80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a8000af, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a01fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3620005c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2464003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc6290ce7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16ac001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ac003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ee6c00d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00fff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000367, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640102e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c0037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a00035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0005d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16f8001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9780000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc035f0ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e764009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19b401f8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ae4003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000b7c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a4003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc01e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13fc0018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dbd800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d98ff15, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x592c00fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd80000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12e00016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x592c007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12e00015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1264001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1620000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12e4001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5924007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013257, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00fdb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9780f5ca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07740003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x269c003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e4004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f67000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f674002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab8c006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000bec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000b47, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a8004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc415325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18580037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x262001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d54001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd280200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd680208, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcda80210, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc6930200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc6970208, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc69b0210, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd900003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd940003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9400040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14fc0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24f800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d83c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24e000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x321c0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580ffee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c30, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9480000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800f29, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800f23, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800f1a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9600f502, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0f500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000f05, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16e4001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640f4f4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33740002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40f4f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00ac005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc8000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28884900, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ff3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400ee1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c40a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c40c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c40d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d0007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15580010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x255400ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c411, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c40f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c40e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c410, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e80033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ec0034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c414, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c415, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c413, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c030011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c038011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431c417, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435c416, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c419, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc418, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf413261, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013262, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13263, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813264, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc0030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d77000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51b80020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f97801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ca7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc0031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435c40b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4280032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000cf4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc032800b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d42011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800e6c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x596001fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce0c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x505c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e800c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x122c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d1f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d57, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0328009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04143000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e51001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d2d0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19640057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19580213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19600199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da6400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04142000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d80034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280d83, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d8a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000db1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000dbc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e010001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d75400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580f3d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x526c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2ec01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5ae0073a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580f3c6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc3a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fff5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01c405, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd441c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580f3b1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580f3a5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00da7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5aac007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12d80017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56a00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e82400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e58c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19d4003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20880188, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20240090, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ac0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ac0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0001a2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2220003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18fc0034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24e8000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80e71, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000edd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ea1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000eaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e7c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e87, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e8f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9e001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213262, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253261, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213264, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253263, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e82005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8180072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x59a001fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421c401, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c401, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ede, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db09001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db09011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5a10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5a50000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280eea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f11, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f2e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f1f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0f26f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7daec01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5af8073a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eba800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0f25c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c405, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0f24e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40f247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0f240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ef2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db09002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db09012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c034001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c038001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f88, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e52401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1334000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24e02000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f63400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f9d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51e40020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13380016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e00039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1220001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31140005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31140006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280fb7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28140002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fc2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fd1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e80039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52a8003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140004b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x159c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31a00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31a40001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e25800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0fff5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fff4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d100010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0340008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x208801a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000102f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1cccfe08, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00b33, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da2400f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da28002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1ac002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d2ac002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3ef40010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40f11d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde410000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde010000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c024001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100086, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5510003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001075, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d520002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cde0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e20001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001071, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00b01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc200000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc40003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a400e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12500009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x248c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x200c006d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x200c0228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18881fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d4072c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc00d1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3094000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x38d80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x311c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30940007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1620001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010c4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a00030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c0fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000aac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07a810d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000104c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x200c007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x192400fd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06681110, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19180070, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19100078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f40058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001117, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001118, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000112d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001130, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001133, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02a0200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e8e8009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x22a8003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x22a80074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2774001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13740014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eb6800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25ecffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55700020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15f40010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13740002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x275c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc1c01e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e62000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001165, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1a0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e0d000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e02401e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05d80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc2401e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da2000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9600ffe6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce00001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x22640435, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0528117e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x312c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001185, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a0400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d81c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de2c00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011a3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d654001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c020001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2730003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3b380006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3f38000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0430000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb10004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e57000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e578002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d67c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0be40001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d3a4002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e640010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07a811cf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00feb8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x954009a7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f0012f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f40612, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc00c1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cf7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39600004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0140004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18fc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011ee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a6c003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ac007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab00030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aac0fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001205, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a2800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30d00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640090f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19180038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab0c006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000127f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313257, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab0c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f67800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0012e1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x964008d7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9800036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300677, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012aa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a8002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7edec00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1858003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0cc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d407f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d5d4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d52000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d514002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d958001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd5c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ccc001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd980003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9800040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800051, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b74003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50700020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04e81324, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d71401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x596401fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b74008d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a640000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000132c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000133b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001344, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42530b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a68003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2024003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11980014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d19000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8240011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffe0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c007eb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0d001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x591c01fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45140210, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x595801fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11980009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a307fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x23304076, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4514020c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a2001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a204001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a64003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15dc000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dcdc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5dc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45140248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013257, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0434000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdb000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0337fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f220009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d01c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f01c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8240072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd240001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19682011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5a6c01fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eeac00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfa0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d40038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540073d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18c80066, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30880001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4220000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24e80007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24ec0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5310000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001465, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f02011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5aec01fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a8146a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1f0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f334002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e024001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000144a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fbfc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800014a9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0328007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c428001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c430001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a0800fd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x109c000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce080228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9880000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0ec75, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52a80020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc80260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80288, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf080290, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0802a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4802a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc802b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80802b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x178c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b8003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cf8c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8802c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc802c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8802d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8802d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25b8ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd2800c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5230309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e3a400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001539, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd880353, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b0353, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd14005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000154f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd080238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d200008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd900309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd910ce7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4190ce6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d918005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d918004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd810ce6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdd1054f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000156e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x090c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdcd050e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x110c0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41230a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41230b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41230c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41230d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc480329, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc48032a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc4802e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09940001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x44100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x69100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000157f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970290, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b0288, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49f0298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dcdc002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d924019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d26400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001579, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d010021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d914019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd480298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd8802a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10d40010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12180016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc51f0309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d95800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d62000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdd00309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce113320, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc01e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9400e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015aa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a302b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab02a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4c0319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d8002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea14005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015bc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d25000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fff4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd0d3330, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce0802b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd8802b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab02e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa807f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f02d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49702d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49f02c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d4e000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9600000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d964002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cde4002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de94001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd64002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015cd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d698002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd4802d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x129c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc50f0319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a0000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1198000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd953300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e0e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a8000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce953301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce100319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b70280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x536c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9780eb68, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001609, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30b40000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b70258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53780020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb3801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7faf8019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x67b40001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bb0260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fab8001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf880260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66f40001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7f4009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fff7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x269c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a00018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a00060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x269c0018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a40060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b70228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f514005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001644, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd080240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f130005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001688, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f130004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01051e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d051f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ed2c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c0fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01051f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5170309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195c07f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x196007f6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x6b740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001665, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a702a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab0298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f634014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8113320, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce480298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce8802a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5170319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b702b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x255c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f5f4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8113330, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4802b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11340001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195c07e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x196007ee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8353300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1e4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8353301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4802d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8100309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd4c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x64d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580005c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd2000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7df5c00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800016f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a7003e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a700064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800016df, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800016f2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18fc0064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00042, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf0258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53fc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e7e401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x667c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eebc00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x43300007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7db30011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd3000025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03ec005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfca200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x203c003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0017f5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18fc01e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00185b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40ffd5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0ea24, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d4001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d52400e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49f0258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a30250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d534002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dae4005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000174f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00178a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40fff3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab0268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7daa4005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32a0001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001765, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0017f2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b3034b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f13000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001855, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32a4001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd080260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce880268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ffc0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ec28001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e72400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680fff7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa4003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32680003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa400e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017e2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc027ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2e6400ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a4009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e403e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26680003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e40064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea64002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4292083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea68005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a400ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2024007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a70280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab0278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae8014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce480278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce880280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43b02eb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42302ec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa3801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x47b8020c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1220000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a206032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x513c001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e3e001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000180f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b3c0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd200000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd3800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc30001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc413248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3269, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33fc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bfc0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd441326a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x173c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3f0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001842, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x23fc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd441326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1fb8ffc6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xddc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001852, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49f02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41f02ed, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42302ee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2a0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x313c0bcc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x393c051f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d3c050e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x393c0560, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d3c054f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x393c1538, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d3c1537, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e8007c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a8189a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800018c5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800018f2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09240002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a24002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14cc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd8c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce0130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bb80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9600e8a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640e8a5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800018a9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dad800c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffd2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fff9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x442c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940fff1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26240007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940fff7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc023007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e4003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dee000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x261c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940fff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e00064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06281911, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001915, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800019af, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a2b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc48032b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc480333, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc48033b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc480343, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98800011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b3c0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e3e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a1c003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00065, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1e0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800062, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x43bc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fcbc001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc7df032b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1fc00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0101, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001994, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001982, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffcb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001995, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x41bc0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53fc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e7fc011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd3c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x653c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dbd8001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ff8f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d91800c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580005d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a70003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33240003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a7000e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a21, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f270009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x266400ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27240003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a0f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e730002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4252083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x267000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a22, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ff9f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001a31, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b180057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1a000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30f00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800056, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001aa2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a90, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001aa3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4664001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x244c00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc4c0200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc44f0200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d158010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x059cc000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccdd0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500e69a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d40021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0120840, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282c0040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001ae8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0121841, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282c001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940e66b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00047, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d003ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d47fea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d87ff4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40004e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd80004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c405, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x295c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11980002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4110000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0160800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0164010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400048, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c40a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901c40d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c410, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c40e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c40f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140096, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411c401, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11100002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c40c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0180034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c411, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841c414, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2468000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419c416, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x41980003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dda0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c40c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901c411, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c412, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce292e40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc120000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31144000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc3c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9780e601, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x188cfff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04e40002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b74, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x54106500, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e020204, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00a0505, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf8c007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb8900904, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb8911a04, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb8920304, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb8930b44, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921c0d0c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921c1c13, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921d0c12, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x811c1d1c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x811c111c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921cff1c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921dff10, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x81181d1c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e040218, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x54106900, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0x7e080200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e100204, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbefc00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00010000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24200087, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x262200ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000001f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20222282, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28182111, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x54116f00, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54116f00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb454105e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54117300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4541065, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54117700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4541069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000444, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000008a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54117b00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL }, + { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x54116f00, mmCP_MQD_BASE_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, + { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, + { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, + { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, + { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, + { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, + { PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x54117300, mmCP_MQD_BASE_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, + { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, + { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, + { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, + { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, + { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, + { PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x54117700, mmCP_MQD_BASE_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, + { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, + { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, + { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, + { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, + { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, + { PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x54117b00, mmCP_MQD_BASE_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, + { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, + { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, + { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, + { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, + { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, + { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000104, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000204, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000304, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000404, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000504, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000604, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000704, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000105, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000205, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000305, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000405, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000505, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000605, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000705, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000106, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000206, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000306, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000406, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000506, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000606, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000706, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000107, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000207, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000307, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000407, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000507, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000607, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000707, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000008, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000108, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000208, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000308, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000408, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000508, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000608, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000708, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000009, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000109, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000209, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000309, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000409, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000509, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000609, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000709, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1 }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdEnd, 0x00000000, 0x00000000 }, +}; + + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h index f816262..f6a7591 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h @@ -705,6 +705,7 @@ struct SMU7_Discrete_Pm_Status_Table { uint16_t Sclk_dpm_residency[8]; uint16_t Uvd_dpm_residency[8]; uint16_t Vce_dpm_residency[8]; + uint16_t Mclk_dpm_residency[4]; uint32_t P_vddci_acc; uint32_t P_vddr1_acc; @@ -779,6 +780,47 @@ typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard; #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 +// DIDT Defines +#define SQ_Enable_MASK 0x1 +#define SQ_IR_MASK 0x2 +#define SQ_PCC_MASK 0x4 +#define SQ_EDC_MASK 0x8 + +#define TCP_Enable_MASK 0x100 +#define TCP_IR_MASK 0x200 +#define TCP_PCC_MASK 0x400 +#define TCP_EDC_MASK 0x800 + +#define TD_Enable_MASK 0x10000 +#define TD_IR_MASK 0x20000 +#define TD_PCC_MASK 0x40000 +#define TD_EDC_MASK 0x80000 + +#define DB_Enable_MASK 0x1000000 +#define DB_IR_MASK 0x2000000 +#define DB_PCC_MASK 0x4000000 +#define DB_EDC_MASK 0x8000000 + +#define SQ_Enable_SHIFT 0 +#define SQ_IR_SHIFT 1 +#define SQ_PCC_SHIFT 2 +#define SQ_EDC_SHIFT 3 + +#define TCP_Enable_SHIFT 8 +#define TCP_IR_SHIFT 9 +#define TCP_PCC_SHIFT 10 +#define TCP_EDC_SHIFT 11 + +#define TD_Enable_SHIFT 16 +#define TD_IR_SHIFT 17 +#define TD_PCC_SHIFT 18 +#define TD_EDC_SHIFT 19 + +#define DB_Enable_SHIFT 24 +#define DB_IR_SHIFT 25 +#define DB_PCC_SHIFT 26 +#define DB_EDC_SHIFT 27 + #pragma pack(pop) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile index 4f751e5..f10fb64 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile @@ -2,7 +2,7 @@ # Makefile for the 'smu manager' sub-component of powerplay. # It provides the smu management services for the driver. -SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o ellesmere_smumgr.o +SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o polaris10_smumgr.o AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR)) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c deleted file mode 100644 index 6395065..0000000 --- a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c +++ /dev/null @@ -1,983 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "smumgr.h" -#include "smu74.h" -#include "smu_ucode_xfer_vi.h" -#include "ellesmere_smumgr.h" -#include "smu74_discrete.h" -#include "smu/smu_7_1_3_d.h" -#include "smu/smu_7_1_3_sh_mask.h" -#include "gmc/gmc_8_1_d.h" -#include "gmc/gmc_8_1_sh_mask.h" -#include "oss/oss_3_0_d.h" -#include "gca/gfx_8_0_d.h" -#include "bif/bif_5_0_d.h" -#include "bif/bif_5_0_sh_mask.h" -#include "ellesmere_pwrvirus.h" -#include "ppatomctrl.h" -#include "pp_debug.h" -#include "cgs_common.h" - -#define ELLESMERE_SMC_SIZE 0x20000 -#define VOLTAGE_SCALE 4 - -/* Microcode file is stored in this buffer */ -#define BUFFER_SIZE 80000 -#define MAX_STRING_SIZE 15 -#define BUFFER_SIZETWO 131072 /* 128 *1024 */ - -#define SMC_RAM_END 0x40000 - -SMU74_Discrete_GraphicsLevel avfs_graphics_level_ellesmere[8] = { - /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */ - /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */ - { 0x3c0fd047, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x30750000, 0, 0, 0, 0, 0, 0, 0 } }, - { 0xa00fd047, 0x01, 0x04, 0x1e00, 0x00800510, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x409c0000, 0, 0, 0, 0, 0, 0, 0 } }, - { 0x0410d047, 0x01, 0x00, 0x1e00, 0x00600410, 0x87020000, 0, 0, 0x0e, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x50c30000, 0, 0, 0, 0, 0, 0, 0 } }, - { 0x6810d047, 0x01, 0x00, 0x1e00, 0x00800410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x60ea0000, 0, 0, 0, 0, 0, 0, 0 } }, - { 0xcc10d047, 0x01, 0x00, 0x1e00, 0x00e00410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xe8fd0000, 0, 0, 0, 0, 0, 0, 0 } }, - { 0x3011d047, 0x01, 0x00, 0x1e00, 0x00400510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x70110100, 0, 0, 0, 0, 0, 0, 0 } }, - { 0x9411d047, 0x01, 0x00, 0x1e00, 0x00a00510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xf8240100, 0, 0, 0, 0, 0, 0, 0 } }, - { 0xf811d047, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x80380100, 0, 0, 0, 0, 0, 0, 0 } } -}; - -SMU74_Discrete_MemoryLevel avfs_memory_level_ellesmere = {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00}; - -/** -* Set the address for reading/writing the SMC SRAM space. -* @param smumgr the address of the powerplay hardware manager. -* @param smcAddress the address in the SMC RAM to access. -*/ -static int ellesmere_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit) -{ - PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL); - PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL); - - cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr); - SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); - - return 0; -} - -/** -* Copy bytes from SMC RAM space into driver memory. -* -* @param smumgr the address of the powerplay SMU manager. -* @param smc_start_address the start address in the SMC RAM to copy bytes from -* @param src the byte array to copy the bytes to. -* @param byte_count the number of bytes to copy. -*/ -int ellesmere_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit) -{ - uint32_t data; - uint32_t addr; - uint8_t *dest_byte; - uint8_t i, data_byte[4] = {0}; - uint32_t *pdata = (uint32_t *)&data_byte; - - PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1;); - PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1); - - addr = smc_start_address; - - while (byte_count >= 4) { - ellesmere_read_smc_sram_dword(smumgr, addr, &data, limit); - - *dest = PP_SMC_TO_HOST_UL(data); - - dest += 1; - byte_count -= 4; - addr += 4; - } - - if (byte_count) { - ellesmere_read_smc_sram_dword(smumgr, addr, &data, limit); - *pdata = PP_SMC_TO_HOST_UL(data); - /* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */ - dest_byte = (uint8_t *)dest; - for (i = 0; i < byte_count; i++) - dest_byte[i] = data_byte[i]; - } - - return 0; -} - -/** -* Copy bytes from an array into the SMC RAM space. -* -* @param pSmuMgr the address of the powerplay SMU manager. -* @param smc_start_address the start address in the SMC RAM to copy bytes to. -* @param src the byte array to copy the bytes from. -* @param byte_count the number of bytes to copy. -*/ -int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, - const uint8_t *src, uint32_t byte_count, uint32_t limit) -{ - int result; - uint32_t data = 0; - uint32_t original_data; - uint32_t addr = 0; - uint32_t extra_shift; - - PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1); - PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1); - - addr = smc_start_address; - - while (byte_count >= 4) { - /* Bytes are written into the SMC addres space with the MSB first. */ - data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; - - result = ellesmere_set_smc_sram_address(smumgr, addr, limit); - - if (0 != result) - return result; - - cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data); - - src += 4; - byte_count -= 4; - addr += 4; - } - - if (0 != byte_count) { - - data = 0; - - result = ellesmere_set_smc_sram_address(smumgr, addr, limit); - - if (0 != result) - return result; - - - original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11); - - extra_shift = 8 * (4 - byte_count); - - while (byte_count > 0) { - /* Bytes are written into the SMC addres space with the MSB first. */ - data = (0x100 * data) + *src++; - byte_count--; - } - - data <<= extra_shift; - - data |= (original_data & ~((~0UL) << extra_shift)); - - result = ellesmere_set_smc_sram_address(smumgr, addr, limit); - - if (0 != result) - return result; - - cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data); - } - - return 0; -} - - -static int ellesmere_program_jump_on_start(struct pp_smumgr *smumgr) -{ - static unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 }; - - ellesmere_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1); - - return 0; -} - -/** -* Return if the SMC is currently running. -* -* @param smumgr the address of the powerplay hardware manager. -*/ -bool ellesmere_is_smc_ram_running(struct pp_smumgr *smumgr) -{ - return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) - && (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C))); -} - -/** -* Send a message to the SMC, and wait for its response. -* -* @param smumgr the address of the powerplay hardware manager. -* @param msg the message to send. -* @return The response that came from the SMC. -*/ -int ellesmere_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) -{ - if (!ellesmere_is_smc_ram_running(smumgr)) - return -1; - - SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); - - if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) - printk("Failed to send Previous Message.\n"); - - - cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); - - SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); - - if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) - printk("Failed to send Message.\n"); - - return 0; -} - - -/** -* Send a message to the SMC, and do not wait for its response. -* -* @param smumgr the address of the powerplay hardware manager. -* @param msg the message to send. -* @return Always return 0. -*/ -int ellesmere_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg) -{ - cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); - - return 0; -} - -/** -* Send a message to the SMC with parameter -* -* @param smumgr: the address of the powerplay hardware manager. -* @param msg: the message to send. -* @param parameter: the parameter to send -* @return The response that came from the SMC. -*/ -int ellesmere_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) -{ - if (!ellesmere_is_smc_ram_running(smumgr)) { - return -1; - } - - SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); - - cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); - - return ellesmere_send_msg_to_smc(smumgr, msg); -} - - -/** -* Send a message to the SMC with parameter, do not wait for response -* -* @param smumgr: the address of the powerplay hardware manager. -* @param msg: the message to send. -* @param parameter: the parameter to send -* @return The response that came from the SMC. -*/ -int ellesmere_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) -{ - cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); - - return ellesmere_send_msg_to_smc_without_waiting(smumgr, msg); -} - -int ellesmere_send_msg_to_smc_offset(struct pp_smumgr *smumgr) -{ - cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000); - - cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test); - - SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); - - if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) - printk("Failed to send Message.\n"); - - return 0; -} - -/** -* Wait until the SMC is doing nithing. Doing nothing means that the SMC is either turned off or it is sitting on the STOP instruction. -* -* @param smumgr the address of the powerplay hardware manager. -* @param msg the message to send. -* @return The response that came from the SMC. -*/ -int ellesmere_wait_for_smc_inactive(struct pp_smumgr *smumgr) -{ - /* If the SMC is not even on it qualifies as inactive. */ - if (!ellesmere_is_smc_ram_running(smumgr)) - return -1; - - SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0); - return 0; -} - - -/** -* Upload the SMC firmware to the SMC microcontroller. -* -* @param smumgr the address of the powerplay hardware manager. -* @param pFirmware the data structure containing the various sections of the firmware. -*/ -static int ellesmere_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit) -{ - uint32_t byte_count = length; - - PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -1); - - cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000); - SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1); - - for (; byte_count >= 4; byte_count -= 4) - cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++); - - SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); - - PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -1); - - return 0; -} - -static enum cgs_ucode_id ellesmere_convert_fw_type_to_cgs(uint32_t fw_type) -{ - enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM; - - switch (fw_type) { - case UCODE_ID_SMU: - result = CGS_UCODE_ID_SMU; - break; - case UCODE_ID_SMU_SK: - result = CGS_UCODE_ID_SMU_SK; - break; - case UCODE_ID_SDMA0: - result = CGS_UCODE_ID_SDMA0; - break; - case UCODE_ID_SDMA1: - result = CGS_UCODE_ID_SDMA1; - break; - case UCODE_ID_CP_CE: - result = CGS_UCODE_ID_CP_CE; - break; - case UCODE_ID_CP_PFP: - result = CGS_UCODE_ID_CP_PFP; - break; - case UCODE_ID_CP_ME: - result = CGS_UCODE_ID_CP_ME; - break; - case UCODE_ID_CP_MEC: - result = CGS_UCODE_ID_CP_MEC; - break; - case UCODE_ID_CP_MEC_JT1: - result = CGS_UCODE_ID_CP_MEC_JT1; - break; - case UCODE_ID_CP_MEC_JT2: - result = CGS_UCODE_ID_CP_MEC_JT2; - break; - case UCODE_ID_RLC_G: - result = CGS_UCODE_ID_RLC_G; - break; - default: - break; - } - - return result; -} - -static int ellesmere_upload_smu_firmware_image(struct pp_smumgr *smumgr) -{ - int result = 0; - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); - - struct cgs_firmware_info info = {0}; - - if (smu_data->security_hard_key == 1) - cgs_get_firmware_info(smumgr->device, - ellesmere_convert_fw_type_to_cgs(UCODE_ID_SMU), &info); - else - cgs_get_firmware_info(smumgr->device, - ellesmere_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info); - - /* TO DO cgs_init_samu_load_smu(smumgr->device, (uint32_t *)info.kptr, info.image_size, smu_data->post_initial_boot);*/ - result = ellesmere_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, ELLESMERE_SMC_SIZE); - - return result; -} - -/** -* Read a 32bit value from the SMC SRAM space. -* ALL PARAMETERS ARE IN HOST BYTE ORDER. -* @param smumgr the address of the powerplay hardware manager. -* @param smcAddress the address in the SMC RAM to access. -* @param value and output parameter for the data read from the SMC SRAM. -*/ -int ellesmere_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit) -{ - int result; - - result = ellesmere_set_smc_sram_address(smumgr, smc_addr, limit); - - if (result) - return result; - - *value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11); - return 0; -} - -/** -* Write a 32bit value to the SMC SRAM space. -* ALL PARAMETERS ARE IN HOST BYTE ORDER. -* @param smumgr the address of the powerplay hardware manager. -* @param smc_addr the address in the SMC RAM to access. -* @param value to write to the SMC SRAM. -*/ -int ellesmere_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit) -{ - int result; - - result = ellesmere_set_smc_sram_address(smumgr, smc_addr, limit); - - if (result) - return result; - - cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value); - - return 0; -} - - -int ellesmere_smu_fini(struct pp_smumgr *smumgr) -{ - if (smumgr->backend) { - kfree(smumgr->backend); - smumgr->backend = NULL; - } - return 0; -} - -/* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */ -static uint32_t ellesmere_get_mask_for_firmware_type(uint32_t fw_type) -{ - uint32_t result = 0; - - switch (fw_type) { - case UCODE_ID_SDMA0: - result = UCODE_ID_SDMA0_MASK; - break; - case UCODE_ID_SDMA1: - result = UCODE_ID_SDMA1_MASK; - break; - case UCODE_ID_CP_CE: - result = UCODE_ID_CP_CE_MASK; - break; - case UCODE_ID_CP_PFP: - result = UCODE_ID_CP_PFP_MASK; - break; - case UCODE_ID_CP_ME: - result = UCODE_ID_CP_ME_MASK; - break; - case UCODE_ID_CP_MEC_JT1: - case UCODE_ID_CP_MEC_JT2: - result = UCODE_ID_CP_MEC_MASK; - break; - case UCODE_ID_RLC_G: - result = UCODE_ID_RLC_G_MASK; - break; - default: - printk("UCode type is out of range! \n"); - result = 0; - } - - return result; -} - -/* Populate one firmware image to the data structure */ - -static int ellesmere_populate_single_firmware_entry(struct pp_smumgr *smumgr, - uint32_t fw_type, - struct SMU_Entry *entry) -{ - int result = 0; - struct cgs_firmware_info info = {0}; - - result = cgs_get_firmware_info(smumgr->device, - ellesmere_convert_fw_type_to_cgs(fw_type), - &info); - - if (!result) { - entry->version = info.version; - entry->id = (uint16_t)fw_type; - entry->image_addr_high = smu_upper_32_bits(info.mc_addr); - entry->image_addr_low = smu_lower_32_bits(info.mc_addr); - entry->meta_data_addr_high = 0; - entry->meta_data_addr_low = 0; - entry->data_size_byte = info.image_size; - entry->num_register_entries = 0; - } - - if (fw_type == UCODE_ID_RLC_G) - entry->flags = 1; - else - entry->flags = 0; - - return 0; -} - -static int ellesmere_request_smu_load_fw(struct pp_smumgr *smumgr) -{ - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); - uint32_t fw_to_load; - - int result = 0; - struct SMU_DRAMData_TOC *toc; - - if (!smumgr->reload_fw) { - printk(KERN_INFO "[ powerplay ] skip reloading...\n"); - return 0; - } - - if (smu_data->soft_regs_start) - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, - smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus), - 0x0); - - ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high); - ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low); - - toc = (struct SMU_DRAMData_TOC *)smu_data->header; - toc->num_entries = 0; - toc->structure_version = 1; - - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - - ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high); - ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low); - - fw_to_load = UCODE_ID_RLC_G_MASK - + UCODE_ID_SDMA0_MASK - + UCODE_ID_SDMA1_MASK - + UCODE_ID_CP_CE_MASK - + UCODE_ID_CP_ME_MASK - + UCODE_ID_CP_PFP_MASK - + UCODE_ID_CP_MEC_MASK; - - if (ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load)) - printk(KERN_ERR "Fail to Request SMU Load uCode"); - - return result; -} - -/* Check if the FW has been loaded, SMU will not return if loading has not finished. */ -static int ellesmere_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type) -{ - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); - uint32_t fw_mask = ellesmere_get_mask_for_firmware_type(fw_type); - uint32_t ret; - /* Check SOFT_REGISTERS_TABLE_28.UcodeLoadStatus */ - ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11, - smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus), - fw_mask, fw_mask); - - return ret; -} - -static int ellesmere_reload_firmware(struct pp_smumgr *smumgr) -{ - return smumgr->smumgr_funcs->start_smu(smumgr); -} - -static int ellesmere_setup_pwr_virus(struct pp_smumgr *smumgr) -{ - int i; - int result = -1; - uint32_t reg, data; - - PWR_Command_Table *pvirus = pwr_virus_table; - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); - - - for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { - switch (pvirus->command) { - case PwrCmdWrite: - reg = pvirus->reg; - data = pvirus->data; - cgs_write_register(smumgr->device, reg, data); - break; - - case PwrCmdEnd: - result = 0; - break; - - default: - printk("Table Exit with Invalid Command!"); - smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; - result = -1; - break; - } - pvirus++; - } - - return result; -} - -static int ellesmere_perform_btc(struct pp_smumgr *smumgr) -{ - int result = 0; - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); - - if (0 != smu_data->avfs.avfs_btc_param) { - if (0 != ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { - printk("[AVFS][SmuEllesmere_PerformBtc] PerformBTC SMU msg failed"); - result = -1; - } - } - if (smu_data->avfs.avfs_btc_param > 1) { - /* Soft-Reset to reset the engine before loading uCode */ - /* halt */ - cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000); - /* reset everything */ - cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff); - cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0); - } - return result; -} - - -int ellesmere_setup_graphics_level_structure(struct pp_smumgr *smumgr) -{ - uint32_t vr_config; - uint32_t dpm_table_start; - - uint16_t u16_boot_mvdd; - uint32_t graphics_level_address, vr_config_address, graphics_level_size; - - graphics_level_size = sizeof(avfs_graphics_level_ellesmere); - u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE); - - PP_ASSERT_WITH_CODE(0 == ellesmere_read_smc_sram_dword(smumgr, - SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable), - &dpm_table_start, 0x40000), - "[AVFS][Ellesmere_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table", - return -1); - - /* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */ - vr_config = 0x01000500; /* Real value:0x50001 */ - - vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig); - - PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, vr_config_address, - (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000), - "[AVFS][Ellesmere_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC", - return -1); - - graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); - - PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address, - (uint8_t *)(&avfs_graphics_level_ellesmere), - graphics_level_size, 0x40000), - "[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of SCLK DPM table failed!", - return -1); - - graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel); - - PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address, - (uint8_t *)(&avfs_memory_level_ellesmere), sizeof(avfs_memory_level_ellesmere), 0x40000), - "[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of MCLK DPM table failed!", - return -1); - - /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */ - - graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd); - - PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address, - (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000), - "[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of DPM table failed!", - return -1); - - return 0; -} - -int ellesmere_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) -{ - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); - - switch (smu_data->avfs.avfs_btc_status) { - case AVFS_BTC_COMPLETED_PREVIOUSLY: - break; - - case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */ - - smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED; - PP_ASSERT_WITH_CODE(0 == ellesmere_setup_graphics_level_structure(smumgr), - "[AVFS][Ellesmere_AVFSEventMgr] Could not Copy Graphics Level table over to SMU", - return -1); - - if (smu_data->avfs.avfs_btc_param > 1) { - printk("[AVFS][Ellesmere_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting."); - smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; - PP_ASSERT_WITH_CODE(-1 == ellesmere_setup_pwr_virus(smumgr), - "[AVFS][Ellesmere_AVFSEventMgr] Could not setup Pwr Virus for AVFS ", - return -1); - } - - smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED; - PP_ASSERT_WITH_CODE(0 == ellesmere_perform_btc(smumgr), - "[AVFS][Ellesmere_AVFSEventMgr] Failure at SmuEllesmere_PerformBTC. AVFS Disabled", - return -1); - - break; - - case AVFS_BTC_DISABLED: - case AVFS_BTC_NOTSUPPORTED: - break; - - default: - printk("[AVFS] Something is broken. See log!"); - break; - } - - return 0; -} - -static int ellesmere_start_smu_in_protection_mode(struct pp_smumgr *smumgr) -{ - int result = 0; - - /* Wait for smc boot up */ - /* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */ - - /* Assert reset */ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, - SMC_SYSCON_RESET_CNTL, rst_reg, 1); - - result = ellesmere_upload_smu_firmware_image(smumgr); - if (result != 0) - return result; - - /* Clear status */ - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); - - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, - SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); - - /* De-assert reset */ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, - SMC_SYSCON_RESET_CNTL, rst_reg, 0); - - - SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); - - - /* Call Test SMU message with 0x20000 offset to trigger SMU start */ - ellesmere_send_msg_to_smc_offset(smumgr); - - /* Wait done bit to be set */ - /* Check pass/failed indicator */ - - SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMU_STATUS, SMU_DONE, 0); - - if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, - SMU_STATUS, SMU_PASS)) - PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); - - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); - - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, - SMC_SYSCON_RESET_CNTL, rst_reg, 1); - - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, - SMC_SYSCON_RESET_CNTL, rst_reg, 0); - - /* Wait for firmware to initialize */ - SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); - - return result; -} - -static int ellesmere_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr) -{ - int result = 0; - - /* wait for smc boot up */ - SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); - - /* Clear firmware interrupt enable flag */ - /* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */ - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, - ixFIRMWARE_FLAGS, 0); - - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, - SMC_SYSCON_RESET_CNTL, - rst_reg, 1); - - result = ellesmere_upload_smu_firmware_image(smumgr); - if (result != 0) - return result; - - /* Set smc instruct start point at 0x0 */ - ellesmere_program_jump_on_start(smumgr); - - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, - SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); - - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, - SMC_SYSCON_RESET_CNTL, rst_reg, 0); - - /* Wait for firmware to initialize */ - - SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, - FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); - - return result; -} - -static int ellesmere_start_smu(struct pp_smumgr *smumgr) -{ - int result = 0; - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); - bool SMU_VFT_INTACT; - - /* Only start SMC if SMC RAM is not running */ - if (!ellesmere_is_smc_ram_running(smumgr)) { - SMU_VFT_INTACT = false; - smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)); - smu_data->security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL)); - - /* Check if SMU is running in protected mode */ - if (smu_data->protected_mode == 0) { - result = ellesmere_start_smu_in_non_protection_mode(smumgr); - } else { - result = ellesmere_start_smu_in_protection_mode(smumgr); - - /* If failed, try with different security Key. */ - if (result != 0) { - smu_data->security_hard_key ^= 1; - result = ellesmere_start_smu_in_protection_mode(smumgr); - } - } - - if (result != 0) - PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); - - ellesmere_avfs_event_mgr(smumgr, true); - } else - SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */ - - smu_data->post_initial_boot = true; - ellesmere_avfs_event_mgr(smumgr, SMU_VFT_INTACT); - /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */ - ellesmere_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters), - &(smu_data->soft_regs_start), 0x40000); - - result = ellesmere_request_smu_load_fw(smumgr); - - return result; -} - -static int ellesmere_smu_init(struct pp_smumgr *smumgr) -{ - struct ellesmere_smumgr *smu_data; - uint8_t *internal_buf; - uint64_t mc_addr = 0; - /* Allocate memory for backend private data */ - smu_data = (struct ellesmere_smumgr *)(smumgr->backend); - smu_data->header_buffer.data_size = - ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096; - smu_data->smu_buffer.data_size = 200*4096; - smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED; -/* Allocate FW image data structure and header buffer and - * send the header buffer address to SMU */ - smu_allocate_memory(smumgr->device, - smu_data->header_buffer.data_size, - CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, - PAGE_SIZE, - &mc_addr, - &smu_data->header_buffer.kaddr, - &smu_data->header_buffer.handle); - - smu_data->header = smu_data->header_buffer.kaddr; - smu_data->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr); - smu_data->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr); - - PP_ASSERT_WITH_CODE((NULL != smu_data->header), - "Out of memory.", - kfree(smumgr->backend); - cgs_free_gpu_mem(smumgr->device, - (cgs_handle_t)smu_data->header_buffer.handle); - return -1); - -/* Allocate buffer for SMU internal buffer and send the address to SMU. - * Iceland SMU does not need internal buffer.*/ - smu_allocate_memory(smumgr->device, - smu_data->smu_buffer.data_size, - CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, - PAGE_SIZE, - &mc_addr, - &smu_data->smu_buffer.kaddr, - &smu_data->smu_buffer.handle); - - internal_buf = smu_data->smu_buffer.kaddr; - smu_data->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr); - smu_data->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr); - - PP_ASSERT_WITH_CODE((NULL != internal_buf), - "Out of memory.", - kfree(smumgr->backend); - cgs_free_gpu_mem(smumgr->device, - (cgs_handle_t)smu_data->smu_buffer.handle); - return -1;); - - return 0; -} - -static const struct pp_smumgr_func ellsemere_smu_funcs = { - .smu_init = ellesmere_smu_init, - .smu_fini = ellesmere_smu_fini, - .start_smu = ellesmere_start_smu, - .check_fw_load_finish = ellesmere_check_fw_load_finish, - .request_smu_load_fw = ellesmere_reload_firmware, - .request_smu_load_specific_fw = NULL, - .send_msg_to_smc = ellesmere_send_msg_to_smc, - .send_msg_to_smc_with_parameter = ellesmere_send_msg_to_smc_with_parameter, - .download_pptable_settings = NULL, - .upload_pptable_settings = NULL, -}; - -int ellesmere_smum_init(struct pp_smumgr *smumgr) -{ - struct ellesmere_smumgr *ellesmere_smu = NULL; - - ellesmere_smu = kzalloc(sizeof(struct ellesmere_smumgr), GFP_KERNEL); - - if (ellesmere_smu == NULL) - return -1; - - smumgr->backend = ellesmere_smu; - smumgr->smumgr_funcs = &ellsemere_smu_funcs; - - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h deleted file mode 100644 index 05d636a..0000000 --- a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _ELLESMERE_SMUMANAGER_H -#define _ELLESMERE_SMUMANAGER_H - -#include -#include - -struct ellesmere_avfs { - enum AVFS_BTC_STATUS avfs_btc_status; - uint32_t avfs_btc_param; -}; - -struct ellesmere_buffer_entry { - uint32_t data_size; - uint32_t mc_addr_low; - uint32_t mc_addr_high; - void *kaddr; - unsigned long handle; -}; - -struct ellesmere_smumgr { - uint8_t *header; - uint8_t *mec_image; - struct ellesmere_buffer_entry smu_buffer; - struct ellesmere_buffer_entry header_buffer; - uint32_t soft_regs_start; - uint8_t *read_rrm_straps; - uint32_t read_drm_straps_mc_address_high; - uint32_t read_drm_straps_mc_address_low; - uint32_t acpi_optimization; - bool post_initial_boot; - uint8_t protected_mode; - uint8_t security_hard_key; - struct ellesmere_avfs avfs; -}; - - -int ellesmere_smum_init(struct pp_smumgr *smumgr); - -int ellesmere_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit); -int ellesmere_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit); -int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, - const uint8_t *src, uint32_t byte_count, uint32_t limit); - -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c new file mode 100644 index 0000000..667e055 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c @@ -0,0 +1,983 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "smumgr.h" +#include "smu74.h" +#include "smu_ucode_xfer_vi.h" +#include "polaris10_smumgr.h" +#include "smu74_discrete.h" +#include "smu/smu_7_1_3_d.h" +#include "smu/smu_7_1_3_sh_mask.h" +#include "gmc/gmc_8_1_d.h" +#include "gmc/gmc_8_1_sh_mask.h" +#include "oss/oss_3_0_d.h" +#include "gca/gfx_8_0_d.h" +#include "bif/bif_5_0_d.h" +#include "bif/bif_5_0_sh_mask.h" +#include "polaris10_pwrvirus.h" +#include "ppatomctrl.h" +#include "pp_debug.h" +#include "cgs_common.h" + +#define POLARIS10_SMC_SIZE 0x20000 +#define VOLTAGE_SCALE 4 + +/* Microcode file is stored in this buffer */ +#define BUFFER_SIZE 80000 +#define MAX_STRING_SIZE 15 +#define BUFFER_SIZETWO 131072 /* 128 *1024 */ + +#define SMC_RAM_END 0x40000 + +SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = { + /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */ + /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */ + { 0x3c0fd047, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x30750000, 0, 0, 0, 0, 0, 0, 0 } }, + { 0xa00fd047, 0x01, 0x04, 0x1e00, 0x00800510, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x409c0000, 0, 0, 0, 0, 0, 0, 0 } }, + { 0x0410d047, 0x01, 0x00, 0x1e00, 0x00600410, 0x87020000, 0, 0, 0x0e, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x50c30000, 0, 0, 0, 0, 0, 0, 0 } }, + { 0x6810d047, 0x01, 0x00, 0x1e00, 0x00800410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x60ea0000, 0, 0, 0, 0, 0, 0, 0 } }, + { 0xcc10d047, 0x01, 0x00, 0x1e00, 0x00e00410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xe8fd0000, 0, 0, 0, 0, 0, 0, 0 } }, + { 0x3011d047, 0x01, 0x00, 0x1e00, 0x00400510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x70110100, 0, 0, 0, 0, 0, 0, 0 } }, + { 0x9411d047, 0x01, 0x00, 0x1e00, 0x00a00510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xf8240100, 0, 0, 0, 0, 0, 0, 0 } }, + { 0xf811d047, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x80380100, 0, 0, 0, 0, 0, 0, 0 } } +}; + +SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00}; + +/** +* Set the address for reading/writing the SMC SRAM space. +* @param smumgr the address of the powerplay hardware manager. +* @param smcAddress the address in the SMC RAM to access. +*/ +static int polaris10_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit) +{ + PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL); + PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL); + + cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr); + SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); + + return 0; +} + +/** +* Copy bytes from SMC RAM space into driver memory. +* +* @param smumgr the address of the powerplay SMU manager. +* @param smc_start_address the start address in the SMC RAM to copy bytes from +* @param src the byte array to copy the bytes to. +* @param byte_count the number of bytes to copy. +*/ +int polaris10_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit) +{ + uint32_t data; + uint32_t addr; + uint8_t *dest_byte; + uint8_t i, data_byte[4] = {0}; + uint32_t *pdata = (uint32_t *)&data_byte; + + PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1;); + PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1); + + addr = smc_start_address; + + while (byte_count >= 4) { + polaris10_read_smc_sram_dword(smumgr, addr, &data, limit); + + *dest = PP_SMC_TO_HOST_UL(data); + + dest += 1; + byte_count -= 4; + addr += 4; + } + + if (byte_count) { + polaris10_read_smc_sram_dword(smumgr, addr, &data, limit); + *pdata = PP_SMC_TO_HOST_UL(data); + /* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */ + dest_byte = (uint8_t *)dest; + for (i = 0; i < byte_count; i++) + dest_byte[i] = data_byte[i]; + } + + return 0; +} + +/** +* Copy bytes from an array into the SMC RAM space. +* +* @param pSmuMgr the address of the powerplay SMU manager. +* @param smc_start_address the start address in the SMC RAM to copy bytes to. +* @param src the byte array to copy the bytes from. +* @param byte_count the number of bytes to copy. +*/ +int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, + const uint8_t *src, uint32_t byte_count, uint32_t limit) +{ + int result; + uint32_t data = 0; + uint32_t original_data; + uint32_t addr = 0; + uint32_t extra_shift; + + PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1); + PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1); + + addr = smc_start_address; + + while (byte_count >= 4) { + /* Bytes are written into the SMC addres space with the MSB first. */ + data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; + + result = polaris10_set_smc_sram_address(smumgr, addr, limit); + + if (0 != result) + return result; + + cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data); + + src += 4; + byte_count -= 4; + addr += 4; + } + + if (0 != byte_count) { + + data = 0; + + result = polaris10_set_smc_sram_address(smumgr, addr, limit); + + if (0 != result) + return result; + + + original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11); + + extra_shift = 8 * (4 - byte_count); + + while (byte_count > 0) { + /* Bytes are written into the SMC addres space with the MSB first. */ + data = (0x100 * data) + *src++; + byte_count--; + } + + data <<= extra_shift; + + data |= (original_data & ~((~0UL) << extra_shift)); + + result = polaris10_set_smc_sram_address(smumgr, addr, limit); + + if (0 != result) + return result; + + cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data); + } + + return 0; +} + + +static int polaris10_program_jump_on_start(struct pp_smumgr *smumgr) +{ + static unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 }; + + polaris10_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1); + + return 0; +} + +/** +* Return if the SMC is currently running. +* +* @param smumgr the address of the powerplay hardware manager. +*/ +bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr) +{ + return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) + && (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C))); +} + +/** +* Send a message to the SMC, and wait for its response. +* +* @param smumgr the address of the powerplay hardware manager. +* @param msg the message to send. +* @return The response that came from the SMC. +*/ +int polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) +{ + if (!polaris10_is_smc_ram_running(smumgr)) + return -1; + + SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); + + if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) + printk("Failed to send Previous Message.\n"); + + + cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); + + SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); + + if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) + printk("Failed to send Message.\n"); + + return 0; +} + + +/** +* Send a message to the SMC, and do not wait for its response. +* +* @param smumgr the address of the powerplay hardware manager. +* @param msg the message to send. +* @return Always return 0. +*/ +int polaris10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg) +{ + cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); + + return 0; +} + +/** +* Send a message to the SMC with parameter +* +* @param smumgr: the address of the powerplay hardware manager. +* @param msg: the message to send. +* @param parameter: the parameter to send +* @return The response that came from the SMC. +*/ +int polaris10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) +{ + if (!polaris10_is_smc_ram_running(smumgr)) { + return -1; + } + + SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); + + cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); + + return polaris10_send_msg_to_smc(smumgr, msg); +} + + +/** +* Send a message to the SMC with parameter, do not wait for response +* +* @param smumgr: the address of the powerplay hardware manager. +* @param msg: the message to send. +* @param parameter: the parameter to send +* @return The response that came from the SMC. +*/ +int polaris10_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) +{ + cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); + + return polaris10_send_msg_to_smc_without_waiting(smumgr, msg); +} + +int polaris10_send_msg_to_smc_offset(struct pp_smumgr *smumgr) +{ + cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000); + + cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test); + + SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); + + if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) + printk("Failed to send Message.\n"); + + return 0; +} + +/** +* Wait until the SMC is doing nithing. Doing nothing means that the SMC is either turned off or it is sitting on the STOP instruction. +* +* @param smumgr the address of the powerplay hardware manager. +* @param msg the message to send. +* @return The response that came from the SMC. +*/ +int polaris10_wait_for_smc_inactive(struct pp_smumgr *smumgr) +{ + /* If the SMC is not even on it qualifies as inactive. */ + if (!polaris10_is_smc_ram_running(smumgr)) + return -1; + + SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0); + return 0; +} + + +/** +* Upload the SMC firmware to the SMC microcontroller. +* +* @param smumgr the address of the powerplay hardware manager. +* @param pFirmware the data structure containing the various sections of the firmware. +*/ +static int polaris10_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit) +{ + uint32_t byte_count = length; + + PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -1); + + cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000); + SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1); + + for (; byte_count >= 4; byte_count -= 4) + cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++); + + SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); + + PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -1); + + return 0; +} + +static enum cgs_ucode_id polaris10_convert_fw_type_to_cgs(uint32_t fw_type) +{ + enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM; + + switch (fw_type) { + case UCODE_ID_SMU: + result = CGS_UCODE_ID_SMU; + break; + case UCODE_ID_SMU_SK: + result = CGS_UCODE_ID_SMU_SK; + break; + case UCODE_ID_SDMA0: + result = CGS_UCODE_ID_SDMA0; + break; + case UCODE_ID_SDMA1: + result = CGS_UCODE_ID_SDMA1; + break; + case UCODE_ID_CP_CE: + result = CGS_UCODE_ID_CP_CE; + break; + case UCODE_ID_CP_PFP: + result = CGS_UCODE_ID_CP_PFP; + break; + case UCODE_ID_CP_ME: + result = CGS_UCODE_ID_CP_ME; + break; + case UCODE_ID_CP_MEC: + result = CGS_UCODE_ID_CP_MEC; + break; + case UCODE_ID_CP_MEC_JT1: + result = CGS_UCODE_ID_CP_MEC_JT1; + break; + case UCODE_ID_CP_MEC_JT2: + result = CGS_UCODE_ID_CP_MEC_JT2; + break; + case UCODE_ID_RLC_G: + result = CGS_UCODE_ID_RLC_G; + break; + default: + break; + } + + return result; +} + +static int polaris10_upload_smu_firmware_image(struct pp_smumgr *smumgr) +{ + int result = 0; + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + + struct cgs_firmware_info info = {0}; + + if (smu_data->security_hard_key == 1) + cgs_get_firmware_info(smumgr->device, + polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU), &info); + else + cgs_get_firmware_info(smumgr->device, + polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info); + + /* TO DO cgs_init_samu_load_smu(smumgr->device, (uint32_t *)info.kptr, info.image_size, smu_data->post_initial_boot);*/ + result = polaris10_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, POLARIS10_SMC_SIZE); + + return result; +} + +/** +* Read a 32bit value from the SMC SRAM space. +* ALL PARAMETERS ARE IN HOST BYTE ORDER. +* @param smumgr the address of the powerplay hardware manager. +* @param smcAddress the address in the SMC RAM to access. +* @param value and output parameter for the data read from the SMC SRAM. +*/ +int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit) +{ + int result; + + result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit); + + if (result) + return result; + + *value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11); + return 0; +} + +/** +* Write a 32bit value to the SMC SRAM space. +* ALL PARAMETERS ARE IN HOST BYTE ORDER. +* @param smumgr the address of the powerplay hardware manager. +* @param smc_addr the address in the SMC RAM to access. +* @param value to write to the SMC SRAM. +*/ +int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit) +{ + int result; + + result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit); + + if (result) + return result; + + cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value); + + return 0; +} + + +int polaris10_smu_fini(struct pp_smumgr *smumgr) +{ + if (smumgr->backend) { + kfree(smumgr->backend); + smumgr->backend = NULL; + } + return 0; +} + +/* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */ +static uint32_t polaris10_get_mask_for_firmware_type(uint32_t fw_type) +{ + uint32_t result = 0; + + switch (fw_type) { + case UCODE_ID_SDMA0: + result = UCODE_ID_SDMA0_MASK; + break; + case UCODE_ID_SDMA1: + result = UCODE_ID_SDMA1_MASK; + break; + case UCODE_ID_CP_CE: + result = UCODE_ID_CP_CE_MASK; + break; + case UCODE_ID_CP_PFP: + result = UCODE_ID_CP_PFP_MASK; + break; + case UCODE_ID_CP_ME: + result = UCODE_ID_CP_ME_MASK; + break; + case UCODE_ID_CP_MEC_JT1: + case UCODE_ID_CP_MEC_JT2: + result = UCODE_ID_CP_MEC_MASK; + break; + case UCODE_ID_RLC_G: + result = UCODE_ID_RLC_G_MASK; + break; + default: + printk("UCode type is out of range! \n"); + result = 0; + } + + return result; +} + +/* Populate one firmware image to the data structure */ + +static int polaris10_populate_single_firmware_entry(struct pp_smumgr *smumgr, + uint32_t fw_type, + struct SMU_Entry *entry) +{ + int result = 0; + struct cgs_firmware_info info = {0}; + + result = cgs_get_firmware_info(smumgr->device, + polaris10_convert_fw_type_to_cgs(fw_type), + &info); + + if (!result) { + entry->version = info.version; + entry->id = (uint16_t)fw_type; + entry->image_addr_high = smu_upper_32_bits(info.mc_addr); + entry->image_addr_low = smu_lower_32_bits(info.mc_addr); + entry->meta_data_addr_high = 0; + entry->meta_data_addr_low = 0; + entry->data_size_byte = info.image_size; + entry->num_register_entries = 0; + } + + if (fw_type == UCODE_ID_RLC_G) + entry->flags = 1; + else + entry->flags = 0; + + return 0; +} + +static int polaris10_request_smu_load_fw(struct pp_smumgr *smumgr) +{ + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + uint32_t fw_to_load; + + int result = 0; + struct SMU_DRAMData_TOC *toc; + + if (!smumgr->reload_fw) { + printk(KERN_INFO "[ powerplay ] skip reloading...\n"); + return 0; + } + + if (smu_data->soft_regs_start) + cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, + smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus), + 0x0); + + polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high); + polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low); + + toc = (struct SMU_DRAMData_TOC *)smu_data->header; + toc->num_entries = 0; + toc->structure_version = 1; + + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + + polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high); + polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low); + + fw_to_load = UCODE_ID_RLC_G_MASK + + UCODE_ID_SDMA0_MASK + + UCODE_ID_SDMA1_MASK + + UCODE_ID_CP_CE_MASK + + UCODE_ID_CP_ME_MASK + + UCODE_ID_CP_PFP_MASK + + UCODE_ID_CP_MEC_MASK; + + if (polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load)) + printk(KERN_ERR "Fail to Request SMU Load uCode"); + + return result; +} + +/* Check if the FW has been loaded, SMU will not return if loading has not finished. */ +static int polaris10_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type) +{ + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + uint32_t fw_mask = polaris10_get_mask_for_firmware_type(fw_type); + uint32_t ret; + /* Check SOFT_REGISTERS_TABLE_28.UcodeLoadStatus */ + ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11, + smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus), + fw_mask, fw_mask); + + return ret; +} + +static int polaris10_reload_firmware(struct pp_smumgr *smumgr) +{ + return smumgr->smumgr_funcs->start_smu(smumgr); +} + +static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr) +{ + int i; + int result = -1; + uint32_t reg, data; + + PWR_Command_Table *pvirus = pwr_virus_table; + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + + + for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { + switch (pvirus->command) { + case PwrCmdWrite: + reg = pvirus->reg; + data = pvirus->data; + cgs_write_register(smumgr->device, reg, data); + break; + + case PwrCmdEnd: + result = 0; + break; + + default: + printk("Table Exit with Invalid Command!"); + smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; + result = -1; + break; + } + pvirus++; + } + + return result; +} + +static int polaris10_perform_btc(struct pp_smumgr *smumgr) +{ + int result = 0; + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + + if (0 != smu_data->avfs.avfs_btc_param) { + if (0 != polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { + printk("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed"); + result = -1; + } + } + if (smu_data->avfs.avfs_btc_param > 1) { + /* Soft-Reset to reset the engine before loading uCode */ + /* halt */ + cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000); + /* reset everything */ + cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff); + cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0); + } + return result; +} + + +int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) +{ + uint32_t vr_config; + uint32_t dpm_table_start; + + uint16_t u16_boot_mvdd; + uint32_t graphics_level_address, vr_config_address, graphics_level_size; + + graphics_level_size = sizeof(avfs_graphics_level_polaris10); + u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE); + + PP_ASSERT_WITH_CODE(0 == polaris10_read_smc_sram_dword(smumgr, + SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable), + &dpm_table_start, 0x40000), + "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table", + return -1); + + /* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */ + vr_config = 0x01000500; /* Real value:0x50001 */ + + vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig); + + PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, vr_config_address, + (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000), + "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC", + return -1); + + graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); + + PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address, + (uint8_t *)(&avfs_graphics_level_polaris10), + graphics_level_size, 0x40000), + "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!", + return -1); + + graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel); + + PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address, + (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000), + "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!", + return -1); + + /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */ + + graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd); + + PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address, + (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000), + "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!", + return -1); + + return 0; +} + +int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) +{ + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + + switch (smu_data->avfs.avfs_btc_status) { + case AVFS_BTC_COMPLETED_PREVIOUSLY: + break; + + case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */ + + smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED; + PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(smumgr), + "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU", + return -1); + + if (smu_data->avfs.avfs_btc_param > 1) { + printk("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting."); + smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; + PP_ASSERT_WITH_CODE(-1 == polaris10_setup_pwr_virus(smumgr), + "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ", + return -1); + } + + smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED; + PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(smumgr), + "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled", + return -1); + + break; + + case AVFS_BTC_DISABLED: + case AVFS_BTC_NOTSUPPORTED: + break; + + default: + printk("[AVFS] Something is broken. See log!"); + break; + } + + return 0; +} + +static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr) +{ + int result = 0; + + /* Wait for smc boot up */ + /* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */ + + /* Assert reset */ + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_RESET_CNTL, rst_reg, 1); + + result = polaris10_upload_smu_firmware_image(smumgr); + if (result != 0) + return result; + + /* Clear status */ + cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); + + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); + + /* De-assert reset */ + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_RESET_CNTL, rst_reg, 0); + + + SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); + + + /* Call Test SMU message with 0x20000 offset to trigger SMU start */ + polaris10_send_msg_to_smc_offset(smumgr); + + /* Wait done bit to be set */ + /* Check pass/failed indicator */ + + SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMU_STATUS, SMU_DONE, 0); + + if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMU_STATUS, SMU_PASS)) + PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); + + cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); + + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_RESET_CNTL, rst_reg, 1); + + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_RESET_CNTL, rst_reg, 0); + + /* Wait for firmware to initialize */ + SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); + + return result; +} + +static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr) +{ + int result = 0; + + /* wait for smc boot up */ + SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); + + /* Clear firmware interrupt enable flag */ + /* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */ + cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, + ixFIRMWARE_FLAGS, 0); + + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_RESET_CNTL, + rst_reg, 1); + + result = polaris10_upload_smu_firmware_image(smumgr); + if (result != 0) + return result; + + /* Set smc instruct start point at 0x0 */ + polaris10_program_jump_on_start(smumgr); + + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); + + SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + SMC_SYSCON_RESET_CNTL, rst_reg, 0); + + /* Wait for firmware to initialize */ + + SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, + FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); + + return result; +} + +static int polaris10_start_smu(struct pp_smumgr *smumgr) +{ + int result = 0; + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + bool SMU_VFT_INTACT; + + /* Only start SMC if SMC RAM is not running */ + if (!polaris10_is_smc_ram_running(smumgr)) { + SMU_VFT_INTACT = false; + smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)); + smu_data->security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL)); + + /* Check if SMU is running in protected mode */ + if (smu_data->protected_mode == 0) { + result = polaris10_start_smu_in_non_protection_mode(smumgr); + } else { + result = polaris10_start_smu_in_protection_mode(smumgr); + + /* If failed, try with different security Key. */ + if (result != 0) { + smu_data->security_hard_key ^= 1; + result = polaris10_start_smu_in_protection_mode(smumgr); + } + } + + if (result != 0) + PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); + + polaris10_avfs_event_mgr(smumgr, true); + } else + SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */ + + smu_data->post_initial_boot = true; + polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT); + /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */ + polaris10_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters), + &(smu_data->soft_regs_start), 0x40000); + + result = polaris10_request_smu_load_fw(smumgr); + + return result; +} + +static int polaris10_smu_init(struct pp_smumgr *smumgr) +{ + struct polaris10_smumgr *smu_data; + uint8_t *internal_buf; + uint64_t mc_addr = 0; + /* Allocate memory for backend private data */ + smu_data = (struct polaris10_smumgr *)(smumgr->backend); + smu_data->header_buffer.data_size = + ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096; + smu_data->smu_buffer.data_size = 200*4096; + smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED; +/* Allocate FW image data structure and header buffer and + * send the header buffer address to SMU */ + smu_allocate_memory(smumgr->device, + smu_data->header_buffer.data_size, + CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, + PAGE_SIZE, + &mc_addr, + &smu_data->header_buffer.kaddr, + &smu_data->header_buffer.handle); + + smu_data->header = smu_data->header_buffer.kaddr; + smu_data->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr); + smu_data->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr); + + PP_ASSERT_WITH_CODE((NULL != smu_data->header), + "Out of memory.", + kfree(smumgr->backend); + cgs_free_gpu_mem(smumgr->device, + (cgs_handle_t)smu_data->header_buffer.handle); + return -1); + +/* Allocate buffer for SMU internal buffer and send the address to SMU. + * Iceland SMU does not need internal buffer.*/ + smu_allocate_memory(smumgr->device, + smu_data->smu_buffer.data_size, + CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, + PAGE_SIZE, + &mc_addr, + &smu_data->smu_buffer.kaddr, + &smu_data->smu_buffer.handle); + + internal_buf = smu_data->smu_buffer.kaddr; + smu_data->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr); + smu_data->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr); + + PP_ASSERT_WITH_CODE((NULL != internal_buf), + "Out of memory.", + kfree(smumgr->backend); + cgs_free_gpu_mem(smumgr->device, + (cgs_handle_t)smu_data->smu_buffer.handle); + return -1;); + + return 0; +} + +static const struct pp_smumgr_func ellsemere_smu_funcs = { + .smu_init = polaris10_smu_init, + .smu_fini = polaris10_smu_fini, + .start_smu = polaris10_start_smu, + .check_fw_load_finish = polaris10_check_fw_load_finish, + .request_smu_load_fw = polaris10_reload_firmware, + .request_smu_load_specific_fw = NULL, + .send_msg_to_smc = polaris10_send_msg_to_smc, + .send_msg_to_smc_with_parameter = polaris10_send_msg_to_smc_with_parameter, + .download_pptable_settings = NULL, + .upload_pptable_settings = NULL, +}; + +int polaris10_smum_init(struct pp_smumgr *smumgr) +{ + struct polaris10_smumgr *polaris10_smu = NULL; + + polaris10_smu = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL); + + if (polaris10_smu == NULL) + return -1; + + smumgr->backend = polaris10_smu; + smumgr->smumgr_funcs = &ellsemere_smu_funcs; + + return 0; +} diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h new file mode 100644 index 0000000..e5377ae --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h @@ -0,0 +1,68 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _POLARIS10_SMUMANAGER_H +#define _POLARIS10_SMUMANAGER_H + +#include +#include + +struct polaris10_avfs { + enum AVFS_BTC_STATUS avfs_btc_status; + uint32_t avfs_btc_param; +}; + +struct polaris10_buffer_entry { + uint32_t data_size; + uint32_t mc_addr_low; + uint32_t mc_addr_high; + void *kaddr; + unsigned long handle; +}; + +struct polaris10_smumgr { + uint8_t *header; + uint8_t *mec_image; + struct polaris10_buffer_entry smu_buffer; + struct polaris10_buffer_entry header_buffer; + uint32_t soft_regs_start; + uint8_t *read_rrm_straps; + uint32_t read_drm_straps_mc_address_high; + uint32_t read_drm_straps_mc_address_low; + uint32_t acpi_optimization; + bool post_initial_boot; + uint8_t protected_mode; + uint8_t security_hard_key; + struct polaris10_avfs avfs; +}; + + +int polaris10_smum_init(struct pp_smumgr *smumgr); + +int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit); +int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit); +int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, + const uint8_t *src, uint32_t byte_count, uint32_t limit); + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c index 06bbe90..c483baf 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c @@ -30,7 +30,7 @@ #include "cz_smumgr.h" #include "tonga_smumgr.h" #include "fiji_smumgr.h" -#include "ellesmere_smumgr.h" +#include "polaris10_smumgr.h" int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle) { @@ -63,9 +63,9 @@ int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle) case CHIP_FIJI: fiji_smum_init(smumgr); break; - case CHIP_BAFFIN: - case CHIP_ELLESMERE: - ellesmere_smum_init(smumgr); + case CHIP_POLARIS11: + case CHIP_POLARIS10: + polaris10_smum_init(smumgr); break; default: return -EINVAL; -- 2.7.4