From fc9ff27e7e072eaadd0604c99d1f2fe4b78c8dc3 Mon Sep 17 00:00:00 2001 From: David Rokhvarg Date: Mon, 8 Feb 2016 12:02:53 -0500 Subject: [PATCH 0781/1110] drm/amd/dal: Create interface for Virtual HW programming. These are the data types for Virtual HW Layer of DAL3. The intended uses are: 1. Generation pseudocode sequences for HW programming. 2. Implementation of real HW programming by HW Sequencer of DAL3. Signed-off-by: David Rokhvarg Acked-by: Jordan Lazare --- drivers/gpu/drm/amd/dal/dc/dc_hw_types.h | 282 +++++++++++++++++++ drivers/gpu/drm/amd/dal/dc/dc_types.h | 313 ++------------------- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 4 +- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 35 ++- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h | 11 +- drivers/gpu/drm/amd/dal/dc/inc/mem_input.h | 19 +- drivers/gpu/drm/amd/dal/dc/inc/transform.h | 6 +- 7 files changed, 358 insertions(+), 312 deletions(-) create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_hw_types.h diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h new file mode 100644 index 0000000..71d6301 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h @@ -0,0 +1,282 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef DC_HW_TYPES_H +#define DC_HW_TYPES_H + +/****************************************************************************** + * Data types for Virtual HW Layer of DAL3. + * (see DAL3 design documents for HW Layer definition) + * + * The intended uses are: + * 1. Generation pseudocode sequences for HW programming. + * 2. Implementation of real HW programming by HW Sequencer of DAL3. + * + * Note: do *not* add any types which are *not* used for HW programming - this + * will ensure separation of Logic layer from HW layer. + ******************************************************************************/ + +union large_integer { + struct { + uint32_t low_part; + int32_t high_part; + }; + + struct { + uint32_t low_part; + int32_t high_part; + } u; + + int64_t quad_part; +}; + +#define PHYSICAL_ADDRESS_LOC union large_integer + +enum dc_plane_addr_type { + PLN_ADDR_TYPE_GRAPHICS = 0, + PLN_ADDR_TYPE_GRPH_STEREO, + PLN_ADDR_TYPE_VIDEO_PROGRESSIVE, +}; + +struct dc_plane_address { + enum dc_plane_addr_type type; + union { + struct{ + PHYSICAL_ADDRESS_LOC addr; + } grph; + + /*stereo*/ + struct { + PHYSICAL_ADDRESS_LOC left_addr; + PHYSICAL_ADDRESS_LOC right_addr; + } grph_stereo; + + /*video progressive*/ + struct { + PHYSICAL_ADDRESS_LOC chroma_addr; + PHYSICAL_ADDRESS_LOC luma_addr; + } video_progressive; + }; +}; + +struct rect { + uint32_t x; + uint32_t y; + uint32_t width; + uint32_t height; +}; + +union plane_size { + /* Grph or Video will be selected + * based on format above: + * Use Video structure if + * format >= DalPixelFormat_VideoBegin + * else use Grph structure + */ + struct { + struct rect surface_size; + /* Graphic surface pitch in pixels. + * In LINEAR_GENERAL mode, pitch + * is 32 pixel aligned. + */ + uint32_t surface_pitch; + } grph; + + struct { + struct rect luma_size; + /* Graphic surface pitch in pixels. + * In LINEAR_GENERAL mode, pitch is + * 32 pixel aligned. + */ + uint32_t luma_pitch; + + struct rect chroma_size; + /* Graphic surface pitch in pixels. + * In LINEAR_GENERAL mode, pitch is + * 32 pixel aligned. + */ + uint32_t chroma_pitch; + } video; +}; + +/*Displayable pixel format in fb*/ +enum surface_pixel_format { + SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0, + /*TOBE REMOVED paletta 256 colors*/ + SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS = + SURFACE_PIXEL_FORMAT_GRPH_BEGIN, + /*16 bpp*/ + SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, + /*16 bpp*/ + SURFACE_PIXEL_FORMAT_GRPH_RGB565, + /*32 bpp*/ + SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, + /*32 bpp swaped*/ + SURFACE_PIXEL_FORMAT_GRPH_BGRA8888, + + SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, + /*swaped*/ + SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, + /*TOBE REMOVED swaped, XR_BIAS has no differance + * for pixel layout than previous and we can + * delete this after discusion*/ + SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS, + /*64 bpp */ + SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, + /*swaped & float*/ + SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, + /*grow graphics here if necessary */ + + SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, + SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = + SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, + SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, + SURFACE_PIXEL_FORMAT_VIDEO_422_YCb, + SURFACE_PIXEL_FORMAT_VIDEO_422_YCr, + SURFACE_PIXEL_FORMAT_VIDEO_422_CbY, + SURFACE_PIXEL_FORMAT_VIDEO_422_CrY, + /*grow 422/420 video here if necessary */ + SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN, + SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb1555 = + SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN, + SURFACE_PIXEL_FORMAT_VIDEO_444_CrYCb565, + SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb4444, + SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA5551, + SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb8888, + SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb2101010, + SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA1010102 + /*grow 444 video here if necessary */ +}; + +enum tile_split_values { + DC_DISPLAY_MICRO_TILING = 0x0, + DC_THIN_MICRO_TILING = 0x1, + DC_DEPTH_MICRO_TILING = 0x2, + DC_ROTATED_MICRO_TILING = 0x3, +}; + +/* TODO: These values come from hardware spec. We need to readdress this + * if they ever change. + */ +enum array_mode_values { + DC_ARRAY_UNDEFINED = 0, + DC_ARRAY_1D_TILED_THIN1 = 0x2, + DC_ARRAY_2D_TILED_THIN1 = 0x4, +}; + +enum tile_mode_values { + DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +}; + +struct dc_tiling_info { + + /* Specifies the number of memory banks for tiling + * purposes. + * Only applies to 2D and 3D tiling modes. + * POSSIBLE VALUES: 2,4,8,16 + */ + unsigned int num_banks; + /* Specifies the number of tiles in the x direction + * to be incorporated into the same bank. + * Only applies to 2D and 3D tiling modes. + * POSSIBLE VALUES: 1,2,4,8 + */ + unsigned int bank_width; + /* Specifies the number of tiles in the y direction to + * be incorporated into the same bank. + * Only applies to 2D and 3D tiling modes. + * POSSIBLE VALUES: 1,2,4,8 + */ + unsigned int bank_height; + /* Specifies the macro tile aspect ratio. Only applies + * to 2D and 3D tiling modes. + */ + unsigned int tile_aspect; + /* Specifies the number of bytes that will be stored + * contiguously for each tile. + * If the tile data requires more storage than this + * amount, it is split into multiple slices. + * This field must not be larger than + * GB_ADDR_CONFIG.DRAM_ROW_SIZE. + * Only applies to 2D and 3D tiling modes. + * For color render targets, TILE_SPLIT >= 256B. + */ + enum tile_split_values tile_split; + /* Specifies the addressing within a tile. + * 0x0 - DISPLAY_MICRO_TILING + * 0x1 - THIN_MICRO_TILING + * 0x2 - DEPTH_MICRO_TILING + * 0x3 - ROTATED_MICRO_TILING + */ + enum tile_mode_values tile_mode; + /* Specifies the number of pipes and how they are + * interleaved in the surface. + * Refer to memory addressing document for complete + * details and constraints. + */ + unsigned int pipe_config; + /* Specifies the tiling mode of the surface. + * THIN tiles use an 8x8x1 tile size. + * THICK tiles use an 8x8x4 tile size. + * 2D tiling modes rotate banks for successive Z slices + * 3D tiling modes rotate pipes and banks for Z slices + * Refer to memory addressing document for complete + * details and constraints. + */ + enum array_mode_values array_mode; +}; + +/* Rotation angle */ +enum dc_rotation_angle { + ROTATION_ANGLE_0 = 0, + ROTATION_ANGLE_90, + ROTATION_ANGLE_180, + ROTATION_ANGLE_270, + ROTATION_ANGLE_COUNT +}; + + +struct dc_cursor_position { + uint32_t x; + uint32_t y; + + uint32_t x_origin; + uint32_t y_origin; + + /* + * This parameter indicates whether HW cursor should be enabled + */ + bool enable; + + /* + * This parameter indicates whether cursor hot spot should be + * programmed + */ + bool hot_spot_enable; +}; + +#endif /* DC_HW_TYPES_H */ + diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h index 1701953..67e62c3 100644 --- a/drivers/gpu/drm/amd/dal/dc/dc_types.h +++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h @@ -29,6 +29,7 @@ #include "fixed31_32.h" #include "irq_types.h" #include "dc_dp_types.h" +#include "dc_hw_types.h" /* forward declarations */ struct dc; @@ -75,54 +76,6 @@ enum surface_color_space { SURFACE_COLOR_SPACE_XRRGB = 0x0010 }; -/*Displayable pixel format in fb*/ -enum surface_pixel_format { - SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0, - /*TOBE REMOVED paletta 256 colors*/ - SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS = - SURFACE_PIXEL_FORMAT_GRPH_BEGIN, - /*16 bpp*/ - SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, - /*16 bpp*/ - SURFACE_PIXEL_FORMAT_GRPH_RGB565, - /*32 bpp*/ - SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, - /*32 bpp swaped*/ - SURFACE_PIXEL_FORMAT_GRPH_BGRA8888, - - SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, - /*swaped*/ - SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, - /*TOBE REMOVED swaped, XR_BIAS has no differance - * for pixel layout than previous and we can - * delete this after discusion*/ - SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS, - /*64 bpp */ - SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, - /*swaped & float*/ - SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, - /*grow graphics here if necessary */ - - SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, - SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = - SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, - SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, - SURFACE_PIXEL_FORMAT_VIDEO_422_YCb, - SURFACE_PIXEL_FORMAT_VIDEO_422_YCr, - SURFACE_PIXEL_FORMAT_VIDEO_422_CbY, - SURFACE_PIXEL_FORMAT_VIDEO_422_CrY, - /*grow 422/420 video here if necessary */ - SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN, - SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb1555 = - SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN, - SURFACE_PIXEL_FORMAT_VIDEO_444_CrYCb565, - SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb4444, - SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA5551, - SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb8888, - SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb2101010, - SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA1010102 - /*grow 444 video here if necessary */ -}; /* Pixel format */ @@ -150,19 +103,13 @@ enum pixel_format { PIXEL_FORMAT_UNKNOWN }; -enum plane_stereo_format { - PLANE_STEREO_FORMAT_NONE = 0, - PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, - PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, - PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, - PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, - PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, - PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 +enum tiling_mode { + TILING_MODE_INVALID, + TILING_MODE_LINEAR, + TILING_MODE_TILED, + TILING_MODE_COUNT }; -/* 3D format for view, typically define how L/R eye surface is arranged within - * frames - */ enum view_3d_format { VIEW_3D_FORMAT_NONE = 0, VIEW_3D_FORMAT_FRAME_SEQUENTIAL, @@ -172,6 +119,25 @@ enum view_3d_format { VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL }; +struct view_stereo_3d_support { + enum view_3d_format format; + struct { + uint32_t CLONE_MODE :1; + uint32_t SCALING :1; + uint32_t SINGLE_FRAME_SW_PACKED :1; + } features; +}; + +enum plane_stereo_format { + PLANE_STEREO_FORMAT_NONE = 0, + PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, + PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, + PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, + PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, + PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, + PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 +}; + enum dc_pixel_encoding { PIXEL_ENCODING_UNDEFINED, PIXEL_ENCODING_RGB, @@ -186,21 +152,6 @@ enum dc_pixel_encoding { * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 */ -union large_integer { - struct { - uint32_t low_part; - int32_t high_part; - }; - - struct { - uint32_t low_part; - int32_t high_part; - } u; - - int64_t quad_part; -}; - -#define PHYSICAL_ADDRESS_LOC union large_integer enum dc_edid_connector_type { EDID_CONNECTOR_UNKNOWN = 0, @@ -285,13 +236,6 @@ struct scaling_ratios { struct fixed31_32 vert_c; }; -struct rect { - uint32_t x; - uint32_t y; - uint32_t width; - uint32_t height; -}; - struct view { uint32_t width; uint32_t height; @@ -495,6 +439,7 @@ enum scanning_type { }; struct dc_crtc_timing { + uint32_t h_total; uint32_t h_border_left; uint32_t h_addressable; @@ -528,34 +473,6 @@ struct dc_mode_timing { struct dc_crtc_timing crtc_timing; }; -/* Rotation angle */ -enum dc_rotation_angle { - ROTATION_ANGLE_0 = 0, - ROTATION_ANGLE_90, - ROTATION_ANGLE_180, - ROTATION_ANGLE_270, - ROTATION_ANGLE_COUNT -}; - -struct dc_cursor_position { - uint32_t x; - uint32_t y; - - uint32_t x_origin; - uint32_t y_origin; - - /* - * This parameter indicates whether HW cursor should be enabled - */ - bool enable; - - /* - * This parameter indicates whether cursor hot spot should be - * programmed - */ - bool hot_spot_enable; -}; - /* This enum is for programming CURSOR_MODE register field. */ /* What this register should be programmed to depends on */ /* OS requested cursor shape flags */ @@ -600,34 +517,6 @@ struct dc_cursor_attributes { }; - -enum dc_plane_addr_type { - PLN_ADDR_TYPE_GRAPHICS = 0, - PLN_ADDR_TYPE_GRPH_STEREO, - PLN_ADDR_TYPE_VIDEO_PROGRESSIVE, -}; - -struct dc_plane_address { - enum dc_plane_addr_type type; - union { - struct{ - PHYSICAL_ADDRESS_LOC addr; - } grph; - - /*stereo*/ - struct { - PHYSICAL_ADDRESS_LOC left_addr; - PHYSICAL_ADDRESS_LOC right_addr; - } grph_stereo; - - /*video progressive*/ - struct { - PHYSICAL_ADDRESS_LOC chroma_addr; - PHYSICAL_ADDRESS_LOC luma_addr; - } video_progressive; - }; -}; - enum dc_power_state { DC_POWER_STATE_ON = 1, DC_POWER_STATE_STANDBY, @@ -772,22 +661,6 @@ enum scaling_transformation { SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE }; -struct view_stereo_3d_support { - enum view_3d_format format; - struct { - uint32_t CLONE_MODE:1; - uint32_t SCALING:1; - uint32_t SINGLE_FRAME_SW_PACKED:1; - } features; -}; - -enum tiling_mode { - TILING_MODE_INVALID, - TILING_MODE_LINEAR, - TILING_MODE_TILED, - TILING_MODE_COUNT -}; - struct view_position { uint32_t x; uint32_t y; @@ -798,138 +671,4 @@ struct render_mode { enum pixel_format pixel_format; }; -struct pixel_format_support { - bool INDEX8 :1; - bool RGB565 :1; - bool ARGB8888 :1; - bool ARGB2101010 :1; - bool ARGB2101010_XRBIAS :1; - bool FP16 :1; -}; - -struct stereo_3d_view { - enum view_3d_format view_3d_format; - union { - uint32_t raw; - struct /*stereo_3d_view_flags*/ - { - bool SINGLE_FRAME_SW_PACKED :1; - bool EXCLUSIVE_3D :1; - } bits; - } flags; -}; - -/* TODO: These values come from hardware spec. We need to readdress this - * if they ever change. - */ -enum array_mode_values { - DC_ARRAY_UNDEFINED = 0, - DC_ARRAY_1D_TILED_THIN1 = 0x2, - DC_ARRAY_2D_TILED_THIN1 = 0x4, -}; - - -enum tile_mode_values { - DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, - DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, -}; - -enum tile_split_values { - DC_DISPLAY_MICRO_TILING = 0x0, - DC_THIN_MICRO_TILING = 0x1, - DC_DEPTH_MICRO_TILING = 0x2, - DC_ROTATED_MICRO_TILING = 0x3, -}; - -struct dc_tiling_info { - - /* Specifies the number of memory banks for tiling - * purposes. - * Only applies to 2D and 3D tiling modes. - * POSSIBLE VALUES: 2,4,8,16 - */ - unsigned int num_banks; - /* Specifies the number of tiles in the x direction - * to be incorporated into the same bank. - * Only applies to 2D and 3D tiling modes. - * POSSIBLE VALUES: 1,2,4,8 - */ - unsigned int bank_width; - /* Specifies the number of tiles in the y direction to - * be incorporated into the same bank. - * Only applies to 2D and 3D tiling modes. - * POSSIBLE VALUES: 1,2,4,8 - */ - unsigned int bank_height; - /* Specifies the macro tile aspect ratio. Only applies - * to 2D and 3D tiling modes. - */ - unsigned int tile_aspect; - /* Specifies the number of bytes that will be stored - * contiguously for each tile. - * If the tile data requires more storage than this - * amount, it is split into multiple slices. - * This field must not be larger than - * GB_ADDR_CONFIG.DRAM_ROW_SIZE. - * Only applies to 2D and 3D tiling modes. - * For color render targets, TILE_SPLIT >= 256B. - */ - enum tile_split_values tile_split; - /* Specifies the addressing within a tile. - * 0x0 - DISPLAY_MICRO_TILING - * 0x1 - THIN_MICRO_TILING - * 0x2 - DEPTH_MICRO_TILING - * 0x3 - ROTATED_MICRO_TILING - */ - enum tile_mode_values tile_mode; - /* Specifies the number of pipes and how they are - * interleaved in the surface. - * Refer to memory addressing document for complete - * details and constraints. - */ - unsigned int pipe_config; - /* Specifies the tiling mode of the surface. - * THIN tiles use an 8x8x1 tile size. - * THICK tiles use an 8x8x4 tile size. - * 2D tiling modes rotate banks for successive Z slices - * 3D tiling modes rotate pipes and banks for Z slices - * Refer to memory addressing document for complete - * details and constraints. - */ - enum array_mode_values array_mode; -}; - -union plane_size { - /* Grph or Video will be selected - * based on format above: - * Use Video structure if - * format >= DalPixelFormat_VideoBegin - * else use Grph structure - */ - struct { - struct rect surface_size; - /* Graphic surface pitch in pixels. - * In LINEAR_GENERAL mode, pitch - * is 32 pixel aligned. - */ - uint32_t surface_pitch; - } grph; - - struct { - struct rect luma_size; - /* Graphic surface pitch in pixels. - * In LINEAR_GENERAL mode, pitch is - * 32 pixel aligned. - */ - uint32_t luma_pitch; - - struct rect chroma_size; - /* Graphic surface pitch in pixels. - * In LINEAR_GENERAL mode, pitch is - * 32 pixel aligned. - */ - uint32_t chroma_pitch; - } video; -}; - #endif /* DC_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c index cee25d8..bacf88d 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c @@ -793,7 +793,9 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx, /*TODO: mst support - use total stream count*/ stream->mi->funcs->allocate_mem_input( stream->mi, - &stream->public.timing, + stream->public.timing.h_total, + stream->public.timing.v_total, + stream->public.timing.pix_clk_khz, context->target_count); if (timing_changed) { diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c index 6d88afe..b718ac1 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c +++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c @@ -717,7 +717,10 @@ void dce110_mem_input_program_display_marks( stutter); } -static uint32_t get_dmif_switch_time_us(struct dc_crtc_timing *timing) +static uint32_t get_dmif_switch_time_us( + uint32_t h_total, + uint32_t v_total, + uint32_t pix_clk_khz) { uint32_t frame_time; uint32_t pixels_per_second; @@ -728,12 +731,12 @@ static uint32_t get_dmif_switch_time_us(struct dc_crtc_timing *timing) /*return double of frame time*/ const uint32_t single_frame_time_multiplier = 2; - if (timing == NULL) + if (!h_total || v_total || !pix_clk_khz) return single_frame_time_multiplier * min_single_frame_time_us; /*TODO: should we use pixel format normalized pixel clock here?*/ - pixels_per_second = timing->pix_clk_khz * 1000; - pixels_per_frame = timing->h_total * timing->v_total; + pixels_per_second = pix_clk_khz * 1000; + pixels_per_frame = h_total * v_total; if (!pixels_per_second || !pixels_per_frame) { /* avoid division by zero */ @@ -761,12 +764,17 @@ static uint32_t get_dmif_switch_time_us(struct dc_crtc_timing *timing) } void dce110_allocate_mem_input( - struct mem_input *mi, - struct dc_crtc_timing *timing, - uint32_t paths_num) + struct mem_input *mi, + uint32_t h_total,/* for current stream */ + uint32_t v_total,/* for current stream */ + uint32_t pix_clk_khz,/* for current stream */ + uint32_t total_stream_num) { const uint32_t retry_delay = 10; - uint32_t retry_count = get_dmif_switch_time_us(timing) / retry_delay; + uint32_t retry_count = get_dmif_switch_time_us( + h_total, + v_total, + pix_clk_khz) / retry_delay; struct dce110_mem_input *bm110 = TO_DCE110_MEM_INPUT(mi); uint32_t addr = bm110->offsets.pipe + mmPIPE0_DMIF_BUFFER_CONTROL; @@ -816,10 +824,10 @@ void dce110_allocate_mem_input( __func__); - if (timing->pix_clk_khz != 0) { + if (pix_clk_khz != 0) { addr = mmDPG_PIPE_ARBITRATION_CONTROL1 + bm110->offsets.dmif; value = dm_read_reg(mi->ctx, addr); - pix_dur = 1000000000ULL / timing->pix_clk_khz; + pix_dur = 1000000000ULL / pix_clk_khz; set_reg_field_value( value, @@ -843,7 +851,7 @@ void dce110_allocate_mem_input( addr = mmMC_HUB_RDREQ_DMIF_LIMIT; value = dm_read_reg(mi->ctx, addr); - if (paths_num > 1) + if (total_stream_num > 1) set_reg_field_value(value, 0, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE); else set_reg_field_value(value, 3, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE); @@ -885,7 +893,8 @@ static void deallocate_dmif_buffer_helper( } void dce110_free_mem_input( - struct mem_input *mi, uint32_t paths_num) + struct mem_input *mi, + uint32_t total_stream_num) { struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mi); uint32_t value; @@ -911,7 +920,7 @@ void dce110_free_mem_input( * Stella Wong proposed this change. */ if (!IS_FPGA_MAXIMUS_DC(mi->ctx->dce_environment)) { value = dm_read_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT); - if (paths_num > 1) + if (total_stream_num > 1) set_reg_field_value(value, 0, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE); else set_reg_field_value(value, 3, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE); diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h index ec83ee1..232d7fb 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h +++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h @@ -78,9 +78,11 @@ void dce110_mem_input_program_display_marks( * pixel duration for pipe */ void dce110_allocate_mem_input( - struct mem_input *mem_input, - struct dc_crtc_timing *timing, - uint32_t paths_num); + struct mem_input *mem_input, + uint32_t h_total,/* for current stream */ + uint32_t v_total,/* for current stream */ + uint32_t pix_clk_khz,/* for current stream */ + uint32_t total_stream_num); /* * dce110_free_mem_input @@ -88,7 +90,8 @@ void dce110_allocate_mem_input( * This function will deallocate a dmif buffer from pipe */ void dce110_free_mem_input( - struct mem_input *mem_input, uint32_t paths_num); + struct mem_input *mem_input, + uint32_t total_stream_num); /* * dce110_mem_input_program_surface_flip_and_addr diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h index cace055..747e5dc 100644 --- a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h +++ b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h @@ -35,7 +35,9 @@ struct mem_input { }; struct mem_input_funcs { - void (*mem_input_program_safe_display_marks)(struct mem_input *mi); + void (*mem_input_program_safe_display_marks)( + struct mem_input *mi); + void (*mem_input_program_display_marks)( struct mem_input *mem_input, struct bw_watermarks nbp, @@ -44,16 +46,23 @@ struct mem_input_funcs { uint32_t h_total, uint32_t pixel_clk_in_khz, uint32_t pstate_blackout_duration_ns); + void (*allocate_mem_input)( - struct mem_input *mem_input, - struct dc_crtc_timing *timing, - uint32_t paths_num); + struct mem_input *mem_input, + uint32_t h_total,/* for current target */ + uint32_t v_total,/* for current target */ + uint32_t pix_clk_khz,/* for current target */ + uint32_t total_streams_num); + void (*free_mem_input)( - struct mem_input *mem_input, uint32_t paths_num); + struct mem_input *mem_input, + uint32_t paths_num); + bool (*mem_input_program_surface_flip_and_addr)( struct mem_input *mem_input, const struct dc_plane_address *address, bool flip_immediate); + bool (*mem_input_program_surface_config)( struct mem_input *mem_input, enum surface_pixel_format format, diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h index e3fb79c..1e5467c 100644 --- a/drivers/gpu/drm/amd/dal/dc/inc/transform.h +++ b/drivers/gpu/drm/amd/dal/dc/inc/transform.h @@ -123,13 +123,15 @@ enum yyc_quantization_range { }; struct transform_funcs { - bool (*transform_power_up)(struct transform *xfm); + bool (*transform_power_up)( + struct transform *xfm); bool (*transform_set_scaler)( struct transform *xfm, const struct scaler_data *data); - void (*transform_set_scaler_bypass)(struct transform *xfm); + void (*transform_set_scaler_bypass)( + struct transform *xfm); bool (*transform_update_viewport)( struct transform *xfm, -- 2.7.4