From 306e22971ffd9d11efda77f6a188e205ca0ac8ad Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Thu, 12 Nov 2015 17:30:52 -0500 Subject: [PATCH 0095/1110] drm/amd/powerplay: enable clock gating for Fiji. Reviewed-by: Alex Deucher Reviewed-by: Jammy Zhou Signed-off-by: Eric Huang --- drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c index c96b458..45997e6 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c @@ -917,7 +917,14 @@ static int fiji_start_smu(struct pp_smumgr *smumgr) } /* To initialize all clock gating before RLC loaded and running.*/ - /*PECI_InitClockGating(peci);*/ + cgs_set_clockgating_state(smumgr->device, + AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE); + cgs_set_clockgating_state(smumgr->device, + AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE); + cgs_set_clockgating_state(smumgr->device, + AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE); + cgs_set_clockgating_state(smumgr->device, + AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE); /* Setup SoftRegsStart here for register lookup in case * DummyBackEnd is used and ProcessFirmwareHeader is not executed -- 2.7.4