diff options
Diffstat (limited to 'meta-amdfalconx86')
108 files changed, 0 insertions, 44943 deletions
diff --git a/meta-amdfalconx86/.gitignore b/meta-amdfalconx86/.gitignore deleted file mode 100644 index e69de29b..00000000 --- a/meta-amdfalconx86/.gitignore +++ /dev/null diff --git a/meta-amdfalconx86/COPYING.MIT b/meta-amdfalconx86/COPYING.MIT deleted file mode 100644 index 89de3547..00000000 --- a/meta-amdfalconx86/COPYING.MIT +++ /dev/null @@ -1,17 +0,0 @@ -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. diff --git a/meta-amdfalconx86/README.md b/meta-amdfalconx86/README.md deleted file mode 100644 index 74d3ff0d..00000000 --- a/meta-amdfalconx86/README.md +++ /dev/null @@ -1,16 +0,0 @@ -# meta-amd/meta-amdfalconx86 - -This is the location for AMD Falcon Family BSP. - -Please see the README file contained in the root meta-amd directory -for general information and usage details. - -## Dependencies - -This layer depends on: - -[bitbake](https://github.com/openembedded/bitbake) layer, -[oe-core](https://github.com/openembedded/openembedded-core) layer, -[meta-oe](https://github.com/openembedded/meta-openembedded) layer, -[meta-python](https://github.com/openembedded/meta-openembedded/meta-python) layer, -meta-amd/common layer diff --git a/meta-amdfalconx86/binary/.gitignore b/meta-amdfalconx86/binary/.gitignore deleted file mode 100644 index e69de29b..00000000 --- a/meta-amdfalconx86/binary/.gitignore +++ /dev/null diff --git a/meta-amdfalconx86/conf/layer.conf b/meta-amdfalconx86/conf/layer.conf deleted file mode 100644 index ad6acfe3..00000000 --- a/meta-amdfalconx86/conf/layer.conf +++ /dev/null @@ -1,13 +0,0 @@ -# We have a conf and classes directory, add to BBPATH -BBPATH .= ":${LAYERDIR}" - -# We have a recipes-* directories, add to BBFILES -BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ - ${LAYERDIR}/recipes-*/*/*.bbappend" - -BBFILE_COLLECTIONS += "amdfalconx86" -BBFILE_PATTERN_amdfalconx86 = "^${LAYERDIR}/" -BBFILE_PRIORITY_amdfalconx86 = "14" -LAYERSERIES_COMPAT_amdfalconx86 = "warrior" - -LAYERDEPENDS_amdfalconx86 = "amd openembedded-layer meta-python" diff --git a/meta-amdfalconx86/conf/local.conf.append.amdfalconx86 b/meta-amdfalconx86/conf/local.conf.append.amdfalconx86 deleted file mode 100644 index 224e8c60..00000000 --- a/meta-amdfalconx86/conf/local.conf.append.amdfalconx86 +++ /dev/null @@ -1,61 +0,0 @@ - -# Set to "yes" to start using the RT Kernel, please -# run 'bitbake -c clean virtual/kernel' before doing so. -RT_KERNEL_AMD = "no" - -# MEL provides the functionality to build packages with license-restricted -# algorithms or software. Their configuration variables can be set to -# "yes" or "no" in the local.conf file to enable or disable the -# functionality to include them in the build. The option to build these -# packages is NOT enabled in the default configuration. After enabling the -# option to build, when you build your target image, the BitBake utility -# fetches package sources from the canonical upstream location. If you do -# not have an active network connection, your build with these packages -# will fail. -# -# Building packages with license-restricted algorithms or software may add -# proprietary IP or functionality with other restrictions to your output. -# Mentor Graphics has no connection with or responsibility for such -# license-restricted algorithms or software, and failure to abide by the -# relevant license terms may have legal consequences. -# -# Mentor Graphics does not distribute or endorse sources for license- -# restricted algorithms or software, and disclaims any liability for their -# use. - -# Using mpv requires the use of license-restricted algorithms -# or software. -INCLUDE_MPV ??= "no" - -COMMERCIAL_LIC_FLAGS_MPV = "commercial_mpv commercial_ffmpeg commercial_x264" -LICENSE_FLAGS_WHITELIST_append = "${@' ${COMMERCIAL_LIC_FLAGS_MPV}' if bb.utils.to_boolean('${INCLUDE_MPV}') else ''}" -CORE_IMAGE_EXTRA_INSTALL_append = "${@' mpv' if bb.utils.to_boolean('${INCLUDE_MPV}') else ''}" - -# Certain multimedia formats also require license restricted codecs and -# software components which are not included in MEL build by default. -INCLUDE_COMMERCIAL_MULTIMEDIA ??= "no" - -COMMERCIAL_LIC_FLAGS_MULTIMEDIA = "commercial_gstreamer1.0-plugins-ugly \ - commercial_lame \ - commercial_mpeg2dec \ - commercial_gstreamer1.0-libav \ - commercial_mpg123" -LICENSE_FLAGS_WHITELIST_append = "${@' ${COMMERCIAL_LIC_FLAGS_MULTIMEDIA}' if bb.utils.to_boolean('${INCLUDE_COMMERCIAL_MULTIMEDIA}') else ''}" -CORE_IMAGE_EXTRA_INSTALL_append = "${@' packagegroup-multimedia-risky' if bb.utils.to_boolean('${INCLUDE_COMMERCIAL_MULTIMEDIA}') else ''}" - -# MEL supports various components that can be enabled by setting the corresponding -# INCLUDE_<component> to "yes". -# Following is a list of <components> that can be enabled if you want them to be -# installed/available on your image. -# Please change the required INCLUDE_<component> to "yes" before building an image, or -# generating an ADE that can be used to develop apps for these components (if applicable): -# -# - VULKAN - Vulkan driver and Loader Layer. -# It is required to run Vulkan based applications. Vulkan is a new generation graphics -# and compute API that provides high-efficiency, cross-platform access to modern GPUs. -# -# - CODEXL - CodeXL remote agent and some sample applications to verify the GPU debugging -# and profiling functionality. -# -INCLUDE_VULKAN ??= "no" -INCLUDE_CODEXL ??= "no" diff --git a/meta-amdfalconx86/conf/machine/amdfalconx86.conf b/meta-amdfalconx86/conf/machine/amdfalconx86.conf deleted file mode 100644 index d610ab0c..00000000 --- a/meta-amdfalconx86/conf/machine/amdfalconx86.conf +++ /dev/null @@ -1,57 +0,0 @@ -#@TYPE: Machine -#@NAME: amdfalconx86 - -#@DESCRIPTION: Machine configuration for amdfalconx86 systems - -PREFERRED_PROVIDER_virtual/kernel ?= "${@bb.utils.contains('RT_KERNEL_AMD', 'yes', "linux-yocto-rt", "linux-yocto", d)}" -PREFERRED_VERSION_linux-yocto-rt ?= "4.4%" - -require conf/machine/include/tune-amdfalconx86.inc - -# Add machine specific AMD features and feature pkgs here -EXTRA_IMAGE_FEATURES += "amd-feature-debug-profile" - -VULKAN_PKGS_amdfalconx86 = "glslang spirv-tools vulkan-loader-layers" -CODEXL_PKGS_amdfalconx86 = "codexl codexl-examples" - -include conf/machine/include/amd-common-configurations.inc -include conf/machine/include/amd-customer-configurations.inc - -# Disable GPU if RT kernel is in use -XSERVER_X86_AMDGPU = "xf86-video-amd \ - ${@bb.utils.contains('DISTRO_FEATURES', 'opengl', 'mesa-driver-radeonsi', '', d)} \ - " -XSERVER_X86_NOGPU = "${@bb.utils.contains('DISTRO_FEATURES', 'opengl', 'mesa-driver-swrast', '', d)}" -XSERVER_X86_GPU = "${@bb.utils.contains('RT_KERNEL_AMD', 'yes', "${XSERVER_X86_NOGPU}", "${XSERVER_X86_AMDGPU}", d)}" - -XSERVER ?= "${XSERVER_X86_BASE} \ - ${XSERVER_X86_EXT} \ - ${XSERVER_X86_FBDEV} \ - ${XSERVER_X86_MODESETTING} \ - ${XSERVER_X86_GPU} \ - " - -MACHINE_EXTRA_RRECOMMENDS += "${@bb.utils.contains('RT_KERNEL_AMD', 'yes', "", "amdgpu-firmware amd-acp-rt286-load", d)}" - -KERNEL_MODULE_AUTOLOAD += "${@bb.utils.contains('RT_KERNEL_AMD', 'yes', "", "snd-soc-acp-pcm snd-soc-acp-rt286-mach", d)}" - -# Setup a getty on all serial ports -# ttyS4/ttyS5 are only needed for Bettongs where console doesn't -# work on ttyS0/ttyS1 so we hope to at least get a getty running -SERIAL_CONSOLES ?= "115200;ttyS0 115200;ttyUSB0 115200;ttyS4 115200;ttyS5" - -# Enable the kernel console on ttyS0/COM0 -KERNEL_SERIAL_CONSOLE ?= "console=ttyS0,115200n8" - -# Enable powerplay -APPEND += "amdgpu.powerplay=1" - -# Disable GPU powergating as a workaround -APPEND += "amdgpu.pg_mask=0" - -TOOLCHAIN_HOST_TASK_append_mel = " ${@bb.utils.contains('INCLUDE_VULKAN', 'yes', "nativesdk-glslang", "", d)}" - -MACHINEOVERRIDES =. "amd:amdx86:amdgpu:" - -# Metadata used by CodeBench for the ADE -ADE_CB_CPU = "general.cpu.excavator" diff --git a/meta-amdfalconx86/conf/machine/include/tune-amdfalconx86.inc b/meta-amdfalconx86/conf/machine/include/tune-amdfalconx86.inc deleted file mode 100644 index dc3911f5..00000000 --- a/meta-amdfalconx86/conf/machine/include/tune-amdfalconx86.inc +++ /dev/null @@ -1,16 +0,0 @@ -DEFAULTTUNE ?= "dbfp4" - -require conf/machine/include/x86/arch-x86.inc -require conf/machine/include/x86-base.inc - -# AMD DB-FP4 64bit (MerlinFalcon) -TUNEVALID[dbfp4] = "Enable AMD DB-FP4 (64 bit) specific processor optimizations" -TUNECONFLICTS[dbfp4] = "m32 mx32" -TUNE_CCARGS .= "${@bb.utils.contains("TUNE_FEATURES", "dbfp4", " -march=bdver4", "", d)}" - -# Extra tune selections -AVAILTUNES += "dbfp4" -TUNE_FEATURES_tune-dbfp4 = "m64 dbfp4" -BASE_LIB_tune-dbfp4 = "lib64" -TUNE_PKGARCH_tune-dbfp4 = "dbfp4" -PACKAGE_EXTRA_ARCHS_tune-dbfp4 = "${TUNE_PKGARCH_tune-dbfp4}" diff --git a/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.c b/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.c deleted file mode 100644 index 41a16765..00000000 --- a/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.c +++ /dev/null @@ -1,529 +0,0 @@ -/***************************************************************************** -* -* Copyright (c) 2014, Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* -***************************************************************************/ -#include <unistd.h> -#include <stdio.h> -#include <stdlib.h> -#include <fcntl.h> -#include <signal.h> -#include <errno.h> -#include <string.h> - -#include <readline/readline.h> -#include <sys/types.h> -#include <sys/wait.h> -#include <sys/ioctl.h> - -#include "gpio-test.h" - -#define GPIO_APP_VERSION "0.2" -#define AMD_GPIO_NUM_PINS 184 -static int gpio_in_use[AMD_GPIO_NUM_PINS]; - -char *show_prompt(void) -{ - return "$ "; -} - -void sighandler(int sig) -{ - printf("\n%s", show_prompt()); -} - -void show_license(void) -{ - printf("/*****************************************************************************\n" - "*\n" - "* Copyright (c) 2014, Advanced Micro Devices, Inc.\n" - "* All rights reserved.\n" - "*\n" - "* Redistribution and use in source and binary forms, with or without\n" - "* modification, are permitted provided that the following conditions are met:\n" - "* * Redistributions of source code must retain the above copyright\n" - "* notice, this list of conditions and the following disclaimer.\n" - "* * Redistributions in binary form must reproduce the above copyright\n" - "* notice, this list of conditions and the following disclaimer in the\n" - "* documentation and/or other materials provided with the distribution.\n" - "* * Neither the name of Advanced Micro Devices, Inc. nor the names of\n" - "* its contributors may be used to endorse or promote products derived\n" - "* from this software without specific prior written permission.\n" - "*\n" - "* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n" - "* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n" - "* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n" - "* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY\n" - "* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n" - "* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n" - "* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n" - "* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n" - "* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n" - "* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n" - "*\n" - "*\n" - "***************************************************************************/\n"); -} - -void print_usage() -{ - printf("\nCommands Supported ->\n"); - printf(" getgpiomode <gpio> : Gets the mode of GPIO pin\n"); - printf(" setgpiomode <gpio> <in/out/high/low> : Sets the mode of GPIO pin to input or output(high/low)\n"); - printf(" getgpiovalue <gpio> : Gets the value of GPIO pin\n"); - printf(" setgpiovalue <gpio> <high/low> : Sets the value of GPO pin to high or low\n"); - printf(" getnumgpio : Gets the number of GPIO pins supported\n"); - printf(" getgpiobase : Gets the number of first GPIO pin\n"); - printf(" getgpioname : Gets the name of GPIO driver currently in use\n"); - printf(" dmesg : Displays the kernel log messages related to GPIO\n"); - printf(" license : Displays the terms of LICENSE for this application\n"); - printf(" help : Displays help text\n"); - printf(" exit : Exits the application\n\n"); -} - -void parse_cmd(const char *cmdline) -{ - int fd; - - if ((cmdline == NULL) || (strncmp(cmdline, "exit", 4) == 0)) { - int i; - int ret; - char gpio[3 + 1]; - - printf("\nExiting...\n"); - - /* We need to unexport all the GPIO pins exported earlier */ - for (i = 0; i < AMD_GPIO_NUM_PINS; i++) { - if (gpio_in_use[i]) { - int fd; - - fd = open("/sys/class/gpio/unexport", O_WRONLY); - if (fd < 0) { - printf("\nPlease make sure AMD GPIO driver is loaded\n"); - exit(EXIT_FAILURE); - } - memset(gpio, '\0', (3 + 1)); - snprintf(gpio, 4, "%d", i); - - ret = write(fd, gpio, strlen(gpio)); - if (ret < 0) - perror("Error writing to /sys/class/gpio/unexport"); - } - } - - exit(EXIT_SUCCESS); - } else if (strncmp(cmdline, "help", 4) == 0) - print_usage(); - else if (strncmp(cmdline, "getnumgpio", 10) == 0) { - int fd; - char ngpio[3 + 1]; - - memset(ngpio, '\0', (3 + 1)); - fd = open("/sys/class/gpio/gpiochip0/ngpio", O_RDONLY); - if (fd < 0) { - printf("\nPlease make sure AMD GPIO driver is loaded\n"); - exit(EXIT_FAILURE); - } - - /* Value read from the file is ASCII text */ - if(read(fd, ngpio, 3) < 0) - perror("Cannot read number of GPIO pins"); - - printf("\nThe maximum number of GPIO pins supported is %d\n", atoi(ngpio)); - close(fd); - } else if (strncmp(cmdline, "getgpiobase", 11) == 0) { - int fd; - char gpiobase[3 + 1]; - - memset(gpiobase, '\0', (3 + 1)); - fd = open("/sys/class/gpio/gpiochip0/base", O_RDONLY); - if (fd < 0) { - printf("\nPlease make sure AMD GPIO driver is loaded\n"); - exit(EXIT_FAILURE); - } - - if(read(fd, gpiobase, 3) < 0) - perror("Cannot read GPIO base"); - - printf("\nGPIO pin numbering starts from %d\n", atoi(gpiobase)); - close(fd); - } else if (strncmp(cmdline, "getgpioname", 11) == 0) { - int fd; - char gpioname[10 + 1]; /* Max 10 characters + NULL character */ - - /* Zero initialize gpioname array */ - memset(gpioname, '\0', sizeof(gpioname)); - - fd = open("/sys/class/gpio/gpiochip0/label", O_RDONLY); - if (fd < 0) { - printf("\nPlease make sure AMD GPIO driver is loaded\n"); - exit(EXIT_FAILURE); - } - - if(read(fd, gpioname, 10) < 0) - perror("Cannot read GPIO driver name"); - - printf("\nGPIO driver loaded is %s\n", gpioname); - close(fd); - } else if (strncmp(cmdline, "getgpiovalue", 12) == 0) { - int fd; - int gpio_num; - char gpio[4 + 1]; - char pathname[80]; - int ret = 0; - - /* Lets point to the end of first token */ - if (sscanf(cmdline, "getgpiovalue %d", &gpio_num) < 1) { - printf("Invalid inputs, please try again\n\n"); - return; - } - - fd = open("/sys/class/gpio/export", O_WRONLY); - if (fd < 0) { - if (errno == EACCES) - printf("\nYou do not have correct permission, please run as root\n"); - else - perror("Error opening /sys/class/gpio/export"); - - exit(EXIT_FAILURE); - } - - memset(gpio, '\0', (3 + 1)); - if (snprintf(gpio, 3, "%d", gpio_num) < 1) { - printf("Invalid inputs, please try again\n"); - close(fd); - return; - } - - ret = write(fd, gpio, strlen(gpio)); - /* - * There can be two situations -> - * 1) The GPIO is being exported for the first time. - * 2) The GPIO is being exported again. - * In the first case, the write to file descriptor should - * succeed, and we should still fall into the if clause. - * - * In the second case, write will fail and errno will be - * set to EBUSY, since the GPIO pin is already exported. - * Rest all is error. - */ - if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) { - /* Close the last file descriptor */ - close(fd); - - memset(pathname, '\0', sizeof(pathname)); - sprintf(pathname, "/sys/class/gpio/gpio%d/value", gpio_num); - - fd = open(pathname, O_RDONLY); - if (fd < 0) - perror("GPIO read error"); - else { - char value[1 + 1]; - - memset(value, '\0', 2); - ret = read(fd, value, 1); - if (ret < 0) - perror("Cannot read GPIO pin"); - - printf("\nGPIO pin %d is at \"%s\"\n", gpio_num, - (strncmp(value, "1", 1) == 0) ? "high" : "low"); - - close(fd); - - /* - * Mark the GPIO as already exported, so that we can use - * unexport them during exit. - */ - gpio_in_use[gpio_num] = 1; - } - } else { - if (errno == EINVAL) - printf("\nInvalid GPIO number\n"); - else - perror("Error exporting GPIO number"); - - close(fd); - } - } else if (strncmp(cmdline, "getgpiomode", 11) == 0) { - int fd; - int gpio_num; - char gpio[4 + 1]; - char pathname[80]; - int ret = 0; - - /* Lets point to the end of first token */ - if (sscanf(cmdline, "getgpiomode %d", &gpio_num) < 1) { - printf("Invalid inputs, please try again\n\n"); - return; - } - - fd = open("/sys/class/gpio/export", O_WRONLY); - if (fd < 0) { - if (errno == EACCES) - printf("\nYou do not have correct permission, please run as root\n"); - else - perror("Error opening /sys/class/gpio/export"); - - exit(EXIT_FAILURE); - } - - memset(gpio, '\0', (3 + 1)); - if (snprintf(gpio, 3, "%d", gpio_num) < 1) { - printf("Invalid inputs, please try again\n"); - close(fd); - return; - } - - ret = write(fd, gpio, strlen(gpio)); - /* - * There can be two situations -> - * 1) The GPIO is being exported for the first time. - * 2) The GPIO is being exported again. - * In the first case, the write to file descriptor should - * succeed, and we should still fall into the if clause. - * - * In the second case, write will fail and errno will be - * set to EBUSY, since the GPIO pin is already exported. - * Rest all is error. - */ - if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) { - /* Close the last file descriptor */ - close(fd); - - memset(pathname, '\0', sizeof(pathname)); - sprintf(pathname, "/sys/class/gpio/gpio%d/direction", gpio_num); - - fd = open(pathname, O_RDONLY); - if (fd < 0) - perror("GPIO read error"); - else { - char mode[3 + 1]; - int c, i = 0; - - memset(mode, '\0', (3 + 1)); - ret = read(fd, mode, 3); - if (ret < 0) - perror("Cannot read GPIO pin"); - - printf("\nGPIO pin %d is in \"%s\" mode\n", gpio_num, - (strncmp(mode, "in", 2) == 0) ? "input" : "output"); - - close(fd); - - /* - * Mark the GPIO as already exported, so that we can use - * unexport them during exit. - */ - gpio_in_use[gpio_num] = 1; - } - } else { - if (errno == EINVAL) - printf("\nInvalid GPIO number\n"); - else - perror("Error exporting GPIO number"); - - close(fd); - } - } else if (strncmp(cmdline, "setgpiomode", 11) == 0) { - int fd; - int gpio_num; - char mode[4 + 1]; - char gpio[3 + 1]; - int ret; - - memset(mode, (4 + 1), 0); - if (sscanf(cmdline, "setgpiomode %d %s", &gpio_num, mode) < 2) { - printf("Invalid inputs, please try again\n\n"); - return; - } - - memset(gpio, '\0', (3 + 1)); - if (snprintf(gpio, 3, "%d", gpio_num) < 1) { - printf("Invalid inputs, please try again\n"); - return; - } - - fd = open("/sys/class/gpio/export", O_WRONLY); - if (fd < 0) { - if (errno == EACCES) - printf("\nYou do not have correct permission, please run as root\n"); - else - perror("Error opening /sys/class/gpio/export"); - - exit(EXIT_FAILURE); - } - - ret = write(fd, gpio, strlen(gpio)); - if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) { - char pathname[80]; - - /* Close the last file descriptor */ - close(fd); - - memset(pathname, '\0', sizeof(pathname)); - sprintf(pathname, "/sys/class/gpio/gpio%d/direction", gpio_num); - - fd = open(pathname, O_WRONLY); - if (fd < 0) - perror("GPIO read error"); - else { - /* Sanity check */ - if ((strncmp(mode, "in", 2) == 0) || - (strncmp(mode, "out", 3) == 0) || - (strncmp(mode, "high", 4) == 0) || - (strncmp(mode, "low", 3) == 0)) { - /* Write mode into /sys/.../direction file */ - ret = write(fd, mode, strlen(mode)); - if (ret < 0) - perror("Error writing GPIO mode"); - } else - printf("\nInvalid GPIO mode, please try again\n"); - - close(fd); - - /* - * Mark the GPIO as exported, so that we can use - * unexport them during exit. - */ - gpio_in_use[gpio_num] = 1; - } - } else { - if (errno == EINVAL) - printf("\nInvalid GPIO number\n"); - else - perror("Error exporting GPIO number"); - - close(fd); - } - } else if (strncmp(cmdline, "setgpiovalue", 12) == 0) { - int fd; - int gpio_num; - char gpio[3 + 1]; - char value[4 + 1]; - int ret; - - memset(value, (4 + 1), 0); - if (sscanf(cmdline, "setgpiovalue %d %s", &gpio_num, value) < 2) { - printf("Invalid inputs, please try again\n\n"); - return; - } - - memset(gpio, '\0', (3 + 1)); - if (snprintf(gpio, 3, "%d", gpio_num) < 1) { - printf("Invalid inputs, please try again\n"); - return; - } - - fd = open("/sys/class/gpio/export", O_WRONLY); - if (fd < 0) { - if (errno == EACCES) - printf("\nYou do not have correct permission, please run as root\n"); - else - perror("Error opening /sys/class/gpio/export"); - - exit(EXIT_FAILURE); - } - - ret = write(fd, gpio, strlen(gpio)); - if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) { - char pathname[80]; - - /* Close the last file descriptor */ - close(fd); - - memset(pathname, '\0', sizeof(pathname)); - sprintf(pathname, "/sys/class/gpio/gpio%d/value", gpio_num); - - fd = open(pathname, O_WRONLY); - if (fd < 0) - perror("GPIO read error"); - else { - if (strncmp(value, "high", 4) == 0) - value[0] = '1'; - else if (strncmp(value, "low", 3) == 0) - value[0] = '0'; - else { - printf("\nInvalid input, please try again...\n"); - return; - } - - /* Write mode into /sys/.../direction file */ - ret = write(fd, value, 1); - if (ret < 0) - perror("Error writing GPIO mode"); - - close(fd); - - /* - * Mark the GPIO as exported, so that we can use - * unexport them during exit. - */ - gpio_in_use[gpio_num] = 1; - } - } else { - if (errno == EINVAL) - printf("\nInvalid GPIO number\n"); - else - perror("Error exporting GPIO number"); - - close(fd); - } - } else if (strncmp(cmdline, "dmesg", 5) == 0) { - if (system("dmesg | grep GPIO") < 0) - perror("Error executing \'dmesg | grep GPIO\'"); - } else if (strncmp(cmdline, "license", 7) == 0) { - show_license(); - } else { - printf("\nUnknown command\n"); - print_usage(); - } -} - -int main(void) -{ - char *cmdline= NULL; - - printf("GPIO sample application version: %s\n", GPIO_APP_VERSION); - printf("Copyright (c) 2014, Advanced Micro Devices, Inc.\n" - "This sample application comes with ABSOLUTELY NO WARRANTY;\n" - "This is free software, and you are welcome to redistribute it\n" - "under certain conditions; type `license' for details.\n\n"); - - /* Handler for Ctrl+C */ - signal(SIGINT, sighandler); - - while (1) { - cmdline = readline(show_prompt()); - parse_cmd(cmdline); - /* Free the memory malloc'ed by readline */ - free(cmdline); - cmdline = NULL; - } - - /* Should never reach here */ - return 0; -} diff --git a/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.h b/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.h deleted file mode 100644 index af9c3b68..00000000 --- a/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _GPIO_TEST_H_ -#define _GPIO_TEST_H_ - - - -/* IOCTL numbers */ - -typedef struct { - int offset; - int value; -}debug_data; - -#define GPIO_TEST_IOC_MAGIC 'k' -#define GPIO_IOC_SWCTRLIN _IOW(GPIO_TEST_IOC_MAGIC, 1, debug_data) -#define GPIO_IOC_SWCTRLEN _IOW(GPIO_TEST_IOC_MAGIC, 2, debug_data) - -#endif /* _GPIO_TEST_H_ */ diff --git a/meta-amdfalconx86/recipes-applications/gpio-test/gpio-test_1.0.bb b/meta-amdfalconx86/recipes-applications/gpio-test/gpio-test_1.0.bb deleted file mode 100644 index 3056c8d2..00000000 --- a/meta-amdfalconx86/recipes-applications/gpio-test/gpio-test_1.0.bb +++ /dev/null @@ -1,23 +0,0 @@ -DESCRIPTION = "Sample application for AMD GPIO driver" -SECTION = "applications" -LICENSE = "BSD" -DEPENDS = "readline" -LIC_FILES_CHKSUM = "file://gpio-test.c;endline=29;md5=8e7a9706367d146e5073510a6e176dc2" - -SRC_URI = "\ - file://gpio-test.c \ - file://gpio-test.h \ - " - -TARGET_CC_ARCH += "${LDFLAGS}" - -S = "${WORKDIR}" - -do_compile() { - ${CC} gpio-test.c -o gpio-test -lreadline -} - -do_install() { - install -d ${D}${bindir} - install -m 0755 gpio-test ${D}${bindir} -} diff --git a/meta-amdfalconx86/recipes-applications/spi-test/files/spirom-test.c b/meta-amdfalconx86/recipes-applications/spi-test/files/spirom-test.c deleted file mode 100644 index d1eb4b5c..00000000 --- a/meta-amdfalconx86/recipes-applications/spi-test/files/spirom-test.c +++ /dev/null @@ -1,798 +0,0 @@ -/***************************************************************************** -* -* Copyright (c) 2014, Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* -***************************************************************************/ -#include <stdint.h> -#include <unistd.h> -#include <stdio.h> -#include <stdlib.h> -#include <fcntl.h> -#include <string.h> -#include <dirent.h> -#include <signal.h> - -#include <sys/types.h> -#include <sys/ioctl.h> -#include <sys/stat.h> - -#include <readline/readline.h> - -#include "spirom.h" - -#define SPI_APP_VERSION "1.0" - -static int device_opened = 0; -static char filename[20]; -static int fd = -1; - -char *show_prompt(void) -{ - return "$ "; -} - -void sighandler(int sig) -{ - /* Do nothing. That is the idea. */ -} - -void show_license(void) -{ - printf("/*****************************************************************************\n" - "*\n" - "* Copyright (c) 2014, Advanced Micro Devices, Inc.\n" - "* All rights reserved.\n" - "*\n" - "* Redistribution and use in source and binary forms, with or without\n" - "* modification, are permitted provided that the following conditions are met:\n" - "* * Redistributions of source code must retain the above copyright\n" - "* notice, this list of conditions and the following disclaimer.\n" - "* * Redistributions in binary form must reproduce the above copyright\n" - "* notice, this list of conditions and the following disclaimer in the\n" - "* documentation and/or other materials provided with the distribution.\n" - "* * Neither the name of Advanced Micro Devices, Inc. nor the names of\n" - "* its contributors may be used to endorse or promote products derived\n" - "* from this software without specific prior written permission.\n" - "*\n" - "* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n" - "* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n" - "* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n" - "* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY\n" - "* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n" - "* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n" - "* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n" - "* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n" - "* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n" - "* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n" - "*\n" - "*\n" - "***************************************************************************/\n"); -} - -void print_usage(void) -{ - printf("\nCommands Supported ->\n"); - printf(" enumerate : List all SPI device nodes available\n"); - printf(" setdevice <dev_id> : Set the SPI device number to access\n"); - printf(" wren : Enable Write operation on SPI device\n"); - printf(" wrdi : Disable Write operation on SPI device\n"); - printf(" chiperase : Erase entire ROM chip\n"); - printf(" rdsr : Read status register of ROM device\n"); - printf(" rdid : Read device identification string\n"); - printf(" sectorerase <addr> <num_sectors> : Erase a fixed number of sectors starting at the address\n" - " specified\n"); - printf(" blockerase <addr> <num_blocks> : Erase a fixed number of blocks starting at the address\n" - " specified\n"); - printf(" read <addr> <num_bytes> <filename> : Read a fixed number of bytes starting at address\n" - " specified, and output the contents into file\n"); - printf(" write <addr> <num_bytes> <filename> : Read a fixed number of bytes from file and output\n" - " the contents to the device starting at the address\n" - " specified\n"); - printf(" license : Displays the terms of LICENSE for this application\n"); - printf(" help : Displays help text\n"); - printf(" exit : Exits the application\n\n"); -} - -void parse_cmd(const char *cmdline) -{ - struct spi_ioc_transfer tr; - unsigned int bytes_chunks; - unsigned int remaining_bytes; - int addr; - int ret; - - if ((cmdline == NULL) || (strncmp(cmdline, "exit", 4) == 0)) { - printf("\nExiting...\n"); - close(fd); - exit(EXIT_SUCCESS); - } else if (strncmp(cmdline, "enumerate", 9) == 0) { - DIR *dir; - struct dirent *dir_entry; - int device_found = 0; - - /* Get the directory handle */ - if ((dir = opendir("/dev")) == NULL) { - printf("\n\nFailed to open directory /dev. Probably you " - "do not have right privilege!\n\n"); - exit(EXIT_FAILURE); - } - - /* Iterate over all the directory entries */ - while ((dir_entry = readdir(dir)) != NULL) { - /* - * If the file is a character device, and its signature - * matches spirom, then we print the corresponding file. - */ - if ((dir_entry->d_type == DT_CHR) && - (strncmp(dir_entry->d_name, "spirom", 6) == 0)) { - printf("/dev/%s\n", dir_entry->d_name); - device_found = 1; - } - } - - printf("\n"); - - /* - * In case we did not find even a single entry, we print a - * message and exit. - */ - if (!device_found) { - printf("\n\nNo spirom device nodes found, load spirom " - "kernel module and try again\n\n"); - exit(EXIT_FAILURE); - } - } else if (strncmp(cmdline, "setdevice", 9) == 0) { - char input[2 + 1]; - int file_desc; - - cmdline += 10; - memset(input, 0, 3); - if (sscanf(cmdline, "%s", input) < 1) { - printf("\nInvalid inputs, please try again\n\n"); - return; - } - - memset(filename, 0, 20); - snprintf(filename, 19, "/dev/spirom%s", input); - file_desc = open(filename, O_RDWR); - if (file_desc < 0) { - printf("\nError opening file %s\n\n", filename); - return; - } - - /* Once we have validated inputs, we store them into the global - * variables used at other places in the program. - */ - fd = file_desc; - device_opened = 1; - printf("\nSPI device set to /dev/spirom%s\n\n", input); - } else if (strncmp(cmdline, "wren", 4) == 0) { - if (!device_opened) { - printf("\nSPI device needs to be set before you can " - "perform this operation\n\n"); - return; - } - - /* command without data */ - tr.buf[0] = ROM_WREN; - tr.direction = 0; - tr.len = 0; - tr.addr_present = 0; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) - printf("\nError executing WREN command\n\n"); - else - printf("\n...WREN completed successfully\n\n"); - } else if (strncmp(cmdline, "wrdi", 4) == 0) { - if (!device_opened) { - printf("\nSPI device needs to be set before you can " - "perform this operation\n\n"); - return; - } - - /* command without data */ - tr.buf[0] = ROM_WRDI; - tr.direction = 0; - tr.len = 0; - tr.addr_present = 0; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) - printf("\nError executing WRDI command\n\n"); - else - printf("\n...WRDI completed successfully\n\n"); - } else if (strncmp(cmdline, "chiperase", 9) == 0) { - if (!device_opened) { - printf("\nSPI device needs to be set before you can " - "perform this operation\n\n"); - return; - } - - tr.buf[0] = ROM_RDSR; - tr.direction = RECEIVE; - tr.addr_present = 0; - tr.len = 1; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing RDSR command\n\n");; - return; - } else if ((tr.buf[1] & 0x02) == 0x00) { - printf("\nCannot execute CHIPERASE command, write is disabled\n\n"); - return; - } - - /* Command without data */ - tr.buf[0] = ROM_CHIP_ERASE; - tr.direction = 0; - tr.len = 0; - tr.addr_present = 0; - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing CHIPERASE command\n\n"); - return; - } - - printf("\n\nCHIPERASE operation in progress, please do not " - " stop in between.\n\n"); - - /* Make sure WIP has been reset */ - while (1) { - memset(&tr, 0, sizeof(struct spi_ioc_transfer)); - tr.buf[0] = ROM_RDSR; - tr.direction = RECEIVE; - tr.addr_present = 0; - tr.len = 1; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing RDSR command\n\n"); - return; - } - - if ((tr.buf[1] & 0x01) == 0x00) - break; - } - - printf("\n\n...CHIPERASE completed successfully\n\n"); - /* Restore signal handler to default */ - } else if (strncmp(cmdline, "rdsr", 4) == 0) { - if (!device_opened) { - printf("\nSPI device needs to be set before you can " - "perform this operation\n\n"); - return; - } - - /* Command with response */ - tr.buf[0] = ROM_RDSR; - tr.direction = RECEIVE; - tr.addr_present = 0; - tr.len = 1; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing RDSR command\n\n"); - return; - } - - /* - * The 1-byte response will be stored in tr.buf, - * so print it out - */ - printf("\nRDSR command returned: 0x%.2x\n\n", tr.buf[1]); - } else if (strncmp(cmdline, "rdid", 4) == 0) { - if (!device_opened) { - printf("\nSPI device needs to be set before you can " - "perform this operation\n\n"); - return; - } - - /* Command with response */ - tr.buf[0] = ROM_RDID; - tr.direction = RECEIVE; - tr.addr_present = 0; - tr.len = 3; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing RDID command\n\n"); - return; - } - - /* - * The 3-bytes response will be stored in tr.buf, - * so print it out - */ - printf("\nRDID command returned: 0x%.2x%.2x%.2x\n", tr.buf[1], - tr.buf[2], tr.buf[3]); - } else if (strncmp(cmdline, "sectorerase", 11) == 0) { - int nsectors; - int i; - - if (!device_opened) { - printf("\nSPI device needs to be set before you can " - "perform this operation\n\n"); - return; - } - - cmdline += 12; - if (sscanf(cmdline, "0x%x 0x%x", &addr, &nsectors) < 2) { - printf("\nInvalid inputs, please try again\n\n"); - return; - } - - tr.buf[0] = ROM_RDSR; - tr.direction = RECEIVE; - tr.addr_present = 0; - tr.len = 1; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing RDSR command\n\n"); - return; - } else if ((tr.buf[1] & 0x02) == 0x00) { - printf("\nCannot execute SECTORERASE command, write is disabled\n\n"); - return; - } - - printf("\n\nSECTORERASE operation in progress, please do not " - " stop in between.\n\n"); - - for (i = 0; i < nsectors; i++) { - /* Write Enable before Sector Erase */ - tr.buf[0] = ROM_WREN; - tr.direction = 0; - tr.len = 0; - tr.addr_present = 0; - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing WREN command\n\n"); - return; - } - - /* Command with address but no data */ - memset(&tr, 0, sizeof(struct spi_ioc_transfer)); - tr.buf[0] = ROM_SECTOR_ERASE; - tr.buf[3] = addr & 0xff; - tr.buf[2] = (addr >> 8) & 0xff; - tr.buf[1] = (addr >> 16) & 0xff; - tr.addr_present = 1; - tr.direction = 0; - tr.len = 0; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing SECTORERASE command\n\n"); - return; - } - - /* point to the next 4k sector */ - addr += 4 * 1024; - - /* - * Before the next loop, we need to make sure that WIP - * bit in the output of RDSR has been reset. - */ - while (1) { - memset(&tr, 0, sizeof(struct spi_ioc_transfer)); - tr.buf[0] = ROM_RDSR; - tr.direction = RECEIVE; - tr.addr_present = 0; - tr.len = 1; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing RDSR command\n\n"); - return; - } - - if ((tr.buf[1] & 0x01) == 0x00) - break; - } - } - - printf("\n\n...SECTORERASE completed successfully\n\n"); - } else if (strncmp(cmdline, "blockerase", 10) == 0) { - int nblocks; - int i; - - if (!device_opened) { - printf("\nSPI device needs to be set before you can " - "perform this operation\n\n"); - return; - } - - cmdline += 11; - if (sscanf(cmdline, "0x%x 0x%x", &addr, &nblocks) < 2) { - printf("\nInvalid inputs, please try again\n\n"); - return; - } - - tr.buf[0] = ROM_RDSR; - tr.direction = RECEIVE; - tr.addr_present = 0; - tr.len = 1; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing RDSR command\n\n"); - return; - } else if ((tr.buf[1] & 0x02) == 0x00) { - printf("\nError executing BLOCKERASE command, write is disabled\n\n"); - return; - } - - printf("\n\nBLOCKERASE operation in progress, please do not " - " stop in between.\n\n"); - - for (i = 0; i < nblocks; i++) { - /* Write Enable before Block Erase */ - tr.buf[0] = ROM_WREN; - tr.direction = 0; - tr.len = 0; - tr.addr_present = 0; - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing WREN command\n\n"); - return; - } - - /* Command with address but no data */ - memset(&tr, 0, sizeof(struct spi_ioc_transfer)); - tr.buf[0] = ROM_BLOCK_ERASE; - tr.buf[3] = addr & 0xff; - tr.buf[2] = (addr >> 8) & 0xff; - tr.buf[1] = (addr >> 16) & 0xff; - tr.addr_present = 1; - tr.direction = 0; - tr.len = 0; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing BLOCKERASE command\n\n"); - return; - } - - /* point to the next 64k block */ - addr += 64 * 1024; - - /* - * Before the next loop, we need to make sure that WIP - * bit in the output of RDSR has been reset. - */ - while (1) { - memset(&tr, 0, sizeof(struct spi_ioc_transfer)); - tr.buf[0] = ROM_RDSR; - tr.direction = RECEIVE; - tr.addr_present = 0; - tr.len = 1; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing RDSR command\n\n"); - return; - } - - if ((tr.buf[1] & 0x01) == 0x00) - break; - } - } - - printf("\n\n...BLOCKERASE completed successfully\n\n"); - } else if (strncmp(cmdline, "read", 4) == 0) { - int nbytes; - int outfile_fd; - int i; - - if (!device_opened) { - printf("\nSPI device needs to be set before you can " - "perform this operation\n\n"); - return; - } - - cmdline += 5; - memset(filename, 0, 20); - if (sscanf(cmdline, "0x%x 0x%x %s", &addr, &nbytes, filename) < 3) { - printf("\nInvalid inputs, please try again\n\n"); - return; - } - - /* - * Open the output file for writing. Create a new file if not - * there, and empty the file before writing if file already - * exists. - */ - outfile_fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, 0644); - if (outfile_fd < 0) { - printf("\nError opening file %s for writing\n\n", filename); - return; - } - - /* - * We will break down the bytes to be received in chunks of - * of 64-bytes. Data might not be a even multiple of 64. So - * in that case, we will have some remaining bytes <4. We - * handle that separately. - */ - bytes_chunks = nbytes / 64; - remaining_bytes = nbytes % 64; - - printf("\n\nREAD operation in progress.\n\n"); - - for (i = 0; i < bytes_chunks; i++) { - /* Command with address and data */ - memset(&tr, 0, sizeof(struct spi_ioc_transfer)); - tr.buf[0] = ROM_READ; - tr.direction = RECEIVE; - /* - * We will store the address into the buffer in little - * endian order. - */ - tr.buf[3] = addr & 0xff; - tr.buf[2] = (addr >> 8) & 0xff; - tr.buf[1] = (addr >> 16) & 0xff; - tr.len = 64; - tr.addr_present = 1; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing READ command\n\n"); - return; - } - - /* Write the data read to output file */ - if (write(outfile_fd, &tr.buf[4], tr.len) < 0) { - printf("\nError writing to file %s\n\n", filename); - return; - } - addr += 64; - } - - if (remaining_bytes) { - memset(&tr, 0, sizeof(struct spi_ioc_transfer)); - tr.buf[0] = ROM_READ; - tr.direction = RECEIVE; - tr.buf[3] = addr & 0xff; - tr.buf[2] = (addr >> 8) & 0xff; - tr.buf[1] = (addr >> 16) & 0xff; - tr.len = remaining_bytes; - tr.addr_present = 1; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing READ command\n\n"); - return; - } - - if (write(outfile_fd, &tr.buf[4], tr.len) < 0) { - printf("\nError writing to file %s\n\n", filename); - return; - } - } - - printf("\n\n...READ completed successfully\n\n"); - close(outfile_fd); - } else if (strncmp(cmdline, "write", 5) == 0) { - int nbytes; - int infile_fd; - int i; - - if (!device_opened) { - printf("\nSPI device needs to be set before you can " - "perform this operation\n\n"); - return; - } - - cmdline += 6; - memset(filename, 0, 20); - if (sscanf(cmdline, "0x%x 0x%x %s", &addr, &nbytes, filename) < 3) { - printf("\nInvalid inputs, please try again\n\n"); - return; - } - - /* Open the input file for reading*/ - infile_fd = open(filename, O_RDONLY); - if (infile_fd < 0) { - printf("\nError opening file %s for reading\n\n", filename); - return; - } - - /* - * We will break down the bytes to be transmitted in chunks of - * of 64-bytes. Like for read, we might not have data in an - * even multiple of 64 bytes. So we will handle the remaining - * bytes in the end. - */ - tr.buf[0] = ROM_RDSR; - tr.direction = RECEIVE; - tr.addr_present = 0; - tr.len = 1; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing RDSR command\n\n"); - return; - } else if ((tr.buf[1] & 0x02) == 0x00) { - printf("\nCannot execute WRITE command, write is disabled\n\n"); - return; - } - - bytes_chunks = nbytes / 64; - remaining_bytes = nbytes % 64; - - printf("\n\nWRITE operation in progress, please do not " - " stop in between.\n\n"); - - for (i = 0; i < bytes_chunks; i++) { - tr.buf[0] = ROM_WREN; - tr.direction = 0; - tr.len = 0; - tr.addr_present = 0; - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing WREN command\n\n"); - return; - } - - /* Command with data and address */ - memset(&tr, 0, sizeof(struct spi_ioc_transfer)); - tr.buf[0] = ROM_WRITE; - tr.direction = TRANSMIT; - /* - * We will store the address into the buffer in little - * endian order. - */ - tr.buf[3] = addr & 0xff; - tr.buf[2] = (addr >> 8) & 0xff; - tr.buf[1] = (addr >> 16) & 0xff; - tr.len = 64; - tr.addr_present = 1; - - /* Read 64 bytes from input file to buffer */ - if (read(infile_fd, &tr.buf[4], tr.len) < 0) { - printf("\nError reading from file %s\n\n", filename); - return; - } - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing WRITE command\n\n"); - return; - } - - addr += 64; - - /* - * Before the next loop, we need to make sure that WIP - * bit in the output of RDSR has been reset. - */ - while (1) { - memset(&tr, 0, sizeof(struct spi_ioc_transfer)); - tr.buf[0] = ROM_RDSR; - tr.direction = RECEIVE; - tr.addr_present = 0; - tr.len = 1; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing RDSR command\n\n"); - return; - } - - if ((tr.buf[1] & 0x01) == 0x00) - break; - } - } - - if (remaining_bytes) { - tr.buf[0] = ROM_WREN; - tr.direction = 0; - tr.len = 0; - tr.addr_present = 0; - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing WREN command\n\n"); - return; - } - - memset(&tr, 0, sizeof(struct spi_ioc_transfer)); - tr.buf[0] = ROM_WRITE; - tr.direction = TRANSMIT; - tr.buf[3] = addr & 0xff; - tr.buf[2] = (addr >> 8) & 0xff; - tr.buf[1] = (addr >> 16) & 0xff; - tr.len = remaining_bytes; - tr.addr_present = 1; - - if (read(infile_fd, &tr.buf[4], tr.len) < 0) { - printf("\nError reading from file %s\n\n", filename); - return; - } - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing WRITE command\n\n"); - return; - } - - while (1) { - memset(&tr, 0, sizeof(struct spi_ioc_transfer)); - tr.buf[0] = ROM_RDSR; - tr.direction = RECEIVE; - tr.addr_present = 0; - tr.len = 1; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - if (ret < 1) { - printf("\nError executing RDSR command\n\n"); - return; - } - - if ((tr.buf[1] & 0x01) == 0x00) - break; - } - } - - printf("\n\n...WRITE completed successfully\n\n"); - close(infile_fd); - } else if (strncmp(cmdline, "license", 7) == 0) { - show_license(); - } else if (strncmp(cmdline, "help", 4) == 0) { - print_usage(); - } else { - printf("\nUnknown command\n"); - print_usage(); - } -} - -int main(void) -{ - char *cmdline= NULL; - - printf("SPI sample application version: %s\n", SPI_APP_VERSION); - printf("Copyright (c) 2014, Advanced Micro Devices, Inc.\n" - "This sample application comes with ABSOLUTELY NO WARRANTY;\n" - "This is free software, and you are welcome to redistribute it\n" - "under certain conditions; type `license` for details.\n\n"); - - /* Set the signal handler */ - signal(SIGINT, sighandler); - - while (1) { - cmdline = readline(show_prompt()); - parse_cmd(cmdline); - /* Free the memory malloc'ed by readline */ - free(cmdline); - } - - /* Restore the default signal handler */ - signal(SIGINT, SIG_DFL); - - /* Should never reach here */ - return 0; -} diff --git a/meta-amdfalconx86/recipes-applications/spi-test/files/spirom.h b/meta-amdfalconx86/recipes-applications/spi-test/files/spirom.h deleted file mode 100644 index f599925f..00000000 --- a/meta-amdfalconx86/recipes-applications/spi-test/files/spirom.h +++ /dev/null @@ -1,53 +0,0 @@ -#ifndef SPIROM_H -#define SPIROM_H - -#include <linux/types.h> - -/*---------------------------------------------------------------------------*/ - -/* IOCTL commands */ - -#define SPI_IOC_MAGIC 'k' - -#define TRANSMIT 1 -#define RECEIVE 2 - -/* - * struct spi_ioc_transfer - interface structure between application and ioctl - * - * @buf: Buffer to hold 1-byte command, 3-bytes address, and 4-byte data for - * transmit or receive. The internal FIFO of our controller can hold a - * maximum of 8 bytes, including the address. But here we assume the - * maximum data excluding address to be 4-bytes long. - * - * @direction: Direction of data transfer, either TRANSMIT or RECEIVE. - * - * @len: Length of data excluding command and address. - * - * @addr_present: Flag to indicate whether 'buf' above contains an address. - */ -struct spi_ioc_transfer { - __u8 buf[64 + 1 + 3]; - __u8 direction; - __u8 len; - __u8 addr_present; -}; - -/* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */ -#define SPI_MSGSIZE(N) \ - ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ - ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) -#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) - -/* SPI ROM command codes */ -#define ROM_WREN 0x06 -#define ROM_WRDI 0x04 -#define ROM_RDSR 0x05 -#define ROM_RDID 0x9F -#define ROM_CHIP_ERASE 0x60 -#define ROM_SECTOR_ERASE 0x20 -#define ROM_BLOCK_ERASE 0xD8 -#define ROM_READ 0x03 -#define ROM_WRITE 0x02 - -#endif /* SPIROM_H */ diff --git a/meta-amdfalconx86/recipes-applications/spi-test/spi-test_1.0.bb b/meta-amdfalconx86/recipes-applications/spi-test/spi-test_1.0.bb deleted file mode 100644 index 764f112a..00000000 --- a/meta-amdfalconx86/recipes-applications/spi-test/spi-test_1.0.bb +++ /dev/null @@ -1,22 +0,0 @@ -DESCRIPTION = "Sample application for AMD SPI driver" -SECTION = "applications" -LICENSE = "BSD" -DEPENDS = "readline" -LIC_FILES_CHKSUM = "file://spirom-test.c;endline=29;md5=8e7a9706367d146e5073510a6e176dc2" - -SRC_URI = "file://spirom-test.c \ - file://spirom.h \ - " - -S = "${WORKDIR}" - -TARGET_CC_ARCH += "${LDFLAGS}" - -do_compile() { - ${CC} spirom-test.c -o spirom-test -lreadline -} - -do_install() { - install -d ${D}${bindir} - install -m 0755 spirom-test ${D}${bindir} -} diff --git a/meta-amdfalconx86/recipes-bsp/formfactor/formfactor/amdfalconx86/machconfig b/meta-amdfalconx86/recipes-bsp/formfactor/formfactor/amdfalconx86/machconfig deleted file mode 100644 index 28ca080e..00000000 --- a/meta-amdfalconx86/recipes-bsp/formfactor/formfactor/amdfalconx86/machconfig +++ /dev/null @@ -1,3 +0,0 @@ -# Assume a USB mouse and keyboard are connected -HAVE_TOUCHSCREEN=n -HAVE_KEYBOARD=y diff --git a/meta-amdfalconx86/recipes-bsp/formfactor/formfactor_0.0.bbappend b/meta-amdfalconx86/recipes-bsp/formfactor/formfactor_0.0.bbappend deleted file mode 100644 index 6d4804d1..00000000 --- a/meta-amdfalconx86/recipes-bsp/formfactor/formfactor_0.0.bbappend +++ /dev/null @@ -1,2 +0,0 @@ -FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" - diff --git a/meta-amdfalconx86/recipes-devtools/glslang/glslang/0001-CMakeLists.txt-obey-CMAKE_INSTALL_LIBDIR.patch b/meta-amdfalconx86/recipes-devtools/glslang/glslang/0001-CMakeLists.txt-obey-CMAKE_INSTALL_LIBDIR.patch deleted file mode 100644 index cef3e8e6..00000000 --- a/meta-amdfalconx86/recipes-devtools/glslang/glslang/0001-CMakeLists.txt-obey-CMAKE_INSTALL_LIBDIR.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 372422ed8ce32e1085cd524156c687df65095237 Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Tue, 25 Oct 2016 14:44:20 +0500 -Subject: [PATCH] CMakeLists.txt: obey CMAKE_INSTALL_LIBDIR - -Not using the exact path that is set through cmake -will end up in a mixed configuration setup where -files are installed on hard-coded locations. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - OGLCompilersDLL/CMakeLists.txt | 2 +- - SPIRV/CMakeLists.txt | 2 +- - glslang/CMakeLists.txt | 2 +- - glslang/OSDependent/Unix/CMakeLists.txt | 2 +- - glslang/OSDependent/Windows/CMakeLists.txt | 2 +- - hlsl/CMakeLists.txt | 2 +- - 6 files changed, 6 insertions(+), 6 deletions(-) - -diff --git a/OGLCompilersDLL/CMakeLists.txt b/OGLCompilersDLL/CMakeLists.txt -index 4954db9..6b518d9 100644 ---- a/OGLCompilersDLL/CMakeLists.txt -+++ b/OGLCompilersDLL/CMakeLists.txt -@@ -8,4 +8,4 @@ if(WIN32) - endif(WIN32) - - install(TARGETS OGLCompiler -- ARCHIVE DESTINATION lib) -+ ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}) -diff --git a/SPIRV/CMakeLists.txt b/SPIRV/CMakeLists.txt -index 48a6c46..c657d56 100755 ---- a/SPIRV/CMakeLists.txt -+++ b/SPIRV/CMakeLists.txt -@@ -41,4 +41,4 @@ if(WIN32) - endif(WIN32) - - install(TARGETS SPIRV SPVRemapper -- ARCHIVE DESTINATION lib) -+ ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}) -diff --git a/glslang/CMakeLists.txt b/glslang/CMakeLists.txt -index ff91135..efb7f15 100644 ---- a/glslang/CMakeLists.txt -+++ b/glslang/CMakeLists.txt -@@ -89,4 +89,4 @@ if(WIN32) - endif(WIN32) - - install(TARGETS glslang -- ARCHIVE DESTINATION lib) -+ ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}) -diff --git a/glslang/OSDependent/Unix/CMakeLists.txt b/glslang/OSDependent/Unix/CMakeLists.txt -index 174cc91..d98057b 100644 ---- a/glslang/OSDependent/Unix/CMakeLists.txt -+++ b/glslang/OSDependent/Unix/CMakeLists.txt -@@ -2,4 +2,4 @@ add_library(OSDependent STATIC ossource.cpp ../osinclude.h) - set_property(TARGET OSDependent PROPERTY FOLDER glslang) - - install(TARGETS OSDependent -- ARCHIVE DESTINATION lib) -+ ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}) -diff --git a/glslang/OSDependent/Windows/CMakeLists.txt b/glslang/OSDependent/Windows/CMakeLists.txt -index 399760c..744bcbb 100644 ---- a/glslang/OSDependent/Windows/CMakeLists.txt -+++ b/glslang/OSDependent/Windows/CMakeLists.txt -@@ -14,4 +14,4 @@ if(WIN32) - endif(WIN32) - - install(TARGETS OSDependent -- ARCHIVE DESTINATION lib) -+ ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}) -diff --git a/hlsl/CMakeLists.txt b/hlsl/CMakeLists.txt -index c7537e2..5111661 100755 ---- a/hlsl/CMakeLists.txt -+++ b/hlsl/CMakeLists.txt -@@ -23,4 +23,4 @@ if(WIN32) - endif(WIN32) - - install(TARGETS HLSL -- ARCHIVE DESTINATION lib) -+ ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}) --- -1.9.1 - diff --git a/meta-amdfalconx86/recipes-devtools/glslang/glslang_git.bb b/meta-amdfalconx86/recipes-devtools/glslang/glslang_git.bb deleted file mode 100644 index 15852cac..00000000 --- a/meta-amdfalconx86/recipes-devtools/glslang/glslang_git.bb +++ /dev/null @@ -1,39 +0,0 @@ -SUMMARY = "An OpenGL and OpenGL ES shader front end and validator." -DESCRIPTION = "Glslang is the official reference compiler front end \ - for the OpenGL ES and OpenGL shading languages. It \ - implements a strict interpretation of the specifications \ - for these languages. It is open and free for anyone to use, \ - either from a command line or programmatically." -SECTION = "graphics" -HOMEPAGE = "https://www.khronos.org/opengles/sdk/tools/Reference-Compiler" - -inherit cmake - -LICENSE = "BSD" -LIC_FILES_CHKSUM = "file://glslang/Include/Types.h;beginline=1;endline=36;md5=6639a5f9543e833d71e2f4e4ff52f34b" - -S = "${WORKDIR}/git" - -SRCREV = "81cd764b5ffc475bc73f1fb35f75fd1171bb2343" -SRC_URI = "git://github.com/KhronosGroup/glslang \ - file://0001-CMakeLists.txt-obey-CMAKE_INSTALL_LIBDIR.patch" - -FILES_${PN} += "${libdir}/*" - -BBCLASSEXTEND = "native nativesdk" - -do_install_append() { - # Some of the vulkan samples/test require these headers - install -d ${D}${includedir}/SPIRV - cp -f ${S}/SPIRV/GlslangToSpv.h ${D}${includedir}/SPIRV - cp -f ${S}/SPIRV/Logger.h ${D}${includedir}/SPIRV - cp -f ${S}/SPIRV/SPVRemapper.h ${D}${includedir}/SPIRV - cp -f ${S}/SPIRV/spvIR.h ${D}${includedir}/SPIRV - - install -d ${D}${includedir}/glslang/Include - cp -f ${S}/glslang/Include/*.h ${D}${includedir}/glslang/Include - install -d ${D}${includedir}/glslang/Public - cp -f ${S}/glslang/Public/*.h ${D}${includedir}/glslang/Public - install -d ${D}${includedir}/glslang/MachineIndependent - cp -f ${S}/glslang/MachineIndependent/Versions.h ${D}${includedir}/glslang/MachineIndependent -} diff --git a/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools/0001-obey-CMAKE_INSTALL_LIBDIR.patch b/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools/0001-obey-CMAKE_INSTALL_LIBDIR.patch deleted file mode 100644 index d1f0f3b1..00000000 --- a/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools/0001-obey-CMAKE_INSTALL_LIBDIR.patch +++ /dev/null @@ -1,28 +0,0 @@ -From a6b250054e5bc27b87414c860c9b808a4beef552 Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Tue, 16 Aug 2016 16:07:45 +0500 -Subject: [PATCH] obey CMAKE_INSTALL_LIBDIR - -If the path to CMAKE_INSTALL_LIBDIR is not followed appropriately -the installation will not work correctly on a multilib platofrm. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - source/CMakeLists.txt | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/source/CMakeLists.txt b/source/CMakeLists.txt -index de227d6..73672a1 100644 ---- a/source/CMakeLists.txt -+++ b/source/CMakeLists.txt -@@ -198,5 +198,5 @@ target_include_directories(${SPIRV_TOOLS} - - install(TARGETS ${SPIRV_TOOLS} - RUNTIME DESTINATION bin -- LIBRARY DESTINATION lib -- ARCHIVE DESTINATION lib) -+ LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} -+ ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}) --- -1.9.1 - diff --git a/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools/0002-spirv-lesspipe.sh-allow-using-generic-shells.patch b/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools/0002-spirv-lesspipe.sh-allow-using-generic-shells.patch deleted file mode 100644 index 2d51f2fd..00000000 --- a/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools/0002-spirv-lesspipe.sh-allow-using-generic-shells.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 93a770330aa21c91a9b7fce798b73d31cad8f16a Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Tue, 25 Oct 2016 16:12:08 +0500 -Subject: [PATCH] spirv-lesspipe.sh: allow using generic shells - -The script is harmless for any type of shell and -shouldn't be tied with bash to allow catering -more possibilities. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - tools/lesspipe/spirv-lesspipe.sh | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/tools/lesspipe/spirv-lesspipe.sh b/tools/lesspipe/spirv-lesspipe.sh -index 05831d1..4e98fee 100644 ---- a/tools/lesspipe/spirv-lesspipe.sh -+++ b/tools/lesspipe/spirv-lesspipe.sh -@@ -1,4 +1,4 @@ --#!/bin/bash -+#!/bin/sh - - # Copyright (c) 2016 The Khronos Group Inc. - # --- -1.9.1 - diff --git a/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools_git.bb b/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools_git.bb deleted file mode 100644 index f9563366..00000000 --- a/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools_git.bb +++ /dev/null @@ -1,29 +0,0 @@ -SUMMARY = "SPIR-V Tools" -DESCRIPTION = "SPIR-V is a binary intermediate language for representing \ - graphical-shader stages and compute kernels for multiple \ - Khronos APIs, such as OpenCL, OpenGL, and Vulkan." -SECTION = "graphics" -HOMEPAGE = "https://www.khronos.org/registry/spir-v" - -inherit cmake python3native - -LICENSE = "MIT" -LIC_FILES_CHKSUM = "file://LICENSE;md5=ce523927d7bcd789d6c3af579d03ad73" - -S = "${WORKDIR}/git" -SPIRV_HEADERS_LOCATION = "${S}/external/spirv-headers" -HEADERS_VERSION = "1.1" - -SRCREV_spirv-tools = "923a4596b44831a07060df45caacb522613730c9" -SRCREV_spirv-headers = "33d41376d378761ed3a4c791fc4b647761897f26" -SRC_URI = "git://github.com/KhronosGroup/SPIRV-Tools;protocol=http;name=spirv-tools \ - git://github.com/KhronosGroup/SPIRV-Headers;name=spirv-headers;destsuffix=${SPIRV_HEADERS_LOCATION} \ - file://0001-obey-CMAKE_INSTALL_LIBDIR.patch \ - file://0002-spirv-lesspipe.sh-allow-using-generic-shells.patch" - -do_install_append() { - if test -d ${SPIRV_HEADERS_LOCATION}/include/spirv/${HEADERS_VERSION}; then - install -d ${D}/${includedir}/SPIRV - install -m 0644 ${SPIRV_HEADERS_LOCATION}/include/spirv/${HEADERS_VERSION}/* ${D}/${includedir}/SPIRV - fi -} diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0001-CMakeLists-add-include-path-so-Xlib.h-is-found-as-ne.patch b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0001-CMakeLists-add-include-path-so-Xlib.h-is-found-as-ne.patch deleted file mode 100644 index 05fbd360..00000000 --- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0001-CMakeLists-add-include-path-so-Xlib.h-is-found-as-ne.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 32f2777c9cc8f7dfc8b1e0c6894191167e76d5c4 Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Tue, 16 Aug 2016 19:35:35 +0500 -Subject: [PATCH] CMakeLists: add include path so Xlib.h is found as needed - -All the targets including vk_platform.h or directly including -X11/Xlib.h require to know the directory for the installed -header. Add the directory to these so the requirements are -filled in properly. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - CMakeLists.txt | 2 ++ - demos/CMakeLists.txt | 2 +- - layers/CMakeLists.txt | 1 + - libs/vkjson/CMakeLists.txt | 1 + - loader/CMakeLists.txt | 1 + - 5 files changed, 6 insertions(+), 1 deletion(-) - -diff --git a/CMakeLists.txt b/CMakeLists.txt -index 263002e..20e9fd6 100644 ---- a/CMakeLists.txt -+++ b/CMakeLists.txt -@@ -190,6 +190,8 @@ find_path(SPIRV_TOOLS_INCLUDE_DIR spirv-tools/libspirv.h HINTS "${EXTERNAL_SOURC - "${EXTERNAL_SOURCE_ROOT}/source/spirv-tools/external/include" - DOC "Path to spirv-tools/libspirv.h") - -+find_path(X11_XLIB_INCLUDE_DIR X11/Xlib.h DOC "Path to X11/Xlib.h") -+ - find_library(GLSLANG_LIB NAMES glslang - HINTS ${GLSLANG_SEARCH_PATH} ) - -diff --git a/demos/CMakeLists.txt b/demos/CMakeLists.txt -index 26e86fb..9fdabf8 100644 ---- a/demos/CMakeLists.txt -+++ b/demos/CMakeLists.txt -@@ -92,7 +92,7 @@ if(NOT WIN32) - link_libraries(${XCB_LIBRARIES}) - endif() - if(BUILD_WSI_XLIB_SUPPORT) -- include_directories(${X11_INCLUDE_DIRS}) -+ include_directories(${X11_INCLUDE_DIRS} ${X11_XLIB_INCLUDE_DIR}) - link_libraries(${X11_LIBRARIES}) - endif() - if(BUILD_WSI_WAYLAND_SUPPORT) -diff --git a/layers/CMakeLists.txt b/layers/CMakeLists.txt -index 076b847..b384803 100644 ---- a/layers/CMakeLists.txt -+++ b/layers/CMakeLists.txt -@@ -90,6 +90,7 @@ include_directories( - ${CMAKE_CURRENT_SOURCE_DIR}/../loader - ${CMAKE_CURRENT_SOURCE_DIR}/../include/vulkan - ${CMAKE_CURRENT_BINARY_DIR} -+ ${X11_XLIB_INCLUDE_DIR} - ) - - if (WIN32) -diff --git a/libs/vkjson/CMakeLists.txt b/libs/vkjson/CMakeLists.txt -index fc69bb6..fe5e814 100644 ---- a/libs/vkjson/CMakeLists.txt -+++ b/libs/vkjson/CMakeLists.txt -@@ -26,6 +26,7 @@ include_directories( - ${CMAKE_CURRENT_SOURCE_DIR} - ${CMAKE_CURRENT_SOURCE_DIR}/../../loader - ${CMAKE_CURRENT_SOURCE_DIR}/../../include/vulkan -+ ${X11_XLIB_INCLUDE_DIR} - ) - - add_library(vkjson STATIC vkjson.cc vkjson_instance.cc ../../loader/cJSON.c) -diff --git a/loader/CMakeLists.txt b/loader/CMakeLists.txt -index a4d2b21..227162c 100644 ---- a/loader/CMakeLists.txt -+++ b/loader/CMakeLists.txt -@@ -1,6 +1,7 @@ - include_directories( - ${CMAKE_CURRENT_SOURCE_DIR} - ${CMAKE_CURRENT_BINARY_DIR} -+ ${X11_XLIB_INCLUDE_DIR} - ) - - if (WIN32) --- -1.9.1 - diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0003-obey-CMAKE_INSTALL_LIBDIR.patch b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0003-obey-CMAKE_INSTALL_LIBDIR.patch deleted file mode 100644 index 3ede3bac..00000000 --- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0003-obey-CMAKE_INSTALL_LIBDIR.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 52231c657cb1241cee099ca2626c1eebcc944e4e Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Wed, 17 Aug 2016 13:25:36 +0500 -Subject: [PATCH 1/2] obey CMAKE_INSTALL_LIBDIR - -The CMAKE_INSTALL_* directories provide a mechanism to -relocate installations so rather than doing this through -hardcoded variable they should be used whereever possible. -This fixes installation to required directory. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - layers/CMakeLists.txt | 4 ++-- - tests/layers/CMakeLists.txt | 2 +- - 2 files changed, 3 insertions(+), 3 deletions(-) - -diff --git a/layers/CMakeLists.txt b/layers/CMakeLists.txt -index 076b847..cfab1bf 100644 ---- a/layers/CMakeLists.txt -+++ b/layers/CMakeLists.txt -@@ -81,7 +81,7 @@ else() - target_link_Libraries(VkLayer_${target} VkLayer_utils) - add_dependencies(VkLayer_${target} generate_vk_layer_helpers) - set_target_properties(VkLayer_${target} PROPERTIES LINK_FLAGS "-Wl,-Bsymbolic") -- install(TARGETS VkLayer_${target} DESTINATION ${PROJECT_BINARY_DIR}/install_staging) -+ install(TARGETS VkLayer_${target} DESTINATION ${CMAKE_INSTALL_LIBDIR}) - endmacro() - endif() - -@@ -148,7 +148,7 @@ if (WIN32) - add_library(VkLayer_utils STATIC vk_layer_config.cpp vk_layer_extension_utils.cpp vk_layer_utils.cpp) - else() - add_library(VkLayer_utils SHARED vk_layer_config.cpp vk_layer_extension_utils.cpp vk_layer_utils.cpp) -- install(TARGETS VkLayer_utils DESTINATION ${PROJECT_BINARY_DIR}/install_staging) -+ install(TARGETS VkLayer_utils DESTINATION ${CMAKE_INSTALL_LIBDIR}) - endif() - - add_vk_layer(core_validation core_validation.cpp vk_layer_table.cpp vk_safe_struct.cpp descriptor_sets.cpp) -diff --git a/tests/layers/CMakeLists.txt b/tests/layers/CMakeLists.txt -index 87d7793..f62e054 100644 ---- a/tests/layers/CMakeLists.txt -+++ b/tests/layers/CMakeLists.txt -@@ -49,7 +49,7 @@ else() - add_library(VkLayer_${target} SHARED ${ARGN}) - add_dependencies(VkLayer_${target} generate_vk_layer_helpers) - set_target_properties(VkLayer_${target} PROPERTIES LINK_FLAGS "-Wl,-Bsymbolic") -- install(TARGETS VkLayer_${target} DESTINATION ${PROJECT_BINARY_DIR}/install_staging) -+ install(TARGETS VkLayer_${target} DESTINATION ${CMAKE_INSTALL_LIBDIR}) - endmacro() - endif() - --- -1.9.1 - diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0004-install-the-vulkan-loader.patch b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0004-install-the-vulkan-loader.patch deleted file mode 100644 index 68026245..00000000 --- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0004-install-the-vulkan-loader.patch +++ /dev/null @@ -1,27 +0,0 @@ -From d30812f7afc355269df0edd5d4f030d470192cad Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Wed, 17 Aug 2016 13:28:32 +0500 -Subject: [PATCH 2/2] install the vulkan loader - -The vulkan loader is an essential component so it should -be installed to the directory that is intended to be -pushed to the target. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - loader/CMakeLists.txt | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/loader/CMakeLists.txt b/loader/CMakeLists.txt -index a4d2b21..2790faa 100644 ---- a/loader/CMakeLists.txt -+++ b/loader/CMakeLists.txt -@@ -84,4 +84,5 @@ else() - add_library(vulkan SHARED ${LOADER_SRCS}) - set_target_properties(vulkan PROPERTIES SOVERSION "1" VERSION "1.0.26") - target_link_libraries(vulkan -ldl -lpthread -lm) -+ install(TARGETS vulkan DESTINATION ${CMAKE_INSTALL_LIBDIR}) - endif() --- -1.9.1 - diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0005-install-demos.patch b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0005-install-demos.patch deleted file mode 100644 index 08f0f8f0..00000000 --- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0005-install-demos.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 15f3a15ce6d65714f7901eab118a13d9d70a9a3b Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Tue, 30 Aug 2016 15:17:55 +0500 -Subject: [PATCH] install demos - -Install demos to the target. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - demos/CMakeLists.txt | 2 ++ - demos/smoke/CMakeLists.txt | 2 ++ - 2 files changed, 4 insertions(+) - -diff --git a/demos/CMakeLists.txt b/demos/CMakeLists.txt -index 9fdabf8..42e5499 100644 ---- a/demos/CMakeLists.txt -+++ b/demos/CMakeLists.txt -@@ -136,5 +136,8 @@ else() - target_link_libraries(cube ${LIBRARIES} ) - endif() - -+install(TARGETS cube DESTINATION ${CMAKE_INSTALL_BINDIR}) -+install(TARGETS tri DESTINATION ${CMAKE_INSTALL_BINDIR}) -+install(TARGETS vulkaninfo DESTINATION ${CMAKE_INSTALL_BINDIR}) - add_subdirectory(smoke) - -diff --git a/demos/smoke/CMakeLists.txt b/demos/smoke/CMakeLists.txt -index 4dc90cd..415ac2f 100644 ---- a/demos/smoke/CMakeLists.txt -+++ b/demos/smoke/CMakeLists.txt -@@ -85,3 +85,5 @@ add_executable(smoketest ${sources}) - target_compile_definitions(smoketest ${definitions}) - target_include_directories(smoketest ${includes}) - target_link_libraries(smoketest ${libraries}) -+ -+install(TARGETS smoketest DESTINATION ${CMAKE_INSTALL_BINDIR}) -diff --git a/libs/vkjson/CMakeLists.txt b/libs/vkjson/CMakeLists.txt -index 4c0aef8..9b03d3d 100644 ---- a/libs/vkjson/CMakeLists.txt -+++ b/libs/vkjson/CMakeLists.txt -@@ -32,6 +32,8 @@ if(UNIX) - set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-sign-compare") - add_executable(vkjson_unittest vkjson_unittest.cc) - add_executable(vkjson_info vkjson_info.cc) -+ install(TARGETS vkjson_unittest DESTINATION ${CMAKE_INSTALL_BINDIR}) -+ install(TARGETS vkjson_info DESTINATION ${CMAKE_INSTALL_BINDIR}) - else() - set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D_CRT_SECURE_NO_WARNINGS") - add_executable(vkjson_unittest vkjson_unittest.cc) --- -1.9.1 - diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0006-json-correct-layer-lib-paths.patch b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0006-json-correct-layer-lib-paths.patch deleted file mode 100644 index 54d092ba..00000000 --- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0006-json-correct-layer-lib-paths.patch +++ /dev/null @@ -1,114 +0,0 @@ -From e66538f44c606d9f6c2ada9d78b310343e4386da Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Wed, 31 Aug 2016 15:13:28 +0500 -Subject: [PATCH] json: correct layer lib paths - -Rather than using a hardcoded ./ path for the libraries -we should use loose paths so the system could search -on its own when the library is required. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - layers/linux/VkLayer_core_validation.json | 2 +- - layers/linux/VkLayer_image.json | 2 +- - layers/linux/VkLayer_object_tracker.json | 2 +- - layers/linux/VkLayer_parameter_validation.json | 2 +- - layers/linux/VkLayer_swapchain.json | 2 +- - layers/linux/VkLayer_threading.json | 2 +- - layers/linux/VkLayer_unique_objects.json | 2 +- - 7 files changed, 7 insertions(+), 7 deletions(-) - -diff --git a/layers/linux/VkLayer_core_validation.json b/layers/linux/VkLayer_core_validation.json -index 3f2162d..c0ef9b7 100644 ---- a/layers/linux/VkLayer_core_validation.json -+++ b/layers/linux/VkLayer_core_validation.json -@@ -3,7 +3,7 @@ - "layer" : { - "name": "VK_LAYER_LUNARG_core_validation", - "type": "GLOBAL", -- "library_path": "./libVkLayer_core_validation.so", -+ "library_path": "libVkLayer_core_validation.so", - "api_version": "1.0.26", - "implementation_version": "1", - "description": "LunarG Validation Layer", -diff --git a/layers/linux/VkLayer_image.json b/layers/linux/VkLayer_image.json -index 97a250e..6fa3bbd 100644 ---- a/layers/linux/VkLayer_image.json -+++ b/layers/linux/VkLayer_image.json -@@ -3,7 +3,7 @@ - "layer" : { - "name": "VK_LAYER_LUNARG_image", - "type": "GLOBAL", -- "library_path": "./libVkLayer_image.so", -+ "library_path": "libVkLayer_image.so", - "api_version": "1.0.26", - "implementation_version": "1", - "description": "LunarG Validation Layer", -diff --git a/layers/linux/VkLayer_object_tracker.json b/layers/linux/VkLayer_object_tracker.json -index 1c5d79b..49e5a29 100644 ---- a/layers/linux/VkLayer_object_tracker.json -+++ b/layers/linux/VkLayer_object_tracker.json -@@ -3,7 +3,7 @@ - "layer" : { - "name": "VK_LAYER_LUNARG_object_tracker", - "type": "GLOBAL", -- "library_path": "./libVkLayer_object_tracker.so", -+ "library_path": "libVkLayer_object_tracker.so", - "api_version": "1.0.26", - "implementation_version": "1", - "description": "LunarG Validation Layer", -diff --git a/layers/linux/VkLayer_parameter_validation.json b/layers/linux/VkLayer_parameter_validation.json -index 899ea88..6df74f8 100644 ---- a/layers/linux/VkLayer_parameter_validation.json -+++ b/layers/linux/VkLayer_parameter_validation.json -@@ -3,7 +3,7 @@ - "layer" : { - "name": "VK_LAYER_LUNARG_parameter_validation", - "type": "GLOBAL", -- "library_path": "./libVkLayer_parameter_validation.so", -+ "library_path": "libVkLayer_parameter_validation.so", - "api_version": "1.0.26", - "implementation_version": "1", - "description": "LunarG Validation Layer", -diff --git a/layers/linux/VkLayer_swapchain.json b/layers/linux/VkLayer_swapchain.json -index 5fe0ef8..6d0b500 100644 ---- a/layers/linux/VkLayer_swapchain.json -+++ b/layers/linux/VkLayer_swapchain.json -@@ -3,7 +3,7 @@ - "layer" : { - "name": "VK_LAYER_LUNARG_swapchain", - "type": "GLOBAL", -- "library_path": "./libVkLayer_swapchain.so", -+ "library_path": "libVkLayer_swapchain.so", - "api_version": "1.0.26", - "implementation_version": "1", - "description": "LunarG Validation Layer", -diff --git a/layers/linux/VkLayer_threading.json b/layers/linux/VkLayer_threading.json -index 59feb59..fd6bedf 100644 ---- a/layers/linux/VkLayer_threading.json -+++ b/layers/linux/VkLayer_threading.json -@@ -3,7 +3,7 @@ - "layer" : { - "name": "VK_LAYER_GOOGLE_threading", - "type": "GLOBAL", -- "library_path": "./libVkLayer_threading.so", -+ "library_path": "libVkLayer_threading.so", - "api_version": "1.0.26", - "implementation_version": "1", - "description": "Google Validation Layer", -diff --git a/layers/linux/VkLayer_unique_objects.json b/layers/linux/VkLayer_unique_objects.json -index 59e1f89..72b77ee 100644 ---- a/layers/linux/VkLayer_unique_objects.json -+++ b/layers/linux/VkLayer_unique_objects.json -@@ -3,7 +3,7 @@ - "layer" : { - "name": "VK_LAYER_GOOGLE_unique_objects", - "type": "GLOBAL", -- "library_path": "./libVkLayer_unique_objects.so", -+ "library_path": "libVkLayer_unique_objects.so", - "api_version": "1.0.26", - "implementation_version": "1", - "description": "Google Validation Layer" --- -1.9.1 - diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0008-demos-make-shader-location-relative.patch b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0008-demos-make-shader-location-relative.patch deleted file mode 100644 index 16409b57..00000000 --- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0008-demos-make-shader-location-relative.patch +++ /dev/null @@ -1,261 +0,0 @@ -From 4e68da29ebc45a41845d7127979878930b4c170b Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Mon, 5 Sep 2016 15:47:16 +0500 -Subject: [PATCH 1/2] demos: make shader location relative - -The demo binaries expect the shader (frag/vert.spv) -location to be PWD so a user has to cd to /usr/bin -if the binaries are installed there in order to -run them correctly. -This patch tries to find the location of the binary -and then assumes that the shaders are located in the -same location as the binary so a user can install -everything to a single dir and that will work. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - demos/cube.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++------ - demos/tri.c | 49 ++++++++++++++++++++++++++++++++++++++++++++-- - 2 files changed, 105 insertions(+), 8 deletions(-) - -diff --git a/demos/cube.c b/demos/cube.c -index 6017444..f79bc59 100644 ---- a/demos/cube.c -+++ b/demos/cube.c -@@ -29,6 +29,7 @@ - #include <stdbool.h> - #include <assert.h> - #include <signal.h> -+#include <unistd.h> - #if defined(VK_USE_PLATFORM_XLIB_KHR) || defined(VK_USE_PLATFORM_XCB_KHR) - #include <X11/Xutil.h> - #endif -@@ -415,6 +416,8 @@ struct demo { - - uint32_t current_buffer; - uint32_t queue_count; -+ -+ char bin_path[255]; - }; - - VKAPI_ATTR VkBool32 VKAPI_CALL -@@ -1206,18 +1209,25 @@ static void demo_prepare_textures(struct demo *demo) { - const VkFormat tex_format = VK_FORMAT_R8G8B8A8_UNORM; - VkFormatProperties props; - uint32_t i; -+ char tex_file[255]; - - vkGetPhysicalDeviceFormatProperties(demo->gpu, tex_format, &props); - - for (i = 0; i < DEMO_TEXTURE_COUNT; i++) { - VkResult U_ASSERT_ONLY err; -- -+ if (strlen(demo->bin_path) > 0) { -+ strcpy(tex_file, demo->bin_path); -+ strcat(tex_file, "/"); -+ strcat(tex_file, tex_files[i]); -+ } -+ else -+ strcpy(tex_file, tex_files[i]); - if ((props.linearTilingFeatures & - VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT) && - !demo->use_staging_buffer) { - /* Device can texture using linear textures */ - demo_prepare_texture_image( -- demo, tex_files[i], &demo->textures[i], VK_IMAGE_TILING_LINEAR, -+ demo, tex_file, &demo->textures[i], VK_IMAGE_TILING_LINEAR, - VK_IMAGE_USAGE_SAMPLED_BIT, - VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | - VK_MEMORY_PROPERTY_HOST_COHERENT_BIT); -@@ -1228,13 +1238,13 @@ static void demo_prepare_textures(struct demo *demo) { - - memset(&staging_texture, 0, sizeof(staging_texture)); - demo_prepare_texture_image( -- demo, tex_files[i], &staging_texture, VK_IMAGE_TILING_LINEAR, -+ demo, tex_file, &staging_texture, VK_IMAGE_TILING_LINEAR, - VK_IMAGE_USAGE_TRANSFER_SRC_BIT, - VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | - VK_MEMORY_PROPERTY_HOST_COHERENT_BIT); - - demo_prepare_texture_image( -- demo, tex_files[i], &demo->textures[i], VK_IMAGE_TILING_OPTIMAL, -+ demo, tex_file, &demo->textures[i], VK_IMAGE_TILING_OPTIMAL, - (VK_IMAGE_USAGE_TRANSFER_DST_BIT | VK_IMAGE_USAGE_SAMPLED_BIT), - VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT); - -@@ -1557,8 +1567,16 @@ static VkShaderModule demo_prepare_vs(struct demo *demo) { - #else - void *vertShaderCode; - size_t size; -+ char fname[255]; -+ if (strlen(demo->bin_path) > 0) { -+ strcpy(fname, demo->bin_path); -+ strcat(fname, "/"); -+ strcat(fname, "cube-vert.spv"); -+ } -+ else -+ strcpy(fname, "cube-vert.spv"); - -- vertShaderCode = demo_read_spv("cube-vert.spv", &size); -+ vertShaderCode = demo_read_spv(fname, &size); - - demo->vert_shader_module = - demo_prepare_shader_module(demo, vertShaderCode, size); -@@ -1582,8 +1600,16 @@ static VkShaderModule demo_prepare_fs(struct demo *demo) { - #else - void *fragShaderCode; - size_t size; -+ char fname[255]; -+ if (strlen(demo->bin_path) > 0) { -+ strcpy(fname, demo->bin_path); -+ strcat(fname, "/"); -+ strcat(fname, "cube-frag.spv"); -+ } -+ else -+ strcpy(fname, "cube-frag.spv"); - -- fragShaderCode = demo_read_spv("cube-frag.spv", &size); -+ fragShaderCode = demo_read_spv(fname, &size); - - demo->frag_shader_module = - demo_prepare_shader_module(demo, fragShaderCode, size); -@@ -3034,6 +3060,30 @@ static void demo_init_connection(struct demo *demo) { - #endif - } - -+static void find_bin_path(char *in_arg, char *ret_path) { -+ char *ptr = getenv("PATH"); -+ char *pch_temp; -+ char pch[255]; -+ -+ if (access(in_arg, F_OK ) == 0) { -+ pch_temp = strrchr(in_arg, '/'); -+ strncpy(ret_path, in_arg, strlen(in_arg) - strlen(pch_temp)); -+ } else if (in_arg[0] != '/') { -+ pch_temp = strtok(ptr, ":"); -+ while (pch_temp != NULL) { -+ strcpy(pch, pch_temp); -+ strcat(pch, "/"); -+ strcat(pch, in_arg); -+ if ((access(pch, F_OK ) == 0)) { -+ strcpy(ret_path, pch_temp); -+ break; -+ } -+ else -+ pch_temp = strtok(NULL, ":"); -+ } -+ } -+} -+ - static void demo_init(struct demo *demo, int argc, char **argv) { - vec3 eye = {0.0f, 3.0f, 5.0f}; - vec3 origin = {0, 0, 0}; -@@ -3053,6 +3053,8 @@ static void demo_init(struct demo *demo, int argc, char **argv) { - mat4x4_identity(demo->model_matrix); - - demo->projection_matrix[1][1]*=-1; //Flip projection matrix from GL to Vulkan orientation. -+ -+ find_bin_path(argv[0], demo->bin_path); - } - - #if defined(VK_USE_PLATFORM_WIN32_KHR) -diff --git a/demos/tri.c b/demos/tri.c -index 35d33f2..77ee5a1 100644 ---- a/demos/tri.c -+++ b/demos/tri.c -@@ -39,6 +39,7 @@ - #include <stdbool.h> - #include <assert.h> - #include <signal.h> -+#include <unistd.h> - - #ifdef _WIN32 - #pragma comment(linker, "/subsystem:windows") -@@ -262,6 +263,8 @@ struct demo { - bool quit; - uint32_t current_buffer; - uint32_t queue_count; -+ -+ char bin_path[255]; - }; - - VKAPI_ATTR VkBool32 VKAPI_CALL -@@ -1288,8 +1291,16 @@ static VkShaderModule demo_prepare_vs(struct demo *demo) { - #else - void *vertShaderCode; - size_t size = 0; -+ char fname[255]; -+ if (strlen(demo->bin_path) > 0) { -+ strcpy(fname, demo->bin_path); -+ strcat(fname, "/"); -+ strcat(fname, "tri-vert.spv"); -+ } -+ else -+ strcpy(fname, "tri-vert.spv"); - -- vertShaderCode = demo_read_spv("tri-vert.spv", &size); -+ vertShaderCode = demo_read_spv(fname, &size); - - demo->vert_shader_module = - demo_prepare_shader_module(demo, vertShaderCode, size); -@@ -1313,8 +1324,16 @@ static VkShaderModule demo_prepare_fs(struct demo *demo) { - #else - void *fragShaderCode; - size_t size; -+ char fname[255]; -+ if (strlen(demo->bin_path) > 0) { -+ strcpy(fname, demo->bin_path); -+ strcat(fname, "/"); -+ strcat(fname, "tri-frag.spv"); -+ } -+ else -+ strcpy(fname, "tri-frag.spv"); - -- fragShaderCode = demo_read_spv("tri-frag.spv", &size); -+ fragShaderCode = demo_read_spv(fname, &size); - - demo->frag_shader_module = - demo_prepare_shader_module(demo, fragShaderCode, size); -@@ -2447,6 +2466,30 @@ static void demo_init_connection(struct demo *demo) { - #endif // _WIN32 - } - -+static void find_bin_path(const char *in_arg, char *ret_path) { -+ char *ptr = getenv("PATH"); -+ char *pch_temp; -+ char pch[255]; -+ -+ if (access(in_arg, F_OK ) == 0) { -+ pch_temp = strrchr(in_arg, '/'); -+ strncpy(ret_path, in_arg, strlen(in_arg) - strlen(pch_temp)); -+ } else if (in_arg[0] != '/') { -+ pch_temp = strtok(ptr, ":"); -+ while (pch_temp != NULL) { -+ strcpy(pch, pch_temp); -+ strcat(pch, "/"); -+ strcat(pch, in_arg); -+ if ((access(pch, F_OK ) == 0)) { -+ strcpy(ret_path, pch_temp); -+ break; -+ } -+ else -+ pch_temp = strtok(NULL, ":"); -+ } -+ } -+} -+ - static void demo_init(struct demo *demo, const int argc, const char *argv[]) - { - memset(demo, 0, sizeof(*demo)); -@@ -2490,6 +2533,8 @@ static void demo_init(struct demo *demo, const int argc, const char *argv[]) - demo->height = 300; - demo->depthStencil = 1.0; - demo->depthIncrement = -0.01f; -+ -+ find_bin_path(argv[0], demo->bin_path); - } - - static void demo_cleanup(struct demo *demo) { --- -1.9.1 - diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0009-vulkaninfo.c-fix-segfault-when-DISPLAY-is-not-set.patch b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0009-vulkaninfo.c-fix-segfault-when-DISPLAY-is-not-set.patch deleted file mode 100644 index 25785ffb..00000000 --- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0009-vulkaninfo.c-fix-segfault-when-DISPLAY-is-not-set.patch +++ /dev/null @@ -1,67 +0,0 @@ -From b73227e97086116e596206b22ce0356bfc9b0a2c Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Fri, 11 Nov 2016 14:48:54 +0500 -Subject: [PATCH] vulkaninfo.c: fix segfault when DISPLAY is not set - -Both xlib and xcb interfaces expect the DISPLAY environment -variable to be set before creation of a window and the -display creation mechanism would segfault if that is -not the case and won't provide the user with details on -what has to be done to correct the problem. -We now handle such scenarios and exit cleanly after -providing the user with some details. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - demos/vulkaninfo.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/demos/vulkaninfo.c b/demos/vulkaninfo.c -index 324720c..da0a7c3 100644 ---- a/demos/vulkaninfo.c -+++ b/demos/vulkaninfo.c -@@ -900,6 +900,9 @@ static void app_create_xlib_window(struct app_instance *inst) { - long visualMask = VisualScreenMask; - int numberOfVisuals; - -+ if (inst->xlib_display == NULL) -+ return; -+ - XVisualInfo vInfoTemplate={}; - vInfoTemplate.screen = DefaultScreen(inst->xlib_display); - XVisualInfo *visualInfo = XGetVisualInfo(inst->xlib_display, visualMask, -@@ -1488,6 +1491,12 @@ int main(int argc, char **argv) { - app_destroy_win32_window(&inst); - } - #endif -+#if defined(VK_USE_PLATFORM_XCB_KHR) || defined(VK_USE_PLATFORM_XLIB_KHR) -+ if (getenv("DISPLAY") == NULL) { -+ printf("'DISPLAY' environment variable not set... Exiting!\n"); -+ goto out; -+ } -+#endif - //--XCB-- - #ifdef VK_USE_PLATFORM_XCB_KHR - if (has_extension(VK_KHR_XCB_SURFACE_EXTENSION_NAME, -@@ -1508,6 +1517,10 @@ int main(int argc, char **argv) { - if (has_extension(VK_KHR_XLIB_SURFACE_EXTENSION_NAME, - inst.global_extension_count, inst.global_extensions)) { - app_create_xlib_window(&inst); -+ if (inst.xlib_display == NULL) { -+ printf("'DISPLAY' variable not set correctly. Exiting!\n'"); -+ goto out; -+ } - for (i = 0; i < gpu_count; i++) { - app_create_xlib_surface(&inst); - printf("GPU id : %u (%s)\n", i, gpus[i].props.deviceName); -@@ -1528,6 +1541,7 @@ int main(int argc, char **argv) { - printf("\n\n"); - } - -+out: - for (i = 0; i < gpu_count; i++) - app_gpu_destroy(&gpus[i]); - --- -1.9.1 - diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers_1.0.26.bb b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers_1.0.26.bb deleted file mode 100644 index e8ea2605..00000000 --- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers_1.0.26.bb +++ /dev/null @@ -1,58 +0,0 @@ -SUMMARY = "Vulkan Ecosystem Components - Loader and Validation Layers" -DESCRIPTION = "Vulkan is a new generation graphics and compute API that \ - provides high-efficiency, cross-platform access to modern \ - GPUs used in a wide variety of devices from PCs and \ - consoles to mobile phones and embedded platforms." -SECTION = "graphics" -HOMEPAGE = "https://www.khronos.org/vulkan" -DEPENDS = "bison-native libx11 libxcb glslang glslang-native spirv-tools \ - libice libxext libsm" - -RDEPENDS_${PN} = "${PN}-layer-libs libxcb-sync libxcb-present libxcb-dri3" - -inherit cmake python3native - -REQUIRED_DISTRO_FEATURES = "x11" - -LICENSE = "Apache-2.0" -LIC_FILES_CHKSUM = "file://LICENSE.txt;md5=99c647ca3d4f6a4b9d8628f757aad156" - -S = "${WORKDIR}/git" - -SRCREV = "ebf46deb849a2d4cab3382c606a9fe36699dfa78" -SRC_URI = "git://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers;branch=sdk-${PV} \ - file://0001-CMakeLists-add-include-path-so-Xlib.h-is-found-as-ne.patch \ - file://0003-obey-CMAKE_INSTALL_LIBDIR.patch \ - file://0004-install-the-vulkan-loader.patch \ - file://0005-install-demos.patch \ - file://0006-json-correct-layer-lib-paths.patch \ - file://0008-demos-make-shader-location-relative.patch \ - file://0009-vulkaninfo.c-fix-segfault-when-DISPLAY-is-not-set.patch" - -EXTRA_OECMAKE = " \ - -DCUSTOM_GLSLANG_BIN_ROOT=1 \ - -DGLSLANG_BINARY_ROOT=${STAGING_DIR_HOST}/usr \ - -DCUSTOM_SPIRV_TOOLS_BIN_ROOT=1 \ - -DSPIRV_TOOLS_BINARY_ROOT=${STAGING_DIR_HOST}/usr \ - -DBUILD_TESTS=1 \ -" - -PACKAGES =+ "${PN}-layer-libs" -FILES_${PN}-layer-libs = "${libdir}/libVkLayer_*.so" - -FILES_SOLIBSDEV = "" -FILES_${PN} += "${libdir}/libvulkan.so" -INSANE_SKIP_${PN} = "dev-so" - -do_install_append() { - cp -f ${B}/demos/*.spv ${D}${bindir} - cp -f ${B}/demos/*.ppm ${D}${bindir} - mv ${D}${bindir}/tri ${D}${bindir}/tri-vulkan - mv ${D}${bindir}/cube ${D}${bindir}/cube-vulkan - - install -d ${D}${sysconfdir}/vulkan/explicit_layer.d - cp -f ${B}/layers/*.json ${D}${sysconfdir}/vulkan/explicit_layer.d - - install -d ${D}${includedir} - cp -rf ${S}/include/vulkan ${D}${includedir} -} diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/amd-spi_1.0.bb b/meta-amdfalconx86/recipes-kernel/amd-spi/amd-spi_1.0.bb deleted file mode 100644 index b23e5ce6..00000000 --- a/meta-amdfalconx86/recipes-kernel/amd-spi/amd-spi_1.0.bb +++ /dev/null @@ -1,16 +0,0 @@ -DESCRIPTION = "This kernel module provides support for AMD SPI controller driver" -LICENSE = "BSD | GPLv2" -LIC_FILES_CHKSUM = "file://spi_amd.c;endline=29;md5=e9fdf6da58412e619d89ec9e135a1be3" - -inherit module - -SRC_URI = "file://Makefile \ - file://spi_amd.c \ - file://spi_amd.h \ - file://spirom.c \ - file://spirom.h \ - " - -S = "${WORKDIR}" - -# The inherit of module.bbclass will take care of the rest diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/Makefile b/meta-amdfalconx86/recipes-kernel/amd-spi/files/Makefile deleted file mode 100644 index f778a69a..00000000 --- a/meta-amdfalconx86/recipes-kernel/amd-spi/files/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -obj-m := spi_amd.o spirom.o - -SRC := $(shell pwd) - -all: - $(MAKE) -C $(KERNEL_SRC) M=$(SRC) - -modules_install: - $(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install - -clean: - rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c - rm -f Module.markers Module.symvers modules.order - rm -rf .tmp_versions Modules.symvers diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.c b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.c deleted file mode 100644 index 76c08cec..00000000 --- a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.c +++ /dev/null @@ -1,476 +0,0 @@ -/***************************************************************************** -* -* Copyright (c) 2013, Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* -***************************************************************************/ -#include <linux/init.h> -#include <linux/module.h> -#include <linux/pci.h> -#include <linux/spi/spi.h> -#include <linux/kthread.h> - -#include "spi_amd.h" - -struct amd_platform_data { - u8 chip_select; -}; - -struct amd_spi { - void __iomem *io_remap_addr; - unsigned long io_base_addr; - u32 rom_addr; - struct spi_master *master; - struct amd_platform_data controller_data; - struct task_struct *kthread_spi; - struct list_head msg_queue; - wait_queue_head_t wq; -}; - -static struct pci_device_id amd_spi_pci_device_id[] = { - { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LPC_BRIDGE) }, - {} -}; -MODULE_DEVICE_TABLE(pci, amd_spi_pci_device_id); - -static inline u8 amd_spi_readreg8(struct spi_master *master, int idx) -{ - struct amd_spi *amd_spi = spi_master_get_devdata(master); - - return ioread8((u8 *)amd_spi->io_remap_addr + idx); -} - -static inline void amd_spi_writereg8(struct spi_master *master, int idx, - u8 val) -{ - struct amd_spi *amd_spi = spi_master_get_devdata(master); - - iowrite8(val, ((u8 *)amd_spi->io_remap_addr + idx)); -} - -static inline void amd_spi_setclear_reg8(struct spi_master *master, int idx, - u8 set, u8 clear) -{ - u8 tmp = amd_spi_readreg8(master, idx); - tmp = (tmp & ~clear) | set; - amd_spi_writereg8(master, idx, tmp); -} - -static inline u32 amd_spi_readreg32(struct spi_master *master, int idx) -{ - struct amd_spi *amd_spi = spi_master_get_devdata(master); - - return ioread32((u8 *)amd_spi->io_remap_addr + idx); -} - -static inline void amd_spi_writereg32(struct spi_master *master, int idx, - u32 val) -{ - struct amd_spi *amd_spi = spi_master_get_devdata(master); - - iowrite32(val, ((u8 *)amd_spi->io_remap_addr + idx)); -} - -static inline void amd_spi_setclear_reg32(struct spi_master *master, int idx, - u32 set, u32 clear) -{ - u32 tmp = amd_spi_readreg32(master, idx); - tmp = (tmp & ~clear) | set; - amd_spi_writereg32(master, idx, tmp); -} - -static void amd_spi_select_chip(struct spi_master *master) -{ - struct amd_spi *amd_spi = spi_master_get_devdata(master); - u8 chip_select = amd_spi->controller_data.chip_select; - - amd_spi_setclear_reg8(master, AMD_SPI_ALT_CS_REG, chip_select, - AMD_SPI_ALT_CS_MASK); -} - - -static void amd_spi_clear_fifo_ptr(struct spi_master *master) -{ - amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, - AMD_SPI_FIFO_CLEAR); -} - -static void amd_spi_set_opcode(struct spi_master *master, u8 cmd_opcode) -{ - amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, cmd_opcode, - AMD_SPI_OPCODE_MASK); -} - -static inline void amd_spi_set_rx_count(struct spi_master *master, - u8 rx_count) -{ - amd_spi_setclear_reg8(master, AMD_SPI_RX_COUNT_REG, rx_count, 0xff); -} - -static inline void amd_spi_set_tx_count(struct spi_master *master, - u8 tx_count) -{ - amd_spi_setclear_reg8(master, AMD_SPI_TX_COUNT_REG, tx_count, 0xff); -} - -static void amd_spi_execute_opcode(struct spi_master *master) -{ - struct amd_spi *amd_spi = spi_master_get_devdata(master); - bool spi_busy; - - /* Set ExecuteOpCode bit in the CTRL0 register */ - amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, - AMD_SPI_EXEC_CMD); - - /* poll for SPI bus to become idle */ - spi_busy = (ioread32((u8 *)amd_spi->io_remap_addr + - AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY; - while (spi_busy) { - set_current_state(TASK_INTERRUPTIBLE); - schedule(); - set_current_state(TASK_RUNNING); - spi_busy = (ioread32((u8 *)amd_spi->io_remap_addr + - AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY; - } -} - -/* Helper function */ -#ifdef CONFIG_SPI_DEBUG -static void amd_spi_dump_reg(struct spi_master *master) -{ - struct amd_spi *amd_spi = spi_master_get_devdata(master); - - printk(KERN_DEBUG DRIVER_NAME ": SPI CTRL 0 registers: 0x%.8x\n", - ioread32((u8 *)amd_spi->io_remap_addr + AMD_SPI_CTRL0_REG)); - /* - * We cannot read CTRL1 register, because reading it would - * inadvertently increment the FIFO pointer. - */ - printk(KERN_DEBUG DRIVER_NAME ": SPI ALT CS registers: 0x%.2x\n", - ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_ALT_CS_REG)); - printk(KERN_DEBUG DRIVER_NAME ": SPI Tx Byte Count: 0x%.2x\n", - ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_TX_COUNT_REG)); - printk(KERN_DEBUG DRIVER_NAME ": SPI Rx Byte Count: 0x%.2x\n", - ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_RX_COUNT_REG)); - printk(KERN_DEBUG DRIVER_NAME ": SPI Status registers: 0x%.8x\n", - ioread32((u8 *)amd_spi->io_remap_addr + AMD_SPI_STATUS_REG)); -} -#else -static void amd_spi_dump_reg(struct spi_master *master) {} -#endif - - -static int amd_spi_master_setup(struct spi_device *spi) -{ - struct spi_master *master = spi->master; - struct amd_spi *amd_spi = spi_master_get_devdata(master); - - amd_spi->controller_data.chip_select = spi->chip_select; - - amd_spi_select_chip(master); - - return 0; -} - -static int amd_spi_master_transfer(struct spi_master *master, - struct spi_message *msg) -{ - struct amd_spi *amd_spi = spi_master_get_devdata(master); - - /* - * Add new message to the queue and let the kernel thread know - * about it. - */ - list_add_tail(&msg->queue, &amd_spi->msg_queue); - wake_up_interruptible(&amd_spi->wq); - - return 0; -} -static int amd_spi_thread(void *t) -{ - struct amd_spi *amd_spi = t; - struct spi_master *master = amd_spi->master; - struct spi_transfer *transfer = NULL; - struct spi_message *message = NULL; - int direction = 0,i = 0,saved_index = 0; - int opcode_found = 0,recv_flag = 0,tx_len = 0,rx_len = 0; - u8 cmd_opcode = 0; - u8 *buffer = NULL; - - /* - * What we do here is actually pretty simple. We pick one message - * at a time from the message queue set up by the controller, and - * then process all the spi_transfers of that spi_message in one go. - * We then remove the message from the queue, and complete the - * transaction. This might not be the best approach, but this is how - * we chose to implement this. Note that out SPI controller has FIFO - * size of 70 bytes, but we consider it to contain a maximum of - * 64-bytes of data and 3-bytes of address. - */ - while (1) { - /* - * Let us wait on a wait queue till the message queue is empty. - */ - wait_event_interruptible(amd_spi->wq, - !list_empty(&amd_spi->msg_queue)); - - /* stop condition */ - if (kthread_should_stop()) { - set_current_state(TASK_RUNNING); - break; - } - - /* - * Else, pull the very first message from the queue and process - * all transfers within that message. And process the messages - * in a pure linear fashion. We also remove the spi_message - * from the queue. - */ - message = list_entry(amd_spi->msg_queue.next, - struct spi_message, queue); - list_del_init(&message->queue); - - /* We store the CS# line to be used for this spi_message */ - amd_spi->controller_data.chip_select = - message->spi->chip_select; - - /* Setting all variables to default value. */ - direction = i = 0; - opcode_found = 0; - recv_flag = tx_len = rx_len = 0; - cmd_opcode = 0; - buffer = NULL; - saved_index = 0; - - amd_spi_select_chip(master); - - /* - * This loop extracts spi_transfers from the spi message, - * programs the command into command register. Pointer variable - * *buffer* points to either tx_buf or rx_buf of spi_transfer - * depending on direction of transfer. Also programs FIFO of - * controller if data has to be transmitted. - */ - list_for_each_entry(transfer, &message->transfers, - transfer_list) - { - if(transfer->rx_buf != NULL) - direction = RECEIVE; - else if(transfer->tx_buf != NULL) - direction = TRANSMIT; - - switch (direction) { - case TRANSMIT: - buffer = (u8 *)transfer->tx_buf; - - if(opcode_found != 1) { - /* Store no. of bytes to be sent into - * FIFO */ - tx_len = transfer->len - 1; - /* Store opcode */ - cmd_opcode = *(u8 *)transfer->tx_buf; - /* Pointing to start of TX data */ - buffer++; - /* Program the command register*/ - amd_spi_set_opcode(master, cmd_opcode); - opcode_found = 1; - } else { - /* Store no. of bytes to be sent into - * FIFO */ - tx_len = transfer->len; - } - - /* Write data into the FIFO. */ - for (i = 0; i < tx_len; i++) { - iowrite8(buffer[i], - ((u8 *)amd_spi->io_remap_addr + - AMD_SPI_FIFO_BASE + - i + saved_index)); - } - - /* Set no. of bytes to be transmitted */ - amd_spi_set_tx_count(master, - tx_len + saved_index); - - /* - * Saving the index, from where next - * spi_transfer's data will be stored in FIFO. - */ - saved_index = i; - break; - case RECEIVE: - /* Store no. of bytes to be received from - * FIFO */ - rx_len = transfer->len; - buffer = (u8 *)transfer->rx_buf; - recv_flag=1; - break; - } - } - - /* Set the RX count to the number of bytes to expect in - * response */ - amd_spi_set_rx_count(master, rx_len ); - amd_spi_clear_fifo_ptr(master); - amd_spi_dump_reg(master); - /* Executing command */ - amd_spi_execute_opcode(master); - amd_spi_dump_reg(master); - - if(recv_flag == 1) { - /* Read data from FIFO to receive buffer */ - for (i = 0; i < rx_len; i++) { - buffer[i] = ioread8((u8 *)amd_spi->io_remap_addr - + AMD_SPI_FIFO_BASE - + tx_len + i); - } - - recv_flag = 0; - } - - /* Update statistics */ - message->actual_length = tx_len + rx_len + 1 ; - /* complete the transaction */ - message->status = 0; - spi_finalize_current_message(master); - } - - return 0; -} - -static int amd_spi_pci_probe(struct pci_dev *pdev, - const struct pci_device_id *id) -{ - struct device *dev = &pdev->dev; - struct spi_master *master; - struct amd_spi *amd_spi; - u32 io_base_addr; - int err = 0; - - /* Allocate storage for spi_master and driver private data */ - master = spi_alloc_master(dev, sizeof(struct amd_spi)); - if (master == NULL) { - dev_err(dev, "Error allocating SPI master\n"); - return -ENOMEM; - } - - amd_spi = spi_master_get_devdata(master); - amd_spi->master = master; - - /* - * Lets first get the base address of SPI registers. The SPI Base - * Address is stored at offset 0xA0 into the LPC PCI configuration - * space. As per the specification, it is stored at bits 6:31 of the - * register. The address is aligned at 64-byte boundary, - * so we should just mask the lower 6 bits and get the address. - */ - pci_read_config_dword(pdev, AMD_PCI_LPC_SPI_BASE_ADDR_REG, - &io_base_addr); - amd_spi->io_base_addr = io_base_addr & AMD_SPI_BASE_ADDR_MASK; - amd_spi->io_remap_addr = ioremap_nocache(amd_spi->io_base_addr, - AMD_SPI_MEM_SIZE); - if (amd_spi->io_remap_addr == NULL) { - dev_err(dev, "ioremap of SPI registers failed\n"); - err = -ENOMEM; - goto err_free_master; - } - dev_dbg(dev, "io_base_addr: 0x%.8lx, io_remap_address: %p\n", - amd_spi->io_base_addr, amd_spi->io_remap_addr); - INIT_LIST_HEAD(&amd_spi->msg_queue); - init_waitqueue_head(&amd_spi->wq); - amd_spi->kthread_spi = kthread_run(amd_spi_thread, amd_spi, - "amd_spi_thread"); - - /* Now lets initialize the fields of spi_master */ - master->bus_num = 0; /* - * This should be the same as passed in - * spi_board_info structure - */ - master->num_chipselect = 4; /* Can be overwritten later during setup */ - master->mode_bits = 0; - master->flags = 0; - master->setup = amd_spi_master_setup; - master->transfer_one_message = amd_spi_master_transfer; - /* Register the controller with SPI framework */ - err = spi_register_master(master); - if (err) { - dev_err(dev, "error registering SPI controller\n"); - goto err_iounmap; - } - pci_set_drvdata(pdev, amd_spi); - - return 0; - -err_iounmap: - iounmap(amd_spi->io_remap_addr); -err_free_master: - spi_master_put(master); - - return 0; -} - -static void amd_spi_pci_remove(struct pci_dev *pdev) -{ - struct amd_spi *amd_spi = pci_get_drvdata(pdev); - - kthread_stop(amd_spi->kthread_spi); - iounmap(amd_spi->io_remap_addr); - spi_unregister_master(amd_spi->master); - spi_master_put(amd_spi->master); - pci_set_drvdata(pdev, NULL); -} - -static struct pci_driver amd_spi_pci_driver = { - .name = "amd_spi", - .id_table = amd_spi_pci_device_id, - .probe = amd_spi_pci_probe, - .remove = amd_spi_pci_remove, -}; - -static int __init amd_spi_init(void) -{ - int ret; - - pr_info("AMD SPI Driver v%s\n", SPI_VERSION); - - ret = pci_register_driver(&amd_spi_pci_driver); - if (ret) - return ret; - - return 0; -} -module_init(amd_spi_init); - -static void __exit amd_spi_exit(void) -{ - pci_unregister_driver(&amd_spi_pci_driver); -} -module_exit(amd_spi_exit); - -MODULE_LICENSE("Dual BSD/GPL"); -MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>"); -MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>"); -MODULE_DESCRIPTION("AMD SPI Master Controller Driver"); diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.h b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.h deleted file mode 100644 index ec58b9a8..00000000 --- a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef SPI_AMD_H -#define SPI_AMD_H - -#define DRIVER_NAME "spi_amd" -#define SPI_VERSION "1.0" - -#define AMD_SPI_CTRL0_REG 0x00 - #define AMD_SPI_EXEC_CMD (0x1 << 16) - #define AMD_SPI_OPCODE_MASK 0xFF - #define AMD_SPI_FIFO_CLEAR (0x1 << 20) - #define AMD_SPI_BUSY (0x1 << 31) -#define AMD_SPI_ALT_CS_REG 0x1D - #define AMD_SPI_ALT_CS_MASK 0x3 -#define AMD_SPI_FIFO_BASE 0x80 -#define AMD_SPI_TX_COUNT_REG 0x48 -#define AMD_SPI_RX_COUNT_REG 0x4B -#define AMD_SPI_STATUS_REG 0x4C - -#define AMD_PCI_LPC_SPI_BASE_ADDR_REG 0xA0 -#define AMD_SPI_BASE_ADDR_MASK ~0x3F -#define AMD_SPI_MEM_SIZE 200 - -#define PCI_DEVICE_ID_AMD_LPC_BRIDGE 0x790E - -#define TRANSMIT 1 -#define RECEIVE 2 - -#endif /* SPI_AMD_H */ diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.c b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.c deleted file mode 100644 index 1a41681a..00000000 --- a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.c +++ /dev/null @@ -1,554 +0,0 @@ -/***************************************************************************** -* -* spirom.c - SPI ROM client driver -* -* Copyright (c) 2014, Advanced Micro Devices, Inc. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -* -***************************************************************************/ -#include <linux/init.h> -#include <linux/module.h> -#include <linux/ioctl.h> -#include <linux/fs.h> -#include <linux/device.h> -#include <linux/err.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/mutex.h> -#include <linux/slab.h> -#include <linux/spi/spi.h> -#include <linux/pci.h> -#include <linux/delay.h> -#include <linux/amd_imc.h> - -#include <asm/uaccess.h> - -#include "spirom.h" - -#define SPIROM_VERSION "0.2" - -/* - * SPI has a character major number assigned. We allocate minor numbers - * dynamically using a bitmask. You must use hotplug tools, such as udev - * (or mdev with busybox) to create and destroy the /dev/spiromB.C device - * nodes, since there is no fixed association of minor numbers with any - * particular SPI bus or device. - */ -#define SPIROM_MAJOR 153 /* assigned */ -#define N_SPI_MINORS 32 /* ... up to 256 */ - -#define SPI_BUS 0 -#define SPI_BUS_CS1 0 - -static unsigned long minors[N_SPI_MINORS / BITS_PER_LONG]; - - -struct spirom_data { - dev_t devt; - spinlock_t spi_lock; - struct spi_device *spi; - struct list_head device_entry; - struct completion done; - - struct mutex buf_lock; - unsigned users; -}; - -static LIST_HEAD(device_list); -static DEFINE_MUTEX(device_list_lock); - -/*-------------------------------------------------------------------------*/ - -/* We need to keep the device pointer because we explicity add the device - * by using spi_new_device at the end of spirom_init. In order to confirm - * a clean exit we need to unregister the device while exiting. - * This cannot be done in the driver's remove call as that would generate - * a recursive loop. - */ - -static struct spi_device *spirom_device; - -/*-------------------------------------------------------------------------*/ - -/* - * We can't use the standard synchronous wrappers for file I/O; we - * need to protect against async removal of the underlying spi_device. - */ -static void spirom_complete(void *arg) -{ - complete(arg); -} - -static ssize_t -spirom_sync(struct spirom_data *spirom, struct spi_message *message) -{ - int status; - - message->complete = spirom_complete; - message->context = &spirom->done; - - spin_lock_irq(&spirom->spi_lock); - if (spirom->spi == NULL) - status = -ESHUTDOWN; - else - status = spi_async(spirom->spi, message); - spin_unlock_irq(&spirom->spi_lock); - - if (status == 0) { - /* - * There might be cases where the controller driver has been - * unloaded in the middle of a transaction. So we might end up - * in a situation where we will be waiting for an event which - * will never happen. So we provide a timeout of 1 second for - * situations like this. - */ - wait_for_completion_timeout(&spirom->done, HZ); - status = message->status; - if (status == 0) - status = message->actual_length; - } - return status; -} - -static int spirom_message(struct spirom_data *spirom, - struct spi_ioc_transfer *u_trans, unsigned long arg) -{ - struct spi_message msg; - struct spi_transfer *transfer; - u8 *buffer; - int status = u_trans->len; - - buffer = u_trans->buf; - spi_message_init(&msg); - - /* The very first spi_transfer will contain the command only */ - transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL); - if (!transfer) - return -ENOMEM; - - transfer->tx_buf = buffer; - transfer->len = 1; - buffer += transfer->len; - spi_message_add_tail(transfer, &msg); - - /* - * If the command expects an address as its argument, we populate - * it in the very next spi_transfer. - */ - if (u_trans->addr_present) { - transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL); - if (!transfer) - return -ENOMEM; - - transfer->tx_buf = buffer; - transfer->len = 3; // 3-byte address - buffer += transfer->len; - spi_message_add_tail(transfer, &msg); - } - - /* - * Next is data, which can have a maximum of 64-bytes, the size limited - * by the number of bytes that can stored in the controller FIFO. - */ - if (u_trans->len) { - transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL); - if (!transfer) - return -ENOMEM; - - if (u_trans->direction == TRANSMIT) - transfer->tx_buf = buffer; - else if (u_trans->direction == RECEIVE) - transfer->rx_buf = buffer; - - transfer->len = u_trans->len; - /* No need to increment buffer pointer */ - spi_message_add_tail(transfer, &msg); - } - - status = spirom_sync(spirom, &msg); - - if (u_trans->direction == RECEIVE) { - /* - * The received data should have been populated in - * u_trans->buf, so we just need to copy it into the - * user-space buffer. - */ - buffer = u_trans->buf; - if (u_trans->addr_present) { - buffer += 4; // 1-byte command and 3-byte address - if(__copy_to_user((u8 __user *) - (((struct spi_ioc_transfer *)arg)->buf) + 4, - buffer, u_trans->len)) { - status = -EFAULT; - } - } else { - buffer += 1; // 1-byte command only - if(__copy_to_user((u8 __user *) - (((struct spi_ioc_transfer *)arg)->buf) + 1, - buffer, u_trans->len)) { - status = -EFAULT; - } - } - } - - /* Done with everything, free the memory taken by spi_transfer */ - while (msg.transfers.next != &msg.transfers) { - transfer = list_entry(msg.transfers.next, struct spi_transfer, - transfer_list); - msg.transfers.next = transfer->transfer_list.next; - transfer->transfer_list.next->prev = &msg.transfers; - kfree(transfer); - } - - return status; -} - -static long -spirom_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) -{ - int err = 0; - int retval = 0; - struct spirom_data *spirom; - struct spi_device *spi; - u32 tmp; - struct spi_ioc_transfer *ioc; - - /* Check type and command number */ - if (_IOC_TYPE(cmd) != SPI_IOC_MAGIC) - return -ENOTTY; - - /* Check access direction once here; don't repeat below. - * IOC_DIR is from the user perspective, while access_ok is - * from the kernel perspective; so they look reversed. - */ - if (_IOC_DIR(cmd) & _IOC_READ) - err = !access_ok(VERIFY_WRITE, - (void __user *)arg, _IOC_SIZE(cmd)); - if (err == 0 && _IOC_DIR(cmd) & _IOC_WRITE) - err = !access_ok(VERIFY_READ, - (void __user *)arg, _IOC_SIZE(cmd)); - if (err) - return -EFAULT; - - /* guard against device removal before, or while, - * we issue this ioctl. - */ - spirom = filp->private_data; - spin_lock_irq(&spirom->spi_lock); - spi = spi_dev_get(spirom->spi); - spin_unlock_irq(&spirom->spi_lock); - - if (spi == NULL) - return -ESHUTDOWN; - - /* use the buffer lock here for triple duty: - * - prevent I/O (from us) so calling spi_setup() is safe; - * - prevent concurrent SPI_IOC_WR_* from morphing - * data fields while SPI_IOC_RD_* reads them; - * - SPI_IOC_MESSAGE needs the buffer locked "normally". - */ - mutex_lock(&spirom->buf_lock); - - /* segmented and/or full-duplex I/O request */ - if (_IOC_NR(cmd) != _IOC_NR(SPI_IOC_MESSAGE(0)) || - _IOC_DIR(cmd) !=_IOC_WRITE) { - retval = -ENOTTY; - goto out; - } - - tmp = sizeof(struct spi_ioc_transfer); - - /* copy into scratch area */ - ioc = kzalloc(tmp, GFP_KERNEL); - if (!ioc) { - retval = -ENOMEM; - goto out; - } - if (__copy_from_user(ioc, (struct spi_ioc_transfer __user *)arg, - tmp)) { - kfree(ioc); - retval = -EFAULT; - goto out; - } - - /* translate to spi_message, execute */ - retval = spirom_message(spirom, ioc, arg); - kfree(ioc); - -out: - mutex_unlock(&spirom->buf_lock); - spi_dev_put(spi); - return retval; -} - -static int spirom_open(struct inode *inode, struct file *filp) -{ - struct spirom_data *spirom; - int status = -ENXIO; - - mutex_lock(&device_list_lock); - - list_for_each_entry(spirom, &device_list, device_entry) { - if (spirom->devt == inode->i_rdev) { - status = 0; - break; - } - } - if (status == 0) { - if (status == 0) { - spirom->users++; - filp->private_data = spirom; - nonseekable_open(inode, filp); - } - } else - pr_debug("spirom: nothing for minor %d\n", iminor(inode)); - - mutex_unlock(&device_list_lock); - - /* - * In case IMC is enabled, we need to inform IMC to stop - * fetching code from the BIOS ROM. We will inform IMC when - * it is safe to start fetching from ROM again once we are - * done with our SPI transactions. - */ - amd_imc_enter_scratch_ram(); - - return status; -} - -static int spirom_release(struct inode *inode, struct file *filp) -{ - struct spirom_data *spirom; - int status = 0; - - mutex_lock(&device_list_lock); - spirom = filp->private_data; - filp->private_data = NULL; - - /* last close? */ - spirom->users--; - if (!spirom->users) { - int dofree; - - /* ... after we unbound from the underlying device? */ - spin_lock_irq(&spirom->spi_lock); - dofree = (spirom->spi == NULL); - spin_unlock_irq(&spirom->spi_lock); - - if (dofree) - kfree(spirom); - } - mutex_unlock(&device_list_lock); - - /* - * In case IMC is enabled, we would have instructed IMC to stop - * fetching from ROM BIOS earlier in the code path. Now that we - * are done, we can safely inform IMC to start fetching from ROM - * again. - */ - amd_imc_exit_scratch_ram(); - - return status; -} - -static const struct file_operations spirom_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = spirom_ioctl, - .open = spirom_open, - .release = spirom_release, -}; - -static int __init add_spi_device_to_bus(void) -{ - struct spi_master *spi_master; - struct spi_board_info spi_info; - - spi_master = spi_busnum_to_master(SPI_BUS); - if (!spi_master) { - printk(KERN_ALERT "Please make sure to \'modprobe " - "spi_amd\' driver first\n"); - return -1; - } - memset(&spi_info, 0, sizeof(struct spi_board_info)); - - strlcpy(spi_info.modalias, "spirom", SPI_NAME_SIZE); - spi_info.bus_num = SPI_BUS; //Bus number of SPI master - spi_info.chip_select = SPI_BUS_CS1; //CS on which SPI device is connected - - spirom_device = spi_new_device(spi_master, &spi_info); - if (!spirom_device) - return -ENODEV; - - return 0; -} - -static void remove_spi_device_from_bus(void) -{ - if (spirom_device) - spi_unregister_device(spirom_device); -} - -/*-------------------------------------------------------------------------*/ - -/* The main reason to have this class is to make mdev/udev create the - * /dev/spiromB.C character device nodes exposing our userspace API. - * It also simplifies memory management. - */ - -static struct class *spirom_class; - -/*-------------------------------------------------------------------------*/ - -static int spirom_probe(struct spi_device *spi) -{ - struct spirom_data *spirom; - int status; - unsigned long minor; - - /* Allocate driver data */ - spirom = kzalloc(sizeof(*spirom), GFP_KERNEL); - if (!spirom) - return -ENOMEM; - - /* Initialize the driver data */ - spirom->spi = spi; - spin_lock_init(&spirom->spi_lock); - mutex_init(&spirom->buf_lock); - - INIT_LIST_HEAD(&spirom->device_entry); - init_completion(&spirom->done); - - /* If we can allocate a minor number, hook up this device. - * Reusing minors is fine so long as udev or mdev is working. - */ - mutex_lock(&device_list_lock); - minor = find_first_zero_bit(minors, N_SPI_MINORS); - if (minor < N_SPI_MINORS) { - struct device *dev; - - spirom->devt = MKDEV(SPIROM_MAJOR, minor); - dev = device_create(spirom_class, &spi->dev, spirom->devt, - spirom, "spirom%d.%d", - spi->master->bus_num, spi->chip_select); - status = IS_ERR(dev) ? PTR_ERR(dev) : 0; - } else { - dev_dbg(&spi->dev, "no minor number available!\n"); - status = -ENODEV; - } - if (status == 0) { - set_bit(minor, minors); - list_add(&spirom->device_entry, &device_list); - } - mutex_unlock(&device_list_lock); - - if (status == 0) - spi_set_drvdata(spi, spirom); - else - kfree(spirom); - - return status; -} - -static int spirom_remove(struct spi_device *spi) -{ - struct spirom_data *spirom = spi_get_drvdata(spi); - - /* make sure ops on existing fds can abort cleanly */ - spin_lock_irq(&spirom->spi_lock); - spirom->spi = NULL; - spi_set_drvdata(spi, NULL); - spin_unlock_irq(&spirom->spi_lock); - - /* prevent new opens */ - mutex_lock(&device_list_lock); - list_del(&spirom->device_entry); - clear_bit(MINOR(spirom->devt), minors); - device_destroy(spirom_class, spirom->devt); - if (spirom->users == 0) - kfree(spirom); - mutex_unlock(&device_list_lock); - - return 0; -} - -static struct spi_driver spirom_spi = { - .driver = { - .name = "spirom", - .owner = THIS_MODULE, - }, - .probe = spirom_probe, - .remove = spirom_remove, - - /* NOTE: suspend/resume methods are not necessary here. - * We don't do anything except pass the requests to/from - * the underlying controller. The refrigerator handles - * most issues; the controller driver handles the rest. - */ -}; - -/*-------------------------------------------------------------------------*/ - -static int __init spirom_init(void) -{ - int status; - - pr_info("AMD SPIROM Driver v%s\n", SPIROM_VERSION); - - /* Claim our 256 reserved device numbers. Then register a class - * that will key udev/mdev to add/remove /dev nodes. Last, register - * the driver which manages those device numbers. - */ - BUILD_BUG_ON(N_SPI_MINORS > 256); - status = register_chrdev(SPIROM_MAJOR, "spi", &spirom_fops); - if (status < 0) - return status; - - spirom_class = class_create(THIS_MODULE, "spirom"); - if (IS_ERR(spirom_class)) { - unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name); - return PTR_ERR(spirom_class); - } - - status = spi_register_driver(&spirom_spi); - if (status < 0) { - class_destroy(spirom_class); - unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name); - } - - status = add_spi_device_to_bus(); - if (status < 0) { - spi_unregister_driver(&spirom_spi); - class_destroy(spirom_class); - unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name); - } - - return status; -} -module_init(spirom_init); - -static void __exit spirom_exit(void) -{ - remove_spi_device_from_bus(); - spi_unregister_driver(&spirom_spi); - class_destroy(spirom_class); - unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name); -} -module_exit(spirom_exit); - -MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>"); -MODULE_DESCRIPTION("User mode SPI ROM interface"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("spi:spirom"); diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.h b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.h deleted file mode 100644 index 941b357a..00000000 --- a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.h +++ /dev/null @@ -1,53 +0,0 @@ -#ifndef SPIROM_H -#define SPIROM_H - -#include <linux/types.h> - -/*---------------------------------------------------------------------------*/ - -/* IOCTL commands */ - -#define SPI_IOC_MAGIC 'k' - -#define TRANSMIT 1 -#define RECEIVE 2 - -/* - * struct spi_ioc_transfer - interface structure between application and ioctl - * - * @buf: Buffer to hold 1-byte command, 3-bytes address, and 64-byte data for - * transmit or receive. The internal FIFO of our controller can hold a - * maximum of 70 bytes, including the address. But here we assume the - * maximum data excluding address to be 64-bytes long. - * - * @direction: Direction of data transfer, either TRANSMIT or RECEIVE. - * - * @len: Length of data excluding command and address. - * - * @addr_present: Flag to indicate whether 'buf' above contains an address. - */ -struct spi_ioc_transfer { - __u8 buf[64 + 1 + 3]; - __u8 direction; - __u8 len; - __u8 addr_present; -}; - -/* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */ -#define SPI_MSGSIZE(N) \ - ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ - ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) -#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) - -/* SPI ROM command codes */ -#define ROM_WREN 0x06 -#define ROM_WRDI 0x04 -#define ROM_RDSR 0x05 -#define ROM_RDID 0x9F -#define ROM_CHIP_ERASE 0x60 -#define ROM_SECTOR_ERASE 0x20 -#define ROM_BLOCK_ERASE 0xD8 -#define ROM_READ 0x03 -#define ROM_WRITE 0x02 - -#endif /* SPIROM_H */ diff --git a/meta-amdfalconx86/recipes-kernel/amd-wdt/amd-wdt_1.0.bb b/meta-amdfalconx86/recipes-kernel/amd-wdt/amd-wdt_1.0.bb deleted file mode 100644 index edaecf5a..00000000 --- a/meta-amdfalconx86/recipes-kernel/amd-wdt/amd-wdt_1.0.bb +++ /dev/null @@ -1,14 +0,0 @@ -DESCRIPTION = "This kernel module provides support for AMD Watchdog driver" -LICENSE = "BSD | GPLv2" -LIC_FILES_CHKSUM = "file://amd_wdt.c;endline=29;md5=8e7a9706367d146e5073510a6e176dc2" - -inherit module - -SRC_URI = "file://Makefile \ - file://amd_wdt.c \ - file://amd_wdt.h \ - " - -S = "${WORKDIR}" - -# The inherit of module.bbclass will take care of the rest diff --git a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/Makefile b/meta-amdfalconx86/recipes-kernel/amd-wdt/files/Makefile deleted file mode 100644 index 36b32f87..00000000 --- a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -obj-m := amd_wdt.o - -SRC := $(shell pwd) - -all: - $(MAKE) -C $(KERNEL_SRC) M=$(SRC) - -modules_install: - $(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install - -clean: - rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c - rm -f Module.markers Module.symvers modules.order - rm -rf .tmp_versions Modules.symvers diff --git a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.c b/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.c deleted file mode 100644 index 82329fe3..00000000 --- a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.c +++ /dev/null @@ -1,418 +0,0 @@ -/***************************************************************************** -* -* Copyright (c) 2014, Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* -***************************************************************************/ -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include <linux/module.h> -#include <linux/moduleparam.h> -#include <linux/types.h> -#include <linux/watchdog.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/ioport.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include "amd_wdt.h" - -/* internal variables */ -static u32 wdtbase_phys; -static void __iomem *wdtbase; -static DEFINE_SPINLOCK(wdt_lock); -static struct pci_dev *amd_wdt_pci; - -/* watchdog platform device */ -static struct platform_device *amd_wdt_platform_device; - -/* module parameters */ -static int heartbeat = AMD_WDT_DEFAULT_TIMEOUT; -module_param(heartbeat, int, 0); -MODULE_PARM_DESC(heartbeat, "Watchdog timeout in frequency units. " - "(default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); - -static char frequency[MAX_LENGTH] = "1s"; -module_param_string(frequency, frequency, MAX_LENGTH, 0); -MODULE_PARM_DESC(frequency, "Watchdog timer frequency units (32us, " - "10ms, 100ms, 1s). (default=1s)"); - -static bool nowayout = WATCHDOG_NOWAYOUT; -module_param(nowayout, bool, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started" - " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); - -static char action[MAX_LENGTH] = "reboot"; -module_param_string(action, action, MAX_LENGTH, 0); -MODULE_PARM_DESC(action, "Watchdog action (reboot/shutdown). (default=reboot) "); - -/* - * Watchdog specific functions - */ -static int amd_wdt_set_timeout(struct watchdog_device *wdt_dev, unsigned int t) -{ - unsigned long flags; - - /* - * In ideal cases the limits will be checked by Watchdog core itself, - * but there might be cases when we call this function directly from - * somewhere else. So check the limits here. - */ - if (t < AMD_WDT_MIN_TIMEOUT) - heartbeat = t = AMD_WDT_MIN_TIMEOUT; - else if (t > AMD_WDT_MAX_TIMEOUT) - heartbeat = t = AMD_WDT_MAX_TIMEOUT; - - /* Write new timeout value to watchdog */ - spin_lock_irqsave(&wdt_lock, flags); - writel(t, AMD_WDT_COUNT(wdtbase)); - spin_unlock_irqrestore(&wdt_lock, flags); - - wdt_dev->timeout = t; - - return 0; -} - -static int amd_wdt_ping(struct watchdog_device *wdt_dev) -{ - u32 val; - unsigned long flags; - - /* Trigger watchdog */ - spin_lock_irqsave(&wdt_lock, flags); - - val = readl(AMD_WDT_CONTROL(wdtbase)); - val |= AMD_WDT_TRIGGER_BIT; - writel(val, AMD_WDT_CONTROL(wdtbase)); - - spin_unlock_irqrestore(&wdt_lock, flags); - - return 0; -} - -static int amd_wdt_start(struct watchdog_device *wdt_dev) -{ - u32 val; - unsigned long flags; - - /* Enable the watchdog timer */ - spin_lock_irqsave(&wdt_lock, flags); - - val = readl(AMD_WDT_CONTROL(wdtbase)); - val |= AMD_WDT_START_STOP_BIT; - writel(val, AMD_WDT_CONTROL(wdtbase)); - - spin_unlock_irqrestore(&wdt_lock, flags); - - /* Trigger the watchdog timer */ - amd_wdt_ping(wdt_dev); - - return 0; -} - -static int amd_wdt_stop(struct watchdog_device *wdt_dev) -{ - u32 val; - unsigned long flags; - - /* Disable the watchdog timer */ - spin_lock_irqsave(&wdt_lock, flags); - - val = readl(AMD_WDT_CONTROL(wdtbase)); - val &= ~AMD_WDT_START_STOP_BIT; - writel(val, AMD_WDT_CONTROL(wdtbase)); - - spin_unlock_irqrestore(&wdt_lock, flags); - - return 0; -} - -static unsigned int amd_wdt_get_timeleft(struct watchdog_device *wdt_dev) -{ - u32 val; - unsigned long flags; - - spin_lock_irqsave(&wdt_lock, flags); - val = readl(AMD_WDT_COUNT(wdtbase)); - spin_unlock_irqrestore(&wdt_lock, flags); - - /* Mask out the upper 16-bits and return */ - return val & AMD_WDT_COUNT_MASK; -} - -static unsigned int amd_wdt_status(struct watchdog_device *wdt_dev) -{ - return wdt_dev->status; -} - -static struct watchdog_ops amd_wdt_ops = { - .owner = THIS_MODULE, - .start = amd_wdt_start, - .stop = amd_wdt_stop, - .ping = amd_wdt_ping, - .status = amd_wdt_status, - .set_timeout = amd_wdt_set_timeout, - .get_timeleft = amd_wdt_get_timeleft, -}; -static struct watchdog_info amd_wdt_info = { - .options = WDIOF_SETTIMEOUT | - WDIOF_MAGICCLOSE | - WDIOF_KEEPALIVEPING, - .firmware_version = 0, - .identity = WDT_MODULE_NAME, -}; - -static struct watchdog_device amd_wdt_dev = { - .info = &amd_wdt_info, - .ops = &amd_wdt_ops, -}; - -/* - * The PCI Device ID table below is used to identify the platform - * the driver is supposed to work for. Since this is a platform - * device, we need a way for us to be able to find the correct - * platform when the driver gets loaded, otherwise we should - * bail out. - */ -static DEFINE_PCI_DEVICE_TABLE(amd_wdt_pci_tbl) = { - { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CARRIZO_SMBUS, PCI_ANY_ID, - PCI_ANY_ID, }, - { 0, }, -}; -MODULE_DEVICE_TABLE(pci, amd_wdt_pci_tbl); - -static unsigned char amd_wdt_setupdevice(void) -{ - struct pci_dev *dev = NULL; - u32 val; - - /* Match the PCI device */ - for_each_pci_dev(dev) { - if (pci_match_id(amd_wdt_pci_tbl, dev) != NULL) { - amd_wdt_pci = dev; - break; - } - } - - if (!amd_wdt_pci) - return 0; - - /* Watchdog Base Address starts from ACPI MMIO Base Address + 0xB00 */ - wdtbase_phys = AMD_ACPI_MMIO_BASE + AMD_WDT_MEM_MAP_OFFSET; - if (!request_mem_region_exclusive(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE, - "AMD Watchdog")) { - pr_err("mmio address 0x%04x already in use\n", wdtbase_phys); - goto exit; - } - - wdtbase = ioremap(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE); - if (!wdtbase) { - pr_err("failed to get wdtbase address\n"); - goto unreg_mem_region; - } - - /* Enable watchdog timer and decode bit */ - outb(AMD_PM_WATCHDOG_EN_REG, AMD_IO_PM_INDEX_REG); - val = inb(AMD_IO_PM_DATA_REG); - val |= AMD_PM_WATCHDOG_TIMER_EN; - outb(val, AMD_IO_PM_DATA_REG); - - /* Set the watchdog timer resolution */ - outb(AMD_PM_WATCHDOG_CONFIG_REG, AMD_IO_PM_INDEX_REG); - val = inb(AMD_IO_PM_DATA_REG); - /* Clear the previous frequency setting, if any */ - val &= ~AMD_PM_WATCHDOG_CONFIG_MASK; - - /* - * Now set the frequency depending on the module load parameter. - * In case the user passes an invalid argument, we consider the - * frequency to be of 1 second resolution. - */ - if (strncmp(frequency, "32us", 4) == 0) - val |= AMD_PM_WATCHDOG_32USEC_RES; - else if (strncmp(frequency, "10ms", 4) == 0) - val |= AMD_PM_WATCHDOG_10MSEC_RES; - else if (strncmp(frequency, "100ms", 5) == 0) - val |= AMD_PM_WATCHDOG_100MSEC_RES; - else { - val |= AMD_PM_WATCHDOG_1SEC_RES; - if (strncmp(frequency, "1s", 2) != 0) - strncpy(frequency, "1s", 2); - } - - outb(val, AMD_IO_PM_DATA_REG); - - /* Check to see if last reboot was due to watchdog timeout */ - val = readl(AMD_WDT_CONTROL(wdtbase)); - if (val & AMD_WDT_FIRED_BIT) - amd_wdt_dev.bootstatus |= WDIOF_CARDRESET; - else - amd_wdt_dev.bootstatus &= ~WDIOF_CARDRESET; - - pr_info("Watchdog reboot %sdetected\n", - (val & AMD_WDT_FIRED_BIT) ? "" : "not "); - - /* Clear out the old status */ - val |= AMD_WDT_FIRED_BIT; - - /* - * Set the watchdog action depending on module load parameter. - * - * If action is specified anything other than reboot or shutdown, - * we default it to reboot. - */ - if (strncmp(action, "shutdown", 8) == 0) - val |= AMD_WDT_ACTION_RESET_BIT; - else { - val &= ~AMD_WDT_ACTION_RESET_BIT; - /* The statement below is required for when the action - * is set anything other than reboot. - */ - if (strncmp(action, "reboot", 6) != 0) - strncpy(action, "reboot", 6); - } - - writel(val, AMD_WDT_CONTROL(wdtbase)); - - return 1; - -unreg_mem_region: - release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE); -exit: - return 0; -} - -static int amd_wdt_init(struct platform_device *dev) -{ - int ret; - u32 val; - - /* Identify our device and initialize watchdog hardware */ - if (!amd_wdt_setupdevice()) - return -ENODEV; - - amd_wdt_dev.timeout = heartbeat; - amd_wdt_dev.min_timeout = AMD_WDT_MIN_TIMEOUT; - amd_wdt_dev.max_timeout = AMD_WDT_MAX_TIMEOUT; - watchdog_set_nowayout(&amd_wdt_dev, nowayout); - - /* Make sure watchdog is not running */ - amd_wdt_stop(&amd_wdt_dev); - - /* Set Watchdog timeout */ - amd_wdt_set_timeout(&amd_wdt_dev, heartbeat); - - ret = watchdog_register_device(&amd_wdt_dev); - if (ret != 0) { - pr_err("Watchdog timer: cannot register watchdog device" - " (err=%d)\n", ret); - goto exit; - } - - pr_info("initialized (0x%p). (timeout=%d units) (frequency=%s) " - "(nowayout=%d) (action=%s)\n", wdtbase, heartbeat, frequency, - nowayout, action); - - return 0; - -exit: - iounmap(wdtbase); - release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE); - return ret; -} - -static void amd_wdt_cleanup(void) -{ - /* Stop the timer before we leave */ - if (!nowayout) - amd_wdt_stop(NULL); - - watchdog_unregister_device(&amd_wdt_dev); - iounmap(wdtbase); - release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE); -} - -static int amd_wdt_remove(struct platform_device *dev) -{ - if (wdtbase) - amd_wdt_cleanup(); - - return 0; -} - -static void amd_wdt_shutdown(struct platform_device *dev) -{ - amd_wdt_stop(NULL); -} - -static struct platform_driver amd_wdt_driver = { - .probe = amd_wdt_init, - .remove = amd_wdt_remove, - .shutdown = amd_wdt_shutdown, - .driver = { - .owner = THIS_MODULE, - .name = WDT_MODULE_NAME, - }, -}; - -static int __init amd_wdt_init_module(void) -{ - int err; - - pr_info("AMD WatchDog Timer Driver v%s\n", WDT_VERSION); - - err = platform_driver_register(&amd_wdt_driver); - if (err) - return err; - - amd_wdt_platform_device = platform_device_register_simple( - WDT_MODULE_NAME, -1, NULL, 0); - if (IS_ERR(amd_wdt_platform_device)) { - err = PTR_ERR(amd_wdt_platform_device); - goto unreg_platform_driver; - } - - return 0; - -unreg_platform_driver: - platform_driver_unregister(&amd_wdt_driver); - return err; -} - -static void __exit amd_wdt_cleanup_module(void) -{ - platform_device_unregister(amd_wdt_platform_device); - platform_driver_unregister(&amd_wdt_driver); - pr_info("AMD Watchdog Module Unloaded\n"); -} - -module_init(amd_wdt_init_module); -module_exit(amd_wdt_cleanup_module); - -MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>"); -MODULE_DESCRIPTION("Watchdog timer driver for AMD chipsets"); -MODULE_LICENSE("Dual BSD/GPL"); diff --git a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.h b/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.h deleted file mode 100644 index 855e6810..00000000 --- a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef _AMD_WDT_H_ -#define _AMD_WDT_H_ - -/* Module and version information */ -#define WDT_VERSION "1.0" -#define WDT_MODULE_NAME "AMD watchdog timer" -#define WDT_DRIVER_NAME WDT_MODULE_NAME ", v" WDT_VERSION - -#define AMD_WDT_DEFAULT_TIMEOUT 60 /* 60 units default heartbeat. */ -#define AMD_WDT_MIN_TIMEOUT 0x0001 /* minimum timeout value */ -#define AMD_WDT_MAX_TIMEOUT 0xFFFF /* maximum timeout value */ -#define MAX_LENGTH (8 + 1) /* shutdown has 8 characters + NULL character */ - -/* Watchdog register definitions */ -#define AMD_ACPI_MMIO_BASE 0xFED80000 -#define AMD_WDT_MEM_MAP_OFFSET 0xB00 -#define AMD_WDT_MEM_MAP_SIZE 0x100 - -#define AMD_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */ - #define AMD_WDT_START_STOP_BIT (1 << 0) - #define AMD_WDT_FIRED_BIT (1 << 1) - #define AMD_WDT_ACTION_RESET_BIT (1 << 2) - #define AMD_WDT_DISABLE_BIT (1 << 3) - /* 6:4 bits Reserved */ - #define AMD_WDT_TRIGGER_BIT (1 << 7) -#define AMD_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */ - #define AMD_WDT_COUNT_MASK 0xFFFF - -#define AMD_PM_WATCHDOG_EN_REG 0x00 - #define AMD_PM_WATCHDOG_TIMER_EN (0x01 << 7) - -#define AMD_PM_WATCHDOG_CONFIG_REG 0x03 - #define AMD_PM_WATCHDOG_32USEC_RES 0x0 - #define AMD_PM_WATCHDOG_10MSEC_RES 0x1 - #define AMD_PM_WATCHDOG_100MSEC_RES 0x2 - #define AMD_PM_WATCHDOG_1SEC_RES 0x3 -#define AMD_PM_WATCHDOG_CONFIG_MASK 0x3 - -/* IO port address for indirect access using ACPI PM registers */ -#define AMD_IO_PM_INDEX_REG 0xCD6 -#define AMD_IO_PM_DATA_REG 0xCD7 - -#define AMD_ACPI_MMIO_ADDR_MASK ~0x1FFF -#define PCI_DEVICE_ID_AMD_CARRIZO_SMBUS 0x790B - -#endif /* _AMD_WDT_H_ */ diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware.bb b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware.bb deleted file mode 100644 index 1d4ea646..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware.bb +++ /dev/null @@ -1,43 +0,0 @@ -DESCRIPTION = "These binaries provide kernel support for newer AMD GPUs" -SECTION = "kernel" -LICENSE = "Firmware-amd" - -SRC_URI = "file://carrizo_ce.bin \ - file://carrizo_me.bin \ - file://carrizo_mec2.bin \ - file://carrizo_mec.bin \ - file://carrizo_pfp.bin \ - file://carrizo_rlc.bin \ - file://carrizo_sdma1.bin \ - file://carrizo_sdma.bin \ - file://carrizo_uvd.bin \ - file://carrizo_vce.bin \ - file://stoney_ce.bin \ - file://stoney_me.bin \ - file://stoney_mec.bin \ - file://stoney_pfp.bin \ - file://stoney_rlc.bin \ - file://stoney_sdma.bin \ - file://stoney_uvd.bin \ - file://stoney_vce.bin \ - file://LICENSE \ - " - -LIC_FILES_CHKSUM = "file://LICENSE;md5=07b0c31777bd686d8e1609c6940b5e74" - -S = "${WORKDIR}" - -# Since, no binaries are generated for a specific target, -# inherit allarch to simply populate prebuilt binaries -inherit allarch - -do_compile() { - : -} - -do_install() { - install -v -m 444 -D ${S}/LICENSE ${D}/lib/firmware/amdgpu/LICENSE - install -v -m 0644 ${S}/*.bin ${D}/lib/firmware/amdgpu -} - -FILES_${PN} = "/lib/firmware/*" diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE deleted file mode 100644 index fe3780b3..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE +++ /dev/null @@ -1,51 +0,0 @@ -Copyright (C) 2009-2014 Advanced Micro Devices, Inc. All rights reserved. - -REDISTRIBUTION: Permission is hereby granted, free of any license fees, -to any person obtaining a copy of this microcode (the "Software"), to -install, reproduce, copy and distribute copies, in binary form only, of -the Software and to permit persons to whom the Software is provided to -do the same, provided that the following conditions are met: - -No reverse engineering, decompilation, or disassembly of this Software -is permitted. - -Redistributions must reproduce the above copyright notice, this -permission notice, and the following disclaimers and notices in the -Software documentation and/or other materials provided with the -Software. - -DISCLAIMER: THE USE OF THE SOFTWARE IS AT YOUR SOLE RISK. THE SOFTWARE -IS PROVIDED "AS IS" AND WITHOUT WARRANTY OF ANY KIND AND COPYRIGHT -HOLDER AND ITS LICENSORS EXPRESSLY DISCLAIM ALL WARRANTIES, EXPRESS AND -IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -COPYRIGHT HOLDER AND ITS LICENSORS DO NOT WARRANT THAT THE SOFTWARE WILL -MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THE SOFTWARE WILL BE -UNINTERRUPTED OR ERROR-FREE. THE ENTIRE RISK ASSOCIATED WITH THE USE OF -THE SOFTWARE IS ASSUMED BY YOU. FURTHERMORE, COPYRIGHT HOLDER AND ITS -LICENSORS DO NOT WARRANT OR MAKE ANY REPRESENTATIONS REGARDING THE USE -OR THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -ACCURACY, RELIABILITY, CURRENTNESS, OR OTHERWISE. - -DISCLAIMER: UNDER NO CIRCUMSTANCES INCLUDING NEGLIGENCE, SHALL COPYRIGHT -HOLDER AND ITS LICENSORS OR ITS DIRECTORS, OFFICERS, EMPLOYEES OR AGENTS -("AUTHORIZED REPRESENTATIVES") BE LIABLE FOR ANY INCIDENTAL, INDIRECT, -SPECIAL OR CONSEQUENTIAL DAMAGES (INCLUDING DAMAGES FOR LOSS OF BUSINESS -PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, AND THE -LIKE) ARISING OUT OF THE USE, MISUSE OR INABILITY TO USE THE SOFTWARE, -BREACH OR DEFAULT, INCLUDING THOSE ARISING FROM INFRINGEMENT OR ALLEGED -INFRINGEMENT OF ANY PATENT, TRADEMARK, COPYRIGHT OR OTHER INTELLECTUAL -PROPERTY RIGHT EVEN IF COPYRIGHT HOLDER AND ITS AUTHORIZED -REPRESENTATIVES HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN -NO EVENT SHALL COPYRIGHT HOLDER OR ITS AUTHORIZED REPRESENTATIVES TOTAL -LIABILITY FOR ALL DAMAGES, LOSSES, AND CAUSES OF ACTION (WHETHER IN -CONTRACT, TORT (INCLUDING NEGLIGENCE) OR OTHERWISE) EXCEED THE AMOUNT OF -US$10. - -Notice: The Software is subject to United States export laws and -regulations. You agree to comply with all domestic and international -export laws and regulations that apply to the Software, including but -not limited to the Export Administration Regulations administered by the -U.S. Department of Commerce and International Traffic in Arm Regulations -administered by the U.S. Department of State. These laws include -restrictions on destinations, end users and end use. diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_ce.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_ce.bin Binary files differdeleted file mode 100644 index 6153fcb7..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_ce.bin +++ /dev/null diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_me.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_me.bin Binary files differdeleted file mode 100644 index 57a9f8a1..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_me.bin +++ /dev/null diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_mec.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_mec.bin Binary files differdeleted file mode 100644 index a5f3a2e4..00000000 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a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_uvd.bin +++ /dev/null diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_vce.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_vce.bin Binary files differdeleted file mode 100644 index ff54327c..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_vce.bin +++ /dev/null diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0001-PATCH-amdgpu-get-maximum-and-used-UVD-handles.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0001-PATCH-amdgpu-get-maximum-and-used-UVD-handles.patch deleted file mode 100644 index 506f127f..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/0001-PATCH-amdgpu-get-maximum-and-used-UVD-handles.patch +++ /dev/null @@ -1,158 +0,0 @@ -From 195d9672a2766fca3c0495884e2ef6a4f133ebb7 Mon Sep 17 00:00:00 2001 -From: Ahsan Hussain <ahsan_hussain@mentor.com> -Date: Wed, 19 Apr 2017 21:01:50 +0500 -Subject: [PATCH] [PATCH] amdgpu: get maximum and used UVD handles - -Change History --------------- - -v4: Changes suggested by Emil, Christian -- return -ENODATA for asics with unlimited sessions - -v3: changes suggested by Christian -- Add a check for UVD IP block using AMDGPU_HW_IP_UVD - query type. -- Add a check for asic_type to be less than - CHIP_POLARIS10 since starting Polaris, we support - unlimited UVD instances. -- Add kerneldoc style comment for - amdgpu_uvd_used_handles(). - -v2: as suggested by Christian -- Add a new query AMDGPU_INFO_NUM_HANDLES -- Create a helper function to return the number - of currently used UVD handles. -- Modify the logic to count the number of used - UVD handles since handles can be freed in - non-linear fashion. - -v1: -- User might want to query the maximum number of UVD - instances supported by firmware. In addition to that, - if there are multiple applications using UVD handles - at the same time, he might also want to query the - currently used number of handles. - - For this we add two variables max_handles and - used_handles inside drm_amdgpu_info_hw_ip. So now - an application (or libdrm) can use AMDGPU_INFO IOCTL - with AMDGPU_INFO_HW_IP_INFO query type to get these - values. - -Signed-off-by: Ahsan Hussain <ahsan_hussain@mentor.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 21 +++++++++++++++++++ - drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 25 +++++++++++++++++++++++ - drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 1 + - drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 9 ++++++++ - 4 files changed, 56 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -index a48783e50..e7ab49d49 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -@@ -505,6 +505,27 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file - return copy_to_user(out, &dev_info, - min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; - } -+ case AMDGPU_INFO_NUM_HANDLES: { -+ struct drm_amdgpu_info_num_handles handle; -+ -+ switch (info->query_hw_ip.type) { -+ case AMDGPU_HW_IP_UVD: -+ /* Starting Polaris, we support unlimited UVD handles */ -+ if (adev->asic_type < CHIP_POLARIS10) { -+ handle.uvd_max_handles = adev->uvd.max_handles; -+ handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); -+ -+ return copy_to_user(out, &handle, -+ min((size_t)size, sizeof(handle))) ? -EFAULT : 0; -+ } else { -+ return -ENODATA; -+ } -+ -+ break; -+ default: -+ return -EINVAL; -+ } -+ } - default: - DRM_DEBUG_KMS("Invalid request %d\n", info->query); - return -EINVAL; -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -index 849c7959c..20960e82a 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -@@ -940,6 +940,31 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) - return 0; - } - -+/** -+ * amdgpu_uvd_used_handles - returns used UVD handles -+ * -+ * @adev: amdgpu_device pointer -+ * -+ * Returns the number of UVD handles in use -+ */ -+uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) -+{ -+ unsigned i; -+ uint32_t used_handles = 0; -+ -+ for (i = 0; i < adev->uvd.max_handles; ++i) { -+ /* -+ * Handles can be freed in any order, and not -+ * necessarily linear. So we need to count -+ * all non-zero handles. -+ */ -+ if (atomic_read(&adev->uvd.handles[i])) -+ used_handles++; -+ } -+ -+ return used_handles; -+} -+ - static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, - bool direct, struct fence **fence) - { -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h -index 9a3b44908..19250d69d 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h -@@ -35,5 +35,6 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, - void amdgpu_uvd_free_handles(struct amdgpu_device *adev, - struct drm_file *filp); - int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx); -+uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev); - - #endif -diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -index c2f06eba3..c4f903d61 100644 ---- a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -+++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -@@ -549,6 +549,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_CAPABILITY 0x50 - /* query pin memory capability */ - #define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) -+/* Query UVD handles */ -+#define AMDGPU_INFO_NUM_HANDLES 0x1C - - #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 - #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff -@@ -710,6 +712,13 @@ struct drm_amdgpu_info_hw_ip { - __u32 _pad; - }; - -+struct drm_amdgpu_info_num_handles { -+ /** Max handles as supported by firmware for UVD */ -+ __u32 uvd_max_handles; -+ /** Handles currently in use for UVD */ -+ __u32 uvd_used_handles; -+}; -+ - struct drm_amdgpu_heap_info { - /** max. physical memory */ - __u64 total_heap_size; --- -2.11.1 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0001-amdgpu-fix-various-compilation-issues.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0001-amdgpu-fix-various-compilation-issues.patch deleted file mode 100644 index 91aa2bb5..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/0001-amdgpu-fix-various-compilation-issues.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 480e54e78f3df2bbc21f7977d3f55dc5aef5317e Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Wed, 13 Jul 2016 15:18:23 -0700 -Subject: [PATCH] amdgpu: fix various compilation issues - -Signed-off-by: Awais Belal <awais_belal@mentor.com> -Signed-off-by: Drew Moseley <drew_moseley@mentor.com> ---- - drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 2 +- - drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c | 1 - - 2 files changed, 1 insertion(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c -index f39499a..e995f9b 100644 ---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c -+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c -@@ -3181,7 +3181,7 @@ static void calculate_bandwidth( - bw_int_to_fixed( - 2), - vbios->mcifwrmc_urgent_latency), -- results->dmif_burst_time[i][j]), -+ results->dmif_burst_time[results->y_clk_level][results->sclk_level]), - results->mcifwr_burst_time[results->y_clk_level][results->sclk_level])), - results->dispclk), - bw_int_to_fixed( -diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c -index 698a34e..13a1449 100644 ---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c -+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c -@@ -41,7 +41,6 @@ - #define CV_SMART_DONGLE_ADDRESS 0x20 - /* DVI-HDMI dongle slave address for retrieving dongle signature*/ - #define DVI_HDMI_DONGLE_ADDRESS 0x68 --static const int8_t dvi_hdmi_dongle_signature_str[] = "6140063500G"; - struct dvi_hdmi_dongle_signature_data { - int8_t vendor[3];/* "AMD" */ - uint8_t version[2]; --- -2.9.1 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0001-ethernet-integrate-r8168-driver.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0001-ethernet-integrate-r8168-driver.patch deleted file mode 100644 index 78a33e47..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/0001-ethernet-integrate-r8168-driver.patch +++ /dev/null @@ -1,28740 +0,0 @@ -From 1a424d423823ae97080922348408e2377eaaca76 Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Fri, 28 Aug 2015 15:08:31 +0500 -Subject: [PATCH] ethernet: integrate r8168 driver - -The NIC on AMD Falcon x86 family requires the r8168 driver -to function properly otherwise conflicts with the on-board -DASH controller are observed which results in a failure -to bring up the ethernet interface. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - drivers/net/ethernet/realtek/Kconfig | 9 + - drivers/net/ethernet/realtek/Makefile | 3 + - drivers/net/ethernet/realtek/r8168.h | 1524 ++ - drivers/net/ethernet/realtek/r8168_asf.c | 419 + - drivers/net/ethernet/realtek/r8168_asf.h | 294 + - drivers/net/ethernet/realtek/r8168_dash.h | 193 + - drivers/net/ethernet/realtek/r8168_n.c | 25364 +++++++++++++++++++++++++ - drivers/net/ethernet/realtek/r8168_realwow.h | 117 + - drivers/net/ethernet/realtek/rtl_eeprom.c | 291 + - drivers/net/ethernet/realtek/rtl_eeprom.h | 55 + - drivers/net/ethernet/realtek/rtltool.c | 304 + - drivers/net/ethernet/realtek/rtltool.h | 49 + - 12 files changed, 28622 insertions(+) - create mode 100755 drivers/net/ethernet/realtek/r8168.h - create mode 100755 drivers/net/ethernet/realtek/r8168_asf.c - create mode 100755 drivers/net/ethernet/realtek/r8168_asf.h - create mode 100755 drivers/net/ethernet/realtek/r8168_dash.h - create mode 100755 drivers/net/ethernet/realtek/r8168_n.c - create mode 100755 drivers/net/ethernet/realtek/r8168_realwow.h - create mode 100755 drivers/net/ethernet/realtek/rtl_eeprom.c - create mode 100755 drivers/net/ethernet/realtek/rtl_eeprom.h - create mode 100755 drivers/net/ethernet/realtek/rtltool.c - create mode 100755 drivers/net/ethernet/realtek/rtltool.h - -diff --git a/drivers/net/ethernet/realtek/Kconfig b/drivers/net/ethernet/realtek/Kconfig -index ae5d027..54667fb 100644 ---- a/drivers/net/ethernet/realtek/Kconfig -+++ b/drivers/net/ethernet/realtek/Kconfig -@@ -112,4 +112,13 @@ config R8169 - To compile this driver as a module, choose M here: the module - will be called r8169. This is recommended. - -+config R8168 -+ tristate "Realtek 8168 gigabit ethernet support" -+ depends on PCI -+ ---help--- -+ Say Y here if you have a Realtek 8168 PCI Gigabit Ethernet adapter. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called r8168. This is recommended. -+ - endif # NET_VENDOR_REALTEK -diff --git a/drivers/net/ethernet/realtek/Makefile b/drivers/net/ethernet/realtek/Makefile -index 71b1da3..2de09ca 100644 ---- a/drivers/net/ethernet/realtek/Makefile -+++ b/drivers/net/ethernet/realtek/Makefile -@@ -6,3 +6,6 @@ obj-$(CONFIG_8139CP) += 8139cp.o - obj-$(CONFIG_8139TOO) += 8139too.o - obj-$(CONFIG_ATP) += atp.o - obj-$(CONFIG_R8169) += r8169.o -+ -+r8168-y += r8168_n.o r8168_asf.o rtl_eeprom.o rtltool.o -+obj-$(CONFIG_R8168) += r8168.o -diff --git a/drivers/net/ethernet/realtek/r8168.h b/drivers/net/ethernet/realtek/r8168.h -new file mode 100755 -index 0000000..95dec0e ---- /dev/null -+++ b/drivers/net/ethernet/realtek/r8168.h -@@ -0,0 +1,1524 @@ -+/* -+################################################################################ -+# -+# r8168 is the Linux device driver released for Realtek Gigabit Ethernet -+# controllers with PCI-Express interface. -+# -+# Copyright(c) 2015 Realtek Semiconductor Corp. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the Free -+# Software Foundation; either version 2 of the License, or (at your option) -+# any later version. -+# -+# This program is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+# more details. -+# -+# You should have received a copy of the GNU General Public License along with -+# this program; if not, see <http://www.gnu.org/licenses/>. -+# -+# Author: -+# Realtek NIC software team <nicfae@realtek.com> -+# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan -+# -+################################################################################ -+*/ -+ -+/************************************************************************************ -+ * This product is covered by one or more of the following patents: -+ * US6,570,884, US6,115,776, and US6,327,625. -+ ***********************************************************************************/ -+ -+#include "r8168_dash.h" -+#include "r8168_realwow.h" -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37) -+#define ENABLE_R8168_PROCFS -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) -+#define NETIF_F_HW_VLAN_RX NETIF_F_HW_VLAN_CTAG_RX -+#define NETIF_F_HW_VLAN_TX NETIF_F_HW_VLAN_CTAG_TX -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0) -+#define __devinit -+#define __devexit -+#define __devexit_p(func) func -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+#define CHECKSUM_PARTIAL CHECKSUM_HW -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define irqreturn_t void -+#define IRQ_HANDLED 1 -+#define IRQ_NONE 0 -+#define IRQ_RETVAL(x) -+#endif -+ -+#ifndef HAVE_FREE_NETDEV -+#define free_netdev(x) kfree(x) -+#endif -+ -+#ifndef SET_NETDEV_DEV -+#define SET_NETDEV_DEV(net, pdev) -+#endif -+ -+#ifndef SET_MODULE_OWNER -+#define SET_MODULE_OWNER(dev) -+#endif -+ -+#ifndef SA_SHIRQ -+#define SA_SHIRQ IRQF_SHARED -+#endif -+ -+#ifndef NETIF_F_GSO -+#define gso_size tso_size -+#define gso_segs tso_segs -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) -+#ifdef CONFIG_NET_POLL_CONTROLLER -+#define RTL_NET_POLL_CONTROLLER dev->poll_controller=rtl8168_netpoll -+#else -+#define RTL_NET_POLL_CONTROLLER -+#endif -+ -+#ifdef CONFIG_R8168_VLAN -+#define RTL_SET_VLAN dev->vlan_rx_register=rtl8168_vlan_rx_register -+#else -+#define RTL_SET_VLAN -+#endif -+ -+#define RTL_NET_DEVICE_OPS(ops) dev->open=rtl8168_open; \ -+ dev->hard_start_xmit=rtl8168_start_xmit; \ -+ dev->get_stats=rtl8168_get_stats; \ -+ dev->stop=rtl8168_close; \ -+ dev->tx_timeout=rtl8168_tx_timeout; \ -+ dev->set_multicast_list=rtl8168_set_rx_mode; \ -+ dev->change_mtu=rtl8168_change_mtu; \ -+ dev->set_mac_address=rtl8168_set_mac_address; \ -+ dev->do_ioctl=rtl8168_do_ioctl; \ -+ RTL_NET_POLL_CONTROLLER; \ -+ RTL_SET_VLAN; -+#else -+#define RTL_NET_DEVICE_OPS(ops) dev->netdev_ops=&ops -+#endif -+ -+#ifndef FALSE -+#define FALSE 0 -+#endif -+ -+#ifndef TRUE -+#define TRUE 1 -+#endif -+ -+#ifndef false -+#define false 0 -+#endif -+ -+#ifndef true -+#define true 1 -+#endif -+ -+//Hardware will continue interrupt 10 times after interrupt finished. -+#define RTK_KEEP_INTERRUPT_COUNT (10) -+ -+//Due to the hardware design of RTL8111B, the low 32 bit address of receive -+//buffer must be 8-byte alignment. -+#ifndef NET_IP_ALIGN -+#define NET_IP_ALIGN 2 -+#endif -+#define RTK_RX_ALIGN 8 -+ -+#ifdef CONFIG_R8168_NAPI -+#define NAPI_SUFFIX "-NAPI" -+#else -+#define NAPI_SUFFIX "" -+#endif -+ -+#define RTL8168_VERSION "8.040.00" NAPI_SUFFIX -+#define MODULENAME "r8168" -+#define PFX MODULENAME ": " -+ -+#define GPL_CLAIM "\ -+r8168 Copyright (C) 2015 Realtek NIC software team <nicfae@realtek.com> \n \ -+This program comes with ABSOLUTELY NO WARRANTY; for details, please see <http://www.gnu.org/licenses/>. \n \ -+This is free software, and you are welcome to redistribute it under certain conditions; see <http://www.gnu.org/licenses/>. \n" -+ -+#ifdef RTL8168_DEBUG -+#define assert(expr) \ -+ if(!(expr)) { \ -+ printk( "Assertion failed! %s,%s,%s,line=%d\n", \ -+ #expr,__FILE__,__FUNCTION__,__LINE__); \ -+ } -+#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0) -+#else -+#define assert(expr) do {} while (0) -+#define dprintk(fmt, args...) do {} while (0) -+#endif /* RTL8168_DEBUG */ -+ -+#define R8168_MSG_DEFAULT \ -+ (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) -+ -+#define TX_BUFFS_AVAIL(tp) \ -+ (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) -+ -+#ifdef CONFIG_R8168_NAPI -+#define rtl8168_rx_hwaccel_skb vlan_hwaccel_receive_skb -+#define rtl8168_rx_quota(count, quota) min(count, quota) -+#else -+#define rtl8168_rx_hwaccel_skb vlan_hwaccel_rx -+#define rtl8168_rx_quota(count, quota) count -+#endif -+ -+/* MAC address length */ -+#ifndef MAC_ADDR_LEN -+#define MAC_ADDR_LEN 6 -+#endif -+ -+#ifndef MAC_PROTOCOL_LEN -+#define MAC_PROTOCOL_LEN 2 -+#endif -+ -+#define Reserved2_data 7 -+#define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */ -+#define TX_DMA_BURST_unlimited 7 -+#define TX_DMA_BURST_1024 6 -+#define TX_DMA_BURST_512 5 -+#define TX_DMA_BURST_256 4 -+#define TX_DMA_BURST_128 3 -+#define TX_DMA_BURST_64 2 -+#define TX_DMA_BURST_32 1 -+#define TX_DMA_BURST_16 0 -+#define Reserved1_data 0x3F -+#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ -+#define Jumbo_Frame_2k (2 * 1024) -+#define Jumbo_Frame_3k (3 * 1024) -+#define Jumbo_Frame_4k (4 * 1024) -+#define Jumbo_Frame_5k (5 * 1024) -+#define Jumbo_Frame_6k (6 * 1024) -+#define Jumbo_Frame_7k (7 * 1024) -+#define Jumbo_Frame_8k (8 * 1024) -+#define Jumbo_Frame_9k (9 * 1024) -+#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ -+#define RxEarly_off_V1 (0x07 << 11) -+#define RxEarly_off_V2 (1 << 11) -+#define Rx_Single_fetch_V2 (1 << 14) -+ -+#define R8168_REGS_SIZE (256) -+#define R8168_MAC_REGS_SIZE (256) -+#define R8168_PHY_REGS_SIZE (16*2) -+#define R8168_EPHY_REGS_SIZE (31*2) -+#define R8168_ERI_REGS_SIZE (0x100) -+#define R8168_REGS_DUMP_SIZE (0x400) -+#define R8168_NAPI_WEIGHT 64 -+ -+#define RTL8168_TX_TIMEOUT (6 * HZ) -+#define RTL8168_LINK_TIMEOUT (1 * HZ) -+#define RTL8168_ESD_TIMEOUT (2 * HZ) -+ -+#define NUM_TX_DESC 1024 /* Number of Tx descriptor registers */ -+#define NUM_RX_DESC 1024 /* Number of Rx descriptor registers */ -+ -+#define RX_BUF_SIZE 0x05F3 /* 0x05F3 = 1522bye + 1 */ -+#define R8168_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) -+#define R8168_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) -+ -+#define NODE_ADDRESS_SIZE 6 -+ -+#define SHORT_PACKET_PADDING_BUF_SIZE 256 -+ -+/* write/read MMIO register */ -+#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) -+#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) -+#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) -+#define RTL_R8(reg) readb (ioaddr + (reg)) -+#define RTL_R16(reg) readw (ioaddr + (reg)) -+#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) -+ -+#ifndef DMA_64BIT_MASK -+#define DMA_64BIT_MASK 0xffffffffffffffffULL -+#endif -+ -+#ifndef DMA_32BIT_MASK -+#define DMA_32BIT_MASK 0x00000000ffffffffULL -+#endif -+ -+#ifndef NETDEV_TX_OK -+#define NETDEV_TX_OK 0 /* driver took care of packet */ -+#endif -+ -+#ifndef NETDEV_TX_BUSY -+#define NETDEV_TX_BUSY 1 /* driver tx path was busy*/ -+#endif -+ -+#ifndef NETDEV_TX_LOCKED -+#define NETDEV_TX_LOCKED -1 /* driver tx lock was already taken */ -+#endif -+ -+#ifndef ADVERTISED_Pause -+#define ADVERTISED_Pause (1 << 13) -+#endif -+ -+#ifndef ADVERTISED_Asym_Pause -+#define ADVERTISED_Asym_Pause (1 << 14) -+#endif -+ -+#ifndef ADVERTISE_PAUSE_CAP -+#define ADVERTISE_PAUSE_CAP 0x400 -+#endif -+ -+#ifndef ADVERTISE_PAUSE_ASYM -+#define ADVERTISE_PAUSE_ASYM 0x800 -+#endif -+ -+#ifndef MII_CTRL1000 -+#define MII_CTRL1000 0x09 -+#endif -+ -+#ifndef ADVERTISE_1000FULL -+#define ADVERTISE_1000FULL 0x200 -+#endif -+ -+#ifndef ADVERTISE_1000HALF -+#define ADVERTISE_1000HALF 0x100 -+#endif -+ -+/*****************************************************************************/ -+ -+//#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) -+#if (( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) || \ -+ (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \ -+ ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) ))) -+/* copied from linux kernel 2.6.20 include/linux/netdev.h */ -+#define NETDEV_ALIGN 32 -+#define NETDEV_ALIGN_CONST (NETDEV_ALIGN - 1) -+ -+static inline void *netdev_priv(struct net_device *dev) -+{ -+ return (char *)dev + ((sizeof(struct net_device) -+ + NETDEV_ALIGN_CONST) -+ & ~NETDEV_ALIGN_CONST); -+} -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) -+ -+/*****************************************************************************/ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -+#define RTLDEV tp -+#else -+#define RTLDEV dev -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -+/*****************************************************************************/ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) -+typedef struct net_device *napi_ptr; -+typedef int *napi_budget; -+ -+#define napi dev -+#define RTL_NAPI_CONFIG(ndev, priv, function, weig) ndev->poll=function; \ -+ ndev->weight=weig; -+#define RTL_NAPI_DEL(priv) -+#define RTL_NAPI_QUOTA(budget, ndev) min(*budget, ndev->quota) -+#define RTL_GET_PRIV(stuct_ptr, priv_struct) netdev_priv(stuct_ptr) -+#define RTL_GET_NETDEV(priv_ptr) -+#define RTL_RX_QUOTA(ndev, budget) ndev->quota -+#define RTL_NAPI_QUOTA_UPDATE(ndev, work_done, budget) *budget -= work_done; \ -+ ndev->quota -= work_done; -+#define RTL_NETIF_RX_COMPLETE(dev, napi) netif_rx_complete(dev) -+#define RTL_NETIF_RX_SCHEDULE_PREP(dev, napi) netif_rx_schedule_prep(dev) -+#define __RTL_NETIF_RX_SCHEDULE(dev, napi) __netif_rx_schedule(dev) -+#define RTL_NAPI_RETURN_VALUE work_done >= work_to_do -+#define RTL_NAPI_ENABLE(dev, napi) netif_poll_enable(dev) -+#define RTL_NAPI_DISABLE(dev, napi) netif_poll_disable(dev) -+#define DMA_BIT_MASK(value) ((1ULL << value) - 1) -+#else -+typedef struct napi_struct *napi_ptr; -+typedef int napi_budget; -+ -+#define RTL_NAPI_CONFIG(ndev, priv, function, weight) netif_napi_add(ndev, &priv->napi, function, weight) -+#define RTL_NAPI_DEL(priv) netif_napi_del(&priv->napi) -+#define RTL_NAPI_QUOTA(budget, ndev) min(budget, budget) -+#define RTL_GET_PRIV(stuct_ptr, priv_struct) container_of(stuct_ptr, priv_struct, stuct_ptr) -+#define RTL_GET_NETDEV(priv_ptr) struct net_device *dev = priv_ptr->dev; -+#define RTL_RX_QUOTA(ndev, budget) budget -+#define RTL_NAPI_QUOTA_UPDATE(ndev, work_done, budget) -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) -+#define RTL_NETIF_RX_COMPLETE(dev, napi) netif_rx_complete(dev, napi) -+#define RTL_NETIF_RX_SCHEDULE_PREP(dev, napi) netif_rx_schedule_prep(dev, napi) -+#define __RTL_NETIF_RX_SCHEDULE(dev, napi) __netif_rx_schedule(dev, napi) -+#endif -+#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,29) -+#define RTL_NETIF_RX_COMPLETE(dev, napi) netif_rx_complete(napi) -+#define RTL_NETIF_RX_SCHEDULE_PREP(dev, napi) netif_rx_schedule_prep(napi) -+#define __RTL_NETIF_RX_SCHEDULE(dev, napi) __netif_rx_schedule(napi) -+#endif -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29) -+#define RTL_NETIF_RX_COMPLETE(dev, napi) napi_complete(napi) -+#define RTL_NETIF_RX_SCHEDULE_PREP(dev, napi) napi_schedule_prep(napi) -+#define __RTL_NETIF_RX_SCHEDULE(dev, napi) __napi_schedule(napi) -+#endif -+#define RTL_NAPI_RETURN_VALUE work_done -+#define RTL_NAPI_ENABLE(dev, napi) napi_enable(napi) -+#define RTL_NAPI_DISABLE(dev, napi) napi_disable(napi) -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) -+ -+/*****************************************************************************/ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9) -+#ifdef __CHECKER__ -+#define __iomem __attribute__((noderef, address_space(2))) -+extern void __chk_io_ptr(void __iomem *); -+#define __bitwise __attribute__((bitwise)) -+#else -+#define __iomem -+#define __chk_io_ptr(x) (void)0 -+#define __bitwise -+#endif -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9) -+ -+/*****************************************************************************/ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) -+#ifdef __CHECKER__ -+#define __force __attribute__((force)) -+#else -+#define __force -+#endif -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) -+ -+#ifndef module_param -+#define module_param(v,t,p) MODULE_PARM(v, "i"); -+#endif -+ -+#ifndef PCI_DEVICE -+#define PCI_DEVICE(vend,dev) \ -+ .vendor = (vend), .device = (dev), \ -+ .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID -+#endif -+ -+/*****************************************************************************/ -+/* 2.5.28 => 2.4.23 */ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) ) -+ -+static inline void _kc_synchronize_irq(void) -+{ -+ synchronize_irq(); -+} -+#undef synchronize_irq -+#define synchronize_irq(X) _kc_synchronize_irq() -+ -+#include <linux/tqueue.h> -+#define work_struct tq_struct -+#undef INIT_WORK -+#define INIT_WORK(a,b,c) INIT_TQUEUE(a,(void (*)(void *))b,c) -+#undef container_of -+#define container_of list_entry -+#define schedule_work schedule_task -+#define flush_scheduled_work flush_scheduled_tasks -+#endif /* 2.5.28 => 2.4.17 */ -+ -+/*****************************************************************************/ -+/* 2.6.4 => 2.6.0 */ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) -+#define MODULE_VERSION(_version) MODULE_INFO(version, _version) -+#endif /* 2.6.4 => 2.6.0 */ -+/*****************************************************************************/ -+/* 2.6.0 => 2.5.28 */ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) -+#define MODULE_INFO(version, _version) -+#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT -+#define CONFIG_E1000_DISABLE_PACKET_SPLIT 1 -+#endif -+ -+#define pci_set_consistent_dma_mask(dev,mask) 1 -+ -+#undef dev_put -+#define dev_put(dev) __dev_put(dev) -+ -+#ifndef skb_fill_page_desc -+#define skb_fill_page_desc _kc_skb_fill_page_desc -+extern void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, int off, int size); -+#endif -+ -+#ifndef pci_dma_mapping_error -+#define pci_dma_mapping_error _kc_pci_dma_mapping_error -+static inline int _kc_pci_dma_mapping_error(dma_addr_t dma_addr) -+{ -+ return dma_addr == 0; -+} -+#endif -+ -+#undef ALIGN -+#define ALIGN(x,a) (((x)+(a)-1)&~((a)-1)) -+ -+#endif /* 2.6.0 => 2.5.28 */ -+ -+/*****************************************************************************/ -+/* 2.4.22 => 2.4.17 */ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) ) -+#define pci_name(x) ((x)->slot_name) -+#endif /* 2.4.22 => 2.4.17 */ -+ -+/*****************************************************************************/ -+/* 2.6.5 => 2.6.0 */ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) -+#define pci_dma_sync_single_for_cpu pci_dma_sync_single -+#define pci_dma_sync_single_for_device pci_dma_sync_single_for_cpu -+#endif /* 2.6.5 => 2.6.0 */ -+ -+/*****************************************************************************/ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+/* -+ * initialize a work-struct's func and data pointers: -+ */ -+#define PREPARE_WORK(_work, _func, _data) \ -+ do { \ -+ (_work)->func = _func; \ -+ (_work)->data = _data; \ -+ } while (0) -+ -+#endif -+/*****************************************************************************/ -+/* 2.6.4 => 2.6.0 */ -+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,25) || \ -+ ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \ -+ LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) ) -+#define ETHTOOL_OPS_COMPAT -+#endif /* 2.6.4 => 2.6.0 */ -+ -+/*****************************************************************************/ -+/* Installations with ethtool version without eeprom, adapter id, or statistics -+ * support */ -+ -+#ifndef ETH_GSTRING_LEN -+#define ETH_GSTRING_LEN 32 -+#endif -+ -+#ifndef ETHTOOL_GSTATS -+#define ETHTOOL_GSTATS 0x1d -+#undef ethtool_drvinfo -+#define ethtool_drvinfo k_ethtool_drvinfo -+struct k_ethtool_drvinfo { -+ u32 cmd; -+ char driver[32]; -+ char version[32]; -+ char fw_version[32]; -+ char bus_info[32]; -+ char reserved1[32]; -+ char reserved2[16]; -+ u32 n_stats; -+ u32 testinfo_len; -+ u32 eedump_len; -+ u32 regdump_len; -+}; -+ -+struct ethtool_stats { -+ u32 cmd; -+ u32 n_stats; -+ u64 data[0]; -+}; -+#endif /* ETHTOOL_GSTATS */ -+ -+#ifndef ETHTOOL_PHYS_ID -+#define ETHTOOL_PHYS_ID 0x1c -+#endif /* ETHTOOL_PHYS_ID */ -+ -+#ifndef ETHTOOL_GSTRINGS -+#define ETHTOOL_GSTRINGS 0x1b -+enum ethtool_stringset { -+ ETH_SS_TEST = 0, -+ ETH_SS_STATS, -+}; -+struct ethtool_gstrings { -+ u32 cmd; /* ETHTOOL_GSTRINGS */ -+ u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/ -+ u32 len; /* number of strings in the string set */ -+ u8 data[0]; -+}; -+#endif /* ETHTOOL_GSTRINGS */ -+ -+#ifndef ETHTOOL_TEST -+#define ETHTOOL_TEST 0x1a -+enum ethtool_test_flags { -+ ETH_TEST_FL_OFFLINE = (1 << 0), -+ ETH_TEST_FL_FAILED = (1 << 1), -+}; -+struct ethtool_test { -+ u32 cmd; -+ u32 flags; -+ u32 reserved; -+ u32 len; -+ u64 data[0]; -+}; -+#endif /* ETHTOOL_TEST */ -+ -+#ifndef ETHTOOL_GEEPROM -+#define ETHTOOL_GEEPROM 0xb -+#undef ETHTOOL_GREGS -+struct ethtool_eeprom { -+ u32 cmd; -+ u32 magic; -+ u32 offset; -+ u32 len; -+ u8 data[0]; -+}; -+ -+struct ethtool_value { -+ u32 cmd; -+ u32 data; -+}; -+#endif /* ETHTOOL_GEEPROM */ -+ -+#ifndef ETHTOOL_GLINK -+#define ETHTOOL_GLINK 0xa -+#endif /* ETHTOOL_GLINK */ -+ -+#ifndef ETHTOOL_GREGS -+#define ETHTOOL_GREGS 0x00000004 /* Get NIC registers */ -+#define ethtool_regs _kc_ethtool_regs -+/* for passing big chunks of data */ -+struct _kc_ethtool_regs { -+ u32 cmd; -+ u32 version; /* driver-specific, indicates different chips/revs */ -+ u32 len; /* bytes */ -+ u8 data[0]; -+}; -+#endif /* ETHTOOL_GREGS */ -+ -+#ifndef ETHTOOL_GMSGLVL -+#define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */ -+#endif -+#ifndef ETHTOOL_SMSGLVL -+#define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level, priv. */ -+#endif -+#ifndef ETHTOOL_NWAY_RST -+#define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation, priv */ -+#endif -+#ifndef ETHTOOL_GLINK -+#define ETHTOOL_GLINK 0x0000000a /* Get link status */ -+#endif -+#ifndef ETHTOOL_GEEPROM -+#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */ -+#endif -+#ifndef ETHTOOL_SEEPROM -+#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data */ -+#endif -+#ifndef ETHTOOL_GCOALESCE -+#define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */ -+/* for configuring coalescing parameters of chip */ -+#define ethtool_coalesce _kc_ethtool_coalesce -+struct _kc_ethtool_coalesce { -+ u32 cmd; /* ETHTOOL_{G,S}COALESCE */ -+ -+ /* How many usecs to delay an RX interrupt after -+ * a packet arrives. If 0, only rx_max_coalesced_frames -+ * is used. -+ */ -+ u32 rx_coalesce_usecs; -+ -+ /* How many packets to delay an RX interrupt after -+ * a packet arrives. If 0, only rx_coalesce_usecs is -+ * used. It is illegal to set both usecs and max frames -+ * to zero as this would cause RX interrupts to never be -+ * generated. -+ */ -+ u32 rx_max_coalesced_frames; -+ -+ /* Same as above two parameters, except that these values -+ * apply while an IRQ is being serviced by the host. Not -+ * all cards support this feature and the values are ignored -+ * in that case. -+ */ -+ u32 rx_coalesce_usecs_irq; -+ u32 rx_max_coalesced_frames_irq; -+ -+ /* How many usecs to delay a TX interrupt after -+ * a packet is sent. If 0, only tx_max_coalesced_frames -+ * is used. -+ */ -+ u32 tx_coalesce_usecs; -+ -+ /* How many packets to delay a TX interrupt after -+ * a packet is sent. If 0, only tx_coalesce_usecs is -+ * used. It is illegal to set both usecs and max frames -+ * to zero as this would cause TX interrupts to never be -+ * generated. -+ */ -+ u32 tx_max_coalesced_frames; -+ -+ /* Same as above two parameters, except that these values -+ * apply while an IRQ is being serviced by the host. Not -+ * all cards support this feature and the values are ignored -+ * in that case. -+ */ -+ u32 tx_coalesce_usecs_irq; -+ u32 tx_max_coalesced_frames_irq; -+ -+ /* How many usecs to delay in-memory statistics -+ * block updates. Some drivers do not have an in-memory -+ * statistic block, and in such cases this value is ignored. -+ * This value must not be zero. -+ */ -+ u32 stats_block_coalesce_usecs; -+ -+ /* Adaptive RX/TX coalescing is an algorithm implemented by -+ * some drivers to improve latency under low packet rates and -+ * improve throughput under high packet rates. Some drivers -+ * only implement one of RX or TX adaptive coalescing. Anything -+ * not implemented by the driver causes these values to be -+ * silently ignored. -+ */ -+ u32 use_adaptive_rx_coalesce; -+ u32 use_adaptive_tx_coalesce; -+ -+ /* When the packet rate (measured in packets per second) -+ * is below pkt_rate_low, the {rx,tx}_*_low parameters are -+ * used. -+ */ -+ u32 pkt_rate_low; -+ u32 rx_coalesce_usecs_low; -+ u32 rx_max_coalesced_frames_low; -+ u32 tx_coalesce_usecs_low; -+ u32 tx_max_coalesced_frames_low; -+ -+ /* When the packet rate is below pkt_rate_high but above -+ * pkt_rate_low (both measured in packets per second) the -+ * normal {rx,tx}_* coalescing parameters are used. -+ */ -+ -+ /* When the packet rate is (measured in packets per second) -+ * is above pkt_rate_high, the {rx,tx}_*_high parameters are -+ * used. -+ */ -+ u32 pkt_rate_high; -+ u32 rx_coalesce_usecs_high; -+ u32 rx_max_coalesced_frames_high; -+ u32 tx_coalesce_usecs_high; -+ u32 tx_max_coalesced_frames_high; -+ -+ /* How often to do adaptive coalescing packet rate sampling, -+ * measured in seconds. Must not be zero. -+ */ -+ u32 rate_sample_interval; -+}; -+#endif /* ETHTOOL_GCOALESCE */ -+ -+#ifndef ETHTOOL_SCOALESCE -+#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */ -+#endif -+#ifndef ETHTOOL_GRINGPARAM -+#define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */ -+/* for configuring RX/TX ring parameters */ -+#define ethtool_ringparam _kc_ethtool_ringparam -+struct _kc_ethtool_ringparam { -+ u32 cmd; /* ETHTOOL_{G,S}RINGPARAM */ -+ -+ /* Read only attributes. These indicate the maximum number -+ * of pending RX/TX ring entries the driver will allow the -+ * user to set. -+ */ -+ u32 rx_max_pending; -+ u32 rx_mini_max_pending; -+ u32 rx_jumbo_max_pending; -+ u32 tx_max_pending; -+ -+ /* Values changeable by the user. The valid values are -+ * in the range 1 to the "*_max_pending" counterpart above. -+ */ -+ u32 rx_pending; -+ u32 rx_mini_pending; -+ u32 rx_jumbo_pending; -+ u32 tx_pending; -+}; -+#endif /* ETHTOOL_GRINGPARAM */ -+ -+#ifndef ETHTOOL_SRINGPARAM -+#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters, priv. */ -+#endif -+#ifndef ETHTOOL_GPAUSEPARAM -+#define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */ -+/* for configuring link flow control parameters */ -+#define ethtool_pauseparam _kc_ethtool_pauseparam -+struct _kc_ethtool_pauseparam { -+ u32 cmd; /* ETHTOOL_{G,S}PAUSEPARAM */ -+ -+ /* If the link is being auto-negotiated (via ethtool_cmd.autoneg -+ * being true) the user may set 'autonet' here non-zero to have the -+ * pause parameters be auto-negotiated too. In such a case, the -+ * {rx,tx}_pause values below determine what capabilities are -+ * advertised. -+ * -+ * If 'autoneg' is zero or the link is not being auto-negotiated, -+ * then {rx,tx}_pause force the driver to use/not-use pause -+ * flow control. -+ */ -+ u32 autoneg; -+ u32 rx_pause; -+ u32 tx_pause; -+}; -+#endif /* ETHTOOL_GPAUSEPARAM */ -+ -+#ifndef ETHTOOL_SPAUSEPARAM -+#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */ -+#endif -+#ifndef ETHTOOL_GRXCSUM -+#define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */ -+#endif -+#ifndef ETHTOOL_SRXCSUM -+#define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */ -+#endif -+#ifndef ETHTOOL_GTXCSUM -+#define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */ -+#endif -+#ifndef ETHTOOL_STXCSUM -+#define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */ -+#endif -+#ifndef ETHTOOL_GSG -+#define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable -+* (ethtool_value) */ -+#endif -+#ifndef ETHTOOL_SSG -+#define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable -+* (ethtool_value). */ -+#endif -+#ifndef ETHTOOL_TEST -+#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test, priv. */ -+#endif -+#ifndef ETHTOOL_GSTRINGS -+#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */ -+#endif -+#ifndef ETHTOOL_PHYS_ID -+#define ETHTOOL_PHYS_ID 0x0000001c /* identify the NIC */ -+#endif -+#ifndef ETHTOOL_GSTATS -+#define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */ -+#endif -+#ifndef ETHTOOL_GTSO -+#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */ -+#endif -+#ifndef ETHTOOL_STSO -+#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */ -+#endif -+ -+#ifndef ETHTOOL_BUSINFO_LEN -+#define ETHTOOL_BUSINFO_LEN 32 -+#endif -+ -+/*****************************************************************************/ -+ -+enum RTL8168_DSM_STATE { -+ DSM_MAC_INIT = 1, -+ DSM_NIC_GOTO_D3 = 2, -+ DSM_IF_DOWN = 3, -+ DSM_NIC_RESUME_D3 = 4, -+ DSM_IF_UP = 5, -+}; -+ -+enum RTL8168_registers { -+ MAC0 = 0x00, /* Ethernet hardware address. */ -+ MAC4 = 0x04, -+ MAR0 = 0x08, /* Multicast filter. */ -+ CounterAddrLow = 0x10, -+ CounterAddrHigh = 0x14, -+ CustomLED = 0x18, -+ TxDescStartAddrLow = 0x20, -+ TxDescStartAddrHigh = 0x24, -+ TxHDescStartAddrLow = 0x28, -+ TxHDescStartAddrHigh = 0x2c, -+ FLASH = 0x30, -+ ERSR = 0x36, -+ ChipCmd = 0x37, -+ TxPoll = 0x38, -+ IntrMask = 0x3C, -+ IntrStatus = 0x3E, -+ TxConfig = 0x40, -+ RxConfig = 0x44, -+ TCTR = 0x48, -+ Cfg9346 = 0x50, -+ Config0 = 0x51, -+ Config1 = 0x52, -+ Config2 = 0x53, -+ Config3 = 0x54, -+ Config4 = 0x55, -+ Config5 = 0x56, -+ TDFNR = 0x57, -+ TimeInt0 = 0x58, -+ TimeInt1 = 0x5C, -+ PHYAR = 0x60, -+ CSIDR = 0x64, -+ CSIAR = 0x68, -+ PHYstatus = 0x6C, -+ MACDBG = 0x6D, -+ GPIO = 0x6E, -+ PMCH = 0x6F, -+ ERIDR = 0x70, -+ ERIAR = 0x74, -+ EPHY_RXER_NUM = 0x7C, -+ EPHYAR = 0x80, -+ TimeInt2 = 0x8C, -+ OCPDR = 0xB0, -+ MACOCP = 0xB0, -+ OCPAR = 0xB4, -+ SecMAC0 = 0xB4, -+ SecMAC4 = 0xB8, -+ PHYOCP = 0xB8, -+ DBG_reg = 0xD1, -+ TwiCmdReg = 0xD2, -+ MCUCmd_reg = 0xD3, -+ RxMaxSize = 0xDA, -+ EFUSEAR = 0xDC, -+ CPlusCmd = 0xE0, -+ IntrMitigate = 0xE2, -+ RxDescAddrLow = 0xE4, -+ RxDescAddrHigh = 0xE8, -+ MTPS = 0xEC, -+ FuncEvent = 0xF0, -+ PPSW = 0xF2, -+ FuncEventMask = 0xF4, -+ TimeInt3 = 0xF4, -+ FuncPresetState = 0xF8, -+ IBCR0 = 0xF8, -+ IBCR2 = 0xF9, -+ IBIMR0 = 0xFA, -+ IBISR0 = 0xFB, -+ FuncForceEvent = 0xFC, -+}; -+ -+enum RTL8168_register_content { -+ /* InterruptStatusBits */ -+ SYSErr = 0x8000, -+ PCSTimeout = 0x4000, -+ SWInt = 0x0100, -+ TxDescUnavail = 0x0080, -+ RxFIFOOver = 0x0040, -+ LinkChg = 0x0020, -+ RxDescUnavail = 0x0010, -+ TxErr = 0x0008, -+ TxOK = 0x0004, -+ RxErr = 0x0002, -+ RxOK = 0x0001, -+ -+ /* RxStatusDesc */ -+ RxRWT = (1 << 22), -+ RxRES = (1 << 21), -+ RxRUNT = (1 << 20), -+ RxCRC = (1 << 19), -+ -+ /* ChipCmdBits */ -+ StopReq = 0x80, -+ CmdReset = 0x10, -+ CmdRxEnb = 0x08, -+ CmdTxEnb = 0x04, -+ RxBufEmpty = 0x01, -+ -+ /* Cfg9346Bits */ -+ Cfg9346_Lock = 0x00, -+ Cfg9346_Unlock = 0xC0, -+ Cfg9346_EEDO = (1 << 0), -+ Cfg9346_EEDI = (1 << 1), -+ Cfg9346_EESK = (1 << 2), -+ Cfg9346_EECS = (1 << 3), -+ Cfg9346_EEM0 = (1 << 6), -+ Cfg9346_EEM1 = (1 << 7), -+ -+ /* rx_mode_bits */ -+ AcceptErr = 0x20, -+ AcceptRunt = 0x10, -+ AcceptBroadcast = 0x08, -+ AcceptMulticast = 0x04, -+ AcceptMyPhys = 0x02, -+ AcceptAllPhys = 0x01, -+ -+ /* Transmit Priority Polling*/ -+ HPQ = 0x80, -+ NPQ = 0x40, -+ FSWInt = 0x01, -+ -+ /* RxConfigBits */ -+ Reserved2_shift = 13, -+ RxCfgDMAShift = 8, -+ RxCfg_128_int_en = (1 << 15), -+ RxCfg_fet_multi_en = (1 << 14), -+ RxCfg_half_refetch = (1 << 13), -+ RxCfg_9356SEL = (1 << 6), -+ -+ /* TxConfigBits */ -+ TxInterFrameGapShift = 24, -+ TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ -+ TxMACLoopBack = (1 << 17), /* MAC loopback */ -+ -+ /* Config1 register */ -+ LEDS1 = (1 << 7), -+ LEDS0 = (1 << 6), -+ Speed_down = (1 << 4), -+ MEMMAP = (1 << 3), -+ IOMAP = (1 << 2), -+ VPD = (1 << 1), -+ PMEnable = (1 << 0), /* Power Management Enable */ -+ -+ /* Config2 register */ -+ PMSTS_En = (1 << 5), -+ -+ /* Config3 register */ -+ Isolate_en = (1 << 12), /* Isolate enable */ -+ MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ -+ LinkUp = (1 << 4), /* This bit is reserved in RTL8168B.*/ -+ /* Wake up when the cable connection is re-established */ -+ ECRCEN = (1 << 3), /* This bit is reserved in RTL8168B*/ -+ Jumbo_En0 = (1 << 2), /* This bit is reserved in RTL8168B*/ -+ RDY_TO_L23 = (1 << 1), /* This bit is reserved in RTL8168B*/ -+ Beacon_en = (1 << 0), /* This bit is reserved in RTL8168B*/ -+ -+ /* Config4 register */ -+ Jumbo_En1 = (1 << 1), /* This bit is reserved in RTL8168B*/ -+ -+ /* Config5 register */ -+ BWF = (1 << 6), /* Accept Broadcast wakeup frame */ -+ MWF = (1 << 5), /* Accept Multicast wakeup frame */ -+ UWF = (1 << 4), /* Accept Unicast wakeup frame */ -+ LanWake = (1 << 1), /* LanWake enable/disable */ -+ PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ -+ -+ /* CPlusCmd */ -+ EnableBist = (1 << 15), -+ Macdbgo_oe = (1 << 14), -+ Normal_mode = (1 << 13), -+ Force_halfdup = (1 << 12), -+ Force_rxflow_en = (1 << 11), -+ Force_txflow_en = (1 << 10), -+ Cxpl_dbg_sel = (1 << 9),//This bit is reserved in RTL8168B -+ ASF = (1 << 8),//This bit is reserved in RTL8168C -+ PktCntrDisable = (1 << 7), -+ RxVlan = (1 << 6), -+ RxChkSum = (1 << 5), -+ Macdbgo_sel = 0x001C, -+ INTT_0 = 0x0000, -+ INTT_1 = 0x0001, -+ INTT_2 = 0x0002, -+ INTT_3 = 0x0003, -+ -+ /* rtl8168_PHYstatus */ -+ PowerSaveStatus = 0x80, -+ TxFlowCtrl = 0x40, -+ RxFlowCtrl = 0x20, -+ _1000bpsF = 0x10, -+ _100bps = 0x08, -+ _10bps = 0x04, -+ LinkStatus = 0x02, -+ FullDup = 0x01, -+ -+ /* DBG_reg */ -+ Fix_Nak_1 = (1 << 4), -+ Fix_Nak_2 = (1 << 3), -+ DBGPIN_E2 = (1 << 0), -+ -+ /* DumpCounterCommand */ -+ CounterDump = 0x8, -+ -+ /* PHY access */ -+ PHYAR_Flag = 0x80000000, -+ PHYAR_Write = 0x80000000, -+ PHYAR_Read = 0x00000000, -+ PHYAR_Reg_Mask = 0x1f, -+ PHYAR_Reg_shift = 16, -+ PHYAR_Data_Mask = 0xffff, -+ -+ /* EPHY access */ -+ EPHYAR_Flag = 0x80000000, -+ EPHYAR_Write = 0x80000000, -+ EPHYAR_Read = 0x00000000, -+ EPHYAR_Reg_Mask = 0x1f, -+ EPHYAR_Reg_shift = 16, -+ EPHYAR_Data_Mask = 0xffff, -+ -+ /* CSI access */ -+ CSIAR_Flag = 0x80000000, -+ CSIAR_Write = 0x80000000, -+ CSIAR_Read = 0x00000000, -+ CSIAR_ByteEn = 0x0f, -+ CSIAR_ByteEn_shift = 12, -+ CSIAR_Addr_Mask = 0x0fff, -+ -+ /* ERI access */ -+ ERIAR_Flag = 0x80000000, -+ ERIAR_Write = 0x80000000, -+ ERIAR_Read = 0x00000000, -+ ERIAR_Addr_Align = 4, /* ERI access register address must be 4 byte alignment */ -+ ERIAR_ExGMAC = 0, -+ ERIAR_MSIX = 1, -+ ERIAR_ASF = 2, -+ ERIAR_OOB = 2, -+ ERIAR_Type_shift = 16, -+ ERIAR_ByteEn = 0x0f, -+ ERIAR_ByteEn_shift = 12, -+ -+ /* OCP GPHY access */ -+ OCPDR_Write = 0x80000000, -+ OCPDR_Read = 0x00000000, -+ OCPDR_Reg_Mask = 0xFF, -+ OCPDR_Data_Mask = 0xFFFF, -+ OCPDR_GPHY_Reg_shift = 16, -+ OCPAR_Flag = 0x80000000, -+ OCPAR_GPHY_Write = 0x8000F060, -+ OCPAR_GPHY_Read = 0x0000F060, -+ OCPR_Write = 0x80000000, -+ OCPR_Read = 0x00000000, -+ OCPR_Addr_Reg_shift = 16, -+ OCPR_Flag = 0x80000000, -+ OCP_STD_PHY_BASE_PAGE = 0x0A40, -+ -+ /* MCU Command */ -+ Now_is_oob = (1 << 7), -+ Txfifo_empty = (1 << 5), -+ Rxfifo_empty = (1 << 4), -+ -+ /* E-FUSE access */ -+ EFUSE_WRITE = 0x80000000, -+ EFUSE_WRITE_OK = 0x00000000, -+ EFUSE_READ = 0x00000000, -+ EFUSE_READ_OK = 0x80000000, -+ EFUSE_Reg_Mask = 0x03FF, -+ EFUSE_Reg_Shift = 8, -+ EFUSE_Check_Cnt = 300, -+ EFUSE_READ_FAIL = 0xFF, -+ EFUSE_Data_Mask = 0x000000FF, -+ -+ /* GPIO */ -+ GPIO_en = (1 << 0), -+ -+}; -+ -+enum _DescStatusBit { -+ DescOwn = (1 << 31), /* Descriptor is owned by NIC */ -+ RingEnd = (1 << 30), /* End of descriptor ring */ -+ FirstFrag = (1 << 29), /* First segment of a packet */ -+ LastFrag = (1 << 28), /* Final segment of a packet */ -+ -+ /* Tx private */ -+ /*------ offset 0 of tx descriptor ------*/ -+ LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ -+ LargeSend_DP = (1 << 16), /* TCP Large Send Offload (TSO) */ -+ MSSShift = 16, /* MSS value position */ -+ MSSMask = 0x7FFU, /* MSS value 11 bits */ -+ TxIPCS = (1 << 18), /* Calculate IP checksum */ -+ TxUDPCS = (1 << 17), /* Calculate UDP/IP checksum */ -+ TxTCPCS = (1 << 16), /* Calculate TCP/IP checksum */ -+ TxVlanTag = (1 << 17), /* Add VLAN tag */ -+ -+ /*@@@@@@ offset 4 of tx descriptor => bits for RTL8168C/CP only begin @@@@@@*/ -+ TxUDPCS_C = (1 << 31), /* Calculate UDP/IP checksum */ -+ TxTCPCS_C = (1 << 30), /* Calculate TCP/IP checksum */ -+ TxIPCS_C = (1 << 29), /* Calculate IP checksum */ -+ /*@@@@@@ offset 4 of tx descriptor => bits for RTL8168C/CP only end @@@@@@*/ -+ -+ -+ /* Rx private */ -+ /*------ offset 0 of rx descriptor ------*/ -+ PID1 = (1 << 18), /* Protocol ID bit 1/2 */ -+ PID0 = (1 << 17), /* Protocol ID bit 2/2 */ -+ -+#define RxProtoUDP (PID1) -+#define RxProtoTCP (PID0) -+#define RxProtoIP (PID1 | PID0) -+#define RxProtoMask RxProtoIP -+ -+ RxIPF = (1 << 16), /* IP checksum failed */ -+ RxUDPF = (1 << 15), /* UDP/IP checksum failed */ -+ RxTCPF = (1 << 14), /* TCP/IP checksum failed */ -+ RxVlanTag = (1 << 16), /* VLAN tag available */ -+ -+ /*@@@@@@ offset 0 of rx descriptor => bits for RTL8168C/CP only begin @@@@@@*/ -+ RxUDPT = (1 << 18), -+ RxTCPT = (1 << 17), -+ /*@@@@@@ offset 0 of rx descriptor => bits for RTL8168C/CP only end @@@@@@*/ -+ -+ /*@@@@@@ offset 4 of rx descriptor => bits for RTL8168C/CP only begin @@@@@@*/ -+ RxV6F = (1 << 31), -+ RxV4F = (1 << 30), -+ /*@@@@@@ offset 4 of rx descriptor => bits for RTL8168C/CP only end @@@@@@*/ -+}; -+ -+enum features { -+// RTL_FEATURE_WOL = (1 << 0), -+ RTL_FEATURE_MSI = (1 << 1), -+}; -+ -+enum wol_capability { -+ WOL_DISABLED = 0, -+ WOL_ENABLED = 1 -+}; -+ -+enum bits { -+ BIT_0 = (1 << 0), -+ BIT_1 = (1 << 1), -+ BIT_2 = (1 << 2), -+ BIT_3 = (1 << 3), -+ BIT_4 = (1 << 4), -+ BIT_5 = (1 << 5), -+ BIT_6 = (1 << 6), -+ BIT_7 = (1 << 7), -+ BIT_8 = (1 << 8), -+ BIT_9 = (1 << 9), -+ BIT_10 = (1 << 10), -+ BIT_11 = (1 << 11), -+ BIT_12 = (1 << 12), -+ BIT_13 = (1 << 13), -+ BIT_14 = (1 << 14), -+ BIT_15 = (1 << 15), -+ BIT_16 = (1 << 16), -+ BIT_17 = (1 << 17), -+ BIT_18 = (1 << 18), -+ BIT_19 = (1 << 19), -+ BIT_20 = (1 << 20), -+ BIT_21 = (1 << 21), -+ BIT_22 = (1 << 22), -+ BIT_23 = (1 << 23), -+ BIT_24 = (1 << 24), -+ BIT_25 = (1 << 25), -+ BIT_26 = (1 << 26), -+ BIT_27 = (1 << 27), -+ BIT_28 = (1 << 28), -+ BIT_29 = (1 << 29), -+ BIT_30 = (1 << 30), -+ BIT_31 = (1 << 31) -+}; -+ -+enum effuse { -+ EFUSE_NOT_SUPPORT = 0, -+ EFUSE_SUPPORT_V1, -+ EFUSE_SUPPORT_V2, -+ EFUSE_SUPPORT_V3, -+}; -+#define RsvdMask 0x3fffc000 -+ -+struct TxDesc { -+ u32 opts1; -+ u32 opts2; -+ u64 addr; -+}; -+ -+struct RxDesc { -+ u32 opts1; -+ u32 opts2; -+ u64 addr; -+}; -+ -+struct ring_info { -+ struct sk_buff *skb; -+ u32 len; -+ u8 __pad[sizeof(void *) - sizeof(u32)]; -+}; -+ -+struct pci_resource { -+ u8 cmd; -+ u8 cls; -+ u16 io_base_h; -+ u16 io_base_l; -+ u16 mem_base_h; -+ u16 mem_base_l; -+ u8 ilr; -+ u16 resv_0x1c_h; -+ u16 resv_0x1c_l; -+ u16 resv_0x20_h; -+ u16 resv_0x20_l; -+ u16 resv_0x24_h; -+ u16 resv_0x24_l; -+ u16 resv_0x2c_h; -+ u16 resv_0x2c_l; -+ u32 pci_sn_l; -+ u32 pci_sn_h; -+}; -+ -+struct rtl8168_private { -+ void __iomem *mmio_addr; /* memory map physical address */ -+ struct pci_dev *pci_dev; /* Index of PCI device */ -+ struct net_device *dev; -+#ifdef CONFIG_R8168_NAPI -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) -+ struct napi_struct napi; -+#endif -+#endif -+ struct net_device_stats stats; /* statistics of net device */ -+ spinlock_t lock; /* spin lock flag */ -+ spinlock_t phy_lock; /* spin lock flag for GPHY */ -+ u32 msg_enable; -+ u32 tx_tcp_csum_cmd; -+ u32 tx_udp_csum_cmd; -+ u32 tx_ip_csum_cmd; -+ int max_jumbo_frame_size; -+ int chipset; -+ u32 mcfg; -+ u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ -+ u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ -+ u32 dirty_rx; -+ u32 dirty_tx; -+ struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ -+ struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ -+ dma_addr_t TxPhyAddr; -+ dma_addr_t RxPhyAddr; -+ struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ -+ struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ -+ unsigned rx_buf_sz; -+ struct timer_list esd_timer; -+ struct timer_list link_timer; -+ struct pci_resource pci_cfg_space; -+ unsigned int esd_flag; -+ unsigned int pci_cfg_is_read; -+ unsigned int rtl8168_rx_config; -+ u16 cp_cmd; -+ u16 intr_mask; -+ u16 timer_intr_mask; -+ int phy_auto_nego_reg; -+ int phy_1000_ctrl_reg; -+ u8 org_mac_addr[NODE_ADDRESS_SIZE]; -+ struct rtl8168_counters *tally_vaddr; -+ dma_addr_t tally_paddr; -+ -+#ifdef CONFIG_R8168_VLAN -+ struct vlan_group *vlgrp; -+#endif -+ u8 wol_enabled; -+ u32 wol_opts; -+ u8 efuse_ver; -+ u8 eeprom_type; -+ u8 autoneg; -+ u8 duplex; -+ u16 speed; -+ u16 eeprom_len; -+ u16 cur_page; -+ u32 bios_setting; -+ -+ int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); -+ void (*get_settings)(struct net_device *, struct ethtool_cmd *); -+ void (*phy_reset_enable)(struct net_device *); -+ unsigned int (*phy_reset_pending)(struct net_device *); -+ unsigned int (*link_ok)(struct net_device *); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ struct work_struct task; -+#else -+ struct delayed_work task; -+#endif -+ unsigned features; -+ -+ u8 org_pci_offset_99; -+ u8 org_pci_offset_180; -+ u8 issue_offset_99_event; -+ -+ u8 org_pci_offset_80; -+ u8 org_pci_offset_81; -+ u8 use_timer_interrrupt; -+ -+ u32 keep_intr_cnt; -+ -+ u8 HwIcVerUnknown; -+ u8 NotWrRamCodeToMicroP; -+ u8 NotWrMcuPatchCode; -+ u8 HwHasWrRamCodeToMicroP; -+ -+ u16 sw_ram_code_ver; -+ u16 hw_ram_code_ver; -+ -+ u8 rtk_enable_diag; -+ -+ u8 ShortPacketSwChecksum; -+ -+ u8 UseSwPaddingShortPkt; -+ -+ void *ShortPacketEmptyBuffer; -+ dma_addr_t ShortPacketEmptyBufferPhy; -+ -+ u8 RequireAdcBiasPatch; -+ u16 AdcBiasPatchIoffset; -+ -+ u8 RequireAdjustUpsTxLinkPulseTiming; -+ u16 SwrCnt1msIni; -+ -+ u8 HwSuppNowIsOobVer; -+ -+ u8 RequiredSecLanDonglePatch; -+ -+ //Dash+++++++++++++++++ -+ u8 HwSuppDashVer; -+ u8 DASH; -+ -+#ifdef ENABLE_DASH_SUPPORT -+ u16 AfterRecvFromFwBufLen; -+ u8 AfterRecvFromFwBuf[RECV_FROM_FW_BUF_SIZE]; -+ u16 AfterSendToFwBufLen; -+ u8 AfterSendToFwBuf[SEND_TO_FW_BUF_SIZE]; -+ u16 SendToFwBufferLen; -+ u32 SizeOfSendToFwBuffer ; -+ u32 SizeOfSendToFwBufferMemAlloc ; -+ u32 NumOfSendToFwBuffer ; -+ -+ u8 OobReq; -+ u8 OobAck; -+ u32 OobReqComplete; -+ u32 OobAckComplete; -+ -+ u8 RcvFwReqSysOkEvt; -+ u8 RcvFwDashOkEvt; -+ u8 SendFwHostOkEvt; -+ -+ u8 DashFwDisableRx; -+ -+ void *UnalignedSendToFwBufferVa; -+ void *SendToFwBuffer ; -+ u64 SendToFwBufferPhy ; -+ u8 SendingToFw; -+ u64 UnalignedSendToFwBufferPa; -+ PTX_DASH_SEND_FW_DESC TxDashSendFwDesc; -+ u64 TxDashSendFwDescPhy; -+ u8 *UnalignedTxDashSendFwDescVa; -+ u32 SizeOfTxDashSendFwDescMemAlloc; -+ u32 SizeOfTxDashSendFwDesc ; -+ u32 NumTxDashSendFwDesc ; -+ u32 CurrNumTxDashSendFwDesc ; -+ u64 UnalignedTxDashSendFwDescPa; -+ -+ u32 NumRecvFromFwBuffer ; -+ u32 SizeOfRecvFromFwBuffer ; -+ u32 SizeOfRecvFromFwBufferMemAlloc ; -+ void *RecvFromFwBuffer ; -+ u64 RecvFromFwBufferPhy ; -+ -+ void *UnalignedRecvFromFwBufferVa; -+ u64 UnalignedRecvFromFwBufferPa; -+ PRX_DASH_FROM_FW_DESC RxDashRecvFwDesc; -+ u64 RxDashRecvFwDescPhy; -+ u8 *UnalignedRxDashRecvFwDescVa; -+ u32 SizeOfRxDashRecvFwDescMemAlloc; -+ u32 SizeOfRxDashRecvFwDesc ; -+ u32 NumRxDashRecvFwDesc ; -+ u32 CurrNumRxDashRecvFwDesc ; -+ u64 UnalignedRxDashRecvFwDescPa; -+ u8 DashReqRegValue; -+ u16 HostReqValue; -+ -+ u32 CmacResetIsrCounter; -+ u8 CmacResetIsr1st ; -+ u8 CmacResetIsr2nd ; -+ u8 CmacResetting ; -+ u8 CmacOobIssueCmacReset ; -+ //Dash----------------- -+#endif //ENABLE_DASH_SUPPORT -+ -+ //Realwow++++++++++++++ -+ u8 HwSuppKCPOffloadVer; -+ -+ u8 EnableDhcpTimeoutWake; -+ u8 EnableTeredoOffload; -+ u8 EnableKCPOffload; -+#ifdef ENABLE_REALWOW_SUPPORT -+ u32 DhcpTimeout; -+ MP_KCP_INFO MpKCPInfo; -+ //Realwow-------------- -+#endif //ENABLE_REALWOW_SUPPORT -+ -+#ifdef ENABLE_R8168_PROCFS -+ //Procfs support -+ struct proc_dir_entry *proc_dir; -+#endif -+}; -+ -+enum eetype { -+ EEPROM_TYPE_NONE=0, -+ EEPROM_TYPE_93C46, -+ EEPROM_TYPE_93C56, -+ EEPROM_TWSI -+}; -+ -+enum mcfg { -+ CFG_METHOD_1=0, -+ CFG_METHOD_2, -+ CFG_METHOD_3, -+ CFG_METHOD_4, -+ CFG_METHOD_5, -+ CFG_METHOD_6, -+ CFG_METHOD_7, -+ CFG_METHOD_8, -+ CFG_METHOD_9 , -+ CFG_METHOD_10, -+ CFG_METHOD_11, -+ CFG_METHOD_12, -+ CFG_METHOD_13, -+ CFG_METHOD_14, -+ CFG_METHOD_15, -+ CFG_METHOD_16, -+ CFG_METHOD_17, -+ CFG_METHOD_18, -+ CFG_METHOD_19, -+ CFG_METHOD_20, -+ CFG_METHOD_21, -+ CFG_METHOD_22, -+ CFG_METHOD_23, -+ CFG_METHOD_24, -+ CFG_METHOD_25, -+ CFG_METHOD_26, -+ CFG_METHOD_27, -+ CFG_METHOD_28, -+ CFG_METHOD_29, -+ CFG_METHOD_30, -+ CFG_METHOD_MAX, -+ CFG_METHOD_DEFAULT = 0xFF -+}; -+ -+#define OOB_CMD_RESET 0x00 -+#define OOB_CMD_DRIVER_START 0x05 -+#define OOB_CMD_DRIVER_STOP 0x06 -+#define OOB_CMD_SET_IPMAC 0x41 -+ -+ -+//Ram Code Version -+#define NIC_RAMCODE_VERSION_CFG_METHOD_14 (0x0057) -+#define NIC_RAMCODE_VERSION_CFG_METHOD_16 (0x0055) -+#define NIC_RAMCODE_VERSION_CFG_METHOD_18 (0x0044) -+#define NIC_RAMCODE_VERSION_CFG_METHOD_20 (0x0044) -+#define NIC_RAMCODE_VERSION_CFG_METHOD_21 (0x0042) -+#define NIC_RAMCODE_VERSION_CFG_METHOD_24 (0x0001) -+#define NIC_RAMCODE_VERSION_CFG_METHOD_23 (0x0015) -+#define NIC_RAMCODE_VERSION_CFG_METHOD_26 (0x0012) -+#define NIC_RAMCODE_VERSION_CFG_METHOD_28 (0x0010) -+#define NIC_RAMCODE_VERSION_CFG_METHOD_29 (0x0018) -+ -+//hwoptimize -+#define HW_PATCH_SAMSUNG_LAN_DONGLE (BIT_2) -+ -+void mdio_write(struct rtl8168_private *tp, u32 RegAddr, u32 value); -+void mdio_prot_write(struct rtl8168_private *tp, u32 RegAddr, u32 value); -+void rtl8168_ephy_write(void __iomem *ioaddr, int RegAddr, int value); -+void mac_ocp_write(struct rtl8168_private *tp, u16 reg_addr, u16 value); -+u16 mac_ocp_read(struct rtl8168_private *tp, u16 reg_addr); -+void ClearEthPhyBit(struct rtl8168_private *tp, u8 addr, u16 mask); -+void SetEthPhyBit(struct rtl8168_private *tp, u8 addr, u16 mask); -+void OCP_write(struct rtl8168_private *tp, u16 addr, u8 len, u32 data); -+void OOB_notify(struct rtl8168_private *tp, u8 cmd); -+void rtl8168_init_ring_indexes(struct rtl8168_private *tp); -+void rtl8168_wait_ll_share_fifo_ready(struct net_device *dev); -+int rtl8168_eri_write(void __iomem *ioaddr, int addr, int len, u32 value, int type); -+void OOB_mutex_lock(struct rtl8168_private *tp); -+u32 mdio_read(struct rtl8168_private *tp, u32 RegAddr); -+u32 OCP_read(struct rtl8168_private *tp, u16 addr, u8 len); -+u32 rtl8168_eri_read(void __iomem *ioaddr, int addr, int len, int type); -+u16 rtl8168_ephy_read(void __iomem *ioaddr, int RegAddr); -+void rtl8168_hw_disable_mac_mcu_bps(struct net_device *dev); -+void rtl8168_wait_txrx_fifo_empty(struct net_device *dev); -+void EnableNowIsOob(struct rtl8168_private *tp); -+void DisableNowIsOob(struct rtl8168_private *tp); -+void OOB_mutex_unlock(struct rtl8168_private *tp); -+void Dash2DisableTx(struct rtl8168_private *tp); -+void Dash2EnableTx(struct rtl8168_private *tp); -+void Dash2DisableRx(struct rtl8168_private *tp); -+void Dash2EnableRx(struct rtl8168_private *tp); -+ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34) -+#define netdev_mc_count(dev) ((dev)->mc_count) -+#define netdev_mc_empty(dev) (netdev_mc_count(dev) == 0) -+#define netdev_for_each_mc_addr(mclist, dev) \ -+ for (mclist = dev->mc_list; mclist; mclist = mclist->next) -+#endif -diff --git a/drivers/net/ethernet/realtek/r8168_asf.c b/drivers/net/ethernet/realtek/r8168_asf.c -new file mode 100755 -index 0000000..ac7e343 ---- /dev/null -+++ b/drivers/net/ethernet/realtek/r8168_asf.c -@@ -0,0 +1,419 @@ -+/* -+################################################################################ -+# -+# r8168 is the Linux device driver released for Realtek Gigabit Ethernet -+# controllers with PCI-Express interface. -+# -+# Copyright(c) 2015 Realtek Semiconductor Corp. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the Free -+# Software Foundation; either version 2 of the License, or (at your option) -+# any later version. -+# -+# This program is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+# more details. -+# -+# You should have received a copy of the GNU General Public License along with -+# this program; if not, see <http://www.gnu.org/licenses/>. -+# -+# Author: -+# Realtek NIC software team <nicfae@realtek.com> -+# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan -+# -+################################################################################ -+*/ -+ -+/************************************************************************************ -+ * This product is covered by one or more of the following patents: -+ * US6,570,884, US6,115,776, and US6,327,625. -+ ***********************************************************************************/ -+ -+#include <linux/module.h> -+#include <linux/version.h> -+#include <linux/pci.h> -+#include <linux/netdevice.h> -+#include <linux/etherdevice.h> -+#include <linux/delay.h> -+#include <linux/ethtool.h> -+#include <linux/mii.h> -+#include <linux/if_vlan.h> -+#include <linux/crc32.h> -+#include <linux/in.h> -+#include <linux/ip.h> -+#include <linux/tcp.h> -+#include <linux/init.h> -+#include <linux/rtnetlink.h> -+ -+#include <asm/uaccess.h> -+ -+#include "r8168.h" -+#include "r8168_asf.h" -+#include "rtl_eeprom.h" -+ -+int rtl8168_asf_ioctl(struct net_device *dev, -+ struct ifreq *ifr) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ void *user_data = ifr->ifr_data; -+ struct asf_ioctl_struct asf_usrdata; -+ -+ if (tp->mcfg != CFG_METHOD_7 && tp->mcfg != CFG_METHOD_8) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&asf_usrdata, user_data, sizeof(struct asf_ioctl_struct))) -+ return -EFAULT; -+ -+ switch (asf_usrdata.offset) { -+ case HBPeriod: -+ rtl8168_asf_hbperiod(ioaddr, asf_usrdata.arg, asf_usrdata.u.data); -+ break; -+ case WD8Timer: -+ break; -+ case WD16Rst: -+ rtl8168_asf_wd16rst(ioaddr, asf_usrdata.arg, asf_usrdata.u.data); -+ break; -+ case WD8Rst: -+ rtl8168_asf_time_period(ioaddr, asf_usrdata.arg, WD8Rst, asf_usrdata.u.data); -+ break; -+ case LSnsrPollCycle: -+ rtl8168_asf_time_period(ioaddr, asf_usrdata.arg, LSnsrPollCycle, asf_usrdata.u.data); -+ break; -+ case ASFSnsrPollPrd: -+ rtl8168_asf_time_period(ioaddr, asf_usrdata.arg, ASFSnsrPollPrd, asf_usrdata.u.data); -+ break; -+ case AlertReSendItvl: -+ rtl8168_asf_time_period(ioaddr, asf_usrdata.arg, AlertReSendItvl, asf_usrdata.u.data); -+ break; -+ case SMBAddr: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, SMBAddr, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case ASFConfigR0: -+ rtl8168_asf_config_regs(ioaddr, asf_usrdata.arg, ASFConfigR0, asf_usrdata.u.data); -+ break; -+ case ASFConfigR1: -+ rtl8168_asf_config_regs(ioaddr, asf_usrdata.arg, ASFConfigR1, asf_usrdata.u.data); -+ break; -+ case ConsoleMA: -+ rtl8168_asf_console_mac(tp, asf_usrdata.arg, asf_usrdata.u.data); -+ break; -+ case ConsoleIP: -+ rtl8168_asf_ip_address(ioaddr, asf_usrdata.arg, ConsoleIP, asf_usrdata.u.data); -+ break; -+ case IPAddr: -+ rtl8168_asf_ip_address(tp, asf_usrdata.arg, IPAddr, asf_usrdata.u.data); -+ break; -+ case UUID: -+ rtl8168_asf_rw_uuid(ioaddr, asf_usrdata.arg, asf_usrdata.u.data); -+ break; -+ case IANA: -+ rtl8168_asf_rw_iana(ioaddr, asf_usrdata.arg, asf_usrdata.u.data); -+ break; -+ case SysID: -+ rtl8168_asf_rw_systemid(ioaddr, asf_usrdata.arg, asf_usrdata.u.data); -+ break; -+ case Community: -+ rtl8168_asf_community_string(ioaddr, asf_usrdata.arg, asf_usrdata.u.string); -+ break; -+ case StringLength: -+ rtl8168_asf_community_string_len(ioaddr, asf_usrdata.arg, asf_usrdata.u.data); -+ break; -+ case FmCapMsk: -+ rtl8168_asf_capability_masks(ioaddr, asf_usrdata.arg, FmCapMsk, asf_usrdata.u.data); -+ break; -+ case SpCMDMsk: -+ rtl8168_asf_capability_masks(ioaddr, asf_usrdata.arg, SpCMDMsk, asf_usrdata.u.data); -+ break; -+ case SysCapMsk: -+ rtl8168_asf_capability_masks(ioaddr, asf_usrdata.arg, SysCapMsk, asf_usrdata.u.data); -+ break; -+ case RmtRstAddr: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtRstAddr, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case RmtRstCmd: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtRstCmd, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case RmtRstData: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtRstData, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case RmtPwrOffAddr: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOffAddr, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case RmtPwrOffCmd: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOffCmd, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case RmtPwrOffData: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOffData, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case RmtPwrOnAddr: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOnAddr, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case RmtPwrOnCmd: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOnCmd, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case RmtPwrOnData: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOnData, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case RmtPCRAddr: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPCRAddr, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case RmtPCRCmd: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPCRCmd, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case RmtPCRData: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPCRData, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case ASFSnsr0Addr: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, ASFSnsr0Addr, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case LSnsrAddr0: -+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, LSnsrAddr0, RW_ONE_BYTE, asf_usrdata.u.data); -+ break; -+ case KO: -+ /* Get/Set Key Operation */ -+ rtl8168_asf_key_access(ioaddr, asf_usrdata.arg, KO, asf_usrdata.u.data); -+ break; -+ case KA: -+ /* Get/Set Key Administrator */ -+ rtl8168_asf_key_access(ioaddr, asf_usrdata.arg, KA, asf_usrdata.u.data); -+ break; -+ case KG: -+ /* Get/Set Key Generation */ -+ rtl8168_asf_key_access(ioaddr, asf_usrdata.arg, KG, asf_usrdata.u.data); -+ break; -+ case KR: -+ /* Get/Set Key Random */ -+ rtl8168_asf_key_access(tp, asf_usrdata.arg, KR, asf_usrdata.u.data); -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ if (copy_to_user(user_data, &asf_usrdata, sizeof(struct asf_ioctl_struct))) -+ return -EFAULT; -+ -+ return 0; -+} -+ -+void rtl8168_asf_hbperiod(void __iomem *ioaddr, int arg, unsigned int *data) -+{ -+ if (arg == ASF_GET) -+ data[ASFHBPERIOD] = rtl8168_eri_read(ioaddr, HBPeriod, RW_TWO_BYTES, ERIAR_ASF); -+ else if (arg == ASF_SET) { -+ rtl8168_eri_write(ioaddr, HBPeriod, RW_TWO_BYTES, data[ASFHBPERIOD], ERIAR_ASF); -+ rtl8168_eri_write(ioaddr, 0x1EC, RW_ONE_BYTE, 0x07, ERIAR_ASF); -+ } -+} -+ -+void rtl8168_asf_wd16rst(void __iomem *ioaddr, int arg, unsigned int *data) -+{ -+ data[ASFWD16RST] = rtl8168_eri_read(ioaddr, WD16Rst, RW_TWO_BYTES, ERIAR_ASF); -+} -+ -+void rtl8168_asf_console_mac(struct rtl8168_private *tp, int arg, unsigned int *data) -+{ -+ void __iomem *ioaddr=tp->mmio_addr; -+ int i; -+ -+ if (arg == ASF_GET) { -+ for (i = 0; i < 6; i++) -+ data[i] = rtl8168_eri_read(ioaddr, ConsoleMA + i, RW_ONE_BYTE, ERIAR_ASF); -+ } else if (arg == ASF_SET) { -+ for (i = 0; i < 6; i++) -+ rtl8168_eri_write(ioaddr, ConsoleMA + i, RW_ONE_BYTE, data[i], ERIAR_ASF); -+ -+ /* write the new console MAC address to EEPROM */ -+ rtl_eeprom_write_sc(tp, 70, (data[1] << 8) | data[0]); -+ rtl_eeprom_write_sc(tp, 71, (data[3] << 8) | data[2]); -+ rtl_eeprom_write_sc(tp, 72, (data[5] << 8) | data[4]); -+ } -+} -+ -+void rtl8168_asf_ip_address(struct rtl8168_private *tp, int arg, int offset, unsigned int *data) -+{ -+ void __iomem *ioaddr=tp->mmio_addr; -+ int i; -+ int eeprom_off = 0; -+ -+ if (arg == ASF_GET) { -+ for (i = 0; i < 4; i++) -+ data[i] = rtl8168_eri_read(ioaddr, offset + i, RW_ONE_BYTE, ERIAR_ASF); -+ } else if (arg == ASF_SET) { -+ for (i = 0; i < 4; i++) -+ rtl8168_eri_write(ioaddr, offset + i, RW_ONE_BYTE, data[i], ERIAR_ASF); -+ -+ if (offset == ConsoleIP) -+ eeprom_off = 73; -+ else if (offset == IPAddr) -+ eeprom_off = 75; -+ -+ /* write the new IP address to EEPROM */ -+ rtl_eeprom_write_sc(tp, eeprom_off, (data[1] << 8) | data[0]); -+ rtl_eeprom_write_sc(tp, eeprom_off + 1, (data[3] << 8) | data[2]); -+ -+ } -+} -+ -+void rtl8168_asf_config_regs(void __iomem *ioaddr, int arg, int offset, unsigned int *data) -+{ -+ unsigned int value; -+ -+ if (arg == ASF_GET) { -+ data[ASFCAPABILITY] = (rtl8168_eri_read(ioaddr, offset, RW_ONE_BYTE, ERIAR_ASF) & data[ASFCONFIG]) ? FUNCTION_ENABLE : FUNCTION_DISABLE; -+ } else if (arg == ASF_SET) { -+ value = rtl8168_eri_read(ioaddr, offset, RW_ONE_BYTE, ERIAR_ASF); -+ -+ if (data[ASFCAPABILITY] == FUNCTION_ENABLE) -+ value |= data[ASFCONFIG]; -+ else if (data[ASFCAPABILITY] == FUNCTION_DISABLE) -+ value &= ~data[ASFCONFIG]; -+ -+ rtl8168_eri_write(ioaddr, offset, RW_ONE_BYTE, value, ERIAR_ASF); -+ } -+} -+ -+void rtl8168_asf_capability_masks(void __iomem *ioaddr, int arg, int offset, unsigned int *data) -+{ -+ unsigned int len, bit_mask; -+ -+ bit_mask = DISABLE_MASK; -+ -+ if (offset == FmCapMsk) { -+ /* System firmware capabilities */ -+ len = RW_FOUR_BYTES; -+ if (data[ASFCAPMASK] == FUNCTION_ENABLE) -+ bit_mask = FMW_CAP_MASK; -+ } else if (offset == SpCMDMsk) { -+ /* Special commands */ -+ len = RW_TWO_BYTES; -+ if (data[ASFCAPMASK] == FUNCTION_ENABLE) -+ bit_mask = SPC_CMD_MASK; -+ } else { -+ /* System capability (offset == SysCapMsk)*/ -+ len = RW_ONE_BYTE; -+ if (data[ASFCAPMASK] == FUNCTION_ENABLE) -+ bit_mask = SYS_CAP_MASK; -+ } -+ -+ if (arg == ASF_GET) -+ data[ASFCAPMASK] = rtl8168_eri_read(ioaddr, offset, len, ERIAR_ASF) ? FUNCTION_ENABLE : FUNCTION_DISABLE; -+ else /* arg == ASF_SET */ -+ rtl8168_eri_write(ioaddr, offset, len, bit_mask, ERIAR_ASF); -+} -+ -+void rtl8168_asf_community_string(void __iomem *ioaddr, int arg, char *string) -+{ -+ int i; -+ -+ if (arg == ASF_GET) { -+ for (i = 0; i < COMMU_STR_MAX_LEN; i++) -+ string[i] = rtl8168_eri_read(ioaddr, Community + i, RW_ONE_BYTE, ERIAR_ASF); -+ } else { /* arg == ASF_SET */ -+ for (i = 0; i < COMMU_STR_MAX_LEN; i++) -+ rtl8168_eri_write(ioaddr, Community + i, RW_ONE_BYTE, string[i], ERIAR_ASF); -+ } -+} -+ -+void rtl8168_asf_community_string_len(void __iomem *ioaddr, int arg, unsigned int *data) -+{ -+ if (arg == ASF_GET) -+ data[ASFCOMMULEN] = rtl8168_eri_read(ioaddr, StringLength, RW_ONE_BYTE, ERIAR_ASF); -+ else /* arg == ASF_SET */ -+ rtl8168_eri_write(ioaddr, StringLength, RW_ONE_BYTE, data[ASFCOMMULEN], ERIAR_ASF); -+} -+ -+void rtl8168_asf_time_period(void __iomem *ioaddr, int arg, int offset, unsigned int *data) -+{ -+ int pos = 0; -+ -+ if (offset == WD8Rst) -+ pos = ASFWD8RESET; -+ else if (offset == LSnsrPollCycle) -+ pos = ASFLSNRPOLLCYC; -+ else if (offset == ASFSnsrPollPrd) -+ pos = ASFSNRPOLLCYC; -+ else if (offset == AlertReSendItvl) -+ pos = ASFALERTRESND; -+ -+ if (arg == ASF_GET) -+ data[pos] = rtl8168_eri_read(ioaddr, offset, RW_ONE_BYTE, ERIAR_ASF); -+ else /* arg == ASF_SET */ -+ rtl8168_eri_write(ioaddr, offset, RW_ONE_BYTE, data[pos], ERIAR_ASF); -+ -+} -+ -+void rtl8168_asf_key_access(struct rtl8168_private *tp, int arg, int offset, unsigned int *data) -+{ -+ void __iomem *ioaddr=tp->mmio_addr; -+ int i, j; -+ int key_off = 0; -+ -+ if (arg == ASF_GET) { -+ for (i = 0; i < KEY_LEN; i++) -+ data[i] = rtl8168_eri_read(ioaddr, offset + KEY_LEN - (i + 1), RW_ONE_BYTE, ERIAR_ASF); -+ } else { -+ if (offset == KO) -+ key_off = 162; -+ else if (offset == KA) -+ key_off = 172; -+ else if (offset == KG) -+ key_off = 182; -+ else if (offset == KR) -+ key_off = 192; -+ -+ /* arg == ASF_SET */ -+ for (i = 0; i < KEY_LEN; i++) -+ rtl8168_eri_write(ioaddr, offset + KEY_LEN - (i + 1), RW_ONE_BYTE, data[i], ERIAR_ASF); -+ -+ /* write the new key to EEPROM */ -+ for (i = 0, j = 19; i < 10; i++, j = j - 2) -+ rtl_eeprom_write_sc(tp, key_off + i, (data[j - 1] << 8) | data[j]); -+ } -+} -+ -+void rtl8168_asf_rw_hexadecimal(void __iomem *ioaddr, int arg, int offset, int len, unsigned int *data) -+{ -+ if (arg == ASF_GET) -+ data[ASFRWHEXNUM] = rtl8168_eri_read(ioaddr, offset, len, ERIAR_ASF); -+ else /* arg == ASF_SET */ -+ rtl8168_eri_write(ioaddr, offset, len, data[ASFRWHEXNUM], ERIAR_ASF); -+} -+ -+void rtl8168_asf_rw_systemid(void __iomem *ioaddr, int arg, unsigned int *data) -+{ -+ int i; -+ -+ if (arg == ASF_GET) -+ for (i = 0; i < SYSID_LEN ; i++) -+ data[i] = rtl8168_eri_read(ioaddr, SysID + i, RW_ONE_BYTE, ERIAR_ASF); -+ else /* arg == ASF_SET */ -+ for (i = 0; i < SYSID_LEN ; i++) -+ rtl8168_eri_write(ioaddr, SysID + i, RW_ONE_BYTE, data[i], ERIAR_ASF); -+} -+ -+void rtl8168_asf_rw_iana(void __iomem *ioaddr, int arg, unsigned int *data) -+{ -+ int i; -+ -+ if (arg == ASF_GET) -+ for (i = 0; i < RW_FOUR_BYTES; i++) -+ data[i] = rtl8168_eri_read(ioaddr, IANA + i, RW_ONE_BYTE, ERIAR_ASF); -+ else /* arg == ASF_SET */ -+ for (i = 0; i < RW_FOUR_BYTES; i++) -+ rtl8168_eri_write(ioaddr, IANA + i, RW_ONE_BYTE, data[i], ERIAR_ASF); -+} -+ -+void rtl8168_asf_rw_uuid(void __iomem *ioaddr, int arg, unsigned int *data) -+{ -+ int i, j; -+ -+ if (arg == ASF_GET) -+ for (i = UUID_LEN - 1, j = 0; i >= 0 ; i--, j++) -+ data[j] = rtl8168_eri_read(ioaddr, UUID + i, RW_ONE_BYTE, ERIAR_ASF); -+ else /* arg == ASF_SET */ -+ for (i = UUID_LEN - 1, j = 0; i >= 0 ; i--, j++) -+ rtl8168_eri_write(ioaddr, UUID + i, RW_ONE_BYTE, data[j], ERIAR_ASF); -+} -diff --git a/drivers/net/ethernet/realtek/r8168_asf.h b/drivers/net/ethernet/realtek/r8168_asf.h -new file mode 100755 -index 0000000..e4097f2 ---- /dev/null -+++ b/drivers/net/ethernet/realtek/r8168_asf.h -@@ -0,0 +1,294 @@ -+/* -+################################################################################ -+# -+# r8168 is the Linux device driver released for Realtek Gigabit Ethernet -+# controllers with PCI-Express interface. -+# -+# Copyright(c) 2015 Realtek Semiconductor Corp. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the Free -+# Software Foundation; either version 2 of the License, or (at your option) -+# any later version. -+# -+# This program is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+# more details. -+# -+# You should have received a copy of the GNU General Public License along with -+# this program; if not, see <http://www.gnu.org/licenses/>. -+# -+# Author: -+# Realtek NIC software team <nicfae@realtek.com> -+# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan -+# -+################################################################################ -+*/ -+ -+/************************************************************************************ -+ * This product is covered by one or more of the following patents: -+ * US6,570,884, US6,115,776, and US6,327,625. -+ ***********************************************************************************/ -+ -+#define SIOCDEVPRIVATE_RTLASF SIOCDEVPRIVATE -+ -+#define FUNCTION_ENABLE 1 -+#define FUNCTION_DISABLE 0 -+ -+#define ASFCONFIG 0 -+#define ASFCAPABILITY 1 -+#define ASFCOMMULEN 0 -+#define ASFHBPERIOD 0 -+#define ASFWD16RST 0 -+#define ASFCAPMASK 0 -+#define ASFALERTRESND 0 -+#define ASFLSNRPOLLCYC 0 -+#define ASFSNRPOLLCYC 0 -+#define ASFWD8RESET 0 -+#define ASFRWHEXNUM 0 -+ -+#define FMW_CAP_MASK 0x0000F867 -+#define SPC_CMD_MASK 0x1F00 -+#define SYS_CAP_MASK 0xFF -+#define DISABLE_MASK 0x00 -+ -+#define MAX_DATA_LEN 200 -+#define MAX_STR_LEN 200 -+ -+#define COMMU_STR_MAX_LEN 23 -+ -+#define KEY_LEN 20 -+#define UUID_LEN 16 -+#define SYSID_LEN 2 -+ -+#define RW_ONE_BYTE 1 -+#define RW_TWO_BYTES 2 -+#define RW_FOUR_BYTES 4 -+ -+enum asf_registers { -+ HBPeriod = 0x0000, -+ WD8Rst = 0x0002, -+ WD8Timer = 0x0003, -+ WD16Rst = 0x0004, -+ LSnsrPollCycle = 0x0006, -+ ASFSnsrPollPrd = 0x0007, -+ AlertReSendCnt = 0x0008, -+ AlertReSendItvl = 0x0009, -+ SMBAddr = 0x000A, -+ SMBCap = 0x000B, -+ ASFConfigR0 = 0x000C, -+ ASFConfigR1 = 0x000D, -+ WD16Timer = 0x000E, -+ ConsoleMA = 0x0010, -+ ConsoleIP = 0x0016, -+ IPAddr = 0x001A, -+ -+ UUID = 0x0020, -+ IANA = 0x0030, -+ SysID = 0x0034, -+ Community = 0x0036, -+ StringLength = 0x004D, -+ LC = 0x004E, -+ EntityInst = 0x004F, -+ FmCapMsk = 0x0050, -+ SpCMDMsk = 0x0054, -+ SysCapMsk = 0x0056, -+ WDSysSt = 0x0057, -+ RxMsgType = 0x0058, -+ RxSpCMD = 0x0059, -+ RxSpCMDPa = 0x005A, -+ RxBtOpMsk = 0x005C, -+ RmtRstAddr = 0x005E, -+ RmtRstCmd = 0x005F, -+ RmtRstData = 0x0060, -+ RmtPwrOffAddr = 0x0061, -+ RmtPwrOffCmd = 0x0062, -+ RmtPwrOffData = 0x0063, -+ RmtPwrOnAddr = 0x0064, -+ RmtPwrOnCmd = 0x0065, -+ RmtPwrOnData = 0x0066, -+ RmtPCRAddr = 0x0067, -+ RmtPCRCmd = 0x0068, -+ RmtPCRData = 0x0069, -+ RMCP_IANA = 0x006A, -+ RMCP_OEM = 0x006E, -+ ASFSnsr0Addr = 0x0070, -+ -+ ASFSnsrEvSt = 0x0073, -+ ASFSnsrEvAlert = 0x0081, -+ -+ LSnsrNo = 0x00AD, -+ AssrtEvntMsk = 0x00AE, -+ DeAssrtEvntMsk = 0x00AF, -+ -+ LSnsrAddr0 = 0x00B0, -+ LAlertCMD0 = 0x00B1, -+ LAlertDataMsk0 = 0x00B2, -+ LAlertCmp0 = 0x00B3, -+ LAlertESnsrT0 = 0x00B4, -+ LAlertET0 = 0x00B5, -+ LAlertEOffset0 = 0x00B6, -+ LAlertES0 = 0x00B7, -+ LAlertSN0 = 0x00B8, -+ LAlertEntity0 = 0x00B9, -+ LAlertEI0 = 0x00BA, -+ LSnsrState0 = 0x00BB, -+ -+ LSnsrAddr1 = 0x00BD, -+ LAlertCMD1 = 0x00BE, -+ LAlertDataMsk1 = 0x00BF, -+ LAlertCmp1 = 0x00C0, -+ LAlertESnsrT1 = 0x00C1, -+ LAlertET1 = 0x00C2, -+ LAlertEOffset1 = 0x00C3, -+ LAlertES1 = 0x00C4, -+ LAlertSN1 = 0x00C5, -+ LAlertEntity1 = 0x00C6, -+ LAlertEI1 = 0x00C7, -+ LSnsrState1 = 0x00C8, -+ -+ LSnsrAddr2 = 0x00CA, -+ LAlertCMD2 = 0x00CB, -+ LAlertDataMsk2 = 0x00CC, -+ LAlertCmp2 = 0x00CD, -+ LAlertESnsrT2 = 0x00CE, -+ LAlertET2 = 0x00CF, -+ LAlertEOffset2 = 0x00D0, -+ LAlertES2 = 0x00D1, -+ LAlertSN2 = 0x00D2, -+ LAlertEntity2 = 0x00D3, -+ LAlertEI2 = 0x00D4, -+ LSnsrState2 = 0x00D5, -+ -+ LSnsrAddr3 = 0x00D7, -+ LAlertCMD3 = 0x00D8, -+ LAlertDataMsk3 = 0x00D9, -+ LAlertCmp3 = 0x00DA, -+ LAlertESnsrT3 = 0x00DB, -+ LAlertET3 = 0x00DC, -+ LAlertEOffset3 = 0x00DD, -+ LAlertES3 = 0x00DE, -+ LAlertSN3 = 0x00DF, -+ LAlertEntity3 = 0x00E0, -+ LAlertEI3 = 0x00E1, -+ LSnsrState3 = 0x00E2, -+ -+ LSnsrAddr4 = 0x00E4, -+ LAlertCMD4 = 0x00E5, -+ LAlertDataMsk4 = 0x00E6, -+ LAlertCmp4 = 0x00E7, -+ LAlertESnsrT4 = 0x00E8, -+ LAlertET4 = 0x00E9, -+ LAlertEOffset4 = 0x00EA, -+ LAlertES4 = 0x00EB, -+ LAlertSN4 = 0x00EC, -+ LAlertEntity4 = 0x00ED, -+ LAlertEI4 = 0x00EE, -+ LSnsrState4 = 0x00EF, -+ -+ LSnsrAddr5 = 0x00F1, -+ LAlertCMD5 = 0x00F2, -+ LAlertDataMsk5 = 0x00F3, -+ LAlertCmp5 = 0x00F4, -+ LAlertESnsrT5 = 0x00F5, -+ LAlertET5 = 0x00F6, -+ LAlertEOffset5 = 0x00F7, -+ LAlertES5 = 0x00F8, -+ LAlertSN5 = 0x00F9, -+ LAlertEntity5 = 0x00FA, -+ LAlertEI5 = 0x00FB, -+ LSnsrState5 = 0x00FC, -+ -+ LSnsrAddr6 = 0x00FE, -+ LAlertCMD6 = 0x00FF, -+ LAlertDataMsk6 = 0x0100, -+ LAlertCmp6 = 0x0101, -+ LAlertESnsrT6 = 0x0102, -+ LAlertET6 = 0x0103, -+ LAlertEOffset6 = 0x0104, -+ LAlertES6 = 0x0105, -+ LAlertSN6 = 0x0106, -+ LAlertEntity6 = 0x0107, -+ LAlertEI6 = 0x0108, -+ LSnsrState6 = 0x0109, -+ -+ LSnsrAddr7 = 0x010B, -+ LAlertCMD7 = 0x010C, -+ LAlertDataMsk7 = 0x010D, -+ LAlertCmp7 = 0x010E, -+ LAlertESnsrT7 = 0x010F, -+ LAlertET7 = 0x0110, -+ LAlertEOffset7 = 0x0111, -+ LAlertES7 = 0x0112, -+ LAlertSN7 = 0x0113, -+ LAlertEntity7 = 0x0114, -+ LAlertEI7 = 0x0115, -+ LSnsrState7 = 0x0116, -+ LAssert = 0x0117, -+ LDAssert = 0x0118, -+ IPServiceType = 0x0119, -+ IPIdfr = 0x011A, -+ FlagFOffset = 0x011C, -+ TTL = 0x011E, -+ HbtEI = 0x011F, -+ MgtConSID1 = 0x0120, -+ MgtConSID2 = 0x0124, -+ MgdCltSID = 0x0128, -+ StCd = 0x012C, -+ MgtConUR = 0x012D, -+ MgtConUNL = 0x012E, -+ -+ AuthPd = 0x0130, -+ IntyPd = 0x0138, -+ MgtConRN = 0x0140, -+ MgdCtlRN = 0x0150, -+ MgtConUN = 0x0160, -+ Rakp2IntCk = 0x0170, -+ KO = 0x017C, -+ KA = 0x0190, -+ KG = 0x01A4, -+ KR = 0x01B8, -+ CP = 0x01CC, -+ CQ = 0x01D0, -+ KC = 0x01D4, -+ ConsoleSid = 0x01E8, -+ -+ SIK1 = 0x01FC, -+ SIK2 = 0x0210, -+ Udpsrc_port = 0x0224, -+ Udpdes_port = 0x0226, -+ Asf_debug_mux = 0x0228 -+}; -+ -+enum asf_cmdln_opt { -+ ASF_GET, -+ ASF_SET, -+ ASF_HELP -+}; -+ -+struct asf_ioctl_struct { -+ unsigned int arg; -+ unsigned int offset; -+ union { -+ unsigned int data[MAX_DATA_LEN]; -+ char string[MAX_STR_LEN]; -+ } u; -+}; -+ -+int rtl8168_asf_ioctl(struct net_device *dev, struct ifreq *ifr); -+void rtl8168_asf_hbperiod(void __iomem *ioaddr, int arg, unsigned int *data); -+void rtl8168_asf_wd16rst(void __iomem *ioaddr, int arg, unsigned int *data); -+void rtl8168_asf_console_mac(struct rtl8168_private *, int arg, unsigned int *data); -+void rtl8168_asf_ip_address(struct rtl8168_private *, int arg, int offset, unsigned int *data); -+void rtl8168_asf_config_regs(void __iomem *ioaddr, int arg, int offset, unsigned int *data); -+void rtl8168_asf_capability_masks(void __iomem *ioaddr, int arg, int offset, unsigned int *data); -+void rtl8168_asf_community_string(void __iomem *ioaddr, int arg, char *string); -+void rtl8168_asf_community_string_len(void __iomem *ioaddr, int arg, unsigned int *data); -+void rtl8168_asf_alert_resend_interval(void __iomem *ioaddr, int arg, unsigned int *data); -+void rtl8168_asf_time_period(void __iomem *ioaddr, int arg, int offset, unsigned int *data); -+void rtl8168_asf_key_access(struct rtl8168_private *, int arg, int offset, unsigned int *data); -+void rtl8168_asf_rw_hexadecimal(void __iomem *ioaddr, int arg, int offset, int len, unsigned int *data); -+void rtl8168_asf_rw_iana(void __iomem *ioaddr, int arg, unsigned int *data); -+void rtl8168_asf_rw_uuid(void __iomem *ioaddr, int arg, unsigned int *data); -+void rtl8168_asf_rw_systemid(void __iomem *ioaddr, int arg, unsigned int *data); -diff --git a/drivers/net/ethernet/realtek/r8168_dash.h b/drivers/net/ethernet/realtek/r8168_dash.h -new file mode 100755 -index 0000000..19fac01 ---- /dev/null -+++ b/drivers/net/ethernet/realtek/r8168_dash.h -@@ -0,0 +1,193 @@ -+/* -+################################################################################ -+# -+# r8168 is the Linux device driver released for Realtek Gigabit Ethernet -+# controllers with PCI-Express interface. -+# -+# Copyright(c) 2015 Realtek Semiconductor Corp. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the Free -+# Software Foundation; either version 2 of the License, or (at your option) -+# any later version. -+# -+# This program is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+# more details. -+# -+# You should have received a copy of the GNU General Public License along with -+# this program; if not, see <http://www.gnu.org/licenses/>. -+# -+# Author: -+# Realtek NIC software team <nicfae@realtek.com> -+# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan -+# -+################################################################################ -+*/ -+ -+/************************************************************************************ -+ * This product is covered by one or more of the following patents: -+ * US6,570,884, US6,115,776, and US6,327,625. -+ ***********************************************************************************/ -+ -+#ifndef _LINUX_R8168_DASH_H -+#define _LINUX_R8168_DASH_H -+ -+#define SIOCDEVPRIVATE_RTLDASH SIOCDEVPRIVATE+2 -+ -+enum rtl_dash_cmd { -+ -+ RTL_DASH_ARP_NS_OFFLOAD=0, -+ RTL_DASH_SET_OOB_IPMAC, -+ RTL_DASH_NOTIFY_OOB, -+ -+ RTL_DASH_SEND_BUFFER_DATA_TO_DASH_FW, -+ RTL_DASH_CHECK_SEND_BUFFER_TO_DASH_FW_COMPLETE, -+ RTL_DASH_GET_RCV_FROM_FW_BUFFER_DATA, -+ -+ RTLT_DASH_COMMAND_INVALID -+}; -+ -+struct rtl_dash_ip_mac { -+ struct sockaddr ifru_addr; -+ struct sockaddr ifru_netmask; -+ struct sockaddr ifru_hwaddr; -+}; -+ -+struct rtl_dash_ioctl_struct { -+ __u32 cmd; -+ __u32 offset; -+ __u32 len; -+ union { -+ __u32 data; -+ void *data_buffer; -+ }; -+}; -+ -+typedef struct _RX_DASH_FROM_FW_DESC { -+ u16 length; -+ u8 statusLowByte; -+ u8 statusHighByte; -+ u32 resv; -+ u64 BufferAddress; -+} -+RX_DASH_FROM_FW_DESC, *PRX_DASH_FROM_FW_DESC; -+ -+typedef struct _TX_DASH_SEND_FW_DESC { -+ u16 length; -+ u8 statusLowByte; -+ u8 statusHighByte; -+ u32 resv; -+ u64 BufferAddress; -+} -+TX_DASH_SEND_FW_DESC, *PTX_DASH_SEND_FW_DESC; -+ -+typedef struct _OSOOBHdr { -+ u32 len; -+ u8 type; -+ u8 flag; -+ u8 hostReqV; -+ u8 res; -+} -+OSOOBHdr, *POSOOBHdr; -+ -+typedef struct _RX_DASH_BUFFER_TYPE_2 { -+ OSOOBHdr oobhdr; -+ void *RxDataBuffer; -+} -+RX_DASH_BUFFER_TYPE_2, *PRX_DASH_BUFFER_TYPE_2; -+ -+#define ALIGN_8 (0x7) -+#define ALIGN_16 (0xf) -+#define ALIGN_32 (0x1f) -+#define ALIGN_64 (0x3f) -+#define ALIGN_256 (0xff) -+#define ALIGN_4096 (0xfff) -+ -+#define OCP_REG_CONFIG0 (0x10) -+#define OCP_REG_CONFIG0_REV_F (0xB8) -+#define OCP_REG_DASH_POLL (0x30) -+#define OCP_REG_HOST_REQ (0x34) -+#define OCP_REG_DASH_REQ (0x35) -+#define OCP_REG_CR (0x36) -+#define OCP_REG_DMEMSTA (0x38) -+#define OCP_REG_GPHYAR (0x60) -+ -+ -+#define OCP_REG_CONFIG0_DASHEN BIT_15 -+#define OCP_REG_CONFIG0_OOBRESET BIT_14 -+#define OCP_REG_CONFIG0_APRDY BIT_13 -+#define OCP_REG_CONFIG0_FIRMWARERDY BIT_12 -+#define OCP_REG_CONFIG0_DRIVERRDY BIT_11 -+#define OCP_REG_CONFIG0_OOB_WDT BIT_9 -+#define OCP_REG_CONFIG0_DRV_WAIT_OOB BIT_8 -+#define OCP_REG_CONFIG0_TLSEN BIT_7 -+ -+#define HW_DASH_SUPPORT_DASH(_M) ((_M)->HwSuppDashVer > 0 ) -+#define HW_DASH_SUPPORT_TYPE_1(_M) ((_M)->HwSuppDashVer == 1 ) -+#define HW_DASH_SUPPORT_TYPE_2(_M) ((_M)->HwSuppDashVer == 2 ) -+ -+#define RECV_FROM_FW_BUF_SIZE (1518) -+#define SEND_TO_FW_BUF_SIZE (1518) -+ -+#define RX_DASH_FROM_FW_OWN BIT_15 -+#define TX_DASH_SEND_FW_OWN BIT_15 -+#define TX_DASH_SEND_FW_OWN_HIGHBYTE BIT_7 -+ -+#define TXS_CC3_0 (BIT_0|BIT_1|BIT_2|BIT_3) -+#define TXS_EXC BIT_4 -+#define TXS_LNKF BIT_5 -+#define TXS_OWC BIT_6 -+#define TXS_TES BIT_7 -+#define TXS_UNF BIT_9 -+#define TXS_LGSEN BIT_11 -+#define TXS_LS BIT_12 -+#define TXS_FS BIT_13 -+#define TXS_EOR BIT_14 -+#define TXS_OWN BIT_15 -+ -+#define TPPool_HRDY 0x20 -+ -+#define HostReqReg (0xC0) -+#define SystemMasterDescStartAddrLow (0xF0) -+#define SystemMasterDescStartAddrHigh (0xF4) -+#define SystemSlaveDescStartAddrLow (0xF8) -+#define SystemSlaveDescStartAddrHigh (0xFC) -+ -+//DASH Request Type -+#define WSMANREG 0x01 -+#define OSPUSHDATA 0x02 -+ -+#define RXS_OWN BIT_15 -+#define RXS_EOR BIT_14 -+#define RXS_FS BIT_13 -+#define RXS_LS BIT_12 -+ -+#define ISRIMR_DP_DASH_OK BIT_15 -+#define ISRIMR_DP_HOST_OK BIT_13 -+#define ISRIMR_DP_REQSYS_OK BIT_11 -+ -+#define ISRIMR_DASH_INTR_EN BIT_12 -+#define ISRIMR_DASH_INTR_CMAC_RESET BIT_15 -+ -+#define ISRIMR_DASH_TYPE2_ROK BIT_0 -+#define ISRIMR_DASH_TYPE2_RDU BIT_1 -+#define ISRIMR_DASH_TYPE2_TOK BIT_2 -+#define ISRIMR_DASH_TYPE2_TDU BIT_3 -+#define ISRIMR_DASH_TYPE2_TX_FIFO_FULL BIT_4 -+#define ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE BIT_5 -+#define ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE BIT_6 -+ -+#define CMAC_OOB_STOP 0x25 -+#define CMAC_OOB_INIT 0x26 -+#define CMAC_OOB_RESET 0x2a -+ -+int rtl8168_dash_ioctl(struct net_device *dev, struct ifreq *ifr); -+void HandleDashInterrupt(struct net_device *dev); -+int AllocateDashShareMemory(struct net_device *dev); -+void FreeAllocatedDashShareMemory(struct net_device *dev); -+void DashHwInit(struct net_device *dev); -+ -+ -+#endif /* _LINUX_R8168_DASH_H */ -\ No newline at end of file -diff --git a/drivers/net/ethernet/realtek/r8168_n.c b/drivers/net/ethernet/realtek/r8168_n.c -new file mode 100755 -index 0000000..8b08e63 ---- /dev/null -+++ b/drivers/net/ethernet/realtek/r8168_n.c -@@ -0,0 +1,25364 @@ -+/* -+################################################################################ -+# -+# r8168 is the Linux device driver released for Realtek Gigabit Ethernet -+# controllers with PCI-Express interface. -+# -+# Copyright(c) 2015 Realtek Semiconductor Corp. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the Free -+# Software Foundation; either version 2 of the License, or (at your option) -+# any later version. -+# -+# This program is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+# more details. -+# -+# You should have received a copy of the GNU General Public License along with -+# this program; if not, see <http://www.gnu.org/licenses/>. -+# -+# Author: -+# Realtek NIC software team <nicfae@realtek.com> -+# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan -+# -+################################################################################ -+*/ -+ -+/************************************************************************************ -+ * This product is covered by one or more of the following patents: -+ * US6,570,884, US6,115,776, and US6,327,625. -+ ***********************************************************************************/ -+ -+/* -+ * This driver is modified from r8169.c in Linux kernel 2.6.18 -+ */ -+ -+#include <linux/module.h> -+#include <linux/version.h> -+#include <linux/pci.h> -+#include <linux/netdevice.h> -+#include <linux/etherdevice.h> -+#include <linux/delay.h> -+#include <linux/ethtool.h> -+#include <linux/mii.h> -+#include <linux/if_vlan.h> -+#include <linux/crc32.h> -+#include <linux/interrupt.h> -+#include <linux/in.h> -+#include <linux/ip.h> -+#include <linux/tcp.h> -+#include <linux/init.h> -+#include <linux/rtnetlink.h> -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) -+#include <linux/pci-aspm.h> -+#endif -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37) -+#include <linux/prefetch.h> -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define dev_printk(A,B,fmt,args...) printk(A fmt,##args) -+#else -+#include <linux/dma-mapping.h> -+#include <linux/moduleparam.h> -+#endif -+ -+#include <asm/io.h> -+#include <asm/irq.h> -+#include <asm/uaccess.h> -+ -+#include "r8168.h" -+#include "r8168_asf.h" -+#include "rtl_eeprom.h" -+#include "rtltool.h" -+ -+#ifdef ENABLE_R8168_PROCFS -+#include <linux/proc_fs.h> -+#include <linux/seq_file.h> -+#endif -+ -+/* Maximum events (Rx packets, etc.) to handle at each interrupt. */ -+static const int max_interrupt_work = 20; -+ -+/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). -+ The RTL chips use a 64 element hash table based on the Ethernet CRC. */ -+static const int multicast_filter_limit = 32; -+ -+#define _R(NAME,MAC,RCR,MASK, JumFrameSz) \ -+ { .name = NAME, .mcfg = MAC, .RCR_Cfg = RCR, .RxConfigMask = MASK, .jumbo_frame_sz = JumFrameSz } -+ -+static const struct { -+ const char *name; -+ u8 mcfg; -+ u32 RCR_Cfg; -+ u32 RxConfigMask; /* Clears the bits supported by this chip */ -+ u32 jumbo_frame_sz; -+} rtl_chip_info[] = { -+ _R("RTL8168B/8111B", -+ CFG_METHOD_1, -+ (Reserved2_data << Reserved2_shift) | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_4k), -+ -+ _R("RTL8168B/8111B", -+ CFG_METHOD_2, -+ (Reserved2_data << Reserved2_shift) | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_4k), -+ -+ _R("RTL8168B/8111B", -+ CFG_METHOD_3, -+ (Reserved2_data << Reserved2_shift) | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_4k), -+ -+ _R("RTL8168C/8111C", -+ CFG_METHOD_4, -+ RxCfg_128_int_en | RxCfg_fet_multi_en | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_6k), -+ -+ _R("RTL8168C/8111C", -+ CFG_METHOD_5, -+ RxCfg_128_int_en | RxCfg_fet_multi_en | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_6k), -+ -+ _R("RTL8168C/8111C", -+ CFG_METHOD_6, -+ RxCfg_128_int_en | RxCfg_fet_multi_en | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_6k), -+ -+ _R("RTL8168CP/8111CP", -+ CFG_METHOD_7, -+ RxCfg_128_int_en | RxCfg_fet_multi_en | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_6k), -+ -+ _R("RTL8168CP/8111CP", -+ CFG_METHOD_8, -+ RxCfg_128_int_en | RxCfg_fet_multi_en | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_6k), -+ -+ _R("RTL8168D/8111D", -+ CFG_METHOD_9, -+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168D/8111D", -+ CFG_METHOD_10, -+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168DP/8111DP", -+ CFG_METHOD_11, -+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168DP/8111DP", -+ CFG_METHOD_12, -+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168DP/8111DP", -+ CFG_METHOD_13, -+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168E/8111E", -+ CFG_METHOD_14, -+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168E/8111E", -+ CFG_METHOD_15, -+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168E-VL/8111E-VL", -+ CFG_METHOD_16, -+ RxCfg_128_int_en | RxEarly_off_V1 | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e0080, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168E-VL/8111E-VL", -+ CFG_METHOD_17, -+ RxCfg_128_int_en | RxEarly_off_V1 | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168F/8111F", -+ CFG_METHOD_18, -+ RxCfg_128_int_en | RxEarly_off_V1 | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168F/8111F", -+ CFG_METHOD_19, -+ RxCfg_128_int_en | RxEarly_off_V1 | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8411", -+ CFG_METHOD_20, -+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e1880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168G/8111G", -+ CFG_METHOD_21, -+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e5880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168G/8111G", -+ CFG_METHOD_22, -+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e5880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168EP/8111EP", -+ CFG_METHOD_23, -+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e5880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168GU/8111GU", -+ CFG_METHOD_24, -+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e5880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168GU/8111GU", -+ CFG_METHOD_25, -+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e5880, -+ Jumbo_Frame_9k), -+ -+ _R("8411B", -+ CFG_METHOD_26, -+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e5880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168EP/8111EP", -+ CFG_METHOD_27, -+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e5880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168EP/8111EP", -+ CFG_METHOD_28, -+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e5880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168H/8111H", -+ CFG_METHOD_29, -+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e5880, -+ Jumbo_Frame_9k), -+ -+ _R("RTL8168H/8111H", -+ CFG_METHOD_30, -+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e5880, -+ Jumbo_Frame_9k), -+ -+ _R("Unknown", -+ CFG_METHOD_DEFAULT, -+ (RX_DMA_BURST << RxCfgDMAShift), -+ 0xff7e5880, -+ RX_BUF_SIZE) -+}; -+#undef _R -+ -+#ifndef PCI_VENDOR_ID_DLINK -+#define PCI_VENDOR_ID_DLINK 0x1186 -+#endif -+ -+static struct pci_device_id rtl8168_pci_tbl[] = { -+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), }, -+ { PCI_VENDOR_ID_DLINK, 0x4300, 0x1186, 0x4b10,}, -+ {0,}, -+}; -+ -+MODULE_DEVICE_TABLE(pci, rtl8168_pci_tbl); -+ -+static int rx_copybreak = 200; -+static int timer_count = 0x2600; -+ -+static struct { -+ u32 msg_enable; -+} debug = { -1 }; -+ -+static unsigned short speed = SPEED_1000; -+static int duplex = DUPLEX_FULL; -+static int autoneg = AUTONEG_ENABLE; -+#ifdef CONFIG_ASPM -+static int aspm = 1; -+#else -+static int aspm = 0; -+#endif -+#ifdef ENABLE_S5WOL -+static int s5wol = 1; -+#else -+static int s5wol = 0; -+#endif -+#ifdef ENABLE_EEE -+static int eee_enable = 1; -+#else -+static int eee_enable = 0; -+#endif -+static ulong hwoptimize = 0; -+ -+MODULE_AUTHOR("Realtek and the Linux r8168 crew <netdev@vger.kernel.org>"); -+MODULE_DESCRIPTION("RealTek RTL-8168 Gigabit Ethernet driver"); -+ -+module_param(speed, ushort, 0); -+MODULE_PARM_DESC(speed, "force phy operation. Deprecated by ethtool (8)."); -+ -+module_param(duplex, int, 0); -+MODULE_PARM_DESC(duplex, "force phy operation. Deprecated by ethtool (8)."); -+ -+module_param(autoneg, int, 0); -+MODULE_PARM_DESC(autoneg, "force phy operation. Deprecated by ethtool (8)."); -+ -+module_param(aspm, int, 0); -+MODULE_PARM_DESC(aspm, "Enable ASPM."); -+ -+module_param(s5wol, int, 0); -+MODULE_PARM_DESC(s5wol, "Enable Shutdown Wake On Lan."); -+ -+module_param(rx_copybreak, int, 0); -+MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); -+ -+module_param(timer_count, int, 0); -+MODULE_PARM_DESC(timer_count, "Timer Interrupt Interval."); -+ -+module_param(eee_enable, int, 0); -+MODULE_PARM_DESC(eee_enable, "Enable Energy Efficient Ethernet."); -+ -+module_param(hwoptimize, ulong, 0); -+MODULE_PARM_DESC(hwoptimize, "Enable HW optimization function."); -+ -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+module_param_named(debug, debug.msg_enable, int, 0); -+MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); -+#endif//LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ -+MODULE_LICENSE("GPL"); -+ -+MODULE_VERSION(RTL8168_VERSION); -+ -+static void rtl8168_sleep_rx_enable(struct net_device *dev); -+static void rtl8168_dsm(struct net_device *dev, int dev_state); -+ -+static void rtl8168_esd_timer(unsigned long __opaque); -+static void rtl8168_link_timer(unsigned long __opaque); -+static void rtl8168_tx_clear(struct rtl8168_private *tp); -+static void rtl8168_rx_clear(struct rtl8168_private *tp); -+ -+static int rtl8168_open(struct net_device *dev); -+static int rtl8168_start_xmit(struct sk_buff *skb, struct net_device *dev); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+static irqreturn_t rtl8168_interrupt(int irq, void *dev_instance, struct pt_regs *regs); -+#else -+static irqreturn_t rtl8168_interrupt(int irq, void *dev_instance); -+#endif -+static void rtl8168_rx_desc_offset0_init(struct rtl8168_private *, int); -+static int rtl8168_init_ring(struct net_device *dev); -+static void rtl8168_hw_config(struct net_device *dev); -+static void rtl8168_hw_start(struct net_device *dev); -+static int rtl8168_close(struct net_device *dev); -+static void rtl8168_set_rx_mode(struct net_device *dev); -+static void rtl8168_tx_timeout(struct net_device *dev); -+static struct net_device_stats *rtl8168_get_stats(struct net_device *dev); -+static int rtl8168_rx_interrupt(struct net_device *, struct rtl8168_private *, void __iomem *, u32 budget); -+static int rtl8168_change_mtu(struct net_device *dev, int new_mtu); -+static void rtl8168_down(struct net_device *dev); -+ -+static int rtl8168_set_mac_address(struct net_device *dev, void *p); -+void rtl8168_rar_set(struct rtl8168_private *tp, uint8_t *addr); -+static void rtl8168_desc_addr_fill(struct rtl8168_private *); -+static void rtl8168_tx_desc_init(struct rtl8168_private *tp); -+static void rtl8168_rx_desc_init(struct rtl8168_private *tp); -+ -+static void rtl8168_hw_reset(struct net_device *dev); -+ -+static void rtl8168_phy_power_up(struct net_device *dev); -+static void rtl8168_phy_power_down(struct net_device *dev); -+static int rtl8168_set_speed(struct net_device *dev, u8 autoneg, u16 speed, u8 duplex); -+ -+#ifdef CONFIG_R8168_NAPI -+static int rtl8168_poll(napi_ptr napi, napi_budget budget); -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#undef ethtool_ops -+#define ethtool_ops _kc_ethtool_ops -+ -+struct _kc_ethtool_ops { -+ int (*get_settings)(struct net_device *, struct ethtool_cmd *); -+ int (*set_settings)(struct net_device *, struct ethtool_cmd *); -+ void (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *); -+ int (*get_regs_len)(struct net_device *); -+ void (*get_regs)(struct net_device *, struct ethtool_regs *, void *); -+ void (*get_wol)(struct net_device *, struct ethtool_wolinfo *); -+ int (*set_wol)(struct net_device *, struct ethtool_wolinfo *); -+ u32 (*get_msglevel)(struct net_device *); -+ void (*set_msglevel)(struct net_device *, u32); -+ int (*nway_reset)(struct net_device *); -+ u32 (*get_link)(struct net_device *); -+ int (*get_eeprom_len)(struct net_device *); -+ int (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); -+ int (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); -+ int (*get_coalesce)(struct net_device *, struct ethtool_coalesce *); -+ int (*set_coalesce)(struct net_device *, struct ethtool_coalesce *); -+ void (*get_ringparam)(struct net_device *, struct ethtool_ringparam *); -+ int (*set_ringparam)(struct net_device *, struct ethtool_ringparam *); -+ void (*get_pauseparam)(struct net_device *, -+ struct ethtool_pauseparam*); -+ int (*set_pauseparam)(struct net_device *, -+ struct ethtool_pauseparam*); -+ u32 (*get_rx_csum)(struct net_device *); -+ int (*set_rx_csum)(struct net_device *, u32); -+ u32 (*get_tx_csum)(struct net_device *); -+ int (*set_tx_csum)(struct net_device *, u32); -+ u32 (*get_sg)(struct net_device *); -+ int (*set_sg)(struct net_device *, u32); -+ u32 (*get_tso)(struct net_device *); -+ int (*set_tso)(struct net_device *, u32); -+ int (*self_test_count)(struct net_device *); -+ void (*self_test)(struct net_device *, struct ethtool_test *, u64 *); -+ void (*get_strings)(struct net_device *, u32 stringset, u8 *); -+ int (*phys_id)(struct net_device *, u32); -+ int (*get_stats_count)(struct net_device *); -+ void (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, -+ u64 *); -+} *ethtool_ops = NULL; -+ -+#undef SET_ETHTOOL_OPS -+#define SET_ETHTOOL_OPS(netdev, ops) (ethtool_ops = (ops)) -+ -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0) -+#ifndef SET_ETHTOOL_OPS -+#define SET_ETHTOOL_OPS(netdev,ops) \ -+ ( (netdev)->ethtool_ops = (ops) ) -+#endif //SET_ETHTOOL_OPS -+#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0) -+ -+//#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) -+#ifndef netif_msg_init -+#define netif_msg_init _kc_netif_msg_init -+/* copied from linux kernel 2.6.20 include/linux/netdevice.h */ -+static inline u32 netif_msg_init(int debug_value, int default_msg_enable_bits) -+{ -+ /* use default */ -+ if (debug_value < 0 || debug_value >= (sizeof(u32) * 8)) -+ return default_msg_enable_bits; -+ if (debug_value == 0) /* no output */ -+ return 0; -+ /* set low N bits */ -+ return (1 << debug_value) - 1; -+} -+ -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) -+ -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22) -+static inline void eth_copy_and_sum (struct sk_buff *dest, -+ const unsigned char *src, -+ int len, int base) -+{ -+ memcpy (dest->data, src, len); -+} -+#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) -+/* copied from linux kernel 2.6.20 /include/linux/time.h */ -+/* Parameters used to convert the timespec values: */ -+#define MSEC_PER_SEC 1000L -+ -+/* copied from linux kernel 2.6.20 /include/linux/jiffies.h */ -+/* -+ * Change timeval to jiffies, trying to avoid the -+ * most obvious overflows.. -+ * -+ * And some not so obvious. -+ * -+ * Note that we don't want to return MAX_LONG, because -+ * for various timeout reasons we often end up having -+ * to wait "jiffies+1" in order to guarantee that we wait -+ * at _least_ "jiffies" - so "jiffies+1" had better still -+ * be positive. -+ */ -+#define MAX_JIFFY_OFFSET ((~0UL >> 1)-1) -+ -+/* -+ * Convert jiffies to milliseconds and back. -+ * -+ * Avoid unnecessary multiplications/divisions in the -+ * two most common HZ cases: -+ */ -+static inline unsigned int _kc_jiffies_to_msecs(const unsigned long j) -+{ -+#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) -+ return (MSEC_PER_SEC / HZ) * j; -+#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) -+ return (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC); -+#else -+ return (j * MSEC_PER_SEC) / HZ; -+#endif -+} -+ -+static inline unsigned long _kc_msecs_to_jiffies(const unsigned int m) -+{ -+ if (m > _kc_jiffies_to_msecs(MAX_JIFFY_OFFSET)) -+ return MAX_JIFFY_OFFSET; -+#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) -+ return (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ); -+#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) -+ return m * (HZ / MSEC_PER_SEC); -+#else -+ return (m * HZ + MSEC_PER_SEC - 1) / MSEC_PER_SEC; -+#endif -+} -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) -+ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) -+ -+/* copied from linux kernel 2.6.12.6 /include/linux/pm.h */ -+typedef int __bitwise pci_power_t; -+ -+/* copied from linux kernel 2.6.12.6 /include/linux/pci.h */ -+typedef u32 __bitwise pm_message_t; -+ -+#define PCI_D0 ((pci_power_t __force) 0) -+#define PCI_D1 ((pci_power_t __force) 1) -+#define PCI_D2 ((pci_power_t __force) 2) -+#define PCI_D3hot ((pci_power_t __force) 3) -+#define PCI_D3cold ((pci_power_t __force) 4) -+#define PCI_POWER_ERROR ((pci_power_t __force) -1) -+ -+/* copied from linux kernel 2.6.12.6 /drivers/pci/pci.c */ -+/** -+ * pci_choose_state - Choose the power state of a PCI device -+ * @dev: PCI device to be suspended -+ * @state: target sleep state for the whole system. This is the value -+ * that is passed to suspend() function. -+ * -+ * Returns PCI power state suitable for given device and given system -+ * message. -+ */ -+ -+pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) -+{ -+ if (!pci_find_capability(dev, PCI_CAP_ID_PM)) -+ return PCI_D0; -+ -+ switch (state) { -+ case 0: -+ return PCI_D0; -+ case 3: -+ return PCI_D3hot; -+ default: -+ printk("They asked me for state %d\n", state); -+// BUG(); -+ } -+ return PCI_D0; -+} -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9) -+/** -+ * msleep_interruptible - sleep waiting for waitqueue interruptions -+ * @msecs: Time in milliseconds to sleep for -+ */ -+#define msleep_interruptible _kc_msleep_interruptible -+unsigned long _kc_msleep_interruptible(unsigned int msecs) -+{ -+ unsigned long timeout = _kc_msecs_to_jiffies(msecs); -+ -+ while (timeout && !signal_pending(current)) { -+ set_current_state(TASK_INTERRUPTIBLE); -+ timeout = schedule_timeout(timeout); -+ } -+ return _kc_jiffies_to_msecs(timeout); -+} -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) -+/* copied from linux kernel 2.6.20 include/linux/sched.h */ -+#ifndef __sched -+#define __sched __attribute__((__section__(".sched.text"))) -+#endif -+ -+/* copied from linux kernel 2.6.20 kernel/timer.c */ -+signed long __sched schedule_timeout_uninterruptible(signed long timeout) -+{ -+ __set_current_state(TASK_UNINTERRUPTIBLE); -+ return schedule_timeout(timeout); -+} -+ -+/* copied from linux kernel 2.6.20 include/linux/mii.h */ -+#undef if_mii -+#define if_mii _kc_if_mii -+static inline struct mii_ioctl_data *if_mii(struct ifreq *rq) -+{ -+ return (struct mii_ioctl_data *) &rq->ifr_ifru; -+} -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) -+ -+static const char rtl8168_gstrings[][ETH_GSTRING_LEN] = { -+ "tx_packets", -+ "rx_packets", -+ "tx_errors", -+ "rx_errors", -+ "rx_missed", -+ "align_errors", -+ "tx_single_collisions", -+ "tx_multi_collisions", -+ "unicast", -+ "broadcast", -+ "multicast", -+ "tx_aborted", -+ "tx_underrun", -+}; -+ -+struct rtl8168_counters { -+ u64 tx_packets; -+ u64 rx_packets; -+ u64 tx_errors; -+ u32 rx_errors; -+ u16 rx_missed; -+ u16 align_errors; -+ u32 tx_one_collision; -+ u32 tx_multi_collision; -+ u64 rx_unicast; -+ u64 rx_broadcast; -+ u32 rx_multicast; -+ u16 tx_aborted; -+ u16 tx_underun; -+}; -+ -+#ifdef ENABLE_R8168_PROCFS -+/**************************************************************************** -+* -----------------------------PROCFS STUFF------------------------- -+***************************************************************************** -+*/ -+ -+static struct proc_dir_entry *rtl8168_proc; -+static int proc_init_num = 0; -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) -+static int proc_get_driver_variable(struct seq_file *m, void *v) -+{ -+ struct net_device *dev = m->private; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned long flags; -+ -+ seq_puts(m, "\nDump Driver Variable\n"); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ seq_puts(m, "Variable\tValue\n----------\t-----\n"); -+ seq_printf(m, "MODULENAME\t%s\n", MODULENAME); -+ seq_printf(m, "driver version\t%s\n", RTL8168_VERSION); -+ seq_printf(m, "chipset\t%d\n", tp->chipset); -+ seq_printf(m, "chipset_name\t%s\n", rtl_chip_info[tp->chipset].name); -+ seq_printf(m, "mtu\t%d\n", dev->mtu); -+ seq_printf(m, "NUM_RX_DESC\t0x%x\n", NUM_RX_DESC); -+ seq_printf(m, "cur_rx\t0x%x\n", tp->cur_rx); -+ seq_printf(m, "dirty_rx\t0x%x\n", tp->dirty_rx); -+ seq_printf(m, "NUM_TX_DESC\t0x%x\n", NUM_TX_DESC); -+ seq_printf(m, "cur_tx\t0x%x\n", tp->cur_tx); -+ seq_printf(m, "dirty_tx\t0x%x\n", tp->dirty_tx); -+ seq_printf(m, "rx_buf_sz\t0x%x\n", tp->rx_buf_sz); -+ seq_printf(m, "esd_flag\t0x%x\n", tp->esd_flag); -+ seq_printf(m, "pci_cfg_is_read\t0x%x\n", tp->pci_cfg_is_read); -+ seq_printf(m, "rtl8168_rx_config\t0x%x\n", tp->rtl8168_rx_config); -+ seq_printf(m, "cp_cmd\t0x%x\n", tp->cp_cmd); -+ seq_printf(m, "intr_mask\t0x%x\n", tp->intr_mask); -+ seq_printf(m, "timer_intr_mask\t0x%x\n", tp->timer_intr_mask); -+ seq_printf(m, "wol_enabled\t0x%x\n", tp->wol_enabled); -+ seq_printf(m, "wol_opts\t0x%x\n", tp->wol_opts); -+ seq_printf(m, "efuse_ver\t0x%x\n", tp->efuse_ver); -+ seq_printf(m, "eeprom_type\t0x%x\n", tp->eeprom_type); -+ seq_printf(m, "autoneg\t0x%x\n", tp->autoneg); -+ seq_printf(m, "duplex\t0x%x\n", tp->duplex); -+ seq_printf(m, "speed\t%d\n", tp->speed); -+ seq_printf(m, "eeprom_len\t0x%x\n", tp->eeprom_len); -+ seq_printf(m, "cur_page\t0x%x\n", tp->cur_page); -+ seq_printf(m, "bios_setting\t0x%x\n", tp->bios_setting); -+ seq_printf(m, "features\t0x%x\n", tp->features); -+ seq_printf(m, "org_pci_offset_99\t0x%x\n", tp->org_pci_offset_99); -+ seq_printf(m, "org_pci_offset_180\t0x%x\n", tp->org_pci_offset_180); -+ seq_printf(m, "issue_offset_99_event\t0x%x\n", tp->issue_offset_99_event); -+ seq_printf(m, "org_pci_offset_80\t0x%x\n", tp->org_pci_offset_80); -+ seq_printf(m, "org_pci_offset_81\t0x%x\n", tp->org_pci_offset_81); -+ seq_printf(m, "use_timer_interrrupt\t0x%x\n", tp->use_timer_interrrupt); -+ seq_printf(m, "HwIcVerUnknown\t0x%x\n", tp->HwIcVerUnknown); -+ seq_printf(m, "NotWrRamCodeToMicroP\t0x%x\n", tp->NotWrRamCodeToMicroP); -+ seq_printf(m, "NotWrMcuPatchCode\t0x%x\n", tp->NotWrMcuPatchCode); -+ seq_printf(m, "HwHasWrRamCodeToMicroP\t0x%x\n", tp->HwHasWrRamCodeToMicroP); -+ seq_printf(m, "sw_ram_code_ver\t0x%x\n", tp->sw_ram_code_ver); -+ seq_printf(m, "hw_ram_code_ver\t0x%x\n", tp->hw_ram_code_ver); -+ seq_printf(m, "rtk_enable_diag\t0x%x\n", tp->rtk_enable_diag); -+ seq_printf(m, "ShortPacketSwChecksum\t0x%x\n", tp->ShortPacketSwChecksum); -+ seq_printf(m, "UseSwPaddingShortPkt\t0x%x\n", tp->UseSwPaddingShortPkt); -+ seq_printf(m, "RequireAdcBiasPatch\t0x%x\n", tp->RequireAdcBiasPatch); -+ seq_printf(m, "AdcBiasPatchIoffset\t0x%x\n", tp->AdcBiasPatchIoffset); -+ seq_printf(m, "RequireAdjustUpsTxLinkPulseTiming\t0x%x\n", tp->RequireAdjustUpsTxLinkPulseTiming); -+ seq_printf(m, "SwrCnt1msIni\t0x%x\n", tp->SwrCnt1msIni); -+ seq_printf(m, "HwSuppNowIsOobVer\t0x%x\n", tp->HwSuppNowIsOobVer); -+ seq_printf(m, "RequiredSecLanDonglePatch\t0x%x\n", tp->RequiredSecLanDonglePatch); -+ seq_printf(m, "HwSuppDashVer\t0x%x\n", tp->HwSuppDashVer); -+ seq_printf(m, "DASH\t0x%x\n", tp->DASH); -+ seq_printf(m, "HwSuppKCPOffloadVer\t0x%x\n", tp->HwSuppKCPOffloadVer); -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ seq_putc(m, '\n'); -+ return 0; -+} -+ -+static int proc_get_tally_counter(struct seq_file *m, void *v) -+{ -+ struct net_device *dev = m->private; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ struct rtl8168_counters *counters; -+ dma_addr_t paddr; -+ u32 cmd; -+ u32 WaitCnt; -+ unsigned long flags; -+ -+ seq_puts(m, "\nDump Tally Counter\n"); -+ -+ ASSERT_RTNL(); -+ -+ counters = tp->tally_vaddr; -+ paddr = tp->tally_paddr; -+ if (!counters) { -+ seq_puts(m, "\nDump Tally Counter Fail\n"); -+ return 0; -+ } -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ RTL_W32(CounterAddrHigh, (u64)paddr >> 32); -+ cmd = (u64)paddr & DMA_BIT_MASK(32); -+ RTL_W32(CounterAddrLow, cmd); -+ RTL_W32(CounterAddrLow, cmd | CounterDump); -+ -+ WaitCnt = 0; -+ while (RTL_R32(CounterAddrLow) & CounterDump) { -+ udelay(10); -+ -+ WaitCnt++; -+ if (WaitCnt > 20) -+ break; -+ } -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ seq_puts(m, "Statistics\tValue\n----------\t-----\n"); -+ seq_printf(m, "tx_packets\t%lld\n", le64_to_cpu(counters->tx_packets)); -+ seq_printf(m, "rx_packets\t%lld\n", le64_to_cpu(counters->rx_packets)); -+ seq_printf(m, "tx_errors\t%lld\n", le64_to_cpu(counters->tx_errors)); -+ seq_printf(m, "rx_missed\t%lld\n", le64_to_cpu(counters->rx_missed)); -+ seq_printf(m, "align_errors\t%lld\n", le64_to_cpu(counters->align_errors)); -+ seq_printf(m, "tx_one_collision\t%lld\n", le64_to_cpu(counters->tx_one_collision)); -+ seq_printf(m, "tx_multi_collision\t%lld\n", le64_to_cpu(counters->tx_multi_collision)); -+ seq_printf(m, "rx_unicast\t%lld\n", le64_to_cpu(counters->rx_unicast)); -+ seq_printf(m, "rx_broadcast\t%lld\n", le64_to_cpu(counters->rx_broadcast)); -+ seq_printf(m, "rx_multicast\t%lld\n", le64_to_cpu(counters->rx_multicast)); -+ seq_printf(m, "tx_aborted\t%lld\n", le64_to_cpu(counters->tx_aborted)); -+ seq_printf(m, "tx_underun\t%lld\n", le64_to_cpu(counters->tx_underun)); -+ -+ seq_putc(m, '\n'); -+ return 0; -+} -+ -+static int proc_get_registers(struct seq_file *m, void *v) -+{ -+ struct net_device *dev = m->private; -+ int i, n, max = R8168_MAC_REGS_SIZE; -+ u8 byte_rd; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ unsigned long flags; -+ -+ seq_puts(m, "\nDump MAC Registers\n"); -+ seq_puts(m, "Offset\tValue\n------\t-----\n"); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ for (n = 0; n < max;) { -+ seq_printf(m, "\n0x%02x:\t", n); -+ -+ for (i = 0; i < 16 && n < max; i++, n++) { -+ byte_rd = readb(ioaddr + n); -+ seq_printf(m, "%02x ", byte_rd); -+ } -+ } -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ seq_putc(m, '\n'); -+ return 0; -+} -+ -+static int proc_get_pcie_phy(struct seq_file *m, void *v) -+{ -+ struct net_device *dev = m->private; -+ int i, n, max = R8168_EPHY_REGS_SIZE/2; -+ u16 word_rd; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ unsigned long flags; -+ -+ seq_puts(m, "\nDump PCIE PHY\n"); -+ seq_puts(m, "\nOffset\tValue\n------\t-----\n "); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ for (n = 0; n < max;) { -+ seq_printf(m, "\n0x%02x:\t", n); -+ -+ for (i = 0; i < 8 && n < max; i++, n++) { -+ word_rd = rtl8168_ephy_read(ioaddr, n); -+ seq_printf(m, "%04x ", word_rd); -+ } -+ } -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ seq_putc(m, '\n'); -+ return 0; -+} -+ -+static int proc_get_eth_phy(struct seq_file *m, void *v) -+{ -+ struct net_device *dev = m->private; -+ int i, n, max = R8168_PHY_REGS_SIZE/2; -+ u16 word_rd; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned long flags; -+ -+ seq_puts(m, "\nDump Ethernet PHY\n"); -+ seq_puts(m, "\nOffset\tValue\n------\t-----\n "); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ seq_puts(m, "\n####################page 0##################\n "); -+ mdio_write(tp, 0x1f, 0x0000); -+ for (n = 0; n < max;) { -+ seq_printf(m, "\n0x%02x:\t", n); -+ -+ for (i = 0; i < 8 && n < max; i++, n++) { -+ word_rd = mdio_read(tp, n); -+ seq_printf(m, "%04x ", word_rd); -+ } -+ } -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ seq_putc(m, '\n'); -+ return 0; -+} -+ -+static int proc_get_extended_registers(struct seq_file *m, void *v) -+{ -+ struct net_device *dev = m->private; -+ int i, n, max = R8168_ERI_REGS_SIZE; -+ u32 dword_rd; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ unsigned long flags; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_1: -+ case CFG_METHOD_2: -+ case CFG_METHOD_3: -+ /* RTL8168B does not support Extend GMAC */ -+ seq_puts(m, "\nNot Support Dump Extended Registers\n"); -+ return 0; -+ } -+ -+ seq_puts(m, "\nDump Extended Registers\n"); -+ seq_puts(m, "\nOffset\tValue\n------\t-----\n "); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ for (n = 0; n < max;) { -+ seq_printf(m, "\n0x%02x:\t", n); -+ -+ for (i = 0; i < 4 && n < max; i++, n+=4) { -+ dword_rd = rtl8168_eri_read(ioaddr, n, 4, ERIAR_ExGMAC); -+ seq_printf(m, "%08x ", dword_rd); -+ } -+ } -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ seq_putc(m, '\n'); -+ return 0; -+} -+#else -+ -+static int proc_get_driver_variable(char *page, char **start, -+ off_t offset, int count, -+ int *eof, void *data) -+{ -+ struct net_device *dev = data; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned long flags; -+ int len = 0; -+ -+ len += snprintf(page + len, count - len, -+ "\nDump Driver Driver\n"); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ len += snprintf(page + len, count - len, -+ "Variable\tValue\n----------\t-----\n"); -+ -+ len += snprintf(page + len, count - len, -+ "MODULENAME\t%s\n" -+ "driver version\t%s\n" -+ "chipset\t%d\n" -+ "chipset_name\t%s\n" -+ "mtu\t%d\n" -+ "NUM_RX_DESC\t0x%x\n" -+ "cur_rx\t0x%x\n" -+ "dirty_rx\t0x%x\n" -+ "NUM_TX_DESC\t0x%x\n" -+ "cur_tx\t0x%x\n" -+ "dirty_tx\t0x%x\n" -+ "rx_buf_sz\t0x%x\n" -+ "esd_flag\t0x%x\n" -+ "pci_cfg_is_read\t0x%x\n" -+ "rtl8168_rx_config\t0x%x\n" -+ "cp_cmd\t0x%x\n" -+ "intr_mask\t0x%x\n" -+ "timer_intr_mask\t0x%x\n" -+ "wol_enabled\t0x%x\n" -+ "wol_opts\t0x%x\n" -+ "efuse_ver\t0x%x\n" -+ "eeprom_type\t0x%x\n" -+ "autoneg\t0x%x\n" -+ "duplex\t0x%x\n" -+ "speed\t%d\n" -+ "eeprom_len\t0x%x\n" -+ "cur_page\t0x%x\n" -+ "bios_setting\t0x%x\n" -+ "features\t0x%x\n" -+ "org_pci_offset_99\t0x%x\n" -+ "org_pci_offset_180\t0x%x\n" -+ "issue_offset_99_event\t0x%x\n" -+ "org_pci_offset_80\t0x%x\n" -+ "org_pci_offset_81\t0x%x\n" -+ "use_timer_interrrupt\t0x%x\n" -+ "HwIcVerUnknown\t0x%x\n" -+ "NotWrRamCodeToMicroP\t0x%x\n" -+ "NotWrMcuPatchCode\t0x%x\n" -+ "HwHasWrRamCodeToMicroP\t0x%x\n" -+ "sw_ram_code_ver\t0x%x\n" -+ "hw_ram_code_ver\t0x%x\n" -+ "rtk_enable_diag\t0x%x\n" -+ "ShortPacketSwChecksum\t0x%x\n" -+ "UseSwPaddingShortPkt\t0x%x\n" -+ "RequireAdcBiasPatch\t0x%x\n" -+ "AdcBiasPatchIoffset\t0x%x\n" -+ "RequireAdjustUpsTxLinkPulseTiming\t0x%x\n" -+ "SwrCnt1msIni\t0x%x\n" -+ "HwSuppNowIsOobVer\t0x%x\n" -+ "RequiredSecLanDonglePatch\t0x%x\n" -+ "HwSuppDashVer\t0x%x\n" -+ "DASH\t0x%x\n" -+ "HwSuppKCPOffloadVer\t0x%x\n", -+ MODULENAME, -+ RTL8168_VERSION, -+ tp->chipset, -+ rtl_chip_info[tp->chipset].name, -+ dev->mtu, -+ NUM_RX_DESC, -+ tp->cur_rx, -+ tp->dirty_rx, -+ NUM_TX_DESC, -+ tp->cur_tx, -+ tp->dirty_tx, -+ tp->rx_buf_sz, -+ tp->esd_flag, -+ tp->pci_cfg_is_read, -+ tp->rtl8168_rx_config, -+ tp->cp_cmd, -+ tp->intr_mask, -+ tp->timer_intr_mask, -+ tp->wol_enabled, -+ tp->wol_opts, -+ tp->efuse_ver, -+ tp->eeprom_type, -+ tp->autoneg, -+ tp->duplex, -+ tp->speed, -+ tp->eeprom_len, -+ tp->cur_page, -+ tp->bios_setting, -+ tp->features, -+ tp->org_pci_offset_99, -+ tp->org_pci_offset_180, -+ tp->issue_offset_99_event, -+ tp->org_pci_offset_80, -+ tp->org_pci_offset_81, -+ tp->use_timer_interrrupt, -+ tp->HwIcVerUnknown, -+ tp->NotWrRamCodeToMicroP, -+ tp->NotWrMcuPatchCode, -+ tp->HwHasWrRamCodeToMicroP, -+ tp->sw_ram_code_ver, -+ tp->hw_ram_code_ver, -+ tp->rtk_enable_diag, -+ tp->ShortPacketSwChecksum, -+ tp->UseSwPaddingShortPkt, -+ tp->RequireAdcBiasPatch, -+ tp->AdcBiasPatchIoffset, -+ tp->RequireAdjustUpsTxLinkPulseTiming, -+ tp->SwrCnt1msIni, -+ tp->HwSuppNowIsOobVer, -+ tp->RequiredSecLanDonglePatch, -+ tp->HwSuppDashVer, -+ tp->DASH, -+ tp->HwSuppKCPOffloadVer -+ ); -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ len += snprintf(page + len, count - len, "\n"); -+ -+ *eof = 1; -+ return len; -+} -+ -+static int proc_get_tally_counter(char *page, char **start, -+ off_t offset, int count, -+ int *eof, void *data) -+{ -+ struct net_device *dev = data; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ struct rtl8168_counters *counters; -+ dma_addr_t paddr; -+ u32 cmd; -+ u32 WaitCnt; -+ unsigned long flags; -+ int len = 0; -+ -+ len += snprintf(page + len, count - len, -+ "\nDump Tally Counter\n"); -+ -+ ASSERT_RTNL(); -+ -+ counters = tp->tally_vaddr; -+ paddr = tp->tally_paddr; -+ if (!counters) { -+ len += snprintf(page + len, count - len, -+ "\nDump Tally Counter Fail\n"); -+ goto out; -+ } -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ RTL_W32(CounterAddrHigh, (u64)paddr >> 32); -+ cmd = (u64)paddr & DMA_BIT_MASK(32); -+ RTL_W32(CounterAddrLow, cmd); -+ RTL_W32(CounterAddrLow, cmd | CounterDump); -+ -+ WaitCnt = 0; -+ while (RTL_R32(CounterAddrLow) & CounterDump) { -+ udelay(10); -+ -+ WaitCnt++; -+ if (WaitCnt > 20) -+ break; -+ } -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ len += snprintf(page + len, count - len, -+ "Statistics\tValue\n----------\t-----\n"); -+ -+ len += snprintf(page + len, count - len, -+ "tx_packets\t%lld\n" -+ "rx_packets\t%lld\n" -+ "tx_errors\t%lld\n" -+ "rx_missed\t%lld\n" -+ "align_errors\t%lld\n" -+ "tx_one_collision\t%lld\n" -+ "tx_multi_collision\t%lld\n" -+ "rx_unicast\t%lld\n" -+ "rx_broadcast\t%lld\n" -+ "rx_multicast\t%lld\n" -+ "tx_aborted\t%lld\n" -+ "tx_underun\t%lld\n", -+ le64_to_cpu(counters->tx_packets), -+ le64_to_cpu(counters->rx_packets), -+ le64_to_cpu(counters->tx_errors), -+ le64_to_cpu(counters->rx_missed), -+ le64_to_cpu(counters->align_errors), -+ le64_to_cpu(counters->tx_one_collision), -+ le64_to_cpu(counters->tx_multi_collision), -+ le64_to_cpu(counters->rx_unicast), -+ le64_to_cpu(counters->rx_broadcast), -+ le64_to_cpu(counters->rx_multicast), -+ le64_to_cpu(counters->tx_aborted), -+ le64_to_cpu(counters->tx_underun) -+ ); -+ -+ len += snprintf(page + len, count - len, "\n"); -+out: -+ *eof = 1; -+ return len; -+} -+ -+static int proc_get_registers(char *page, char **start, -+ off_t offset, int count, -+ int *eof, void *data) -+{ -+ struct net_device *dev = data; -+ int i, n, max = R8168_MAC_REGS_SIZE; -+ u8 byte_rd; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ unsigned long flags; -+ int len = 0; -+ -+ len += snprintf(page + len, count - len, -+ "\nDump MAC Registers\n" -+ "Offset\tValue\n------\t-----\n"); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ for (n = 0; n < max;) { -+ len += snprintf(page + len, count - len, -+ "\n0x%02x:\t", -+ n); -+ -+ for (i = 0; i < 16 && n < max; i++, n++) { -+ byte_rd = readb(ioaddr + n); -+ len += snprintf(page + len, count - len, -+ "%02x ", -+ byte_rd); -+ } -+ } -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ len += snprintf(page + len, count - len, "\n"); -+ -+ *eof = 1; -+ return len; -+} -+ -+static int proc_get_pcie_phy(char *page, char **start, -+ off_t offset, int count, -+ int *eof, void *data) -+{ -+ struct net_device *dev = data; -+ int i, n, max = R8168_EPHY_REGS_SIZE/2; -+ u16 word_rd; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ unsigned long flags; -+ int len = 0; -+ -+ len += snprintf(page + len, count - len, -+ "\nDump PCIE PHY\n" -+ "Offset\tValue\n------\t-----\n"); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ for (n = 0; n < max;) { -+ len += snprintf(page + len, count - len, -+ "\n0x%02x:\t", -+ n); -+ -+ for (i = 0; i < 8 && n < max; i++, n++) { -+ word_rd = rtl8168_ephy_read(ioaddr, n); -+ len += snprintf(page + len, count - len, -+ "%04x ", -+ word_rd); -+ } -+ } -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ len += snprintf(page + len, count - len, "\n"); -+ -+ *eof = 1; -+ return len; -+} -+ -+static int proc_get_eth_phy(char *page, char **start, -+ off_t offset, int count, -+ int *eof, void *data) -+{ -+ struct net_device *dev = data; -+ int i, n, max = R8168_PHY_REGS_SIZE/2; -+ u16 word_rd; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned long flags; -+ int len = 0; -+ -+ len += snprintf(page + len, count - len, -+ "\nDump Ethernet PHY\n" -+ "Offset\tValue\n------\t-----\n"); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ len += snprintf(page + len, count - len, -+ "\n####################page 0##################\n"); -+ mdio_write(tp, 0x1f, 0x0000); -+ for (n = 0; n < max;) { -+ len += snprintf(page + len, count - len, -+ "\n0x%02x:\t", -+ n); -+ -+ for (i = 0; i < 8 && n < max; i++, n++) { -+ word_rd = mdio_read(tp, n); -+ len += snprintf(page + len, count - len, -+ "%04x ", -+ word_rd); -+ } -+ } -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ len += snprintf(page + len, count - len, "\n"); -+ -+ *eof = 1; -+ return len; -+} -+ -+static int proc_get_extended_registers(char *page, char **start, -+ off_t offset, int count, -+ int *eof, void *data) -+{ -+ struct net_device *dev = data; -+ int i, n, max = R8168_ERI_REGS_SIZE; -+ u32 dword_rd; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ unsigned long flags; -+ int len = 0; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_1: -+ case CFG_METHOD_2: -+ case CFG_METHOD_3: -+ /* RTL8168B does not support Extend GMAC */ -+ len += snprintf(page + len, count - len, -+ "\nNot Support Dump Extended Registers\n"); -+ -+ goto out; -+ } -+ -+ len += snprintf(page + len, count - len, -+ "\nDump Extended Registers\n" -+ "Offset\tValue\n------\t-----\n"); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ for (n = 0; n < max;) { -+ len += snprintf(page + len, count - len, -+ "\n0x%02x:\t", -+ n); -+ -+ for (i = 0; i < 4 && n < max; i++, n+=4) { -+ dword_rd = rtl8168_eri_read(ioaddr, n, 4, ERIAR_ExGMAC); -+ len += snprintf(page + len, count - len, -+ "%08x ", -+ dword_rd); -+ } -+ } -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ len += snprintf(page + len, count - len, "\n"); -+out: -+ *eof = 1; -+ return len; -+} -+ -+#endif -+static void rtl8168_proc_module_init(void) -+{ -+ //in case /proc/net/r8168 already exist -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) -+ remove_proc_subtree(MODULENAME, init_net.proc_net); -+#else -+ remove_proc_entry(MODULENAME, init_net.proc_net); -+#endif -+ -+ //create /proc/net/r8168 -+ rtl8168_proc = proc_mkdir(MODULENAME, init_net.proc_net); -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) -+/* -+ * seq_file wrappers for procfile show routines. -+ */ -+static int rtl8168_proc_open(struct inode *inode, struct file *file) -+{ -+ struct net_device *dev = proc_get_parent_data(inode); -+ int (*show)(struct seq_file *, void *) = PDE_DATA(inode); -+ -+ return single_open(file, show, dev); -+} -+ -+static const struct file_operations rtl8168_proc_fops = { -+ .open = rtl8168_proc_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+#endif -+ -+/* -+ * Table of proc files we need to create. -+ */ -+struct rtl8168_proc_file { -+ char name[12]; -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) -+ int (*show)(struct seq_file *, void *); -+#else -+ int (*show)(char *, char **, off_t, int, int *, void *); -+#endif -+}; -+ -+static const struct rtl8168_proc_file rtl8168_proc_files[] = { -+ { "driver_var", &proc_get_driver_variable }, -+ { "tally", &proc_get_tally_counter }, -+ { "registers", &proc_get_registers }, -+ { "pcie_phy", &proc_get_pcie_phy }, -+ { "eth_phy", &proc_get_eth_phy }, -+ { "ext_regs", &proc_get_extended_registers }, -+ { "" } -+}; -+ -+static void rtl8168_proc_init(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ const struct rtl8168_proc_file *f; -+ struct proc_dir_entry *dir; -+ -+ if (rtl8168_proc && !tp->proc_dir) { -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) -+ dir = proc_mkdir_data(dev->name, 0, rtl8168_proc, dev); -+ if (!dir) { -+ printk("Unable to initialize /proc/net/%s/%s\n", -+ MODULENAME, dev->name); -+ return; -+ } -+ -+ tp->proc_dir = dir; -+ proc_init_num++; -+ -+ for (f = rtl8168_proc_files; f->name[0]; f++) { -+ if (!proc_create_data(f->name, S_IFREG | S_IRUGO, dir, -+ &rtl8168_proc_fops, f->show)) { -+ printk("Unable to initialize " -+ "/proc/net/%s/%s/%s\n", -+ MODULENAME, dev->name, f->name); -+ return; -+ } -+ } -+#else -+ dir = proc_mkdir(dev->name, rtl8168_proc); -+ if (!dir) { -+ printk("Unable to initialize /proc/net/%s/%s\n", -+ MODULENAME, dev->name); -+ return; -+ } -+ -+ tp->proc_dir = dir; -+ proc_init_num++; -+ -+ for (f = rtl8168_proc_files; f->name[0]; f++) { -+ if (!create_proc_read_entry(f->name, S_IFREG | S_IRUGO, -+ dir, f->show, dev)) { -+ printk("Unable to initialize " -+ "/proc/net/%s/%s/%s\n", -+ MODULENAME, dev->name, f->name); -+ return; -+ } -+ } -+#endif -+ } -+} -+ -+static void rtl8168_proc_remove(struct net_device *dev) -+{ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) -+ remove_proc_subtree(dev->name, rtl8168_proc); -+ proc_init_num--; -+#else -+ const struct rtl8168_proc_file *f; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ for (f = rtl8168_proc_files; f->name[0]; f++) -+ remove_proc_entry(f->name, tp->proc_dir); -+ -+ remove_proc_entry(dev->name, rtl8168_proc); -+ proc_init_num--; -+#endif -+} -+ -+#endif //ENABLE_R8168_PROCFS -+ -+static inline u16 map_phy_ocp_addr(u16 PageNum, u8 RegNum) -+{ -+ u16 OcpPageNum = 0; -+ u8 OcpRegNum = 0; -+ u16 OcpPhyAddress = 0; -+ -+ if( PageNum == 0 ) { -+ OcpPageNum = OCP_STD_PHY_BASE_PAGE + ( RegNum / 8 ); -+ OcpRegNum = 0x10 + ( RegNum % 8 ); -+ } else { -+ OcpPageNum = PageNum; -+ OcpRegNum = RegNum; -+ } -+ -+ OcpPageNum <<= 4; -+ -+ if( OcpRegNum < 16 ) { -+ OcpPhyAddress = 0; -+ } else { -+ OcpRegNum -= 16; -+ OcpRegNum <<= 1; -+ -+ OcpPhyAddress = OcpPageNum + OcpRegNum; -+ } -+ -+ -+ return OcpPhyAddress; -+} -+ -+static void mdio_write_phy_ocp(struct rtl8168_private *tp, -+ u16 PageNum, -+ u32 RegAddr, -+ u32 value) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 data32; -+ u16 ocp_addr; -+ int i; -+ -+ ocp_addr = map_phy_ocp_addr(PageNum, RegAddr); -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) -+ WARN_ON_ONCE(ocp_addr % 2); -+#endif -+ data32 = ocp_addr/2; -+ data32 <<= OCPR_Addr_Reg_shift; -+ data32 |= OCPR_Write | value; -+ -+ RTL_W32(PHYOCP, data32); -+ for (i = 0; i < 100; i++) { -+ udelay(1); -+ -+ if (!(RTL_R32(PHYOCP) & OCPR_Flag)) -+ break; -+ } -+} -+ -+static void mdio_real_write(struct rtl8168_private *tp, -+ u32 RegAddr, -+ u32 value) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ int i; -+ -+ if (RegAddr == 0x1F) { -+ tp->cur_page = value; -+ } -+ -+ if (tp->mcfg == CFG_METHOD_11) { -+ RTL_W32(OCPDR, OCPDR_Write | -+ (RegAddr & OCPDR_Reg_Mask) << OCPDR_GPHY_Reg_shift | -+ (value & OCPDR_Data_Mask)); -+ RTL_W32(OCPAR, OCPAR_GPHY_Write); -+ RTL_W32(EPHY_RXER_NUM, 0); -+ -+ for (i = 0; i < 100; i++) { -+ mdelay(1); -+ if (!(RTL_R32(OCPAR) & OCPAR_Flag)) -+ break; -+ } -+ } else if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 || -+ tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 || -+ tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 || -+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 || -+ tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ if (RegAddr == 0x1F) { -+ return; -+ } -+ mdio_write_phy_ocp(tp, tp->cur_page, RegAddr, value); -+ } else { -+ if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13) -+ RTL_W32(0xD0, RTL_R32(0xD0) & ~0x00020000); -+ -+ RTL_W32(PHYAR, PHYAR_Write | -+ (RegAddr & PHYAR_Reg_Mask) << PHYAR_Reg_shift | -+ (value & PHYAR_Data_Mask)); -+ -+ for (i = 0; i < 10; i++) { -+ udelay(100); -+ -+ /* Check if the RTL8168 has completed writing to the specified MII register */ -+ if (!(RTL_R32(PHYAR) & PHYAR_Flag)) { -+ udelay(20); -+ break; -+ } -+ } -+ -+ if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13) -+ RTL_W32(0xD0, RTL_R32(0xD0) | 0x00020000); -+ } -+} -+ -+void mdio_write(struct rtl8168_private *tp, -+ u32 RegAddr, -+ u32 value) -+{ -+ if (tp->rtk_enable_diag) return; -+ -+ mdio_real_write(tp, RegAddr, value); -+} -+ -+void mdio_prot_write(struct rtl8168_private *tp, -+ u32 RegAddr, -+ u32 value) -+{ -+ mdio_real_write(tp, RegAddr, value); -+} -+ -+static u32 mdio_read_phy_ocp(struct rtl8168_private *tp, -+ u16 PageNum, -+ u32 RegAddr) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 data32; -+ u16 ocp_addr; -+ int i, value = 0; -+ -+ ocp_addr = map_phy_ocp_addr(PageNum, RegAddr); -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) -+ WARN_ON_ONCE(ocp_addr % 2); -+#endif -+ data32 = ocp_addr/2; -+ data32 <<= OCPR_Addr_Reg_shift; -+ -+ RTL_W32(PHYOCP, data32); -+ for (i = 0; i < 100; i++) { -+ udelay(1); -+ -+ if (RTL_R32(PHYOCP) & OCPR_Flag) -+ break; -+ } -+ value = RTL_R32(PHYOCP) & OCPDR_Data_Mask; -+ -+ return value; -+} -+ -+u32 mdio_read(struct rtl8168_private *tp, -+ u32 RegAddr) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ int i, value = 0; -+ -+ if (tp->mcfg==CFG_METHOD_11) { -+ RTL_W32(OCPDR, OCPDR_Read | -+ (RegAddr & OCPDR_Reg_Mask) << OCPDR_GPHY_Reg_shift); -+ RTL_W32(OCPAR, OCPAR_GPHY_Write); -+ RTL_W32(EPHY_RXER_NUM, 0); -+ -+ for (i = 0; i < 100; i++) { -+ mdelay(1); -+ if (!(RTL_R32(OCPAR) & OCPAR_Flag)) -+ break; -+ } -+ -+ mdelay(1); -+ RTL_W32(OCPAR, OCPAR_GPHY_Read); -+ RTL_W32(EPHY_RXER_NUM, 0); -+ -+ for (i = 0; i < 100; i++) { -+ mdelay(1); -+ if (RTL_R32(OCPAR) & OCPAR_Flag) -+ break; -+ } -+ -+ value = RTL_R32(OCPDR) & OCPDR_Data_Mask; -+ } else if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 || -+ tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 || -+ tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 || -+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 || -+ tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ value = mdio_read_phy_ocp(tp, tp->cur_page, RegAddr); -+ } else { -+ if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13) -+ RTL_W32(0xD0, RTL_R32(0xD0) & ~0x00020000); -+ -+ RTL_W32(PHYAR, -+ PHYAR_Read | (RegAddr & PHYAR_Reg_Mask) << PHYAR_Reg_shift); -+ -+ for (i = 0; i < 10; i++) { -+ udelay(100); -+ -+ /* Check if the RTL8168 has completed retrieving data from the specified MII register */ -+ if (RTL_R32(PHYAR) & PHYAR_Flag) { -+ value = RTL_R32(PHYAR) & PHYAR_Data_Mask; -+ udelay(20); -+ break; -+ } -+ } -+ -+ if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13) -+ RTL_W32(0xD0, RTL_R32(0xD0) | 0x00020000); -+ } -+ -+ return value; -+} -+ -+static void ClearAndSetEthPhyBit(struct rtl8168_private *tp, u8 addr, u16 clearmask, u16 setmask) -+{ -+ u16 PhyRegValue; -+ -+ -+ PhyRegValue = mdio_read( tp, addr ); -+ PhyRegValue &= ~clearmask; -+ PhyRegValue |= setmask; -+ mdio_write( tp, addr, PhyRegValue); -+} -+ -+void ClearEthPhyBit(struct rtl8168_private *tp, u8 addr, u16 mask) -+{ -+ ClearAndSetEthPhyBit( tp, -+ addr, -+ mask, -+ 0 -+ ); -+} -+ -+void SetEthPhyBit(struct rtl8168_private *tp, u8 addr, u16 mask) -+{ -+ ClearAndSetEthPhyBit( tp, -+ addr, -+ 0, -+ mask -+ ); -+} -+ -+void mac_ocp_write(struct rtl8168_private *tp, u16 reg_addr, u16 value) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 data32; -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) -+ WARN_ON_ONCE(reg_addr % 2); -+#endif -+ -+ data32 = reg_addr/2; -+ data32 <<= OCPR_Addr_Reg_shift; -+ data32 += value; -+ data32 |= OCPR_Write; -+ -+ RTL_W32(MACOCP, data32); -+} -+ -+u16 mac_ocp_read(struct rtl8168_private *tp, u16 reg_addr) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 data32; -+ u16 data16 = 0; -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) -+ WARN_ON_ONCE(reg_addr % 2); -+#endif -+ -+ data32 = reg_addr/2; -+ data32 <<= OCPR_Addr_Reg_shift; -+ -+ RTL_W32(MACOCP, data32); -+ data16 = (u16)RTL_R32(MACOCP); -+ -+ return data16; -+} -+ -+static u32 real_ocp_read(struct rtl8168_private *tp, u16 addr, u8 len) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ int i, val_shift, shift = 0; -+ u32 value1 = 0, value2 = 0, mask; -+ -+ if (len > 4 || len <= 0) -+ return -1; -+ -+ while (len > 0) { -+ val_shift = addr % 4; -+ addr = addr & ~0x3; -+ -+ RTL_W32(OCPAR, (0x0F<<12) | (addr&0xFFF)); -+ -+ for (i = 0; i < 20; i++) { -+ udelay(100); -+ if (RTL_R32(OCPAR) & OCPAR_Flag) -+ break; -+ } -+ -+ if (len == 1) mask = (0xFF << (val_shift * 8)) & 0xFFFFFFFF; -+ else if (len == 2) mask = (0xFFFF << (val_shift * 8)) & 0xFFFFFFFF; -+ else if (len == 3) mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; -+ else mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; -+ -+ value1 = RTL_R32(OCPDR) & mask; -+ value2 |= (value1 >> val_shift * 8) << shift * 8; -+ -+ if (len <= 4 - val_shift) { -+ len = 0; -+ } else { -+ len -= (4 - val_shift); -+ shift = 4 - val_shift; -+ addr += 4; -+ } -+ } -+ -+ udelay(20); -+ -+ return value2; -+} -+ -+u32 OCP_read(struct rtl8168_private *tp, u16 addr, u8 len) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 value = 0; -+ -+ if (tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_27 || -+ tp->mcfg == CFG_METHOD_28) { -+ value = rtl8168_eri_read(ioaddr, addr, len, ERIAR_OOB); -+ } else { -+ value = real_ocp_read(tp, addr, len); -+ } -+ -+ return value; -+} -+ -+static int real_ocp_write(struct rtl8168_private *tp, u16 addr, u8 len, u32 value) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ int i, val_shift, shift = 0; -+ u32 value1 = 0, mask; -+ -+ if (len > 4 || len <= 0) -+ return -1; -+ -+ while (len > 0) { -+ val_shift = addr % 4; -+ addr = addr & ~0x3; -+ -+ if (len == 1) mask = (0xFF << (val_shift * 8)) & 0xFFFFFFFF; -+ else if (len == 2) mask = (0xFFFF << (val_shift * 8)) & 0xFFFFFFFF; -+ else if (len == 3) mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; -+ else mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; -+ -+ value1 = OCP_read(tp, addr, 4) & ~mask; -+ value1 |= ((value << val_shift * 8) >> shift * 8); -+ -+ RTL_W32(OCPDR, value1); -+ RTL_W32(OCPAR, OCPAR_Flag | (0x0F<<12) | (addr&0xFFF)); -+ -+ for (i = 0; i < 10; i++) { -+ udelay(100); -+ -+ /* Check if the RTL8168 has completed ERI write */ -+ if (!(RTL_R32(OCPAR) & OCPAR_Flag)) -+ break; -+ } -+ -+ if (len <= 4 - val_shift) { -+ len = 0; -+ } else { -+ len -= (4 - val_shift); -+ shift = 4 - val_shift; -+ addr += 4; -+ } -+ } -+ -+ udelay(20); -+ -+ return 0; -+} -+ -+void OCP_write(struct rtl8168_private *tp, u16 addr, u8 len, u32 value) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if (tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_27 || -+ tp->mcfg == CFG_METHOD_28) { -+ rtl8168_eri_write(ioaddr, addr, len, value, ERIAR_OOB); -+ } else { -+ real_ocp_write(tp, addr, len, value); -+ } -+} -+ -+void OOB_mutex_lock(struct rtl8168_private *tp) -+{ -+ u8 reg_16, reg_a0; -+ u32 wait_cnt_0, wait_Cnt_1; -+ u16 ocp_reg_mutex_ib; -+ u16 ocp_reg_mutex_oob; -+ u16 ocp_reg_mutex_prio; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ ocp_reg_mutex_oob = 0x16; -+ ocp_reg_mutex_ib = 0x17; -+ ocp_reg_mutex_prio = 0x9C; -+ break; -+ case CFG_METHOD_13: -+ ocp_reg_mutex_oob = 0x06; -+ ocp_reg_mutex_ib = 0x07; -+ ocp_reg_mutex_prio = 0x9C; -+ break; -+ case CFG_METHOD_23: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ default: -+ ocp_reg_mutex_oob = 0x110; -+ ocp_reg_mutex_ib = 0x114; -+ ocp_reg_mutex_prio = 0x11C; -+ break; -+ } -+ -+ OCP_write(tp, ocp_reg_mutex_ib, 1, BIT_0); -+ reg_16 = OCP_read(tp, ocp_reg_mutex_oob, 1); -+ wait_cnt_0 = 0; -+ while(reg_16) { -+ reg_a0 = OCP_read(tp, ocp_reg_mutex_prio, 1); -+ if(reg_a0) { -+ OCP_write(tp, ocp_reg_mutex_ib, 1, 0x00); -+ reg_a0 = OCP_read(tp, ocp_reg_mutex_prio, 1); -+ wait_Cnt_1 = 0; -+ while(reg_a0) { -+ reg_a0 = OCP_read(tp, ocp_reg_mutex_prio, 1); -+ -+ wait_Cnt_1++; -+ -+ if(wait_Cnt_1 > 2000) -+ break; -+ }; -+ OCP_write(tp, ocp_reg_mutex_ib, 1, BIT_0); -+ -+ } -+ reg_16 = OCP_read(tp, ocp_reg_mutex_oob, 1); -+ -+ wait_cnt_0++; -+ -+ if(wait_cnt_0 > 2000) -+ break; -+ }; -+} -+ -+void OOB_mutex_unlock(struct rtl8168_private *tp) -+{ -+ u16 ocp_reg_mutex_ib; -+ u16 ocp_reg_mutex_oob; -+ u16 ocp_reg_mutex_prio; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ ocp_reg_mutex_oob = 0x16; -+ ocp_reg_mutex_ib = 0x17; -+ ocp_reg_mutex_prio = 0x9C; -+ break; -+ case CFG_METHOD_13: -+ ocp_reg_mutex_oob = 0x06; -+ ocp_reg_mutex_ib = 0x07; -+ ocp_reg_mutex_prio = 0x9C; -+ break; -+ case CFG_METHOD_23: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ default: -+ ocp_reg_mutex_oob = 0x110; -+ ocp_reg_mutex_ib = 0x114; -+ ocp_reg_mutex_prio = 0x11C; -+ break; -+ } -+ -+ OCP_write(tp, ocp_reg_mutex_prio, 1, BIT_0); -+ OCP_write(tp, ocp_reg_mutex_ib, 1, 0x00); -+} -+ -+void OOB_notify(struct rtl8168_private *tp, u8 cmd) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ rtl8168_eri_write(ioaddr, 0xE8, 1, cmd, ERIAR_ExGMAC); -+ -+ OCP_write(tp, 0x30, 1, 0x01); -+} -+ -+static int rtl8168_check_dash(struct rtl8168_private *tp) -+{ -+ if (tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_27 || -+ tp->mcfg == CFG_METHOD_28) { -+ if (OCP_read(tp, 0x128, 1) & BIT_0) -+ return 1; -+ else -+ return 0; -+ } else { -+ u32 reg; -+ -+ if (tp->mcfg == CFG_METHOD_13) -+ reg = 0xb8; -+ else -+ reg = 0x10; -+ -+ if (OCP_read(tp, reg, 2) & 0x00008000) -+ return 1; -+ else -+ return 0; -+ } -+} -+ -+void Dash2DisableTx(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if (!tp->DASH) return; -+ -+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) { -+ u16 WaitCnt; -+ u8 TmpUchar; -+ -+ //Disable oob Tx -+ RTL_W8(IBCR2, RTL_R8(IBCR2) & ~( BIT_0 )); -+ WaitCnt = 0; -+ -+ //wait oob tx disable -+ do { -+ TmpUchar = RTL_R8(IBISR0); -+ -+ if( TmpUchar & ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE ) { -+ break; -+ } -+ -+ udelay( 50 ); -+ WaitCnt++; -+ } while(WaitCnt < 2000); -+ -+ //Clear ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE -+ RTL_W8(IBISR0, RTL_R8(IBISR0) | ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE); -+ } -+} -+ -+void Dash2EnableTx(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if (!tp->DASH) return; -+ -+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) -+ RTL_W8(IBCR2, RTL_R8(IBCR2) | BIT_0); -+} -+ -+void Dash2DisableRx(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if (!tp->DASH) return; -+ -+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) -+ RTL_W8(IBCR0, RTL_R8(IBCR0) & ~( BIT_0 )); -+} -+ -+void Dash2EnableRx(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if (!tp->DASH) return; -+ -+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) -+ RTL_W8(IBCR0, RTL_R8(IBCR0) | BIT_0); -+} -+ -+static void Dash2DisableTxRx(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) { -+ Dash2DisableTx( tp ); -+ Dash2DisableRx( tp ); -+ } -+} -+ -+static void rtl8168_driver_start(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if (!tp->DASH) -+ return; -+ -+ if (tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_27 || -+ tp->mcfg == CFG_METHOD_28) { -+ int timeout; -+ u32 tmp_value; -+ -+ OCP_write(tp, 0x180, 1, OOB_CMD_DRIVER_START); -+ tmp_value = OCP_read(tp, 0x30, 1); -+ tmp_value |= BIT_0; -+ OCP_write(tp, 0x30, 1, tmp_value); -+ -+ for (timeout = 0; timeout < 10; timeout++) { -+ mdelay(10); -+ if (OCP_read(tp, 0x124, 1) & BIT_0) -+ break; -+ } -+ } else { -+ int timeout; -+ u32 reg; -+ -+ if (tp->mcfg == CFG_METHOD_13) { -+ RTL_W8(TwiCmdReg, RTL_R8(TwiCmdReg) | ( BIT_7 )); -+ } -+ -+ OOB_notify(tp, OOB_CMD_DRIVER_START); -+ -+ if (tp->mcfg == CFG_METHOD_13) -+ reg = 0xB8; -+ else -+ reg = 0x10; -+ -+ for (timeout = 0; timeout < 10; timeout++) { -+ mdelay(10); -+ if (OCP_read(tp, reg, 2) & BIT_11) -+ break; -+ } -+ } -+} -+ -+static void rtl8168_driver_stop(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if (!tp->DASH) -+ return; -+ -+ if (tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_27 || -+ tp->mcfg == CFG_METHOD_28) { -+ struct net_device *dev = tp->dev; -+ int timeout; -+ u32 tmp_value; -+ -+ Dash2DisableTxRx(dev); -+ -+ OCP_write(tp, 0x180, 1, OOB_CMD_DRIVER_STOP); -+ tmp_value = OCP_read(tp, 0x30, 1); -+ tmp_value |= BIT_0; -+ OCP_write(tp, 0x30, 1, tmp_value); -+ -+ for (timeout = 0; timeout < 10; timeout++) { -+ mdelay(10); -+ if (!(OCP_read(tp, 0x124, 1) & BIT_0)) -+ break; -+ } -+ } else { -+ int timeout; -+ u32 reg; -+ -+ OOB_notify(tp, OOB_CMD_DRIVER_STOP); -+ -+ if (tp->mcfg == CFG_METHOD_13) -+ reg = 0xB8; -+ else -+ reg = 0x10; -+ -+ for (timeout = 0; timeout < 10; timeout++) { -+ mdelay(10); -+ if ((OCP_read(tp, reg, 2) & BIT_11) == 0) -+ break; -+ } -+ -+ if (tp->mcfg == CFG_METHOD_13) { -+ RTL_W8(TwiCmdReg, RTL_R8(TwiCmdReg) & ~( BIT_7 )); -+ } -+ } -+} -+ -+void rtl8168_ephy_write(void __iomem *ioaddr, int RegAddr, int value) -+{ -+ int i; -+ -+ RTL_W32(EPHYAR, -+ EPHYAR_Write | -+ (RegAddr & EPHYAR_Reg_Mask) << EPHYAR_Reg_shift | -+ (value & EPHYAR_Data_Mask)); -+ -+ for (i = 0; i < 10; i++) { -+ udelay(100); -+ -+ /* Check if the RTL8168 has completed EPHY write */ -+ if (!(RTL_R32(EPHYAR) & EPHYAR_Flag)) -+ break; -+ } -+ -+ udelay(20); -+} -+ -+u16 rtl8168_ephy_read(void __iomem *ioaddr, int RegAddr) -+{ -+ int i; -+ u16 value = 0xffff; -+ -+ RTL_W32(EPHYAR, -+ EPHYAR_Read | (RegAddr & EPHYAR_Reg_Mask) << EPHYAR_Reg_shift); -+ -+ for (i = 0; i < 10; i++) { -+ udelay(100); -+ -+ /* Check if the RTL8168 has completed EPHY read */ -+ if (RTL_R32(EPHYAR) & EPHYAR_Flag) { -+ value = (u16) (RTL_R32(EPHYAR) & EPHYAR_Data_Mask); -+ break; -+ } -+ } -+ -+ udelay(20); -+ -+ return value; -+} -+ -+static void ClearAndSetPCIePhyBit(struct rtl8168_private *tp, u8 addr, u16 clearmask, u16 setmask) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u16 EphyValue; -+ -+ EphyValue = rtl8168_ephy_read( ioaddr, addr ); -+ EphyValue &= ~clearmask; -+ EphyValue |= setmask; -+ rtl8168_ephy_write( ioaddr, addr, EphyValue); -+} -+ -+static void ClearPCIePhyBit(struct rtl8168_private *tp, u8 addr, u16 mask) -+{ -+ ClearAndSetPCIePhyBit( tp, -+ addr, -+ mask, -+ 0 -+ ); -+} -+ -+static void SetPCIePhyBit( struct rtl8168_private *tp, u8 addr, u16 mask) -+{ -+ ClearAndSetPCIePhyBit( tp, -+ addr, -+ 0, -+ mask -+ ); -+} -+ -+static u32 -+rtl8168_csi_other_fun_read(struct rtl8168_private *tp, -+ u8 multi_fun_sel_bit, -+ u32 addr) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 cmd; -+ int i; -+ u32 value = 0; -+ -+ cmd = CSIAR_Read | CSIAR_ByteEn << CSIAR_ByteEn_shift | (addr & CSIAR_Addr_Mask); -+ -+ if (tp->mcfg != CFG_METHOD_20 && tp->mcfg != CFG_METHOD_23 && -+ tp->mcfg != CFG_METHOD_26 && tp->mcfg != CFG_METHOD_27 && -+ tp->mcfg != CFG_METHOD_28) { -+ multi_fun_sel_bit = 0; -+ } -+ -+ if( multi_fun_sel_bit > 7 ) { -+ return 0xffffffff; -+ } -+ -+ cmd |= multi_fun_sel_bit << 16; -+ -+ RTL_W32(CSIAR, cmd); -+ -+ for (i = 0; i < 10; i++) { -+ udelay(100); -+ -+ /* Check if the RTL8168 has completed CSI read */ -+ if (RTL_R32(CSIAR) & CSIAR_Flag) { -+ value = (u32)RTL_R32(CSIDR); -+ break; -+ } -+ } -+ -+ udelay(20); -+ -+ return value; -+} -+ -+static void -+rtl8168_csi_other_fun_write(struct rtl8168_private *tp, -+ u8 multi_fun_sel_bit, -+ u32 addr, -+ u32 value) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 cmd; -+ int i; -+ -+ RTL_W32(CSIDR, value); -+ cmd = CSIAR_Write | CSIAR_ByteEn << CSIAR_ByteEn_shift | (addr & CSIAR_Addr_Mask); -+ if (tp->mcfg != CFG_METHOD_20 && tp->mcfg != CFG_METHOD_23 && -+ tp->mcfg != CFG_METHOD_26 && tp->mcfg != CFG_METHOD_27 && -+ tp->mcfg != CFG_METHOD_28) { -+ multi_fun_sel_bit = 0; -+ } -+ -+ if( multi_fun_sel_bit > 7 ) { -+ return; -+ } -+ -+ cmd |= multi_fun_sel_bit << 16; -+ -+ RTL_W32(CSIAR, cmd); -+ -+ for (i = 0; i < 10; i++) { -+ udelay(100); -+ -+ /* Check if the RTL8168 has completed CSI write */ -+ if (!(RTL_R32(CSIAR) & CSIAR_Flag)) -+ break; -+ } -+ -+ udelay(20); -+} -+ -+static u32 -+rtl8168_csi_read(struct rtl8168_private *tp, -+ u32 addr) -+{ -+ u8 multi_fun_sel_bit; -+ -+ if (tp->mcfg == CFG_METHOD_20) -+ multi_fun_sel_bit = 2; -+ else if (tp->mcfg == CFG_METHOD_26) -+ multi_fun_sel_bit = 1; -+ else -+ multi_fun_sel_bit = 0; -+ -+ -+ return rtl8168_csi_other_fun_read(tp, multi_fun_sel_bit, addr); -+} -+ -+static void -+rtl8168_csi_write(struct rtl8168_private *tp, -+ u32 addr, -+ u32 value) -+{ -+ u8 multi_fun_sel_bit; -+ -+ if (tp->mcfg == CFG_METHOD_20) -+ multi_fun_sel_bit = 2; -+ else if (tp->mcfg == CFG_METHOD_26) -+ multi_fun_sel_bit = 1; -+ else -+ multi_fun_sel_bit = 0; -+ -+ rtl8168_csi_other_fun_write(tp, multi_fun_sel_bit, addr, value); -+} -+ -+static u8 -+rtl8168_csi_fun0_read_byte(struct rtl8168_private *tp, -+ u32 addr) -+{ -+ u8 RetVal = 0; -+ -+ if (tp->mcfg == CFG_METHOD_20 || tp->mcfg == CFG_METHOD_26) { -+ u32 TmpUlong; -+ u16 RegAlignAddr; -+ u8 ShiftByte; -+ -+ RegAlignAddr = addr & ~(0x3); -+ ShiftByte = addr & (0x3); -+ TmpUlong = rtl8168_csi_other_fun_read(tp, 0, addr); -+ TmpUlong >>= (8*ShiftByte); -+ RetVal = (u8)TmpUlong; -+ } else { -+ struct pci_dev *pdev = tp->pci_dev; -+ -+ pci_read_config_byte(pdev, addr, &RetVal); -+ } -+ -+ udelay(20); -+ -+ return RetVal; -+} -+ -+static void -+rtl8168_csi_fun0_write_byte(struct rtl8168_private *tp, -+ u32 addr, -+ u8 value) -+{ -+ if (tp->mcfg == CFG_METHOD_20 || tp->mcfg == CFG_METHOD_26) { -+ u32 TmpUlong; -+ u16 RegAlignAddr; -+ u8 ShiftByte; -+ -+ RegAlignAddr = addr & ~(0x3); -+ ShiftByte = addr & (0x3); -+ TmpUlong = rtl8168_csi_other_fun_read(tp, 0, RegAlignAddr); -+ TmpUlong &= ~(0xFF << (8*ShiftByte)); -+ TmpUlong |= (value << (8*ShiftByte)); -+ rtl8168_csi_other_fun_write( tp, 0, RegAlignAddr, TmpUlong ); -+ } else { -+ struct pci_dev *pdev = tp->pci_dev; -+ -+ pci_write_config_byte(pdev, addr, value); -+ } -+ -+ udelay(20); -+} -+ -+u32 rtl8168_eri_read(void __iomem *ioaddr, int addr, int len, int type) -+{ -+ int i, val_shift, shift = 0; -+ u32 value1 = 0, value2 = 0, mask; -+ u32 eri_cmd; -+ -+ if (len > 4 || len <= 0) -+ return -1; -+ -+ while (len > 0) { -+ val_shift = addr % ERIAR_Addr_Align; -+ addr = addr & ~0x3; -+ -+ eri_cmd = ERIAR_Read | -+ type << ERIAR_Type_shift | -+ ERIAR_ByteEn << ERIAR_ByteEn_shift | -+ (addr & 0x0FFF); -+ if (addr & 0xF000) { -+ u32 tmp; -+ -+ tmp = addr & 0xF000; -+ tmp >>= 12; -+ eri_cmd |= (tmp << 20) & 0x00F00000; -+ } -+ -+ RTL_W32(ERIAR, eri_cmd); -+ -+ for (i = 0; i < 10; i++) { -+ udelay(100); -+ -+ /* Check if the RTL8168 has completed ERI read */ -+ if (RTL_R32(ERIAR) & ERIAR_Flag) -+ break; -+ } -+ -+ if (len == 1) mask = (0xFF << (val_shift * 8)) & 0xFFFFFFFF; -+ else if (len == 2) mask = (0xFFFF << (val_shift * 8)) & 0xFFFFFFFF; -+ else if (len == 3) mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; -+ else mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; -+ -+ value1 = RTL_R32(ERIDR) & mask; -+ value2 |= (value1 >> val_shift * 8) << shift * 8; -+ -+ if (len <= 4 - val_shift) { -+ len = 0; -+ } else { -+ len -= (4 - val_shift); -+ shift = 4 - val_shift; -+ addr += 4; -+ } -+ } -+ -+ udelay(20); -+ -+ return value2; -+} -+ -+int rtl8168_eri_write(void __iomem *ioaddr, int addr, int len, u32 value, int type) -+{ -+ -+ int i, val_shift, shift = 0; -+ u32 value1 = 0, mask; -+ u32 eri_cmd; -+ -+ if (len > 4 || len <= 0) -+ return -1; -+ -+ while (len > 0) { -+ val_shift = addr % ERIAR_Addr_Align; -+ addr = addr & ~0x3; -+ -+ if (len == 1) mask = (0xFF << (val_shift * 8)) & 0xFFFFFFFF; -+ else if (len == 2) mask = (0xFFFF << (val_shift * 8)) & 0xFFFFFFFF; -+ else if (len == 3) mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; -+ else mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; -+ -+ value1 = rtl8168_eri_read(ioaddr, addr, 4, type) & ~mask; -+ value1 |= ((value << val_shift * 8) >> shift * 8); -+ -+ RTL_W32(ERIDR, value1); -+ -+ eri_cmd = ERIAR_Write | -+ type << ERIAR_Type_shift | -+ ERIAR_ByteEn << ERIAR_ByteEn_shift | -+ (addr & 0x0FFF); -+ if (addr & 0xF000) { -+ u32 tmp; -+ -+ tmp = addr & 0xF000; -+ tmp >>= 12; -+ eri_cmd |= (tmp << 20) & 0x00F00000; -+ } -+ -+ RTL_W32(ERIAR, eri_cmd); -+ -+ for (i = 0; i < 10; i++) { -+ udelay(100); -+ -+ /* Check if the RTL8168 has completed ERI write */ -+ if (!(RTL_R32(ERIAR) & ERIAR_Flag)) -+ break; -+ } -+ -+ if (len <= 4 - val_shift) { -+ len = 0; -+ } else { -+ len -= (4 - val_shift); -+ shift = 4 - val_shift; -+ addr += 4; -+ } -+ } -+ -+ udelay(20); -+ -+ return 0; -+} -+ -+static void -+rtl8168_enable_rxdvgate(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ RTL_W8(0xF2, RTL_R8(0xF2) | BIT_3); -+ mdelay(2); -+ break; -+ } -+} -+ -+static void -+rtl8168_disable_rxdvgate(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ RTL_W8(0xF2, RTL_R8(0xF2) & ~BIT_3); -+ mdelay(2); -+ break; -+ } -+} -+ -+void -+rtl8168_wait_txrx_fifo_empty(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ int i; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ for (i = 0; i < 10; i++) { -+ udelay(100); -+ if (RTL_R32(TxConfig) & BIT_11) -+ break; -+ } -+ -+ for (i = 0; i < 10; i++) { -+ udelay(100); -+ if ((RTL_R8(MCUCmd_reg) & (Txfifo_empty | Rxfifo_empty)) == (Txfifo_empty | Rxfifo_empty)) -+ break; -+ -+ } -+ break; -+ } -+} -+ -+#ifdef ENABLE_DASH_SUPPORT -+ -+inline void -+rtl8168_enable_dash2_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr) -+{ -+ if (!tp->DASH) return; -+ -+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) -+ RTL_W8(IBIMR0, ( ISRIMR_DASH_TYPE2_ROK | ISRIMR_DASH_TYPE2_TOK | ISRIMR_DASH_TYPE2_TDU | ISRIMR_DASH_TYPE2_RDU | ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE )); -+} -+ -+static inline void -+rtl8168_disable_dash2_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr) -+{ -+ if (!tp->DASH) return; -+ -+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) -+ RTL_W8(IBIMR0, 0); -+} -+#endif -+ -+static inline void -+rtl8168_enable_hw_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr) -+{ -+ RTL_W16(IntrMask, tp->intr_mask); -+ -+#ifdef ENABLE_DASH_SUPPORT -+ if (tp->DASH) -+ rtl8168_enable_dash2_interrupt(tp, ioaddr); -+#endif -+} -+ -+static inline void -+rtl8168_disable_hw_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr) -+{ -+ RTL_W16(IntrMask, 0x0000); -+ -+#ifdef ENABLE_DASH_SUPPORT -+ if (tp->DASH) -+ rtl8168_disable_dash2_interrupt(tp, ioaddr); -+#endif -+} -+ -+ -+static inline void -+rtl8168_switch_to_hw_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr) -+{ -+ RTL_W32(TimeInt0, 0x0000); -+ -+ rtl8168_enable_hw_interrupt(tp, ioaddr); -+} -+ -+static inline void -+rtl8168_switch_to_timer_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr) -+{ -+ if (tp->use_timer_interrrupt) { -+ RTL_W32(TCTR, timer_count); -+ RTL_W32(TimeInt0, timer_count); -+ RTL_W16(IntrMask, tp->timer_intr_mask); -+ -+#ifdef ENABLE_DASH_SUPPORT -+ if (tp->DASH) -+ rtl8168_enable_dash2_interrupt(tp, ioaddr); -+#endif -+ } else { -+ rtl8168_switch_to_hw_interrupt(tp, ioaddr); -+ } -+} -+ -+static void -+rtl8168_irq_mask_and_ack(struct rtl8168_private *tp, void __iomem *ioaddr) -+{ -+ rtl8168_disable_hw_interrupt(tp, ioaddr); -+ RTL_W16(IntrStatus, RTL_R16(IntrStatus)); -+ -+#ifdef ENABLE_DASH_SUPPORT -+ if ( tp->DASH ) { -+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) { -+ RTL_W8(IBISR0, RTL_R16(IBISR0)); -+ } -+ } -+#endif -+} -+ -+static void -+rtl8168_nic_reset(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ int i; -+ -+ RTL_W32(RxConfig, (RX_DMA_BURST << RxCfgDMAShift)); -+ -+ rtl8168_enable_rxdvgate(dev); -+ -+ rtl8168_wait_txrx_fifo_empty(dev); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_1: -+ case CFG_METHOD_2: -+ case CFG_METHOD_3: -+ mdelay(10); -+ break; -+ case CFG_METHOD_4: -+ case CFG_METHOD_5: -+ case CFG_METHOD_6: -+ case CFG_METHOD_7: -+ case CFG_METHOD_8: -+ case CFG_METHOD_9: -+ case CFG_METHOD_10: -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ RTL_W8(ChipCmd, StopReq | CmdRxEnb | CmdTxEnb); -+ udelay(100); -+ break; -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ while (RTL_R8(TxPoll) & NPQ) -+ udelay(20); -+ break; -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ mdelay(2); -+ break; -+ default: -+ mdelay(10); -+ break; -+ } -+ -+ /* Soft reset the chip. */ -+ RTL_W8(ChipCmd, CmdReset); -+ -+ /* Check that the chip has finished the reset. */ -+ for (i = 100; i > 0; i--) { -+ udelay(100); -+ if ((RTL_R8(ChipCmd) & CmdReset) == 0) -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_11: -+ OOB_mutex_lock(tp); -+ OCP_write(tp, 0x10, 2, OCP_read(tp, 0x010, 2)&~0x00004000); -+ OOB_mutex_unlock(tp); -+ -+ OOB_notify(tp, OOB_CMD_RESET); -+ -+ for (i = 0; i < 10; i++) { -+ mdelay(10); -+ if (OCP_read(tp, 0x010, 2)&0x00004000) -+ break; -+ } -+ -+ for (i = 0; i < 5; i++) { -+ if ( OCP_read(tp, 0x034, 1) == 0) -+ break; -+ } -+ break; -+ } -+} -+ -+static void -+rtl8168_hw_clear_timer_int(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ RTL_W32(TimeInt0, 0x0000); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_4: -+ case CFG_METHOD_5: -+ case CFG_METHOD_6: -+ case CFG_METHOD_7: -+ case CFG_METHOD_8: -+ RTL_W32(TimeInt1, 0x0000); -+ break; -+ case CFG_METHOD_9: -+ case CFG_METHOD_10: -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ RTL_W32(TimeInt1, 0x0000); -+ RTL_W32(TimeInt2, 0x0000); -+ RTL_W32(TimeInt3, 0x0000); -+ break; -+ } -+} -+ -+static void -+rtl8168_hw_reset(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ /* Disable interrupts */ -+ rtl8168_irq_mask_and_ack(tp, ioaddr); -+ -+ rtl8168_hw_clear_timer_int(dev); -+ -+ rtl8168_nic_reset(dev); -+} -+ -+static void rtl8168_mac_loopback_test(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ struct net_device *dev = tp->dev; -+ struct sk_buff *skb, *rx_skb; -+ dma_addr_t mapping; -+ struct TxDesc *txd; -+ struct RxDesc *rxd; -+ void *tmpAddr; -+ u32 len, rx_len, rx_cmd; -+ u16 type; -+ u8 pattern; -+ int i; -+ -+ if (tp->DASH) -+ return; -+ -+ pattern = 0x5A; -+ len = 60; -+ type = htons(ETH_P_IP); -+ txd = tp->TxDescArray; -+ rxd = tp->RxDescArray; -+ rx_skb = tp->Rx_skbuff[0]; -+ RTL_W32(TxConfig, (RTL_R32(TxConfig) & ~0x00060000) | 0x00020000); -+ -+ do { -+ skb = dev_alloc_skb(len + RTK_RX_ALIGN); -+ if (unlikely(!skb)) -+ dev_printk(KERN_NOTICE, &tp->pci_dev->dev, "-ENOMEM;\n"); -+ } while (unlikely(skb == NULL)); -+ skb_reserve(skb, RTK_RX_ALIGN); -+ -+ memcpy(skb_put(skb, dev->addr_len), dev->dev_addr, dev->addr_len); -+ memcpy(skb_put(skb, dev->addr_len), dev->dev_addr, dev->addr_len); -+ memcpy(skb_put(skb, sizeof(type)), &type, sizeof(type)); -+ tmpAddr = skb_put(skb, len - 14); -+ -+ mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE); -+ pci_dma_sync_single_for_cpu(tp->pci_dev, le64_to_cpu(mapping), -+ len, PCI_DMA_TODEVICE); -+ txd->addr = cpu_to_le64(mapping); -+ txd->opts2 = 0; -+ while (1) { -+ memset(tmpAddr, pattern++, len - 14); -+ pci_dma_sync_single_for_device(tp->pci_dev, -+ le64_to_cpu(mapping), -+ len, PCI_DMA_TODEVICE); -+ txd->opts1 = cpu_to_le32(DescOwn | FirstFrag | LastFrag | len); -+ -+ RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptMyPhys); -+ -+ smp_wmb(); -+ RTL_W8(TxPoll, NPQ); /* set polling bit */ -+ -+ for (i = 0; i < 50; i++) { -+ udelay(200); -+ rx_cmd = le32_to_cpu(rxd->opts1); -+ if ((rx_cmd & DescOwn) == 0) -+ break; -+ } -+ -+ RTL_W32(RxConfig, RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | AcceptAllPhys)); -+ -+ rx_len = rx_cmd & 0x3FFF; -+ rx_len -= 4; -+ rxd->opts1 = cpu_to_le32(DescOwn | tp->rx_buf_sz); -+ -+ pci_dma_sync_single_for_cpu(tp->pci_dev, le64_to_cpu(mapping), len, PCI_DMA_TODEVICE); -+ -+ if (rx_len == len) { -+ pci_dma_sync_single_for_cpu(tp->pci_dev, le64_to_cpu(rxd->addr), tp->rx_buf_sz, PCI_DMA_FROMDEVICE); -+ i = memcmp(skb->data, rx_skb->data, rx_len); -+ pci_dma_sync_single_for_device(tp->pci_dev, le64_to_cpu(rxd->addr), tp->rx_buf_sz, PCI_DMA_FROMDEVICE); -+ if (i == 0) { -+// dev_printk(KERN_INFO, &tp->pci_dev->dev, "loopback test finished\n",rx_len,len); -+ break; -+ } -+ } -+ -+ rtl8168_hw_reset(dev); -+ rtl8168_disable_rxdvgate(dev); -+ RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); -+ } -+ tp->dirty_tx++; -+ tp->dirty_rx++; -+ tp->cur_tx++; -+ tp->cur_rx++; -+ pci_unmap_single(tp->pci_dev, le64_to_cpu(mapping), -+ len, PCI_DMA_TODEVICE); -+ RTL_W32(TxConfig, RTL_R32(TxConfig) & ~0x00060000); -+ dev_kfree_skb_any(skb); -+ RTL_W16(IntrStatus, 0xFFBF); -+} -+ -+static unsigned int -+rtl8168_xmii_reset_pending(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned int retval; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1f, 0x0000); -+ retval = mdio_read(tp, MII_BMCR) & BMCR_RESET; -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ -+ return retval; -+} -+ -+static unsigned int -+rtl8168_xmii_link_ok(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ unsigned int retval; -+ -+ retval = (RTL_R8(PHYstatus) & LinkStatus) ? 1 : 0; -+ -+ return retval; -+} -+ -+static void -+rtl8168_xmii_reset_enable(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ int i, val = 0; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); -+ -+ for (i = 0; i < 2500; i++) { -+ val = mdio_read(tp, MII_BMCR) & BMCR_RESET; -+ -+ if (!val) { -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ return; -+ } -+ -+ mdelay(1); -+ } -+ -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ -+ if (netif_msg_link(tp)) -+ printk(KERN_ERR "%s: PHY reset failed.\n", dev->name); -+} -+ -+static void -+rtl8168dp_10mbps_gphy_para(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ u8 status = RTL_R8(PHYstatus); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ if ((status & LinkStatus) && (status & _10bps)) { -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x10, 0x04EE); -+ } else { -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x10, 0x01EE); -+ } -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+} -+ -+void rtl8168_init_ring_indexes(struct rtl8168_private *tp) -+{ -+ tp->dirty_tx = 0; -+ tp->dirty_rx = 0; -+ tp->cur_tx = 0; -+ tp->cur_rx = 0; -+} -+ -+static void -+rtl8168_issue_offset_99_event(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 csi_tmp; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ if (tp->mcfg == CFG_METHOD_24 || tp->mcfg == CFG_METHOD_25 || -+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28) { -+ rtl8168_eri_write(ioaddr, 0x3FC, 4, 0x00000000, ERIAR_ExGMAC); -+ } else { -+ rtl8168_eri_write(ioaddr, 0x3FC, 4, 0x083C083C, ERIAR_ExGMAC); -+ } -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x3F8, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_0; -+ rtl8168_eri_write(ioaddr, 0x3F8, 1, csi_tmp, ERIAR_ExGMAC); -+ break; -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1EA, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_0; -+ rtl8168_eri_write(ioaddr, 0x1EA, 1, csi_tmp, ERIAR_ExGMAC); -+ break; -+ } -+} -+ -+#ifdef ENABLE_DASH_SUPPORT -+static void -+NICChkTypeEnableDashInterrupt(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if (tp->DASH) { -+ // -+ // even disconnected, enable 3 dash interrupt mask bits for in-band/out-band communication -+ // -+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) { -+ rtl8168_enable_dash2_interrupt(tp, ioaddr); -+ RTL_W16(IntrMask, (ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET)); -+ } else { -+ RTL_W16(IntrMask, (ISRIMR_DP_DASH_OK | ISRIMR_DP_HOST_OK | ISRIMR_DP_REQSYS_OK)); -+ } -+ } -+} -+#endif -+ -+static void -+rtl8168_check_link_status(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ int link_status_on; -+ unsigned long flags; -+ -+ link_status_on = tp->link_ok(dev); -+ -+ if (tp->mcfg == CFG_METHOD_11) -+ rtl8168dp_10mbps_gphy_para(dev); -+ -+ if (netif_carrier_ok(dev) != link_status_on) { -+ if (link_status_on) { -+ if (tp->mcfg == CFG_METHOD_18 || tp->mcfg == CFG_METHOD_19 || tp->mcfg == CFG_METHOD_20) { -+ if (RTL_R8(PHYstatus) & _1000bpsF) { -+ rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x00000011, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x00000005, ERIAR_ExGMAC); -+ } else { -+ rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x0000003f, ERIAR_ExGMAC); -+ } -+ } else if ((tp->mcfg == CFG_METHOD_16 || tp->mcfg == CFG_METHOD_17) && netif_running(dev)) { -+ if (tp->mcfg == CFG_METHOD_16 && (RTL_R8(PHYstatus) & _10bps)) { -+ RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptAllPhys); -+ } else if (tp->mcfg == CFG_METHOD_17) { -+ if (RTL_R8(PHYstatus) & _1000bpsF) { -+ rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x00000011, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x00000005, ERIAR_ExGMAC); -+ } else if (RTL_R8(PHYstatus) & _100bps) { -+ rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x00000005, ERIAR_ExGMAC); -+ } else { -+ rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x0000003f, ERIAR_ExGMAC); -+ } -+ } -+ } else if ((tp->mcfg == CFG_METHOD_14 || tp->mcfg == CFG_METHOD_15) && eee_enable ==1) { -+ /*Full -Duplex mode*/ -+ if (RTL_R8(PHYstatus)&FullDup) { -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0006); -+ mdio_write(tp, 0x00, 0x5a30); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ if (RTL_R8(PHYstatus) & (_10bps | _100bps)) -+ RTL_W32(TxConfig, (RTL_R32(TxConfig) & ~BIT_19) | BIT_25); -+ -+ } else { -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0006); -+ mdio_write(tp, 0x00, 0x5a00); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ if (RTL_R8(PHYstatus) & (_10bps | _100bps)) -+ RTL_W32(TxConfig, (RTL_R32(TxConfig) & ~BIT_19) | (InterFrameGap << TxInterFrameGapShift)); -+ } -+ } else if ((tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 || -+ tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 || -+ tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 || -+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 || -+ tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) && -+ netif_running(dev)) { -+ if (RTL_R8(PHYstatus)&FullDup) -+ RTL_W32(TxConfig, (RTL_R32(TxConfig) | (BIT_24 | BIT_25)) & ~BIT_19); -+ else -+ RTL_W32(TxConfig, (RTL_R32(TxConfig) | BIT_25) & ~(BIT_19 | BIT_24)); -+ } -+ -+ if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 || -+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28) { -+ /*half mode*/ -+ if (!(RTL_R8(PHYstatus)&FullDup)) { -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, MII_ADVERTISE, mdio_read(tp, MII_ADVERTISE)&~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM)); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ } -+ } -+ -+ rtl8168_hw_start(dev); -+ -+ netif_carrier_on(dev); -+ -+ netif_wake_queue(dev); -+ -+ if (netif_msg_ifup(tp)) -+ printk(KERN_INFO PFX "%s: link up\n", dev->name); -+ } else { -+ if (netif_msg_ifdown(tp)) -+ printk(KERN_INFO PFX "%s: link down\n", dev->name); -+ -+ netif_stop_queue(dev); -+ -+ netif_carrier_off(dev); -+ -+ rtl8168_hw_reset(dev); -+ -+ rtl8168_tx_clear(tp); -+ -+ rtl8168_rx_clear(tp); -+ -+ rtl8168_init_ring(dev); -+ -+ rtl8168_set_speed(dev, tp->autoneg, tp->speed, tp->duplex); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ if (tp->org_pci_offset_99 & BIT_2) -+ tp->issue_offset_99_event = TRUE; -+ break; -+ } -+ -+#ifdef ENABLE_DASH_SUPPORT -+ if (tp->DASH) { -+ NICChkTypeEnableDashInterrupt(tp); -+ } -+#endif -+ } -+ } -+ -+ if (!link_status_on) { -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ if (tp->issue_offset_99_event) { -+ if (!(RTL_R8(PHYstatus) & PowerSaveStatus)) { -+ tp->issue_offset_99_event = FALSE; -+ rtl8168_issue_offset_99_event(tp); -+ } -+ } -+ break; -+ } -+ } -+} -+ -+static void -+rtl8168_link_option(u8 *aut, -+ u16 *spd, -+ u8 *dup) -+{ -+ if ((*spd != SPEED_1000) && (*spd != SPEED_100) && (*spd != SPEED_10)) -+ *spd = SPEED_1000; -+ -+ if ((*dup != DUPLEX_FULL) && (*dup != DUPLEX_HALF)) -+ *dup = DUPLEX_FULL; -+ -+ if ((*aut != AUTONEG_ENABLE) && (*aut != AUTONEG_DISABLE)) -+ *aut = AUTONEG_ENABLE; -+} -+ -+void -+rtl8168_wait_ll_share_fifo_ready(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ int i; -+ -+ for (i = 0; i < 10; i++) { -+ udelay(100); -+ if (RTL_R16(0xD2) & BIT_9) -+ break; -+ } -+} -+ -+static void -+rtl8168_disable_pci_offset_99(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 csi_tmp; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x3F2, 2, ERIAR_ExGMAC); -+ csi_tmp &= ~(BIT_0 | BIT_1); -+ rtl8168_eri_write(ioaddr, 0x3F2, 2, csi_tmp, ERIAR_ExGMAC); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_26: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ rtl8168_csi_fun0_write_byte(tp, 0x99, 0x00); -+ break; -+ } -+} -+ -+static void -+rtl8168_enable_pci_offset_99(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 csi_tmp; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_26: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ rtl8168_csi_fun0_write_byte(tp, 0x99, tp->org_pci_offset_99); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x3F2, 2, ERIAR_ExGMAC); -+ csi_tmp &= ~(BIT_0 | BIT_1); -+ if (!(tp->org_pci_offset_99 & (BIT_5 | BIT_6))) -+ csi_tmp |= BIT_1; -+ if (!(tp->org_pci_offset_99 & BIT_2)) -+ csi_tmp |= BIT_0; -+ rtl8168_eri_write(ioaddr, 0x3F2, 2, csi_tmp, ERIAR_ExGMAC); -+ break; -+ } -+} -+ -+static void -+rtl8168_init_pci_offset_99(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 csi_tmp; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_26: -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x5C2, 1, ERIAR_ExGMAC); -+ csi_tmp &= ~BIT_1; -+ rtl8168_eri_write(ioaddr, 0x5C2, 1, csi_tmp, ERIAR_ExGMAC); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x3F2, 2, ERIAR_ExGMAC); -+ csi_tmp &= ~( BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12 | BIT_13 | BIT_14 | BIT_15 ); -+ csi_tmp |= ( BIT_9 | BIT_10 | BIT_13 | BIT_14 | BIT_15 ); -+ rtl8168_eri_write(ioaddr, 0x3F2, 2, csi_tmp, ERIAR_ExGMAC); -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x3F5, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_6 | BIT_7; -+ rtl8168_eri_write(ioaddr, 0x3F5, 1, csi_tmp, ERIAR_ExGMAC); -+ mac_ocp_write(tp, 0xE02C, 0x1880); -+ mac_ocp_write(tp, 0xE02E, 0x4880); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_26: -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x5C8, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_0; -+ rtl8168_eri_write(ioaddr, 0x5C8, 1, csi_tmp, ERIAR_ExGMAC); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_23: -+ rtl8168_eri_write(ioaddr, 0x2E8, 2, 0x883C, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x2EA, 2, 0x8C12, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x2EC, 2, 0x9003, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x2E2, 2, 0x883C, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x2E4, 2, 0x8C12, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x2E6, 2, 0x9003, ERIAR_ExGMAC); -+ break; -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ rtl8168_eri_write(ioaddr, 0x2E8, 2, 0x9003, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x2EA, 2, 0x9003, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x2EC, 2, 0x9003, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x2E2, 2, 0x883C, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x2E4, 2, 0x8C12, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x2E6, 2, 0x9003, ERIAR_ExGMAC); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_26: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ RTL_W8(0xB6, RTL_R8(0xB6) | BIT_0); -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x5C8, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_0; -+ rtl8168_eri_write(ioaddr, 0x5C8, 1, csi_tmp, ERIAR_ExGMAC); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x3FA, 2, ERIAR_ExGMAC); -+ csi_tmp |= BIT_14; -+ rtl8168_eri_write(ioaddr, 0x3FA, 2, csi_tmp, ERIAR_ExGMAC); -+ break; -+ } -+ -+ rtl8168_enable_pci_offset_99(tp); -+} -+ -+static void -+rtl8168_disable_pci_offset_180(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 csi_tmp; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1E2, 1, ERIAR_ExGMAC); -+ csi_tmp &= ~BIT_2; -+ rtl8168_eri_write(ioaddr, 0x1E2, 1, csi_tmp, ERIAR_ExGMAC); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_26: -+ rtl8168_eri_write(ioaddr, 0x1E9, 1, 0x0A, ERIAR_ExGMAC); -+ break; -+ } -+} -+ -+static void -+rtl8168_enable_pci_offset_180(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 csi_tmp; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_25: -+ case CFG_METHOD_28: -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1E8, 4, ERIAR_ExGMAC); -+ csi_tmp &= ~(0x0000FF00); -+ csi_tmp |= (0x00006400); -+ rtl8168_eri_write(ioaddr, 0x1E8, 4, csi_tmp, ERIAR_ExGMAC); -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1E4, 4, ERIAR_ExGMAC); -+ csi_tmp &= ~(0x0000FF00); -+ rtl8168_eri_write(ioaddr, 0x1E4, 4, csi_tmp, ERIAR_ExGMAC); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1E2, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_2; -+ rtl8168_eri_write(ioaddr, 0x1E2, 1, csi_tmp, ERIAR_ExGMAC); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_26: -+ rtl8168_eri_write(ioaddr, 0x1E9, 1, 0x64, ERIAR_ExGMAC); -+ break; -+ } -+ -+ mac_ocp_write(tp, 0xE094, 0x0000); -+} -+ -+static void -+rtl8168_init_pci_offset_180(struct rtl8168_private *tp) -+{ -+ if (tp->org_pci_offset_180 & (BIT_0|BIT_1)) -+ rtl8168_enable_pci_offset_180(tp); -+ else -+ rtl8168_disable_pci_offset_180(tp); -+} -+ -+static void -+rtl8168_set_pci_99_180_exit_driver_para(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ rtl8168_issue_offset_99_event(tp); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ rtl8168_disable_pci_offset_99(tp); -+ break; -+ } -+ switch (tp->mcfg) { -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ rtl8168_disable_pci_offset_180(tp); -+ break; -+ } -+} -+ -+static void -+rtl8168_hw_d3_para(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ unsigned long flags; -+ -+ RTL_W16(RxMaxSize, RX_BUF_SIZE); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ RTL_W8(0xF1, RTL_R8(0xF1) & ~BIT_7); -+ RTL_W8(Cfg9346, Cfg9346_Unlock); -+ RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7); -+ RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0); -+ RTL_W8(Cfg9346, Cfg9346_Lock); -+ break; -+ } -+ -+ if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 || -+ tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 || -+ tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 || -+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28) { -+ rtl8168_eri_write(ioaddr, 0x2F8, 2, 0x0064, ERIAR_ExGMAC); -+ } -+ -+ if (tp->bios_setting & BIT_28) { -+ if (tp->mcfg == CFG_METHOD_18 || tp->mcfg == CFG_METHOD_19 || -+ tp->mcfg == CFG_METHOD_20) { -+ u32 gphy_val; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x04, 0x0061); -+ mdio_write(tp, 0x09, 0x0000); -+ mdio_write(tp, 0x00, 0x9200); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B80); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val &= ~BIT_7; -+ mdio_write(tp, 0x06, gphy_val); -+ mdelay(1); -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x002C); -+ gphy_val = mdio_read(tp, 0x16); -+ gphy_val &= ~BIT_10; -+ mdio_write(tp, 0x16, gphy_val); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ } -+ } -+ -+ rtl8168_set_pci_99_180_exit_driver_para(dev); -+ -+ /*disable ocp phy power saving*/ -+ if (tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 || -+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 || -+ tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write_phy_ocp(tp, 0x0C41, 0x13, 0x0000); -+ mdio_write_phy_ocp(tp, 0x0C41, 0x13, 0x0500); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ } -+ -+ rtl8168_disable_rxdvgate(dev); -+} -+ -+#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) -+ -+static void -+rtl8168_get_hw_wol(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ u8 options; -+ u32 csi_tmp; -+ unsigned long flags; -+ -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ tp->wol_opts = 0; -+ options = RTL_R8(Config1); -+ if (!(options & PMEnable)) -+ goto out_unlock; -+ -+ options = RTL_R8(Config3); -+ if (options & LinkUp) -+ tp->wol_opts |= WAKE_PHY; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ csi_tmp = rtl8168_eri_read(ioaddr, 0xDE, 1, ERIAR_ExGMAC); -+ if (csi_tmp & BIT_0) -+ tp->wol_opts |= WAKE_MAGIC; -+ break; -+ default: -+ if (options & MagicPacket) -+ tp->wol_opts |= WAKE_MAGIC; -+ break; -+ } -+ -+ options = RTL_R8(Config5); -+ if (options & UWF) -+ tp->wol_opts |= WAKE_UCAST; -+ if (options & BWF) -+ tp->wol_opts |= WAKE_BCAST; -+ if (options & MWF) -+ tp->wol_opts |= WAKE_MCAST; -+ -+out_unlock: -+ tp->wol_enabled = (tp->wol_opts) ? WOL_ENABLED : WOL_DISABLED; -+ -+ spin_unlock_irqrestore(&tp->lock, flags); -+} -+ -+static void -+rtl8168_set_hw_wol(struct net_device *dev, u32 wolopts) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ int i,tmp; -+ u32 csi_tmp; -+ static struct { -+ u32 opt; -+ u16 reg; -+ u8 mask; -+ } cfg[] = { -+ { WAKE_PHY, Config3, LinkUp }, -+ { WAKE_UCAST, Config5, UWF }, -+ { WAKE_BCAST, Config5, BWF }, -+ { WAKE_MCAST, Config5, MWF }, -+ { WAKE_ANY, Config5, LanWake }, -+ { WAKE_MAGIC, Config3, MagicPacket }, -+ }; -+ -+ RTL_W8(Cfg9346, Cfg9346_Unlock); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ tmp = ARRAY_SIZE(cfg) - 1; -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0xDE, 1, ERIAR_ExGMAC); -+ if (wolopts & WAKE_MAGIC) -+ csi_tmp |= BIT_0; -+ else -+ csi_tmp &= ~BIT_0; -+ rtl8168_eri_write(ioaddr, 0xDE, 1, csi_tmp, ERIAR_ExGMAC); -+ break; -+ default: -+ tmp = ARRAY_SIZE(cfg); -+ break; -+ } -+ -+ for (i = 0; i < tmp; i++) { -+ u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; -+ if (wolopts & cfg[i].opt) -+ options |= cfg[i].mask; -+ RTL_W8(cfg[i].reg, options); -+ } -+ -+ RTL_W8(Cfg9346, Cfg9346_Lock); -+} -+ -+static void -+rtl8168_powerdown_pll(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if (tp->wol_enabled == WOL_ENABLED || tp->DASH || tp->EnableKCPOffload) { -+ int auto_nego; -+ int giga_ctrl; -+ u16 val; -+ unsigned long flags; -+ -+ rtl8168_set_hw_wol(dev, tp->wol_opts); -+ -+ if (tp->mcfg == CFG_METHOD_16 || tp->mcfg == CFG_METHOD_17 || -+ tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 || -+ tp->mcfg == CFG_METHOD_24 || tp->mcfg == CFG_METHOD_25 || -+ tp->mcfg == CFG_METHOD_26 || tp->mcfg == CFG_METHOD_23 || -+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 || -+ tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ RTL_W8(Cfg9346, Cfg9346_Unlock); -+ RTL_W8(Config2, RTL_R8(Config2) | PMSTS_En); -+ RTL_W8(Cfg9346, Cfg9346_Lock); -+ } -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0000); -+ auto_nego = mdio_read(tp, MII_ADVERTISE); -+ auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL -+ | ADVERTISE_100HALF | ADVERTISE_100FULL); -+ -+ val = mdio_read(tp, MII_LPA); -+ -+#ifdef CONFIG_DOWN_SPEED_100 -+ auto_nego |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10HALF | ADVERTISE_10FULL); -+#else -+ if (val & (LPA_10HALF | LPA_10FULL)) -+ auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL); -+ else -+ auto_nego |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10HALF | ADVERTISE_10FULL); -+#endif -+ -+ if (tp->DASH) -+ auto_nego |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10HALF | ADVERTISE_10FULL); -+ -+ if (((tp->mcfg == CFG_METHOD_7) || (tp->mcfg == CFG_METHOD_8)) && (RTL_R16(CPlusCmd) & ASF)) -+ auto_nego |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10HALF | ADVERTISE_10FULL); -+ -+ giga_ctrl = mdio_read(tp, MII_CTRL1000) & ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); -+ mdio_write(tp, MII_ADVERTISE, auto_nego); -+ mdio_write(tp, MII_CTRL1000, giga_ctrl); -+ mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ -+ RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); -+ -+ return; -+ } -+ -+ if (tp->DASH) -+ return; -+ -+ if (((tp->mcfg == CFG_METHOD_7) || (tp->mcfg == CFG_METHOD_8)) && (RTL_R16(CPlusCmd) & ASF)) -+ return; -+ -+ rtl8168_phy_power_down(dev); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_9: -+ case CFG_METHOD_10: -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ RTL_W8(PMCH, RTL_R8(PMCH) & ~BIT_7); -+ break; -+ } -+} -+ -+static void rtl8168_powerup_pll(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_9: -+ case CFG_METHOD_10: -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ RTL_W8(PMCH, RTL_R8(PMCH) | BIT_7 | BIT_6); -+ break; -+ } -+ -+ rtl8168_phy_power_up(dev); -+} -+ -+static void -+rtl8168_get_wol(struct net_device *dev, -+ struct ethtool_wolinfo *wol) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ u8 options; -+ unsigned long flags; -+ -+ wol->wolopts = 0; -+ -+ if (tp->mcfg == CFG_METHOD_DEFAULT) { -+ wol->supported = 0; -+ return; -+ } else { -+ wol->supported = WAKE_ANY; -+ } -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ options = RTL_R8(Config1); -+ if (!(options & PMEnable)) -+ goto out_unlock; -+ -+ wol->wolopts = tp->wol_opts; -+ -+out_unlock: -+ spin_unlock_irqrestore(&tp->lock, flags); -+} -+ -+static int -+rtl8168_set_wol(struct net_device *dev, -+ struct ethtool_wolinfo *wol) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned long flags; -+ -+ if (tp->mcfg == CFG_METHOD_DEFAULT) -+ return -EOPNOTSUPP; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ tp->wol_opts = wol->wolopts; -+ -+ tp->wol_enabled = (tp->wol_opts) ? WOL_ENABLED : WOL_DISABLED; -+ -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ return 0; -+} -+ -+static void -+rtl8168_get_drvinfo(struct net_device *dev, -+ struct ethtool_drvinfo *info) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ strcpy(info->driver, MODULENAME); -+ strcpy(info->version, RTL8168_VERSION); -+ strcpy(info->bus_info, pci_name(tp->pci_dev)); -+ info->regdump_len = R8168_REGS_DUMP_SIZE; -+ info->eedump_len = tp->eeprom_len; -+} -+ -+static int -+rtl8168_get_regs_len(struct net_device *dev) -+{ -+ return R8168_REGS_DUMP_SIZE; -+} -+ -+static int -+rtl8168_set_speed_xmii(struct net_device *dev, -+ u8 autoneg, -+ u16 speed, -+ u8 duplex) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ int auto_nego = 0; -+ int giga_ctrl = 0; -+ int bmcr_true_force = 0; -+ unsigned long flags; -+ -+ if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ //Disable Giga Lite -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0A42); -+ ClearEthPhyBit(tp, 0x14, BIT_9); -+ mdio_write(tp, 0x1F, 0x0A40); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ } -+ -+ if ((speed != SPEED_1000) && -+ (speed != SPEED_100) && -+ (speed != SPEED_10)) { -+ speed = SPEED_1000; -+ duplex = DUPLEX_FULL; -+ } -+ -+ auto_nego = mdio_read(tp, MII_ADVERTISE); -+ auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); -+ -+ giga_ctrl = mdio_read(tp, MII_CTRL1000); -+ giga_ctrl &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); -+ -+ if ((autoneg == AUTONEG_ENABLE) || (speed == SPEED_1000)) { -+ /*n-way force*/ -+ if ((speed == SPEED_10) && (duplex == DUPLEX_HALF)) { -+ auto_nego |= ADVERTISE_10HALF; -+ } else if ((speed == SPEED_10) && (duplex == DUPLEX_FULL)) { -+ auto_nego |= ADVERTISE_10HALF | -+ ADVERTISE_10FULL; -+ } else if ((speed == SPEED_100) && (duplex == DUPLEX_HALF)) { -+ auto_nego |= ADVERTISE_100HALF | -+ ADVERTISE_10HALF | -+ ADVERTISE_10FULL; -+ } else if ((speed == SPEED_100) && (duplex == DUPLEX_FULL)) { -+ auto_nego |= ADVERTISE_100HALF | -+ ADVERTISE_100FULL | -+ ADVERTISE_10HALF | -+ ADVERTISE_10FULL; -+ } else if (speed == SPEED_1000) { -+ giga_ctrl |= ADVERTISE_1000HALF | -+ ADVERTISE_1000FULL; -+ -+ auto_nego |= ADVERTISE_100HALF | -+ ADVERTISE_100FULL | -+ ADVERTISE_10HALF | -+ ADVERTISE_10FULL; -+ } -+ -+ //flow control -+ if (dev->mtu <= ETH_DATA_LEN) -+ auto_nego |= ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM; -+ -+ tp->phy_auto_nego_reg = auto_nego; -+ tp->phy_1000_ctrl_reg = giga_ctrl; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, MII_ADVERTISE, auto_nego); -+ mdio_write(tp, MII_CTRL1000, giga_ctrl); -+ mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ mdelay(20); -+ } else { -+ /*true force*/ -+#ifndef BMCR_SPEED100 -+#define BMCR_SPEED100 0x0040 -+#endif -+ -+#ifndef BMCR_SPEED10 -+#define BMCR_SPEED10 0x0000 -+#endif -+ if ((speed == SPEED_10) && (duplex == DUPLEX_HALF)) { -+ bmcr_true_force = BMCR_SPEED10; -+ } else if ((speed == SPEED_10) && (duplex == DUPLEX_FULL)) { -+ bmcr_true_force = BMCR_SPEED10 | BMCR_FULLDPLX; -+ } else if ((speed == SPEED_100) && (duplex == DUPLEX_HALF)) { -+ bmcr_true_force = BMCR_SPEED100; -+ } else if ((speed == SPEED_100) && (duplex == DUPLEX_FULL)) { -+ bmcr_true_force = BMCR_SPEED100 | BMCR_FULLDPLX; -+ } -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, MII_BMCR, bmcr_true_force); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ } -+ -+ tp->autoneg = autoneg; -+ tp->speed = speed; -+ tp->duplex = duplex; -+ -+ if (tp->mcfg == CFG_METHOD_11) -+ rtl8168dp_10mbps_gphy_para(dev); -+ -+ return 0; -+} -+ -+static int -+rtl8168_set_speed(struct net_device *dev, -+ u8 autoneg, -+ u16 speed, -+ u8 duplex) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ int ret; -+ -+ ret = tp->set_speed(dev, autoneg, speed, duplex); -+ -+ return ret; -+} -+ -+static int -+rtl8168_set_settings(struct net_device *dev, -+ struct ethtool_cmd *cmd) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ int ret; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ ret = rtl8168_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ return ret; -+} -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) -+static u32 -+rtl8168_get_tx_csum(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ u32 ret; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ ret = ((dev->features & NETIF_F_IP_CSUM) != 0); -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ return ret; -+} -+ -+static u32 -+rtl8168_get_rx_csum(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ u32 ret; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ ret = tp->cp_cmd & RxChkSum; -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ return ret; -+} -+ -+static int -+rtl8168_set_tx_csum(struct net_device *dev, -+ u32 data) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned long flags; -+ -+ if (tp->mcfg == CFG_METHOD_DEFAULT) -+ return -EOPNOTSUPP; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ if (data) -+ dev->features |= NETIF_F_IP_CSUM; -+ else -+ dev->features &= ~NETIF_F_IP_CSUM; -+ -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ return 0; -+} -+ -+static int -+rtl8168_set_rx_csum(struct net_device *dev, -+ u32 data) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ unsigned long flags; -+ -+ if (tp->mcfg == CFG_METHOD_DEFAULT) -+ return -EOPNOTSUPP; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ if (data) -+ tp->cp_cmd |= RxChkSum; -+ else -+ tp->cp_cmd &= ~RxChkSum; -+ -+ RTL_W16(CPlusCmd, tp->cp_cmd); -+ -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ return 0; -+} -+#endif -+ -+#ifdef CONFIG_R8168_VLAN -+ -+static inline u32 -+rtl8168_tx_vlan_tag(struct rtl8168_private *tp, -+ struct sk_buff *skb) -+{ -+ u32 tag; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) -+ tag = (tp->vlgrp && vlan_tx_tag_present(skb)) ? -+ TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) -+ tag = (vlan_tx_tag_present(skb)) ? -+ TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; -+#else -+ tag = (skb_vlan_tag_present(skb)) ? -+ TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; -+#endif -+ -+ return tag; -+} -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) -+ -+static void -+rtl8168_vlan_rx_register(struct net_device *dev, -+ struct vlan_group *grp) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ tp->vlgrp = grp; -+ if (tp->vlgrp) -+ tp->cp_cmd |= RxVlan; -+ else -+ tp->cp_cmd &= ~RxVlan; -+ RTL_W16(CPlusCmd, tp->cp_cmd); -+ RTL_R16(CPlusCmd); -+ spin_unlock_irqrestore(&tp->lock, flags); -+} -+ -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -+static void -+rtl8168_vlan_rx_kill_vid(struct net_device *dev, -+ unsigned short vid) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) -+ if (tp->vlgrp) -+ tp->vlgrp->vlan_devices[vid] = NULL; -+#else -+ vlan_group_set_device(tp->vlgrp, vid, NULL); -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) -+ spin_unlock_irqrestore(&tp->lock, flags); -+} -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -+ -+static int -+rtl8168_rx_vlan_skb(struct rtl8168_private *tp, -+ struct RxDesc *desc, -+ struct sk_buff *skb) -+{ -+ u32 opts2 = le32_to_cpu(desc->opts2); -+ int ret = -1; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) -+ if (tp->vlgrp && (opts2 & RxVlanTag)) { -+ rtl8168_rx_hwaccel_skb(skb, tp->vlgrp, -+ swab16(opts2 & 0xffff)); -+ ret = 0; -+ } -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) -+ if (opts2 & RxVlanTag) -+ __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff)); -+#else -+ if (opts2 & RxVlanTag) -+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); -+#endif -+ -+ desc->opts2 = 0; -+ return ret; -+} -+ -+#else /* !CONFIG_R8168_VLAN */ -+ -+static inline u32 -+rtl8168_tx_vlan_tag(struct rtl8168_private *tp, -+ struct sk_buff *skb) -+{ -+ return 0; -+} -+ -+static int -+rtl8168_rx_vlan_skb(struct rtl8168_private *tp, -+ struct RxDesc *desc, -+ struct sk_buff *skb) -+{ -+ return -1; -+} -+ -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) -+static u32 rtl8168_fix_features(struct net_device *dev, u32 features) -+#else -+static netdev_features_t rtl8168_fix_features(struct net_device *dev, -+ netdev_features_t features) -+#endif -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ if (dev->mtu > ETH_DATA_LEN) { -+ features &= ~NETIF_F_ALL_TSO; -+ features &= ~NETIF_F_ALL_CSUM; -+ } -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ return features; -+} -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) -+static int rtl8168_hw_set_features(struct net_device *dev, u32 features) -+#else -+static int rtl8168_hw_set_features(struct net_device *dev, -+ netdev_features_t features) -+#endif -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if (features & NETIF_F_RXCSUM) -+ tp->cp_cmd |= RxChkSum; -+ else -+ tp->cp_cmd &= ~RxChkSum; -+ -+ if (dev->features & NETIF_F_HW_VLAN_RX) -+ tp->cp_cmd |= RxVlan; -+ else -+ tp->cp_cmd &= ~RxVlan; -+ -+ RTL_W16(CPlusCmd, tp->cp_cmd); -+ RTL_R16(CPlusCmd); -+ -+ return 0; -+} -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) -+static int rtl8168_set_features(struct net_device *dev, u32 features) -+#else -+static int rtl8168_set_features(struct net_device *dev, -+ netdev_features_t features) -+#endif -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ rtl8168_hw_set_features(dev, features); -+ -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ return 0; -+} -+ -+#endif -+ -+static void rtl8168_gset_xmii(struct net_device *dev, -+ struct ethtool_cmd *cmd) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ u8 status; -+ unsigned long flags; -+ -+ cmd->supported = SUPPORTED_10baseT_Half | -+ SUPPORTED_10baseT_Full | -+ SUPPORTED_100baseT_Half | -+ SUPPORTED_100baseT_Full | -+ SUPPORTED_1000baseT_Full | -+ SUPPORTED_Autoneg | -+ SUPPORTED_TP; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0000); -+ cmd->autoneg = (mdio_read(tp, MII_BMCR) & BMCR_ANENABLE) ? 1 : 0; -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg; -+ -+ if (tp->phy_auto_nego_reg & ADVERTISE_10HALF) -+ cmd->advertising |= ADVERTISED_10baseT_Half; -+ if (tp->phy_auto_nego_reg & ADVERTISE_10FULL) -+ cmd->advertising |= ADVERTISED_10baseT_Full; -+ if (tp->phy_auto_nego_reg & ADVERTISE_100HALF) -+ cmd->advertising |= ADVERTISED_100baseT_Half; -+ if (tp->phy_auto_nego_reg & ADVERTISE_100FULL) -+ cmd->advertising |= ADVERTISED_100baseT_Full; -+ if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL) -+ cmd->advertising |= ADVERTISED_1000baseT_Full; -+ -+ status = RTL_R8(PHYstatus); -+ -+ if (status & _1000bpsF) -+ cmd->speed = SPEED_1000; -+ else if (status & _100bps) -+ cmd->speed = SPEED_100; -+ else if (status & _10bps) -+ cmd->speed = SPEED_10; -+ -+ if (status & TxFlowCtrl) -+ cmd->advertising |= ADVERTISED_Asym_Pause; -+ -+ if (status & RxFlowCtrl) -+ cmd->advertising |= ADVERTISED_Pause; -+ -+ cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ? -+ DUPLEX_FULL : DUPLEX_HALF; -+ -+ -+} -+ -+static int -+rtl8168_get_settings(struct net_device *dev, -+ struct ethtool_cmd *cmd) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ tp->get_settings(dev, cmd); -+ -+ return 0; -+} -+ -+static void rtl8168_get_regs(struct net_device *dev, struct ethtool_regs *regs, -+ void *p) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ unsigned int i; -+ u8 *data = p; -+ unsigned long flags; -+ -+ if (regs->len < R8168_REGS_DUMP_SIZE) -+ return /* -EINVAL */; -+ -+ memset(p, 0, regs->len); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ for (i = 0; i < R8168_MAC_REGS_SIZE; i++) -+ *data++ = readb(ioaddr + i); -+ spin_unlock_irqrestore(&tp->lock, flags); -+ data = (u8*)p + 256; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0000); -+ for (i = 0; i < R8168_PHY_REGS_SIZE/2; i++) { -+ *(u16*)data = mdio_read(tp, i); -+ data += 2; -+ } -+ data = (u8*)p + 256 * 2; -+ -+ for (i = 0; i < R8168_EPHY_REGS_SIZE/2; i++) { -+ *(u16*)data = rtl8168_ephy_read(ioaddr, i); -+ data += 2; -+ } -+ data = (u8*)p + 256 * 3; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_1: -+ case CFG_METHOD_2: -+ case CFG_METHOD_3: -+ /* RTL8168B does not support Extend GMAC */ -+ break; -+ default: -+ for (i = 0; i < R8168_ERI_REGS_SIZE; i+=4) { -+ *(u32*)data = rtl8168_eri_read(ioaddr, i , 4, ERIAR_ExGMAC); -+ data += 4; -+ } -+ break; -+ } -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+} -+ -+static u32 -+rtl8168_get_msglevel(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ return tp->msg_enable; -+} -+ -+static void -+rtl8168_set_msglevel(struct net_device *dev, -+ u32 value) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ tp->msg_enable = value; -+} -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33) -+static int rtl8168_get_stats_count(struct net_device *dev) -+{ -+ return ARRAY_SIZE(rtl8168_gstrings); -+} -+#else -+static int rtl8168_get_sset_count(struct net_device *dev, int sset) -+{ -+ switch (sset) { -+ case ETH_SS_STATS: -+ return ARRAY_SIZE(rtl8168_gstrings); -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+#endif -+static void -+rtl8168_get_ethtool_stats(struct net_device *dev, -+ struct ethtool_stats *stats, -+ u64 *data) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ struct rtl8168_counters *counters; -+ dma_addr_t paddr; -+ u32 cmd; -+ u32 WaitCnt; -+ unsigned long flags; -+ -+ ASSERT_RTNL(); -+ -+ counters = tp->tally_vaddr; -+ paddr = tp->tally_paddr; -+ if (!counters) -+ return; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ RTL_W32(CounterAddrHigh, (u64)paddr >> 32); -+ cmd = (u64)paddr & DMA_BIT_MASK(32); -+ RTL_W32(CounterAddrLow, cmd); -+ RTL_W32(CounterAddrLow, cmd | CounterDump); -+ -+ WaitCnt = 0; -+ while (RTL_R32(CounterAddrLow) & CounterDump) { -+ udelay(10); -+ -+ WaitCnt++; -+ if (WaitCnt > 20) -+ break; -+ } -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ data[0] = le64_to_cpu(counters->tx_packets); -+ data[1] = le64_to_cpu(counters->rx_packets); -+ data[2] = le64_to_cpu(counters->tx_errors); -+ data[3] = le32_to_cpu(counters->rx_errors); -+ data[4] = le16_to_cpu(counters->rx_missed); -+ data[5] = le16_to_cpu(counters->align_errors); -+ data[6] = le32_to_cpu(counters->tx_one_collision); -+ data[7] = le32_to_cpu(counters->tx_multi_collision); -+ data[8] = le64_to_cpu(counters->rx_unicast); -+ data[9] = le64_to_cpu(counters->rx_broadcast); -+ data[10] = le32_to_cpu(counters->rx_multicast); -+ data[11] = le16_to_cpu(counters->tx_aborted); -+ data[12] = le16_to_cpu(counters->tx_underun); -+} -+ -+static void -+rtl8168_get_strings(struct net_device *dev, -+ u32 stringset, -+ u8 *data) -+{ -+ switch (stringset) { -+ case ETH_SS_STATS: -+ memcpy(data, *rtl8168_gstrings, sizeof(rtl8168_gstrings)); -+ break; -+ } -+} -+static int rtl_get_eeprom_len(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ return tp->eeprom_len; -+} -+ -+static int rtl_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *buf) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ int i,j,ret; -+ int start_w, end_w; -+ int VPD_addr, VPD_data; -+ u32 *eeprom_buff; -+ u16 tmp; -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if (tp->eeprom_type == EEPROM_TYPE_NONE) { -+ dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Detect none EEPROM\n"); -+ return -EOPNOTSUPP; -+ } else if (eeprom->len == 0 || (eeprom->offset+eeprom->len) > tp->eeprom_len) { -+ dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Invalid parameter\n"); -+ return -EINVAL; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_9: -+ case CFG_METHOD_10: -+ VPD_addr = 0xCE; -+ VPD_data = 0xD0; -+ break; -+ -+ case CFG_METHOD_1: -+ case CFG_METHOD_2: -+ case CFG_METHOD_3: -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ return -EOPNOTSUPP; -+ default: -+ VPD_addr = 0xD2; -+ VPD_data = 0xD4; -+ break; -+ } -+ -+ start_w = eeprom->offset >> 2; -+ end_w = (eeprom->offset + eeprom->len - 1) >> 2; -+ -+ eeprom_buff = kmalloc(sizeof(u32)*(end_w - start_w + 1), GFP_KERNEL); -+ if (!eeprom_buff) -+ return -ENOMEM; -+ -+ RTL_W8(Cfg9346, Cfg9346_Unlock); -+ ret = -EFAULT; -+ for (i=start_w; i<=end_w; i++) { -+ pci_write_config_word(tp->pci_dev, VPD_addr, (u16)i*4); -+ ret = -EFAULT; -+ for (j = 0; j < 10; j++) { -+ udelay(400); -+ pci_read_config_word(tp->pci_dev, VPD_addr, &tmp); -+ if (tmp&0x8000) { -+ ret = 0; -+ break; -+ } -+ } -+ -+ if (ret) -+ break; -+ -+ pci_read_config_dword(tp->pci_dev, VPD_data, &eeprom_buff[i-start_w]); -+ } -+ RTL_W8(Cfg9346, Cfg9346_Lock); -+ -+ if (!ret) -+ memcpy(buf, (u8 *)eeprom_buff + (eeprom->offset & 3), eeprom->len); -+ -+ kfree(eeprom_buff); -+ -+ return ret; -+} -+ -+#undef ethtool_op_get_link -+#define ethtool_op_get_link _kc_ethtool_op_get_link -+u32 _kc_ethtool_op_get_link(struct net_device *dev) -+{ -+ return netif_carrier_ok(dev) ? 1 : 0; -+} -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) -+#undef ethtool_op_get_sg -+#define ethtool_op_get_sg _kc_ethtool_op_get_sg -+u32 _kc_ethtool_op_get_sg(struct net_device *dev) -+{ -+#ifdef NETIF_F_SG -+ return (dev->features & NETIF_F_SG) != 0; -+#else -+ return 0; -+#endif -+} -+ -+#undef ethtool_op_set_sg -+#define ethtool_op_set_sg _kc_ethtool_op_set_sg -+int _kc_ethtool_op_set_sg(struct net_device *dev, u32 data) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ if (tp->mcfg == CFG_METHOD_DEFAULT) -+ return -EOPNOTSUPP; -+ -+#ifdef NETIF_F_SG -+ if (data) -+ dev->features |= NETIF_F_SG; -+ else -+ dev->features &= ~NETIF_F_SG; -+#endif -+ -+ return 0; -+} -+#endif -+ -+static const struct ethtool_ops rtl8168_ethtool_ops = { -+ .get_drvinfo = rtl8168_get_drvinfo, -+ .get_regs_len = rtl8168_get_regs_len, -+ .get_link = ethtool_op_get_link, -+ .get_settings = rtl8168_get_settings, -+ .set_settings = rtl8168_set_settings, -+ .get_msglevel = rtl8168_get_msglevel, -+ .set_msglevel = rtl8168_set_msglevel, -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) -+ .get_rx_csum = rtl8168_get_rx_csum, -+ .set_rx_csum = rtl8168_set_rx_csum, -+ .get_tx_csum = rtl8168_get_tx_csum, -+ .set_tx_csum = rtl8168_set_tx_csum, -+ .get_sg = ethtool_op_get_sg, -+ .set_sg = ethtool_op_set_sg, -+#ifdef NETIF_F_TSO -+ .get_tso = ethtool_op_get_tso, -+ .set_tso = ethtool_op_set_tso, -+#endif -+#endif -+ .get_regs = rtl8168_get_regs, -+ .get_wol = rtl8168_get_wol, -+ .set_wol = rtl8168_set_wol, -+ .get_strings = rtl8168_get_strings, -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33) -+ .get_stats_count = rtl8168_get_stats_count, -+#else -+ .get_sset_count = rtl8168_get_sset_count, -+#endif -+ .get_ethtool_stats = rtl8168_get_ethtool_stats, -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+#ifdef ETHTOOL_GPERMADDR -+ .get_perm_addr = ethtool_op_get_perm_addr, -+#endif -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ .get_eeprom = rtl_get_eeprom, -+ .get_eeprom_len = rtl_get_eeprom_len, -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0) -+ .get_ts_info = ethtool_op_get_ts_info, -+#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0) -+}; -+ -+ -+static int rtl8168_enable_EEE(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ int ret; -+ u16 data; -+ u16 PhyRegValue; -+ u32 WaitCnt; -+ unsigned long flags; -+ -+ ret = 0; -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x0020); -+ data = mdio_read(tp, 0x15) | 0x0100; -+ mdio_write(tp, 0x15, data); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B85); -+ data = mdio_read(tp, 0x06) | 0x2000; -+ mdio_write(tp, 0x06, data); -+ mdio_write(tp, 0x1F, 0x0006); -+ mdio_write(tp, 0x00, 0x5A30); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x0D, 0x0007); -+ mdio_write(tp, 0x0E, 0x003C); -+ mdio_write(tp, 0x0D, 0x4007); -+ mdio_write(tp, 0x0E, 0x0006); -+ mdio_write(tp, 0x0D, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ if ((RTL_R8(Config4)&0x40) && (RTL_R8(0x6D) & BIT_7)) { -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8AC8); -+ mdio_write(tp, 0x06, RTL_R16(CustomLED)); -+ mdio_write(tp, 0x05, 0x8B82); -+ data = mdio_read(tp, 0x06) | 0x0010; -+ mdio_write(tp, 0x05, 0x8B82); -+ mdio_write(tp, 0x06, data); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ } -+ break; -+ -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ data = rtl8168_eri_read(ioaddr,0x1B0 ,4,ERIAR_ExGMAC) | 0x0003; -+ rtl8168_eri_write(ioaddr, 0x1B0, 4, data, ERIAR_ExGMAC); -+ mdio_write(tp,0x1F , 0x0004); -+ mdio_write(tp,0x1F , 0x0007); -+ mdio_write(tp,0x1E , 0x0020); -+ data = mdio_read(tp, 0x15)|0x0100; -+ mdio_write(tp,0x15 , data); -+ mdio_write(tp,0x1F , 0x0002); -+ mdio_write(tp,0x1F , 0x0005); -+ mdio_write(tp,0x05 , 0x8B85); -+ data = mdio_read(tp, 0x06)|0x2000; -+ mdio_write(tp,0x06 , data); -+ mdio_write(tp,0x1F , 0x0000); -+ mdio_write(tp,0x0D , 0x0007); -+ mdio_write(tp,0x0E , 0x003C); -+ mdio_write(tp,0x0D , 0x4007); -+ mdio_write(tp,0x0E , 0x0006); -+ mdio_write(tp,0x1D , 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ data = rtl8168_eri_read(ioaddr,0x1B0 ,4,ERIAR_ExGMAC); -+ data |= BIT_1 | BIT_0; -+ rtl8168_eri_write(ioaddr, 0x1B0, 4, data, ERIAR_ExGMAC); -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1e, 0x0020); -+ data = mdio_read(tp, 0x15); -+ data |= BIT_8; -+ mdio_write(tp, 0x15, data); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B85); -+ data = mdio_read(tp, 0x06); -+ data |= BIT_13; -+ mdio_write(tp, 0x06, data); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x0D, 0x0007); -+ mdio_write(tp, 0x0E, 0x003C); -+ mdio_write(tp, 0x0D, 0x4007); -+ mdio_write(tp, 0x0E, 0x0006); -+ mdio_write(tp, 0x0D, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ data = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC); -+ data |= BIT_1 | BIT_0; -+ rtl8168_eri_write(ioaddr, 0x1B0, 4, data, ERIAR_ExGMAC); -+ mdio_write(tp, 0x1F, 0x0A43); -+ data = mdio_read(tp, 0x11); -+ mdio_write(tp, 0x11, data | BIT_4); -+ mdio_write(tp, 0x1F, 0x0A5D); -+ mdio_write(tp, 0x10, 0x0006); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ default: -+// dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Not Support EEE\n"); -+ ret = -EOPNOTSUPP; -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0A4A); -+ SetEthPhyBit(tp, 0x11, BIT_9); -+ mdio_write(tp, 0x1F, 0x0A42); -+ SetEthPhyBit(tp, 0x14, BIT_7); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ } -+ -+ /*Advanced EEE*/ -+ switch (tp->mcfg) { -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp,0x1F, 0x0B82); -+ SetEthPhyBit(tp, 0x10, BIT_4); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp,0x1F, 0x0B80); -+ WaitCnt = 0; -+ do { -+ PhyRegValue = mdio_read(tp, 0x10); -+ PhyRegValue &= 0x0040; -+ udelay(100); -+ WaitCnt++; -+ } while(PhyRegValue != 0x0040 && WaitCnt <1000); -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_25: -+ rtl8168_eri_write(ioaddr, 0x1EA, 1, 0xFA, ERIAR_ExGMAC); -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0A43); -+ data = mdio_read(tp, 0x10); -+ if (data & BIT_10) { -+ mdio_write(tp, 0x1F, 0x0A42); -+ data = mdio_read(tp, 0x16); -+ data &= ~(BIT_1); -+ mdio_write(tp, 0x16, data); -+ } else { -+ mdio_write(tp, 0x1F, 0x0A42); -+ data = mdio_read(tp, 0x16); -+ data |= BIT_1; -+ mdio_write(tp, 0x16, data); -+ } -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ case CFG_METHOD_26: -+ data = mac_ocp_read(tp, 0xE052); -+ data |= BIT_0; -+ mac_ocp_write(tp, 0xE052, data); -+ data = mac_ocp_read(tp, 0xE056); -+ data &= 0xFF0F; -+ data |= (BIT_4 | BIT_5 | BIT_6); -+ mac_ocp_write(tp, 0xE056, data); -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0A43); -+ data = mdio_read(tp, 0x10); -+ if (data & BIT_10) { -+ mdio_write(tp, 0x1F, 0x0A42); -+ data = mdio_read(tp, 0x16); -+ data &= ~(BIT_1); -+ mdio_write(tp, 0x16, data); -+ } else { -+ mdio_write(tp, 0x1F, 0x0A42); -+ data = mdio_read(tp, 0x16); -+ data |= BIT_1; -+ mdio_write(tp, 0x16, data); -+ } -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ OOB_mutex_lock(tp); -+ data = mac_ocp_read(tp, 0xE052); -+ data |= BIT_0; -+ mac_ocp_write(tp, 0xE052, data); -+ OOB_mutex_unlock(tp); -+ data = mac_ocp_read(tp, 0xE056); -+ data &= 0xFF0F; -+ data |= (BIT_4 | BIT_5 | BIT_6); -+ mac_ocp_write(tp, 0xE056, data); -+ break; -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ data = mac_ocp_read(tp, 0xE052); -+ data |= BIT_0; -+ mac_ocp_write(tp, 0xE052, data); -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0A43); -+ data = mdio_read(tp, 0x10) | BIT_15; -+ mdio_write(tp, 0x10, data); -+ -+ mdio_write(tp, 0x1F, 0x0A44); -+ data = mdio_read( tp, 0x11 ) | BIT_12 | BIT_13| BIT_14; -+ mdio_write(tp, 0x11, data); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0B82); -+ ClearEthPhyBit(tp, 0x10, BIT_4); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ } -+ -+ return ret; -+} -+ -+static int rtl8168_disable_EEE(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ int ret; -+ u16 data; -+ u16 PhyRegValue; -+ u32 WaitCnt; -+ unsigned long flags; -+ -+ ret = 0; -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B85); -+ data = mdio_read(tp, 0x06) & ~0x2000; -+ mdio_write(tp, 0x06, data); -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x0020); -+ data = mdio_read(tp, 0x15) & ~0x0100; -+ mdio_write(tp, 0x15, data); -+ mdio_write(tp, 0x1F, 0x0006); -+ mdio_write(tp, 0x00, 0x5A00); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x0D, 0x0007); -+ mdio_write(tp, 0x0E, 0x003C); -+ mdio_write(tp, 0x0D, 0x4007); -+ mdio_write(tp, 0x0E, 0x0000); -+ mdio_write(tp, 0x0D, 0x0000); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ if (RTL_R8(Config4) & 0x40) { -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B82); -+ data = mdio_read(tp, 0x06) & ~0x0010; -+ mdio_write(tp, 0x05, 0x8B82); -+ mdio_write(tp, 0x06, data); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ } -+ break; -+ -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ data = rtl8168_eri_read(ioaddr,0x1B0 ,4,ERIAR_ExGMAC)& ~0x0003; -+ rtl8168_eri_write(ioaddr, 0x1B0, 4, data, ERIAR_ExGMAC); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B85); -+ data = mdio_read(tp, 0x06) & ~0x2000; -+ mdio_write(tp, 0x06, data); -+ mdio_write(tp, 0x1F, 0x0004); -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x0020); -+ data = mdio_read(tp, 0x15) & ~0x0100; -+ mdio_write(tp,0x15 , data); -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x0D, 0x0007); -+ mdio_write(tp, 0x0E, 0x003C); -+ mdio_write(tp, 0x0D, 0x4007); -+ mdio_write(tp, 0x0E, 0x0000); -+ mdio_write(tp, 0x0D, 0x0000); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ data = rtl8168_eri_read(ioaddr,0x1B0 ,4,ERIAR_ExGMAC); -+ data &= ~(BIT_1 | BIT_0); -+ rtl8168_eri_write(ioaddr, 0x1B0, 4, data, ERIAR_ExGMAC); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B85); -+ data = mdio_read(tp, 0x06); -+ data &= ~BIT_13; -+ mdio_write(tp, 0x06, data); -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1e, 0x0020); -+ data = mdio_read(tp, 0x15); -+ data &= ~BIT_8; -+ mdio_write(tp, 0x15, data); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x0D, 0x0007); -+ mdio_write(tp, 0x0E, 0x003C); -+ mdio_write(tp, 0x0D, 0x4007); -+ mdio_write(tp, 0x0E, 0x0000); -+ mdio_write(tp, 0x0D, 0x0000); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ data = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC); -+ data &= ~(BIT_1 | BIT_0); -+ rtl8168_eri_write(ioaddr, 0x1B0, 4, data, ERIAR_ExGMAC); -+ mdio_write(tp, 0x1F, 0x0A43); -+ data = mdio_read(tp, 0x11); -+ mdio_write(tp, 0x11, data & ~BIT_4); -+ mdio_write(tp, 0x1F, 0x0A5D); -+ mdio_write(tp, 0x10, 0x0000); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ default: -+// dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Not Support EEE\n"); -+ ret = -EOPNOTSUPP; -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0A42); -+ ClearEthPhyBit(tp, 0x14, BIT_7); -+ mdio_write(tp, 0x1F, 0x0A4A); -+ ClearEthPhyBit(tp, 0x11, BIT_9); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ } -+ -+ /*Advanced EEE*/ -+ switch (tp->mcfg) { -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp,0x1F, 0x0B82); -+ SetEthPhyBit(tp, 0x10, BIT_4); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp,0x1F, 0x0B80); -+ WaitCnt = 0; -+ do { -+ PhyRegValue = mdio_read(tp, 0x10); -+ PhyRegValue &= 0x0040; -+ udelay(100); -+ WaitCnt++; -+ } while(PhyRegValue != 0x0040 && WaitCnt <1000); -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_25: -+ rtl8168_eri_write(ioaddr, 0x1EA, 1, 0x00, ERIAR_ExGMAC); -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0A42); -+ data = mdio_read(tp, 0x16); -+ data &= ~(BIT_1); -+ mdio_write(tp, 0x16, data); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ case CFG_METHOD_26: -+ data = mac_ocp_read(tp, 0xE052); -+ data &= ~(BIT_0); -+ mac_ocp_write(tp, 0xE052, data); -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0A42); -+ data = mdio_read(tp, 0x16); -+ data &= ~(BIT_1); -+ mdio_write(tp, 0x16, data); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ data = mac_ocp_read(tp, 0xE052); -+ data &= ~(BIT_0); -+ mac_ocp_write(tp, 0xE052, data); -+ break; -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ data = mac_ocp_read(tp, 0xE052); -+ data &= ~(BIT_0); -+ mac_ocp_write(tp, 0xE052, data); -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0A43); -+ data = mdio_read(tp, 0x10) & ~(BIT_15); -+ mdio_write(tp, 0x10, data); -+ -+ mdio_write(tp, 0x1F, 0x0A44); -+ data = mdio_read( tp, 0x11 ) & ~(BIT_12 | BIT_13 | BIT_14); -+ mdio_write(tp, 0x11, data); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0B82); -+ ClearEthPhyBit(tp, 0x10, BIT_4); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ } -+ -+ return ret; -+} -+ -+#if 0 -+ -+static int rtl8168_enable_green_feature(struct rtl8168_private *tp) -+{ -+ u16 gphy_val; -+ unsigned long flags; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0003); -+ gphy_val = mdio_read(tp, 0x10) | 0x0400; -+ mdio_write(tp, 0x10, gphy_val); -+ gphy_val = mdio_read(tp, 0x19) | 0x0001; -+ mdio_write(tp, 0x19, gphy_val); -+ mdio_write(tp, 0x1F, 0x0005); -+ gphy_val = mdio_read(tp, 0x01) & ~0x0100; -+ mdio_write(tp, 0x01, gphy_val); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x00, 0x9200); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ mdelay(20); -+ break; -+ -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1f, 0x0003); -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val |= BIT_10; -+ mdio_write(tp, 0x10, gphy_val); -+ gphy_val = mdio_read(tp, 0x19); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x19, gphy_val); -+ mdio_write(tp, 0x1F, 0x0005); -+ gphy_val = mdio_read(tp, 0x01); -+ gphy_val |= BIT_8; -+ mdio_write(tp, 0x01, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x00, 0x9200); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ case CFG_METHOD_21: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8011); -+ if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ SetEthPhyBit( tp, 0x14, BIT_15 ); -+ } else { -+ SetEthPhyBit( tp, 0x14, BIT_14 ); -+ } -+ mdio_write(tp, 0x1F, 0x0A40); -+ mdio_write(tp, 0x00, 0x9200); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ default: -+ dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Not Support Green Feature\n"); -+ break; -+ } -+ -+ return 0; -+} -+ -+static int rtl8168_disable_green_feature(struct rtl8168_private *tp) -+{ -+ u16 gphy_val; -+ unsigned long flags; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0005); -+ gphy_val = mdio_read(tp, 0x01) | 0x0100; -+ mdio_write(tp, 0x01, gphy_val); -+ mdio_write(tp, 0x1F, 0x0003); -+ gphy_val = mdio_read(tp, 0x10) & ~0x0400; -+ mdio_write(tp, 0x10, gphy_val); -+ gphy_val = mdio_read(tp, 0x19) & ~0x0001; -+ mdio_write(tp, 0x19, gphy_val); -+ mdio_write(tp, 0x1F, 0x0002); -+ gphy_val = mdio_read(tp, 0x06) & ~0x7000; -+ gphy_val |= 0x3000; -+ mdio_write(tp, 0x06, gphy_val); -+ gphy_val = mdio_read(tp, 0x0D) & 0x0700; -+ gphy_val |= 0x0500; -+ mdio_write(tp, 0x0D, gphy_val); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1f, 0x0003); -+ gphy_val = mdio_read(tp, 0x19); -+ gphy_val &= ~BIT_0; -+ mdio_write(tp, 0x19, gphy_val); -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val &= ~BIT_10; -+ mdio_write(tp, 0x10, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ case CFG_METHOD_21: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8011); -+ if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ ClearEthPhyBit( tp, 0x14, BIT_15 ); -+ } else { -+ ClearEthPhyBit( tp, 0x14, BIT_14 ); -+ } -+ mdio_write(tp, 0x1F, 0x0A40); -+ mdio_write(tp, 0x00, 0x9200); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ default: -+ dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Not Support Green Feature\n"); -+ break; -+ } -+ -+ return 0; -+} -+ -+#endif -+ -+static void rtl8168_get_mac_version(struct rtl8168_private *tp, void __iomem *ioaddr) -+{ -+ u32 reg,val32; -+ u32 ICVerID; -+ -+ val32 = RTL_R32(TxConfig) ; -+ reg = val32 & 0x7c800000; -+ ICVerID = val32 & 0x00700000; -+ -+ switch (reg) { -+ case 0x30000000: -+ tp->mcfg = CFG_METHOD_1; -+ tp->efuse_ver = EFUSE_NOT_SUPPORT; -+ break; -+ case 0x38000000: -+ if (ICVerID == 0x00000000) { -+ tp->mcfg = CFG_METHOD_2; -+ } else if (ICVerID == 0x00500000) { -+ tp->mcfg = CFG_METHOD_3; -+ } else { -+ tp->mcfg = CFG_METHOD_3; -+ tp->HwIcVerUnknown = TRUE; -+ } -+ tp->efuse_ver = EFUSE_NOT_SUPPORT; -+ break; -+ case 0x3C000000: -+ if (ICVerID == 0x00000000) { -+ tp->mcfg = CFG_METHOD_4; -+ } else if (ICVerID == 0x00200000) { -+ tp->mcfg = CFG_METHOD_5; -+ } else if (ICVerID == 0x00400000) { -+ tp->mcfg = CFG_METHOD_6; -+ } else { -+ tp->mcfg = CFG_METHOD_6; -+ tp->HwIcVerUnknown = TRUE; -+ } -+ tp->efuse_ver = EFUSE_NOT_SUPPORT; -+ break; -+ case 0x3C800000: -+ if (ICVerID == 0x00100000) { -+ tp->mcfg = CFG_METHOD_7; -+ } else if (ICVerID == 0x00300000) { -+ tp->mcfg = CFG_METHOD_8; -+ } else { -+ tp->mcfg = CFG_METHOD_8; -+ tp->HwIcVerUnknown = TRUE; -+ } -+ tp->efuse_ver = EFUSE_NOT_SUPPORT; -+ break; -+ case 0x28000000: -+ if (ICVerID == 0x00100000) { -+ tp->mcfg = CFG_METHOD_9; -+ } else if (ICVerID == 0x00300000) { -+ tp->mcfg = CFG_METHOD_10; -+ } else { -+ tp->mcfg = CFG_METHOD_10; -+ tp->HwIcVerUnknown = TRUE; -+ } -+ tp->efuse_ver = EFUSE_SUPPORT_V1; -+ break; -+ case 0x28800000: -+ if (ICVerID == 0x00000000) { -+ tp->mcfg = CFG_METHOD_11; -+ } else if (ICVerID == 0x00200000) { -+ tp->mcfg = CFG_METHOD_12; -+ RTL_W32(0xD0, RTL_R32(0xD0) | 0x00020000); -+ } else if (ICVerID == 0x00300000) { -+ tp->mcfg = CFG_METHOD_13; -+ } else { -+ tp->mcfg = CFG_METHOD_13; -+ tp->HwIcVerUnknown = TRUE; -+ } -+ tp->efuse_ver = EFUSE_SUPPORT_V1; -+ break; -+ case 0x2C000000: -+ if (ICVerID == 0x00100000) { -+ tp->mcfg = CFG_METHOD_14; -+ } else if (ICVerID == 0x00200000) { -+ tp->mcfg = CFG_METHOD_15; -+ } else { -+ tp->mcfg = CFG_METHOD_15; -+ tp->HwIcVerUnknown = TRUE; -+ } -+ tp->efuse_ver = EFUSE_SUPPORT_V2; -+ break; -+ case 0x2C800000: -+ if (ICVerID == 0x00000000) { -+ tp->mcfg = CFG_METHOD_16; -+ } else if (ICVerID == 0x00100000) { -+ tp->mcfg = CFG_METHOD_17; -+ } else { -+ tp->mcfg = CFG_METHOD_17; -+ tp->HwIcVerUnknown = TRUE; -+ } -+ tp->efuse_ver = EFUSE_SUPPORT_V3; -+ break; -+ case 0x48000000: -+ if (ICVerID == 0x00000000) { -+ tp->mcfg = CFG_METHOD_18; -+ } else if (ICVerID == 0x00100000) { -+ tp->mcfg = CFG_METHOD_19; -+ } else { -+ tp->mcfg = CFG_METHOD_19; -+ tp->HwIcVerUnknown = TRUE; -+ } -+ tp->efuse_ver = EFUSE_SUPPORT_V3; -+ break; -+ case 0x48800000: -+ if (ICVerID == 0x00000000) { -+ tp->mcfg = CFG_METHOD_20; -+ } else { -+ tp->mcfg = CFG_METHOD_20; -+ tp->HwIcVerUnknown = TRUE; -+ } -+ -+ tp->efuse_ver = EFUSE_SUPPORT_V3; -+ break; -+ case 0x4C000000: -+ if (ICVerID == 0x00000000) { -+ tp->mcfg = CFG_METHOD_21; -+ } else if (ICVerID == 0x00100000) { -+ tp->mcfg = CFG_METHOD_22; -+ } else { -+ tp->mcfg = CFG_METHOD_22; -+ tp->HwIcVerUnknown = TRUE; -+ } -+ tp->efuse_ver = EFUSE_SUPPORT_V3; -+ break; -+ case 0x50000000: -+ if (ICVerID == 0x00000000) { -+ tp->mcfg = CFG_METHOD_23; -+ } else if (ICVerID == 0x00100000) { -+ tp->mcfg = CFG_METHOD_27; -+ } else if (ICVerID == 0x00200000) { -+ tp->mcfg = CFG_METHOD_28; -+ } else { -+ tp->mcfg = CFG_METHOD_28; -+ tp->HwIcVerUnknown = TRUE; -+ } -+ tp->efuse_ver = EFUSE_SUPPORT_V3; -+ break; -+ case 0x50800000: -+ if (ICVerID == 0x00000000) { -+ tp->mcfg = CFG_METHOD_24; -+ } else if (ICVerID == 0x00100000) { -+ tp->mcfg = CFG_METHOD_25; -+ } else { -+ tp->mcfg = CFG_METHOD_25; -+ tp->HwIcVerUnknown = TRUE; -+ } -+ tp->efuse_ver = EFUSE_SUPPORT_V3; -+ break; -+ case 0x5C800000: -+ if (ICVerID == 0x00000000) { -+ tp->mcfg = CFG_METHOD_26; -+ } else { -+ tp->mcfg = CFG_METHOD_26; -+ tp->HwIcVerUnknown = TRUE; -+ } -+ -+ tp->efuse_ver = EFUSE_SUPPORT_V3; -+ break; -+ case 0x54000000: -+ if (ICVerID == 0x00000000) { -+ tp->mcfg = CFG_METHOD_29; -+ } else if (ICVerID == 0x00100000) { -+ tp->mcfg = CFG_METHOD_30; -+ } else { -+ tp->mcfg = CFG_METHOD_30; -+ tp->HwIcVerUnknown = TRUE; -+ } -+ -+ tp->efuse_ver = EFUSE_SUPPORT_V3; -+ break; -+ default: -+ printk("unknown chip version (%x)\n",reg); -+ tp->mcfg = CFG_METHOD_DEFAULT; -+ tp->HwIcVerUnknown = TRUE; -+ tp->efuse_ver = EFUSE_NOT_SUPPORT; -+ break; -+ } -+} -+ -+static void -+rtl8168_print_mac_version(struct rtl8168_private *tp) -+{ -+ int i; -+ for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) { -+ if (tp->mcfg == rtl_chip_info[i].mcfg) { -+ dprintk("Realtek PCIe GBE Family Controller mcfg = %04d\n", -+ rtl_chip_info[i].mcfg); -+ return; -+ } -+ } -+ -+ dprintk("mac_version == Unknown\n"); -+} -+ -+static u8 rtl8168_calc_efuse_dummy_bit(u16 reg) -+{ -+ int s,a,b; -+ u8 dummyBitPos = 0; -+ -+ -+ s=reg% 32; -+ a=s % 16; -+ b=s/16; -+ -+ if (s/16) { -+ dummyBitPos = (u8)(16-a); -+ } else { -+ dummyBitPos = (u8)a; -+ } -+ -+ return dummyBitPos; -+} -+ -+static u32 rtl8168_decode_efuse_cmd(struct rtl8168_private *tp, u32 DwCmd) -+{ -+ u16 reg = (u16)((DwCmd & 0x00FE0000) >> 17); -+ u32 DummyPos = rtl8168_calc_efuse_dummy_bit(reg); -+ u32 DeCodeDwCmd = DwCmd; -+ u32 Dw17BitData; -+ -+ -+ if(tp->efuse_ver < 3) { -+ DeCodeDwCmd = (DwCmd>>(DummyPos+1))<<DummyPos; -+ if(DummyPos > 0) { -+ DeCodeDwCmd |= ((DwCmd<<(32-DummyPos))>>(32-DummyPos)); -+ } -+ } else { -+ reg = (u16)((DwCmd & 0x007F0000) >> 16); -+ DummyPos = rtl8168_calc_efuse_dummy_bit(reg); -+ Dw17BitData = ((DwCmd & BIT_23) >> 23); -+ Dw17BitData <<= 16; -+ Dw17BitData |= (DwCmd & 0x0000FFFF); -+ DeCodeDwCmd = (Dw17BitData>>(DummyPos+1))<<DummyPos; -+ if(DummyPos > 0) { -+ DeCodeDwCmd |= ((Dw17BitData<<(32-DummyPos))>>(32-DummyPos)); -+ } -+ } -+ -+ return DeCodeDwCmd; -+} -+ -+static u8 rtl8168_efuse_read(struct rtl8168_private *tp, u16 reg) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ u8 efuse_data = 0; -+ u32 temp; -+ int cnt; -+ -+ if (tp->efuse_ver == EFUSE_NOT_SUPPORT) -+ return EFUSE_READ_FAIL; -+ -+ if (tp->efuse_ver == EFUSE_SUPPORT_V1) { -+ temp = EFUSE_READ | ((reg & EFUSE_Reg_Mask) << EFUSE_Reg_Shift); -+ RTL_W32(EFUSEAR, temp); -+ -+ cnt = 0; -+ do { -+ udelay(100); -+ temp = RTL_R32(EFUSEAR); -+ cnt++; -+ } while (!(temp & EFUSE_READ_OK) && (cnt < EFUSE_Check_Cnt)); -+ -+ if (cnt == EFUSE_Check_Cnt) -+ efuse_data = EFUSE_READ_FAIL; -+ else -+ efuse_data = (u8)(RTL_R32(EFUSEAR) & EFUSE_Data_Mask); -+ } else if (tp->efuse_ver == EFUSE_SUPPORT_V2) { -+ temp = (reg/2) & 0x03ff; -+ temp <<= 17; -+ temp |= EFUSE_READ; -+ RTL_W32(EFUSEAR, temp); -+ -+ cnt = 0; -+ do { -+ udelay(100); -+ temp = RTL_R32(EFUSEAR); -+ cnt++; -+ } while (!(temp & EFUSE_READ_OK) && (cnt < EFUSE_Check_Cnt)); -+ -+ if (cnt == EFUSE_Check_Cnt) { -+ efuse_data = EFUSE_READ_FAIL; -+ } else { -+ temp = RTL_R32(EFUSEAR); -+ temp = rtl8168_decode_efuse_cmd(tp, temp); -+ -+ if(reg%2) { -+ temp >>= 8; -+ efuse_data = (u8)temp; -+ } else { -+ efuse_data = (u8)temp; -+ } -+ } -+ -+ } else if (tp->efuse_ver == EFUSE_SUPPORT_V3) { -+ temp = (reg/2) & 0x03ff; -+ temp <<= 16; -+ temp |= EFUSE_READ; -+ RTL_W32(EFUSEAR, temp); -+ -+ cnt = 0; -+ do { -+ udelay(100); -+ temp = RTL_R32(EFUSEAR); -+ cnt++; -+ } while (!(temp & EFUSE_READ_OK) && (cnt < EFUSE_Check_Cnt)); -+ -+ if (cnt == EFUSE_Check_Cnt) { -+ efuse_data = EFUSE_READ_FAIL; -+ } else { -+ temp = RTL_R32(EFUSEAR); -+ temp = rtl8168_decode_efuse_cmd(tp, temp); -+ -+ if(reg%2) { -+ temp >>= 8; -+ efuse_data = (u8)temp; -+ } else { -+ efuse_data = (u8)temp; -+ } -+ } -+ } -+ -+ udelay(20); -+ -+ return efuse_data; -+} -+ -+static void -+rtl8168_tally_counter_addr_fill(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if (!tp->tally_paddr) -+ return; -+ -+ RTL_W32(CounterAddrHigh, (u64)tp->tally_paddr >> 32); -+ RTL_W32(CounterAddrLow, (u64)tp->tally_paddr & (DMA_BIT_MASK(32))); -+} -+ -+static void -+rtl8168_tally_counter_clear(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if (tp->mcfg == CFG_METHOD_1 || tp->mcfg == CFG_METHOD_2 || -+ tp->mcfg == CFG_METHOD_3 ) -+ return; -+ -+ if (!tp->tally_paddr) -+ return; -+ -+ RTL_W32(CounterAddrHigh, (u64)tp->tally_paddr >> 32); -+ RTL_W32(CounterAddrLow, (u64)tp->tally_paddr & (DMA_BIT_MASK(32) | BIT_0)); -+} -+ -+static int -+rtl8168_is_ups_resume(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ return (mac_ocp_read(tp, 0xD408) & BIT_0); -+} -+ -+static void -+rtl8168_clear_ups_resume_bit(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ mac_ocp_write(tp, 0xD408, mac_ocp_read(tp, 0xD408) & ~(BIT_0)); -+} -+ -+static void -+rtl8168_wait_phy_ups_resume(struct net_device *dev, u16 PhyState) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ u16 TmpPhyState; -+ int i=0; -+ -+ do { -+ TmpPhyState = mdio_read_phy_ocp(tp, 0x0A42, 0x10); -+ TmpPhyState &= 0x7; -+ mdelay(1); -+ i++; -+ } while ((i < 100) && (TmpPhyState != PhyState)); -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) -+ WARN_ON_ONCE(i == 100); -+#endif -+} -+ -+void -+EnableNowIsOob(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if( tp->HwSuppNowIsOobVer == 1 ) { -+ RTL_W8(MCUCmd_reg, RTL_R8(MCUCmd_reg) | Now_is_oob); -+ } -+} -+ -+void -+DisableNowIsOob(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if( tp->HwSuppNowIsOobVer == 1 ) { -+ RTL_W8(MCUCmd_reg, RTL_R8(MCUCmd_reg) & ~Now_is_oob); -+ } -+} -+ -+static void -+rtl8168_exit_oob(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ u16 data16; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_23: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ Dash2DisableTxRx(dev); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ case CFG_METHOD_23: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ if (tp->DASH) { -+ rtl8168_driver_stop(tp); -+ rtl8168_driver_start(tp); -+#ifdef ENABLE_DASH_SUPPORT -+ DashHwInit(dev); -+#endif -+ } -+ break; -+ } -+ -+ //Disable realwow function -+ switch (tp->mcfg) { -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ RTL_W32(MACOCP, 0xE5A90000); -+ RTL_W32(MACOCP, 0xF2100010); -+ break; -+ case CFG_METHOD_20: -+ RTL_W32(MACOCP, 0xE5A90000); -+ RTL_W32(MACOCP, 0xE4640000); -+ RTL_W32(MACOCP, 0xF2100010); -+ break; -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ RTL_W32(MACOCP, 0x605E0000); -+ RTL_W32(MACOCP, (0xE05E << 16) | (RTL_R32(MACOCP) & 0xFFFE)); -+ RTL_W32(MACOCP, 0xE9720000); -+ RTL_W32(MACOCP, 0xF2140010); -+ break; -+ case CFG_METHOD_26: -+ RTL_W32(MACOCP, 0xE05E00FF); -+ RTL_W32(MACOCP, 0xE9720000); -+ mac_ocp_write(tp, 0xE428, 0x0010); -+ break; -+ } -+ -+#ifndef ENABLE_REALWOW_SUPPORT -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ rtl8168_eri_write(ioaddr, 0x174, 2, 0x0000, ERIAR_ExGMAC); -+ mac_ocp_write(tp, 0xE428, 0x0010); -+ break; -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_28: -+ rtl8168_eri_write(ioaddr, 0x174, 2, 0x00FF, ERIAR_ExGMAC); -+ mac_ocp_write(tp, 0xE428, 0x0010); -+ break; -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: { -+ u32 csi_tmp; -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x174, 2, ERIAR_ExGMAC); -+ csi_tmp &= ~(BIT_8); -+ csi_tmp |= (BIT_15); -+ rtl8168_eri_write(ioaddr, 0x174, 2, csi_tmp, ERIAR_ExGMAC); -+ mac_ocp_write(tp, 0xE428, 0x0010); -+ } -+ break; -+ } -+#endif //ENABLE_REALWOW_SUPPORT -+ -+#ifdef ENABLE_REALWOW_SUPPORT -+ realwow_hw_init(dev); -+#endif -+ -+ rtl8168_nic_reset(dev); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_20: -+ rtl8168_wait_ll_share_fifo_ready(dev); -+ -+ data16 = mac_ocp_read(tp, 0xD4DE) | BIT_15; -+ mac_ocp_write(tp, 0xD4DE, data16); -+ -+ rtl8168_wait_ll_share_fifo_ready(dev); -+ break; -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ DisableNowIsOob(tp); -+ -+ data16 = mac_ocp_read(tp, 0xE8DE) & ~BIT_14; -+ mac_ocp_write(tp, 0xE8DE, data16); -+ rtl8168_wait_ll_share_fifo_ready(dev); -+ -+ data16 = mac_ocp_read(tp, 0xE8DE) | BIT_15; -+ mac_ocp_write(tp, 0xE8DE, data16); -+ -+ rtl8168_wait_ll_share_fifo_ready(dev); -+ break; -+ } -+ -+ //wait ups resume (phy state 2) -+ switch (tp->mcfg) { -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ if (rtl8168_is_ups_resume(dev)) { -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ -+ rtl8168_wait_phy_ups_resume(dev, 2); -+ -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ -+ rtl8168_clear_ups_resume_bit(dev); -+ } -+ break; -+ }; -+} -+ -+void -+rtl8168_hw_disable_mac_mcu_bps(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ mac_ocp_write(tp, 0xFC28, 0x0000); -+ mac_ocp_write(tp, 0xFC2A, 0x0000); -+ mac_ocp_write(tp, 0xFC2C, 0x0000); -+ mac_ocp_write(tp, 0xFC2E, 0x0000); -+ mac_ocp_write(tp, 0xFC30, 0x0000); -+ mac_ocp_write(tp, 0xFC32, 0x0000); -+ mac_ocp_write(tp, 0xFC34, 0x0000); -+ mac_ocp_write(tp, 0xFC36, 0x0000); -+ mdelay(3); -+ mac_ocp_write(tp, 0xFC26, 0x0000); -+ break; -+ } -+} -+ -+static void -+rtl8168_hw_mac_mcu_config(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ if (tp->NotWrMcuPatchCode == TRUE) return; -+ -+ if (tp->mcfg == CFG_METHOD_21) { -+ mac_ocp_write(tp, 0xE43C, 0x0000); -+ mac_ocp_write(tp, 0xE43E, 0x0000); -+ -+ mac_ocp_write(tp, 0xE434, 0x0004); -+ mac_ocp_write(tp, 0xE43C, 0x0004); -+ -+ rtl8168_hw_disable_mac_mcu_bps(dev); -+ -+ mac_ocp_write( tp, 0xF800, 0xE008 ); -+ mac_ocp_write( tp, 0xF802, 0xE01B ); -+ mac_ocp_write( tp, 0xF804, 0xE01D ); -+ mac_ocp_write( tp, 0xF806, 0xE01F ); -+ mac_ocp_write( tp, 0xF808, 0xE022 ); -+ mac_ocp_write( tp, 0xF80A, 0xE025 ); -+ mac_ocp_write( tp, 0xF80C, 0xE031 ); -+ mac_ocp_write( tp, 0xF80E, 0xE04D ); -+ mac_ocp_write( tp, 0xF810, 0x49D2 ); -+ mac_ocp_write( tp, 0xF812, 0xF10D ); -+ mac_ocp_write( tp, 0xF814, 0x766C ); -+ mac_ocp_write( tp, 0xF816, 0x49E2 ); -+ mac_ocp_write( tp, 0xF818, 0xF00A ); -+ mac_ocp_write( tp, 0xF81A, 0x1EC0 ); -+ mac_ocp_write( tp, 0xF81C, 0x8EE1 ); -+ mac_ocp_write( tp, 0xF81E, 0xC60A ); -+ mac_ocp_write( tp, 0xF820, 0x77C0 ); -+ mac_ocp_write( tp, 0xF822, 0x4870 ); -+ mac_ocp_write( tp, 0xF824, 0x9FC0 ); -+ mac_ocp_write( tp, 0xF826, 0x1EA0 ); -+ mac_ocp_write( tp, 0xF828, 0xC707 ); -+ mac_ocp_write( tp, 0xF82A, 0x8EE1 ); -+ mac_ocp_write( tp, 0xF82C, 0x9D6C ); -+ mac_ocp_write( tp, 0xF82E, 0xC603 ); -+ mac_ocp_write( tp, 0xF830, 0xBE00 ); -+ mac_ocp_write( tp, 0xF832, 0xB416 ); -+ mac_ocp_write( tp, 0xF834, 0x0076 ); -+ mac_ocp_write( tp, 0xF836, 0xE86C ); -+ mac_ocp_write( tp, 0xF838, 0xC602 ); -+ mac_ocp_write( tp, 0xF83A, 0xBE00 ); -+ mac_ocp_write( tp, 0xF83C, 0xA000 ); -+ mac_ocp_write( tp, 0xF83E, 0xC602 ); -+ mac_ocp_write( tp, 0xF840, 0xBE00 ); -+ mac_ocp_write( tp, 0xF842, 0x0000 ); -+ mac_ocp_write( tp, 0xF844, 0x1B76 ); -+ mac_ocp_write( tp, 0xF846, 0xC202 ); -+ mac_ocp_write( tp, 0xF848, 0xBA00 ); -+ mac_ocp_write( tp, 0xF84A, 0x059C ); -+ mac_ocp_write( tp, 0xF84C, 0x1B76 ); -+ mac_ocp_write( tp, 0xF84E, 0xC602 ); -+ mac_ocp_write( tp, 0xF850, 0xBE00 ); -+ mac_ocp_write( tp, 0xF852, 0x065A ); -+ mac_ocp_write( tp, 0xF854, 0x74E6 ); -+ mac_ocp_write( tp, 0xF856, 0x1B78 ); -+ mac_ocp_write( tp, 0xF858, 0x46DC ); -+ mac_ocp_write( tp, 0xF85A, 0x1300 ); -+ mac_ocp_write( tp, 0xF85C, 0xF005 ); -+ mac_ocp_write( tp, 0xF85E, 0x74F8 ); -+ mac_ocp_write( tp, 0xF860, 0x48C3 ); -+ mac_ocp_write( tp, 0xF862, 0x48C4 ); -+ mac_ocp_write( tp, 0xF864, 0x8CF8 ); -+ mac_ocp_write( tp, 0xF866, 0x64E7 ); -+ mac_ocp_write( tp, 0xF868, 0xC302 ); -+ mac_ocp_write( tp, 0xF86A, 0xBB00 ); -+ mac_ocp_write( tp, 0xF86C, 0x06A0 ); -+ mac_ocp_write( tp, 0xF86E, 0x74E4 ); -+ mac_ocp_write( tp, 0xF870, 0x49C5 ); -+ mac_ocp_write( tp, 0xF872, 0xF106 ); -+ mac_ocp_write( tp, 0xF874, 0x49C6 ); -+ mac_ocp_write( tp, 0xF876, 0xF107 ); -+ mac_ocp_write( tp, 0xF878, 0x48C8 ); -+ mac_ocp_write( tp, 0xF87A, 0x48C9 ); -+ mac_ocp_write( tp, 0xF87C, 0xE011 ); -+ mac_ocp_write( tp, 0xF87E, 0x48C9 ); -+ mac_ocp_write( tp, 0xF880, 0x4848 ); -+ mac_ocp_write( tp, 0xF882, 0xE00E ); -+ mac_ocp_write( tp, 0xF884, 0x4848 ); -+ mac_ocp_write( tp, 0xF886, 0x49C7 ); -+ mac_ocp_write( tp, 0xF888, 0xF00A ); -+ mac_ocp_write( tp, 0xF88A, 0x48C9 ); -+ mac_ocp_write( tp, 0xF88C, 0xC60D ); -+ mac_ocp_write( tp, 0xF88E, 0x1D1F ); -+ mac_ocp_write( tp, 0xF890, 0x8DC2 ); -+ mac_ocp_write( tp, 0xF892, 0x1D00 ); -+ mac_ocp_write( tp, 0xF894, 0x8DC3 ); -+ mac_ocp_write( tp, 0xF896, 0x1D11 ); -+ mac_ocp_write( tp, 0xF898, 0x8DC0 ); -+ mac_ocp_write( tp, 0xF89A, 0xE002 ); -+ mac_ocp_write( tp, 0xF89C, 0x4849 ); -+ mac_ocp_write( tp, 0xF89E, 0x94E5 ); -+ mac_ocp_write( tp, 0xF8A0, 0xC602 ); -+ mac_ocp_write( tp, 0xF8A2, 0xBE00 ); -+ mac_ocp_write( tp, 0xF8A4, 0x01F0 ); -+ mac_ocp_write( tp, 0xF8A6, 0xE434 ); -+ mac_ocp_write( tp, 0xF8A8, 0x49D9 ); -+ mac_ocp_write( tp, 0xF8AA, 0xF01B ); -+ mac_ocp_write( tp, 0xF8AC, 0xC31E ); -+ mac_ocp_write( tp, 0xF8AE, 0x7464 ); -+ mac_ocp_write( tp, 0xF8B0, 0x49C4 ); -+ mac_ocp_write( tp, 0xF8B2, 0xF114 ); -+ mac_ocp_write( tp, 0xF8B4, 0xC31B ); -+ mac_ocp_write( tp, 0xF8B6, 0x6460 ); -+ mac_ocp_write( tp, 0xF8B8, 0x14FA ); -+ mac_ocp_write( tp, 0xF8BA, 0xFA02 ); -+ mac_ocp_write( tp, 0xF8BC, 0xE00F ); -+ mac_ocp_write( tp, 0xF8BE, 0xC317 ); -+ mac_ocp_write( tp, 0xF8C0, 0x7460 ); -+ mac_ocp_write( tp, 0xF8C2, 0x49C0 ); -+ mac_ocp_write( tp, 0xF8C4, 0xF10B ); -+ mac_ocp_write( tp, 0xF8C6, 0xC311 ); -+ mac_ocp_write( tp, 0xF8C8, 0x7462 ); -+ mac_ocp_write( tp, 0xF8CA, 0x48C1 ); -+ mac_ocp_write( tp, 0xF8CC, 0x9C62 ); -+ mac_ocp_write( tp, 0xF8CE, 0x4841 ); -+ mac_ocp_write( tp, 0xF8D0, 0x9C62 ); -+ mac_ocp_write( tp, 0xF8D2, 0xC30A ); -+ mac_ocp_write( tp, 0xF8D4, 0x1C04 ); -+ mac_ocp_write( tp, 0xF8D6, 0x8C60 ); -+ mac_ocp_write( tp, 0xF8D8, 0xE004 ); -+ mac_ocp_write( tp, 0xF8DA, 0x1C15 ); -+ mac_ocp_write( tp, 0xF8DC, 0xC305 ); -+ mac_ocp_write( tp, 0xF8DE, 0x8C60 ); -+ mac_ocp_write( tp, 0xF8E0, 0xC602 ); -+ mac_ocp_write( tp, 0xF8E2, 0xBE00 ); -+ mac_ocp_write( tp, 0xF8E4, 0x0384 ); -+ mac_ocp_write( tp, 0xF8E6, 0xE434 ); -+ mac_ocp_write( tp, 0xF8E8, 0xE030 ); -+ mac_ocp_write( tp, 0xF8EA, 0xE61C ); -+ mac_ocp_write( tp, 0xF8EC, 0xE906 ); -+ -+ mac_ocp_write( tp, 0xFC26, 0x8000 ); -+ -+ mac_ocp_write( tp, 0xFC28, 0x0075 ); -+ mac_ocp_write( tp, 0xFC2E, 0x059B ); -+ mac_ocp_write( tp, 0xFC30, 0x0659 ); -+ mac_ocp_write( tp, 0xFC32, 0x0000 ); -+ mac_ocp_write( tp, 0xFC34, 0x0000 ); -+ mac_ocp_write( tp, 0xFC36, 0x0000 ); -+ } else if (tp->mcfg == CFG_METHOD_24) { -+ rtl8168_hw_disable_mac_mcu_bps(dev); -+ -+ mac_ocp_write( tp, 0xF800, 0xE008 ); -+ mac_ocp_write( tp, 0xF802, 0xE011 ); -+ mac_ocp_write( tp, 0xF804, 0xE015 ); -+ mac_ocp_write( tp, 0xF806, 0xE018 ); -+ mac_ocp_write( tp, 0xF808, 0xE01B ); -+ mac_ocp_write( tp, 0xF80A, 0xE027 ); -+ mac_ocp_write( tp, 0xF80C, 0xE043 ); -+ mac_ocp_write( tp, 0xF80E, 0xE065 ); -+ mac_ocp_write( tp, 0xF810, 0x49E2 ); -+ mac_ocp_write( tp, 0xF812, 0xF005 ); -+ mac_ocp_write( tp, 0xF814, 0x49EA ); -+ mac_ocp_write( tp, 0xF816, 0xF003 ); -+ mac_ocp_write( tp, 0xF818, 0xC404 ); -+ mac_ocp_write( tp, 0xF81A, 0xBC00 ); -+ mac_ocp_write( tp, 0xF81C, 0xC403 ); -+ mac_ocp_write( tp, 0xF81E, 0xBC00 ); -+ mac_ocp_write( tp, 0xF820, 0x0496 ); -+ mac_ocp_write( tp, 0xF822, 0x051A ); -+ mac_ocp_write( tp, 0xF824, 0x1D01 ); -+ mac_ocp_write( tp, 0xF826, 0x8DE8 ); -+ mac_ocp_write( tp, 0xF828, 0xC602 ); -+ mac_ocp_write( tp, 0xF82A, 0xBE00 ); -+ mac_ocp_write( tp, 0xF82C, 0x0206 ); -+ mac_ocp_write( tp, 0xF82E, 0x1B76 ); -+ mac_ocp_write( tp, 0xF830, 0xC202 ); -+ mac_ocp_write( tp, 0xF832, 0xBA00 ); -+ mac_ocp_write( tp, 0xF834, 0x058A ); -+ mac_ocp_write( tp, 0xF836, 0x1B76 ); -+ mac_ocp_write( tp, 0xF838, 0xC602 ); -+ mac_ocp_write( tp, 0xF83A, 0xBE00 ); -+ mac_ocp_write( tp, 0xF83C, 0x0648 ); -+ mac_ocp_write( tp, 0xF83E, 0x74E6 ); -+ mac_ocp_write( tp, 0xF840, 0x1B78 ); -+ mac_ocp_write( tp, 0xF842, 0x46DC ); -+ mac_ocp_write( tp, 0xF844, 0x1300 ); -+ mac_ocp_write( tp, 0xF846, 0xF005 ); -+ mac_ocp_write( tp, 0xF848, 0x74F8 ); -+ mac_ocp_write( tp, 0xF84A, 0x48C3 ); -+ mac_ocp_write( tp, 0xF84C, 0x48C4 ); -+ mac_ocp_write( tp, 0xF84E, 0x8CF8 ); -+ mac_ocp_write( tp, 0xF850, 0x64E7 ); -+ mac_ocp_write( tp, 0xF852, 0xC302 ); -+ mac_ocp_write( tp, 0xF854, 0xBB00 ); -+ mac_ocp_write( tp, 0xF856, 0x068E ); -+ mac_ocp_write( tp, 0xF858, 0x74E4 ); -+ mac_ocp_write( tp, 0xF85A, 0x49C5 ); -+ mac_ocp_write( tp, 0xF85C, 0xF106 ); -+ mac_ocp_write( tp, 0xF85E, 0x49C6 ); -+ mac_ocp_write( tp, 0xF860, 0xF107 ); -+ mac_ocp_write( tp, 0xF862, 0x48C8 ); -+ mac_ocp_write( tp, 0xF864, 0x48C9 ); -+ mac_ocp_write( tp, 0xF866, 0xE011 ); -+ mac_ocp_write( tp, 0xF868, 0x48C9 ); -+ mac_ocp_write( tp, 0xF86A, 0x4848 ); -+ mac_ocp_write( tp, 0xF86C, 0xE00E ); -+ mac_ocp_write( tp, 0xF86E, 0x4848 ); -+ mac_ocp_write( tp, 0xF870, 0x49C7 ); -+ mac_ocp_write( tp, 0xF872, 0xF00A ); -+ mac_ocp_write( tp, 0xF874, 0x48C9 ); -+ mac_ocp_write( tp, 0xF876, 0xC60D ); -+ mac_ocp_write( tp, 0xF878, 0x1D1F ); -+ mac_ocp_write( tp, 0xF87A, 0x8DC2 ); -+ mac_ocp_write( tp, 0xF87C, 0x1D00 ); -+ mac_ocp_write( tp, 0xF87E, 0x8DC3 ); -+ mac_ocp_write( tp, 0xF880, 0x1D11 ); -+ mac_ocp_write( tp, 0xF882, 0x8DC0 ); -+ mac_ocp_write( tp, 0xF884, 0xE002 ); -+ mac_ocp_write( tp, 0xF886, 0x4849 ); -+ mac_ocp_write( tp, 0xF888, 0x94E5 ); -+ mac_ocp_write( tp, 0xF88A, 0xC602 ); -+ mac_ocp_write( tp, 0xF88C, 0xBE00 ); -+ mac_ocp_write( tp, 0xF88E, 0x0238 ); -+ mac_ocp_write( tp, 0xF890, 0xE434 ); -+ mac_ocp_write( tp, 0xF892, 0x49D9 ); -+ mac_ocp_write( tp, 0xF894, 0xF01B ); -+ mac_ocp_write( tp, 0xF896, 0xC31E ); -+ mac_ocp_write( tp, 0xF898, 0x7464 ); -+ mac_ocp_write( tp, 0xF89A, 0x49C4 ); -+ mac_ocp_write( tp, 0xF89C, 0xF114 ); -+ mac_ocp_write( tp, 0xF89E, 0xC31B ); -+ mac_ocp_write( tp, 0xF8A0, 0x6460 ); -+ mac_ocp_write( tp, 0xF8A2, 0x14FA ); -+ mac_ocp_write( tp, 0xF8A4, 0xFA02 ); -+ mac_ocp_write( tp, 0xF8A6, 0xE00F ); -+ mac_ocp_write( tp, 0xF8A8, 0xC317 ); -+ mac_ocp_write( tp, 0xF8AA, 0x7460 ); -+ mac_ocp_write( tp, 0xF8AC, 0x49C0 ); -+ mac_ocp_write( tp, 0xF8AE, 0xF10B ); -+ mac_ocp_write( tp, 0xF8B0, 0xC311 ); -+ mac_ocp_write( tp, 0xF8B2, 0x7462 ); -+ mac_ocp_write( tp, 0xF8B4, 0x48C1 ); -+ mac_ocp_write( tp, 0xF8B6, 0x9C62 ); -+ mac_ocp_write( tp, 0xF8B8, 0x4841 ); -+ mac_ocp_write( tp, 0xF8BA, 0x9C62 ); -+ mac_ocp_write( tp, 0xF8BC, 0xC30A ); -+ mac_ocp_write( tp, 0xF8BE, 0x1C04 ); -+ mac_ocp_write( tp, 0xF8C0, 0x8C60 ); -+ mac_ocp_write( tp, 0xF8C2, 0xE004 ); -+ mac_ocp_write( tp, 0xF8C4, 0x1C15 ); -+ mac_ocp_write( tp, 0xF8C6, 0xC305 ); -+ mac_ocp_write( tp, 0xF8C8, 0x8C60 ); -+ mac_ocp_write( tp, 0xF8CA, 0xC602 ); -+ mac_ocp_write( tp, 0xF8CC, 0xBE00 ); -+ mac_ocp_write( tp, 0xF8CE, 0x0374 ); -+ mac_ocp_write( tp, 0xF8D0, 0xE434 ); -+ mac_ocp_write( tp, 0xF8D2, 0xE030 ); -+ mac_ocp_write( tp, 0xF8D4, 0xE61C ); -+ mac_ocp_write( tp, 0xF8D6, 0xE906 ); -+ mac_ocp_write( tp, 0xF8D8, 0xC602 ); -+ mac_ocp_write( tp, 0xF8DA, 0xBE00 ); -+ mac_ocp_write( tp, 0xF8DC, 0x0000 ); -+ -+ mac_ocp_write( tp, 0xFC26, 0x8000 ); -+ -+ mac_ocp_write( tp, 0xFC28, 0x0493 ); -+ mac_ocp_write( tp, 0xFC2A, 0x0205 ); -+ mac_ocp_write( tp, 0xFC2C, 0x0589 ); -+ mac_ocp_write( tp, 0xFC2E, 0x0647 ); -+ mac_ocp_write( tp, 0xFC30, 0x0000 ); -+ mac_ocp_write( tp, 0xFC32, 0x0215 ); -+ mac_ocp_write( tp, 0xFC34, 0x0285 ); -+ } else if (tp->mcfg == CFG_METHOD_25) { -+ rtl8168_hw_disable_mac_mcu_bps(dev); -+ -+ mac_ocp_write( tp, 0xF800, 0xE008 ); -+ mac_ocp_write( tp, 0xF802, 0xE00A ); -+ mac_ocp_write( tp, 0xF804, 0xE01D ); -+ mac_ocp_write( tp, 0xF806, 0xE033 ); -+ mac_ocp_write( tp, 0xF808, 0xE042 ); -+ mac_ocp_write( tp, 0xF80A, 0xE044 ); -+ mac_ocp_write( tp, 0xF80C, 0xE046 ); -+ mac_ocp_write( tp, 0xF80E, 0xE048 ); -+ mac_ocp_write( tp, 0xF810, 0xC602 ); -+ mac_ocp_write( tp, 0xF812, 0xBE00 ); -+ mac_ocp_write( tp, 0xF814, 0x0000 ); -+ mac_ocp_write( tp, 0xF816, 0xC513 ); -+ mac_ocp_write( tp, 0xF818, 0x64A0 ); -+ mac_ocp_write( tp, 0xF81A, 0x49C1 ); -+ mac_ocp_write( tp, 0xF81C, 0xF00A ); -+ mac_ocp_write( tp, 0xF81E, 0x1CEA ); -+ mac_ocp_write( tp, 0xF820, 0x2242 ); -+ mac_ocp_write( tp, 0xF822, 0x0402 ); -+ mac_ocp_write( tp, 0xF824, 0xC50B ); -+ mac_ocp_write( tp, 0xF826, 0x9CA2 ); -+ mac_ocp_write( tp, 0xF828, 0x1C11 ); -+ mac_ocp_write( tp, 0xF82A, 0x9CA0 ); -+ mac_ocp_write( tp, 0xF82C, 0xC506 ); -+ mac_ocp_write( tp, 0xF82E, 0xBD00 ); -+ mac_ocp_write( tp, 0xF830, 0x7444 ); -+ mac_ocp_write( tp, 0xF832, 0xC502 ); -+ mac_ocp_write( tp, 0xF834, 0xBD00 ); -+ mac_ocp_write( tp, 0xF836, 0x0A30 ); -+ mac_ocp_write( tp, 0xF838, 0x0A46 ); -+ mac_ocp_write( tp, 0xF83A, 0xE434 ); -+ mac_ocp_write( tp, 0xF83C, 0xE096 ); -+ mac_ocp_write( tp, 0xF83E, 0x49D9 ); -+ mac_ocp_write( tp, 0xF840, 0xF00F ); -+ mac_ocp_write( tp, 0xF842, 0xC512 ); -+ mac_ocp_write( tp, 0xF844, 0x74A0 ); -+ mac_ocp_write( tp, 0xF846, 0x48C8 ); -+ mac_ocp_write( tp, 0xF848, 0x48CA ); -+ mac_ocp_write( tp, 0xF84A, 0x9CA0 ); -+ mac_ocp_write( tp, 0xF84C, 0xC50F ); -+ mac_ocp_write( tp, 0xF84E, 0x1B00 ); -+ mac_ocp_write( tp, 0xF850, 0x9BA0 ); -+ mac_ocp_write( tp, 0xF852, 0x1B1C ); -+ mac_ocp_write( tp, 0xF854, 0x483F ); -+ mac_ocp_write( tp, 0xF856, 0x9BA2 ); -+ mac_ocp_write( tp, 0xF858, 0x1B04 ); -+ mac_ocp_write( tp, 0xF85A, 0xC5F0 ); -+ mac_ocp_write( tp, 0xF85C, 0x9BA0 ); -+ mac_ocp_write( tp, 0xF85E, 0xC602 ); -+ mac_ocp_write( tp, 0xF860, 0xBE00 ); -+ mac_ocp_write( tp, 0xF862, 0x03DE ); -+ mac_ocp_write( tp, 0xF864, 0xE434 ); -+ mac_ocp_write( tp, 0xF866, 0xE096 ); -+ mac_ocp_write( tp, 0xF868, 0xE860 ); -+ mac_ocp_write( tp, 0xF86A, 0xDE20 ); -+ mac_ocp_write( tp, 0xF86C, 0xC50F ); -+ mac_ocp_write( tp, 0xF86E, 0x76A4 ); -+ mac_ocp_write( tp, 0xF870, 0x49E3 ); -+ mac_ocp_write( tp, 0xF872, 0xF007 ); -+ mac_ocp_write( tp, 0xF874, 0x49C0 ); -+ mac_ocp_write( tp, 0xF876, 0xF103 ); -+ mac_ocp_write( tp, 0xF878, 0xC607 ); -+ mac_ocp_write( tp, 0xF87A, 0xBE00 ); -+ mac_ocp_write( tp, 0xF87C, 0xC606 ); -+ mac_ocp_write( tp, 0xF87E, 0xBE00 ); -+ mac_ocp_write( tp, 0xF880, 0xC602 ); -+ mac_ocp_write( tp, 0xF882, 0xBE00 ); -+ mac_ocp_write( tp, 0xF884, 0x0A88 ); -+ mac_ocp_write( tp, 0xF886, 0x0A64 ); -+ mac_ocp_write( tp, 0xF888, 0x0A68 ); -+ mac_ocp_write( tp, 0xF88A, 0xDC00 ); -+ mac_ocp_write( tp, 0xF88C, 0xC602 ); -+ mac_ocp_write( tp, 0xF88E, 0xBE00 ); -+ mac_ocp_write( tp, 0xF890, 0x0000 ); -+ mac_ocp_write( tp, 0xF892, 0xC602 ); -+ mac_ocp_write( tp, 0xF894, 0xBE00 ); -+ mac_ocp_write( tp, 0xF896, 0x0000 ); -+ mac_ocp_write( tp, 0xF898, 0xC602 ); -+ mac_ocp_write( tp, 0xF89A, 0xBE00 ); -+ mac_ocp_write( tp, 0xF89C, 0x0000 ); -+ mac_ocp_write( tp, 0xF89E, 0xC602 ); -+ mac_ocp_write( tp, 0xF8A0, 0xBE00 ); -+ mac_ocp_write( tp, 0xF8A2, 0x0000 ); -+ -+ mac_ocp_write( tp, 0xFC26, 0x8000 ); -+ -+ mac_ocp_write( tp, 0xFC2A, 0x0A2F ); -+ mac_ocp_write( tp, 0xFC2C, 0x0297 ); -+ mac_ocp_write( tp, 0xFC2E, 0x0A61 ); -+ } else if (tp->mcfg == CFG_METHOD_26) { -+ rtl8168_hw_disable_mac_mcu_bps(dev); -+ -+ mac_ocp_write( tp, 0xF800, 0xE008 ); -+ mac_ocp_write( tp, 0xF802, 0xE00A ); -+ mac_ocp_write( tp, 0xF804, 0xE00C ); -+ mac_ocp_write( tp, 0xF806, 0xE00E ); -+ mac_ocp_write( tp, 0xF808, 0xE027 ); -+ mac_ocp_write( tp, 0xF80A, 0xE04F ); -+ mac_ocp_write( tp, 0xF80C, 0xE05E ); -+ mac_ocp_write( tp, 0xF80E, 0xE065 ); -+ mac_ocp_write( tp, 0xF810, 0xC602 ); -+ mac_ocp_write( tp, 0xF812, 0xBE00 ); -+ mac_ocp_write( tp, 0xF814, 0x0000 ); -+ mac_ocp_write( tp, 0xF816, 0xC502 ); -+ mac_ocp_write( tp, 0xF818, 0xBD00 ); -+ mac_ocp_write( tp, 0xF81A, 0x074C ); -+ mac_ocp_write( tp, 0xF81C, 0xC302 ); -+ mac_ocp_write( tp, 0xF81E, 0xBB00 ); -+ mac_ocp_write( tp, 0xF820, 0x080A ); -+ mac_ocp_write( tp, 0xF822, 0x6420 ); -+ mac_ocp_write( tp, 0xF824, 0x48C2 ); -+ mac_ocp_write( tp, 0xF826, 0x8C20 ); -+ mac_ocp_write( tp, 0xF828, 0xC516 ); -+ mac_ocp_write( tp, 0xF82A, 0x64A4 ); -+ mac_ocp_write( tp, 0xF82C, 0x49C0 ); -+ mac_ocp_write( tp, 0xF82E, 0xF009 ); -+ mac_ocp_write( tp, 0xF830, 0x74A2 ); -+ mac_ocp_write( tp, 0xF832, 0x8CA5 ); -+ mac_ocp_write( tp, 0xF834, 0x74A0 ); -+ mac_ocp_write( tp, 0xF836, 0xC50E ); -+ mac_ocp_write( tp, 0xF838, 0x9CA2 ); -+ mac_ocp_write( tp, 0xF83A, 0x1C11 ); -+ mac_ocp_write( tp, 0xF83C, 0x9CA0 ); -+ mac_ocp_write( tp, 0xF83E, 0xE006 ); -+ mac_ocp_write( tp, 0xF840, 0x74F8 ); -+ mac_ocp_write( tp, 0xF842, 0x48C4 ); -+ mac_ocp_write( tp, 0xF844, 0x8CF8 ); -+ mac_ocp_write( tp, 0xF846, 0xC404 ); -+ mac_ocp_write( tp, 0xF848, 0xBC00 ); -+ mac_ocp_write( tp, 0xF84A, 0xC403 ); -+ mac_ocp_write( tp, 0xF84C, 0xBC00 ); -+ mac_ocp_write( tp, 0xF84E, 0x0BF2 ); -+ mac_ocp_write( tp, 0xF850, 0x0C0A ); -+ mac_ocp_write( tp, 0xF852, 0xE434 ); -+ mac_ocp_write( tp, 0xF854, 0xD3C0 ); -+ mac_ocp_write( tp, 0xF856, 0x49D9 ); -+ mac_ocp_write( tp, 0xF858, 0xF01F ); -+ mac_ocp_write( tp, 0xF85A, 0xC526 ); -+ mac_ocp_write( tp, 0xF85C, 0x64A5 ); -+ mac_ocp_write( tp, 0xF85E, 0x1400 ); -+ mac_ocp_write( tp, 0xF860, 0xF007 ); -+ mac_ocp_write( tp, 0xF862, 0x0C01 ); -+ mac_ocp_write( tp, 0xF864, 0x8CA5 ); -+ mac_ocp_write( tp, 0xF866, 0x1C15 ); -+ mac_ocp_write( tp, 0xF868, 0xC51B ); -+ mac_ocp_write( tp, 0xF86A, 0x9CA0 ); -+ mac_ocp_write( tp, 0xF86C, 0xE013 ); -+ mac_ocp_write( tp, 0xF86E, 0xC519 ); -+ mac_ocp_write( tp, 0xF870, 0x74A0 ); -+ mac_ocp_write( tp, 0xF872, 0x48C4 ); -+ mac_ocp_write( tp, 0xF874, 0x8CA0 ); -+ mac_ocp_write( tp, 0xF876, 0xC516 ); -+ mac_ocp_write( tp, 0xF878, 0x74A4 ); -+ mac_ocp_write( tp, 0xF87A, 0x48C8 ); -+ mac_ocp_write( tp, 0xF87C, 0x48CA ); -+ mac_ocp_write( tp, 0xF87E, 0x9CA4 ); -+ mac_ocp_write( tp, 0xF880, 0xC512 ); -+ mac_ocp_write( tp, 0xF882, 0x1B00 ); -+ mac_ocp_write( tp, 0xF884, 0x9BA0 ); -+ mac_ocp_write( tp, 0xF886, 0x1B1C ); -+ mac_ocp_write( tp, 0xF888, 0x483F ); -+ mac_ocp_write( tp, 0xF88A, 0x9BA2 ); -+ mac_ocp_write( tp, 0xF88C, 0x1B04 ); -+ mac_ocp_write( tp, 0xF88E, 0xC508 ); -+ mac_ocp_write( tp, 0xF890, 0x9BA0 ); -+ mac_ocp_write( tp, 0xF892, 0xC505 ); -+ mac_ocp_write( tp, 0xF894, 0xBD00 ); -+ mac_ocp_write( tp, 0xF896, 0xC502 ); -+ mac_ocp_write( tp, 0xF898, 0xBD00 ); -+ mac_ocp_write( tp, 0xF89A, 0x0300 ); -+ mac_ocp_write( tp, 0xF89C, 0x051E ); -+ mac_ocp_write( tp, 0xF89E, 0xE434 ); -+ mac_ocp_write( tp, 0xF8A0, 0xE018 ); -+ mac_ocp_write( tp, 0xF8A2, 0xE092 ); -+ mac_ocp_write( tp, 0xF8A4, 0xDE20 ); -+ mac_ocp_write( tp, 0xF8A6, 0xD3C0 ); -+ mac_ocp_write( tp, 0xF8A8, 0xC50F ); -+ mac_ocp_write( tp, 0xF8AA, 0x76A4 ); -+ mac_ocp_write( tp, 0xF8AC, 0x49E3 ); -+ mac_ocp_write( tp, 0xF8AE, 0xF007 ); -+ mac_ocp_write( tp, 0xF8B0, 0x49C0 ); -+ mac_ocp_write( tp, 0xF8B2, 0xF103 ); -+ mac_ocp_write( tp, 0xF8B4, 0xC607 ); -+ mac_ocp_write( tp, 0xF8B6, 0xBE00 ); -+ mac_ocp_write( tp, 0xF8B8, 0xC606 ); -+ mac_ocp_write( tp, 0xF8BA, 0xBE00 ); -+ mac_ocp_write( tp, 0xF8BC, 0xC602 ); -+ mac_ocp_write( tp, 0xF8BE, 0xBE00 ); -+ mac_ocp_write( tp, 0xF8C0, 0x0C4C ); -+ mac_ocp_write( tp, 0xF8C2, 0x0C28 ); -+ mac_ocp_write( tp, 0xF8C4, 0x0C2C ); -+ mac_ocp_write( tp, 0xF8C6, 0xDC00 ); -+ mac_ocp_write( tp, 0xF8C8, 0xC707 ); -+ mac_ocp_write( tp, 0xF8CA, 0x1D00 ); -+ mac_ocp_write( tp, 0xF8CC, 0x8DE2 ); -+ mac_ocp_write( tp, 0xF8CE, 0x48C1 ); -+ mac_ocp_write( tp, 0xF8D0, 0xC502 ); -+ mac_ocp_write( tp, 0xF8D2, 0xBD00 ); -+ mac_ocp_write( tp, 0xF8D4, 0x00AA ); -+ mac_ocp_write( tp, 0xF8D6, 0xE0C0 ); -+ mac_ocp_write( tp, 0xF8D8, 0xC502 ); -+ mac_ocp_write( tp, 0xF8DA, 0xBD00 ); -+ mac_ocp_write( tp, 0xF8DC, 0x0132 ); -+ -+ mac_ocp_write( tp, 0xFC26, 0x8000 ); -+ -+ mac_ocp_write( tp, 0xFC2A, 0x0743 ); -+ mac_ocp_write( tp, 0xFC2C, 0x0801 ); -+ mac_ocp_write( tp, 0xFC2E, 0x0BE9 ); -+ mac_ocp_write( tp, 0xFC30, 0x02FD ); -+ mac_ocp_write( tp, 0xFC32, 0x0C25 ); -+ mac_ocp_write( tp, 0xFC34, 0x00A9 ); -+ mac_ocp_write( tp, 0xFC36, 0x012D ); -+ } else if (tp->mcfg == CFG_METHOD_27) { -+ rtl8168_hw_disable_mac_mcu_bps(dev); -+ -+ mac_ocp_write( tp, 0xF800, 0xE008 ); -+ mac_ocp_write( tp, 0xF802, 0xE0D3 ); -+ mac_ocp_write( tp, 0xF804, 0xE0D6 ); -+ mac_ocp_write( tp, 0xF806, 0xE0D9 ); -+ mac_ocp_write( tp, 0xF808, 0xE0DB ); -+ mac_ocp_write( tp, 0xF80A, 0xE0DD ); -+ mac_ocp_write( tp, 0xF80C, 0xE0DF ); -+ mac_ocp_write( tp, 0xF80E, 0xE0E1 ); -+ mac_ocp_write( tp, 0xF810, 0xC251 ); -+ mac_ocp_write( tp, 0xF812, 0x7340 ); -+ mac_ocp_write( tp, 0xF814, 0x49B1 ); -+ mac_ocp_write( tp, 0xF816, 0xF010 ); -+ mac_ocp_write( tp, 0xF818, 0x1D02 ); -+ mac_ocp_write( tp, 0xF81A, 0x8D40 ); -+ mac_ocp_write( tp, 0xF81C, 0xC202 ); -+ mac_ocp_write( tp, 0xF81E, 0xBA00 ); -+ mac_ocp_write( tp, 0xF820, 0x2C3A ); -+ mac_ocp_write( tp, 0xF822, 0xC0F0 ); -+ mac_ocp_write( tp, 0xF824, 0xE8DE ); -+ mac_ocp_write( tp, 0xF826, 0x2000 ); -+ mac_ocp_write( tp, 0xF828, 0x8000 ); -+ mac_ocp_write( tp, 0xF82A, 0xC0B6 ); -+ mac_ocp_write( tp, 0xF82C, 0x268C ); -+ mac_ocp_write( tp, 0xF82E, 0x752C ); -+ mac_ocp_write( tp, 0xF830, 0x49D4 ); -+ mac_ocp_write( tp, 0xF832, 0xF112 ); -+ mac_ocp_write( tp, 0xF834, 0xE025 ); -+ mac_ocp_write( tp, 0xF836, 0xC2F6 ); -+ mac_ocp_write( tp, 0xF838, 0x7146 ); -+ mac_ocp_write( tp, 0xF83A, 0xC2F5 ); -+ mac_ocp_write( tp, 0xF83C, 0x7340 ); -+ mac_ocp_write( tp, 0xF83E, 0x49BE ); -+ mac_ocp_write( tp, 0xF840, 0xF103 ); -+ mac_ocp_write( tp, 0xF842, 0xC7F2 ); -+ mac_ocp_write( tp, 0xF844, 0xE002 ); -+ mac_ocp_write( tp, 0xF846, 0xC7F1 ); -+ mac_ocp_write( tp, 0xF848, 0x304F ); -+ mac_ocp_write( tp, 0xF84A, 0x6226 ); -+ mac_ocp_write( tp, 0xF84C, 0x49A1 ); -+ mac_ocp_write( tp, 0xF84E, 0xF1F0 ); -+ mac_ocp_write( tp, 0xF850, 0x7222 ); -+ mac_ocp_write( tp, 0xF852, 0x49A0 ); -+ mac_ocp_write( tp, 0xF854, 0xF1ED ); -+ mac_ocp_write( tp, 0xF856, 0x2525 ); -+ mac_ocp_write( tp, 0xF858, 0x1F28 ); -+ mac_ocp_write( tp, 0xF85A, 0x3097 ); -+ mac_ocp_write( tp, 0xF85C, 0x3091 ); -+ mac_ocp_write( tp, 0xF85E, 0x9A36 ); -+ mac_ocp_write( tp, 0xF860, 0x752C ); -+ mac_ocp_write( tp, 0xF862, 0x21DC ); -+ mac_ocp_write( tp, 0xF864, 0x25BC ); -+ mac_ocp_write( tp, 0xF866, 0xC6E2 ); -+ mac_ocp_write( tp, 0xF868, 0x77C0 ); -+ mac_ocp_write( tp, 0xF86A, 0x1304 ); -+ mac_ocp_write( tp, 0xF86C, 0xF014 ); -+ mac_ocp_write( tp, 0xF86E, 0x1303 ); -+ mac_ocp_write( tp, 0xF870, 0xF014 ); -+ mac_ocp_write( tp, 0xF872, 0x1302 ); -+ mac_ocp_write( tp, 0xF874, 0xF014 ); -+ mac_ocp_write( tp, 0xF876, 0x1301 ); -+ mac_ocp_write( tp, 0xF878, 0xF014 ); -+ mac_ocp_write( tp, 0xF87A, 0x49D4 ); -+ mac_ocp_write( tp, 0xF87C, 0xF103 ); -+ mac_ocp_write( tp, 0xF87E, 0xC3D7 ); -+ mac_ocp_write( tp, 0xF880, 0xBB00 ); -+ mac_ocp_write( tp, 0xF882, 0xC618 ); -+ mac_ocp_write( tp, 0xF884, 0x67C6 ); -+ mac_ocp_write( tp, 0xF886, 0x752E ); -+ mac_ocp_write( tp, 0xF888, 0x22D7 ); -+ mac_ocp_write( tp, 0xF88A, 0x26DD ); -+ mac_ocp_write( tp, 0xF88C, 0x1505 ); -+ mac_ocp_write( tp, 0xF88E, 0xF013 ); -+ mac_ocp_write( tp, 0xF890, 0xC60A ); -+ mac_ocp_write( tp, 0xF892, 0xBE00 ); -+ mac_ocp_write( tp, 0xF894, 0xC309 ); -+ mac_ocp_write( tp, 0xF896, 0xBB00 ); -+ mac_ocp_write( tp, 0xF898, 0xC308 ); -+ mac_ocp_write( tp, 0xF89A, 0xBB00 ); -+ mac_ocp_write( tp, 0xF89C, 0xC307 ); -+ mac_ocp_write( tp, 0xF89E, 0xBB00 ); -+ mac_ocp_write( tp, 0xF8A0, 0xC306 ); -+ mac_ocp_write( tp, 0xF8A2, 0xBB00 ); -+ mac_ocp_write( tp, 0xF8A4, 0x25C8 ); -+ mac_ocp_write( tp, 0xF8A6, 0x25A6 ); -+ mac_ocp_write( tp, 0xF8A8, 0x25AC ); -+ mac_ocp_write( tp, 0xF8AA, 0x25B2 ); -+ mac_ocp_write( tp, 0xF8AC, 0x25B8 ); -+ mac_ocp_write( tp, 0xF8AE, 0xCD08 ); -+ mac_ocp_write( tp, 0xF8B0, 0x0000 ); -+ mac_ocp_write( tp, 0xF8B2, 0xC0BC ); -+ mac_ocp_write( tp, 0xF8B4, 0xC2FF ); -+ mac_ocp_write( tp, 0xF8B6, 0x7340 ); -+ mac_ocp_write( tp, 0xF8B8, 0x49B0 ); -+ mac_ocp_write( tp, 0xF8BA, 0xF04E ); -+ mac_ocp_write( tp, 0xF8BC, 0x1F46 ); -+ mac_ocp_write( tp, 0xF8BE, 0x308F ); -+ mac_ocp_write( tp, 0xF8C0, 0xC3F7 ); -+ mac_ocp_write( tp, 0xF8C2, 0x1C04 ); -+ mac_ocp_write( tp, 0xF8C4, 0xE84D ); -+ mac_ocp_write( tp, 0xF8C6, 0x1401 ); -+ mac_ocp_write( tp, 0xF8C8, 0xF147 ); -+ mac_ocp_write( tp, 0xF8CA, 0x7226 ); -+ mac_ocp_write( tp, 0xF8CC, 0x49A7 ); -+ mac_ocp_write( tp, 0xF8CE, 0xF044 ); -+ mac_ocp_write( tp, 0xF8D0, 0x7222 ); -+ mac_ocp_write( tp, 0xF8D2, 0x2525 ); -+ mac_ocp_write( tp, 0xF8D4, 0x1F30 ); -+ mac_ocp_write( tp, 0xF8D6, 0x3097 ); -+ mac_ocp_write( tp, 0xF8D8, 0x3091 ); -+ mac_ocp_write( tp, 0xF8DA, 0x7340 ); -+ mac_ocp_write( tp, 0xF8DC, 0xC4EA ); -+ mac_ocp_write( tp, 0xF8DE, 0x401C ); -+ mac_ocp_write( tp, 0xF8E0, 0xF006 ); -+ mac_ocp_write( tp, 0xF8E2, 0xC6E8 ); -+ mac_ocp_write( tp, 0xF8E4, 0x75C0 ); -+ mac_ocp_write( tp, 0xF8E6, 0x49D7 ); -+ mac_ocp_write( tp, 0xF8E8, 0xF105 ); -+ mac_ocp_write( tp, 0xF8EA, 0xE036 ); -+ mac_ocp_write( tp, 0xF8EC, 0x1D08 ); -+ mac_ocp_write( tp, 0xF8EE, 0x8DC1 ); -+ mac_ocp_write( tp, 0xF8F0, 0x0208 ); -+ mac_ocp_write( tp, 0xF8F2, 0x6640 ); -+ mac_ocp_write( tp, 0xF8F4, 0x2764 ); -+ mac_ocp_write( tp, 0xF8F6, 0x1606 ); -+ mac_ocp_write( tp, 0xF8F8, 0xF12F ); -+ mac_ocp_write( tp, 0xF8FA, 0x6346 ); -+ mac_ocp_write( tp, 0xF8FC, 0x133B ); -+ mac_ocp_write( tp, 0xF8FE, 0xF12C ); -+ mac_ocp_write( tp, 0xF900, 0x9B34 ); -+ mac_ocp_write( tp, 0xF902, 0x1B18 ); -+ mac_ocp_write( tp, 0xF904, 0x3093 ); -+ mac_ocp_write( tp, 0xF906, 0xC32A ); -+ mac_ocp_write( tp, 0xF908, 0x1C10 ); -+ mac_ocp_write( tp, 0xF90A, 0xE82A ); -+ mac_ocp_write( tp, 0xF90C, 0x1401 ); -+ mac_ocp_write( tp, 0xF90E, 0xF124 ); -+ mac_ocp_write( tp, 0xF910, 0x1A36 ); -+ mac_ocp_write( tp, 0xF912, 0x308A ); -+ mac_ocp_write( tp, 0xF914, 0x7322 ); -+ mac_ocp_write( tp, 0xF916, 0x25B5 ); -+ mac_ocp_write( tp, 0xF918, 0x0B0E ); -+ mac_ocp_write( tp, 0xF91A, 0x1C00 ); -+ mac_ocp_write( tp, 0xF91C, 0xE82C ); -+ mac_ocp_write( tp, 0xF91E, 0xC71F ); -+ mac_ocp_write( tp, 0xF920, 0x4027 ); -+ mac_ocp_write( tp, 0xF922, 0xF11A ); -+ mac_ocp_write( tp, 0xF924, 0xE838 ); -+ mac_ocp_write( tp, 0xF926, 0x1F42 ); -+ mac_ocp_write( tp, 0xF928, 0x308F ); -+ mac_ocp_write( tp, 0xF92A, 0x1B08 ); -+ mac_ocp_write( tp, 0xF92C, 0xE824 ); -+ mac_ocp_write( tp, 0xF92E, 0x7236 ); -+ mac_ocp_write( tp, 0xF930, 0x7746 ); -+ mac_ocp_write( tp, 0xF932, 0x1700 ); -+ mac_ocp_write( tp, 0xF934, 0xF00D ); -+ mac_ocp_write( tp, 0xF936, 0xC313 ); -+ mac_ocp_write( tp, 0xF938, 0x401F ); -+ mac_ocp_write( tp, 0xF93A, 0xF103 ); -+ mac_ocp_write( tp, 0xF93C, 0x1F00 ); -+ mac_ocp_write( tp, 0xF93E, 0x9F46 ); -+ mac_ocp_write( tp, 0xF940, 0x7744 ); -+ mac_ocp_write( tp, 0xF942, 0x449F ); -+ mac_ocp_write( tp, 0xF944, 0x445F ); -+ mac_ocp_write( tp, 0xF946, 0xE817 ); -+ mac_ocp_write( tp, 0xF948, 0xC70A ); -+ mac_ocp_write( tp, 0xF94A, 0x4027 ); -+ mac_ocp_write( tp, 0xF94C, 0xF105 ); -+ mac_ocp_write( tp, 0xF94E, 0xC302 ); -+ mac_ocp_write( tp, 0xF950, 0xBB00 ); -+ mac_ocp_write( tp, 0xF952, 0x2E08 ); -+ mac_ocp_write( tp, 0xF954, 0x2DC2 ); -+ mac_ocp_write( tp, 0xF956, 0xC7FF ); -+ mac_ocp_write( tp, 0xF958, 0xBF00 ); -+ mac_ocp_write( tp, 0xF95A, 0xCDB8 ); -+ mac_ocp_write( tp, 0xF95C, 0xFFFF ); -+ mac_ocp_write( tp, 0xF95E, 0x0C02 ); -+ mac_ocp_write( tp, 0xF960, 0xA554 ); -+ mac_ocp_write( tp, 0xF962, 0xA5DC ); -+ mac_ocp_write( tp, 0xF964, 0x402F ); -+ mac_ocp_write( tp, 0xF966, 0xF105 ); -+ mac_ocp_write( tp, 0xF968, 0x1400 ); -+ mac_ocp_write( tp, 0xF96A, 0xF1FA ); -+ mac_ocp_write( tp, 0xF96C, 0x1C01 ); -+ mac_ocp_write( tp, 0xF96E, 0xE002 ); -+ mac_ocp_write( tp, 0xF970, 0x1C00 ); -+ mac_ocp_write( tp, 0xF972, 0xFF80 ); -+ mac_ocp_write( tp, 0xF974, 0x49B0 ); -+ mac_ocp_write( tp, 0xF976, 0xF004 ); -+ mac_ocp_write( tp, 0xF978, 0x0B01 ); -+ mac_ocp_write( tp, 0xF97A, 0xA1D3 ); -+ mac_ocp_write( tp, 0xF97C, 0xE003 ); -+ mac_ocp_write( tp, 0xF97E, 0x0B02 ); -+ mac_ocp_write( tp, 0xF980, 0xA5D3 ); -+ mac_ocp_write( tp, 0xF982, 0x3127 ); -+ mac_ocp_write( tp, 0xF984, 0x3720 ); -+ mac_ocp_write( tp, 0xF986, 0x0B02 ); -+ mac_ocp_write( tp, 0xF988, 0xA5D3 ); -+ mac_ocp_write( tp, 0xF98A, 0x3127 ); -+ mac_ocp_write( tp, 0xF98C, 0x3720 ); -+ mac_ocp_write( tp, 0xF98E, 0x1300 ); -+ mac_ocp_write( tp, 0xF990, 0xF1FB ); -+ mac_ocp_write( tp, 0xF992, 0xFF80 ); -+ mac_ocp_write( tp, 0xF994, 0x7322 ); -+ mac_ocp_write( tp, 0xF996, 0x25B5 ); -+ mac_ocp_write( tp, 0xF998, 0x1E28 ); -+ mac_ocp_write( tp, 0xF99A, 0x30DE ); -+ mac_ocp_write( tp, 0xF99C, 0x30D9 ); -+ mac_ocp_write( tp, 0xF99E, 0x7264 ); -+ mac_ocp_write( tp, 0xF9A0, 0x1E11 ); -+ mac_ocp_write( tp, 0xF9A2, 0x2368 ); -+ mac_ocp_write( tp, 0xF9A4, 0x3116 ); -+ mac_ocp_write( tp, 0xF9A6, 0xFF80 ); -+ mac_ocp_write( tp, 0xF9A8, 0x1B7E ); -+ mac_ocp_write( tp, 0xF9AA, 0xC602 ); -+ mac_ocp_write( tp, 0xF9AC, 0xBE00 ); -+ mac_ocp_write( tp, 0xF9AE, 0x06A6 ); -+ mac_ocp_write( tp, 0xF9B0, 0x1B7E ); -+ mac_ocp_write( tp, 0xF9B2, 0xC602 ); -+ mac_ocp_write( tp, 0xF9B4, 0xBE00 ); -+ mac_ocp_write( tp, 0xF9B6, 0x0764 ); -+ mac_ocp_write( tp, 0xF9B8, 0xC602 ); -+ mac_ocp_write( tp, 0xF9BA, 0xBE00 ); -+ mac_ocp_write( tp, 0xF9BC, 0x0000 ); -+ mac_ocp_write( tp, 0xF9BE, 0xC602 ); -+ mac_ocp_write( tp, 0xF9C0, 0xBE00 ); -+ mac_ocp_write( tp, 0xF9C2, 0x0000 ); -+ mac_ocp_write( tp, 0xF9C4, 0xC602 ); -+ mac_ocp_write( tp, 0xF9C6, 0xBE00 ); -+ mac_ocp_write( tp, 0xF9C8, 0x0000 ); -+ mac_ocp_write( tp, 0xF9CA, 0xC602 ); -+ mac_ocp_write( tp, 0xF9CC, 0xBE00 ); -+ mac_ocp_write( tp, 0xF9CE, 0x0000 ); -+ mac_ocp_write( tp, 0xF9D0, 0xC602 ); -+ mac_ocp_write( tp, 0xF9D2, 0xBE00 ); -+ mac_ocp_write( tp, 0xF9D4, 0x0000 ); -+ -+ mac_ocp_write( tp, 0xFC26, 0x8000 ); -+ -+ mac_ocp_write( tp, 0xFC28, 0x2549 ); -+ mac_ocp_write( tp, 0xFC2A, 0x06A5 ); -+ mac_ocp_write( tp, 0xFC2C, 0x0763 ); -+ } else if (tp->mcfg == CFG_METHOD_28) { -+ rtl8168_hw_disable_mac_mcu_bps(dev); -+ -+ mac_ocp_write( tp, 0xF800, 0xE008 ); -+ mac_ocp_write( tp, 0xF802, 0xE017 ); -+ mac_ocp_write( tp, 0xF804, 0xE019 ); -+ mac_ocp_write( tp, 0xF806, 0xE01B ); -+ mac_ocp_write( tp, 0xF808, 0xE01D ); -+ mac_ocp_write( tp, 0xF80A, 0xE01F ); -+ mac_ocp_write( tp, 0xF80C, 0xE021 ); -+ mac_ocp_write( tp, 0xF80E, 0xE023 ); -+ mac_ocp_write( tp, 0xF810, 0xC50F ); -+ mac_ocp_write( tp, 0xF812, 0x76A4 ); -+ mac_ocp_write( tp, 0xF814, 0x49E3 ); -+ mac_ocp_write( tp, 0xF816, 0xF007 ); -+ mac_ocp_write( tp, 0xF818, 0x49C0 ); -+ mac_ocp_write( tp, 0xF81A, 0xF103 ); -+ mac_ocp_write( tp, 0xF81C, 0xC607 ); -+ mac_ocp_write( tp, 0xF81E, 0xBE00 ); -+ mac_ocp_write( tp, 0xF820, 0xC606 ); -+ mac_ocp_write( tp, 0xF822, 0xBE00 ); -+ mac_ocp_write( tp, 0xF824, 0xC602 ); -+ mac_ocp_write( tp, 0xF826, 0xBE00 ); -+ mac_ocp_write( tp, 0xF828, 0x0BDA ); -+ mac_ocp_write( tp, 0xF82A, 0x0BB0 ); -+ mac_ocp_write( tp, 0xF82C, 0x0BBA ); -+ mac_ocp_write( tp, 0xF82E, 0xDC00 ); -+ mac_ocp_write( tp, 0xF830, 0xC602 ); -+ mac_ocp_write( tp, 0xF832, 0xBE00 ); -+ mac_ocp_write( tp, 0xF834, 0x0000 ); -+ mac_ocp_write( tp, 0xF836, 0xC602 ); -+ mac_ocp_write( tp, 0xF838, 0xBE00 ); -+ mac_ocp_write( tp, 0xF83A, 0x0000 ); -+ mac_ocp_write( tp, 0xF83C, 0xC602 ); -+ mac_ocp_write( tp, 0xF83E, 0xBE00 ); -+ mac_ocp_write( tp, 0xF840, 0x0000 ); -+ mac_ocp_write( tp, 0xF842, 0xC602 ); -+ mac_ocp_write( tp, 0xF844, 0xBE00 ); -+ mac_ocp_write( tp, 0xF846, 0x0000 ); -+ mac_ocp_write( tp, 0xF848, 0xC602 ); -+ mac_ocp_write( tp, 0xF84A, 0xBE00 ); -+ mac_ocp_write( tp, 0xF84C, 0x0000 ); -+ mac_ocp_write( tp, 0xF84E, 0xC602 ); -+ mac_ocp_write( tp, 0xF850, 0xBE00 ); -+ mac_ocp_write( tp, 0xF852, 0x0000 ); -+ mac_ocp_write( tp, 0xF854, 0xC602 ); -+ mac_ocp_write( tp, 0xF856, 0xBE00 ); -+ mac_ocp_write( tp, 0xF858, 0x0000 ); -+ -+ mac_ocp_write( tp, 0xFC26, 0x8000 ); -+ -+ mac_ocp_write( tp, 0xFC28, 0x0BB3 ); -+ } else if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ rtl8168_hw_disable_mac_mcu_bps(dev); -+ -+ mac_ocp_write(tp, 0xF800, 0xE008); -+ mac_ocp_write(tp, 0xF802, 0xE00F); -+ mac_ocp_write(tp, 0xF804, 0xE011); -+ mac_ocp_write(tp, 0xF806, 0xE047); -+ mac_ocp_write(tp, 0xF808, 0xE049); -+ mac_ocp_write(tp, 0xF80A, 0xE073); -+ mac_ocp_write(tp, 0xF80C, 0xE075); -+ mac_ocp_write(tp, 0xF80E, 0xE077); -+ mac_ocp_write(tp, 0xF810, 0xC707); -+ mac_ocp_write(tp, 0xF812, 0x1D00); -+ mac_ocp_write(tp, 0xF814, 0x8DE2); -+ mac_ocp_write(tp, 0xF816, 0x48C1); -+ mac_ocp_write(tp, 0xF818, 0xC502); -+ mac_ocp_write(tp, 0xF81A, 0xBD00); -+ mac_ocp_write(tp, 0xF81C, 0x00E4); -+ mac_ocp_write(tp, 0xF81E, 0xE0C0); -+ mac_ocp_write(tp, 0xF820, 0xC502); -+ mac_ocp_write(tp, 0xF822, 0xBD00); -+ mac_ocp_write(tp, 0xF824, 0x0216); -+ mac_ocp_write(tp, 0xF826, 0xC634); -+ mac_ocp_write(tp, 0xF828, 0x75C0); -+ mac_ocp_write(tp, 0xF82A, 0x49D3); -+ mac_ocp_write(tp, 0xF82C, 0xF027); -+ mac_ocp_write(tp, 0xF82E, 0xC631); -+ mac_ocp_write(tp, 0xF830, 0x75C0); -+ mac_ocp_write(tp, 0xF832, 0x49D3); -+ mac_ocp_write(tp, 0xF834, 0xF123); -+ mac_ocp_write(tp, 0xF836, 0xC627); -+ mac_ocp_write(tp, 0xF838, 0x75C0); -+ mac_ocp_write(tp, 0xF83A, 0xB405); -+ mac_ocp_write(tp, 0xF83C, 0xC525); -+ mac_ocp_write(tp, 0xF83E, 0x9DC0); -+ mac_ocp_write(tp, 0xF840, 0xC621); -+ mac_ocp_write(tp, 0xF842, 0x75C8); -+ mac_ocp_write(tp, 0xF844, 0x49D5); -+ mac_ocp_write(tp, 0xF846, 0xF00A); -+ mac_ocp_write(tp, 0xF848, 0x49D6); -+ mac_ocp_write(tp, 0xF84A, 0xF008); -+ mac_ocp_write(tp, 0xF84C, 0x49D7); -+ mac_ocp_write(tp, 0xF84E, 0xF006); -+ mac_ocp_write(tp, 0xF850, 0x49D8); -+ mac_ocp_write(tp, 0xF852, 0xF004); -+ mac_ocp_write(tp, 0xF854, 0x75D2); -+ mac_ocp_write(tp, 0xF856, 0x49D9); -+ mac_ocp_write(tp, 0xF858, 0xF111); -+ mac_ocp_write(tp, 0xF85A, 0xC517); -+ mac_ocp_write(tp, 0xF85C, 0x9DC8); -+ mac_ocp_write(tp, 0xF85E, 0xC516); -+ mac_ocp_write(tp, 0xF860, 0x9DD2); -+ mac_ocp_write(tp, 0xF862, 0xC618); -+ mac_ocp_write(tp, 0xF864, 0x75C0); -+ mac_ocp_write(tp, 0xF866, 0x49D4); -+ mac_ocp_write(tp, 0xF868, 0xF003); -+ mac_ocp_write(tp, 0xF86A, 0x49D0); -+ mac_ocp_write(tp, 0xF86C, 0xF104); -+ mac_ocp_write(tp, 0xF86E, 0xC60A); -+ mac_ocp_write(tp, 0xF870, 0xC50E); -+ mac_ocp_write(tp, 0xF872, 0x9DC0); -+ mac_ocp_write(tp, 0xF874, 0xB005); -+ mac_ocp_write(tp, 0xF876, 0xC607); -+ mac_ocp_write(tp, 0xF878, 0x9DC0); -+ mac_ocp_write(tp, 0xF87A, 0xB007); -+ mac_ocp_write(tp, 0xF87C, 0xC602); -+ mac_ocp_write(tp, 0xF87E, 0xBE00); -+ mac_ocp_write(tp, 0xF880, 0x1A06); -+ mac_ocp_write(tp, 0xF882, 0xB400); -+ mac_ocp_write(tp, 0xF884, 0xE86C); -+ mac_ocp_write(tp, 0xF886, 0xA000); -+ mac_ocp_write(tp, 0xF888, 0x01E1); -+ mac_ocp_write(tp, 0xF88A, 0x0200); -+ mac_ocp_write(tp, 0xF88C, 0x9200); -+ mac_ocp_write(tp, 0xF88E, 0xE84C); -+ mac_ocp_write(tp, 0xF890, 0xE004); -+ mac_ocp_write(tp, 0xF892, 0xE908); -+ mac_ocp_write(tp, 0xF894, 0xC502); -+ mac_ocp_write(tp, 0xF896, 0xBD00); -+ mac_ocp_write(tp, 0xF898, 0x0B58); -+ mac_ocp_write(tp, 0xF89A, 0xB407); -+ mac_ocp_write(tp, 0xF89C, 0xB404); -+ mac_ocp_write(tp, 0xF89E, 0x2195); -+ mac_ocp_write(tp, 0xF8A0, 0x25BD); -+ mac_ocp_write(tp, 0xF8A2, 0x9BE0); -+ mac_ocp_write(tp, 0xF8A4, 0x1C1C); -+ mac_ocp_write(tp, 0xF8A6, 0x484F); -+ mac_ocp_write(tp, 0xF8A8, 0x9CE2); -+ mac_ocp_write(tp, 0xF8AA, 0x72E2); -+ mac_ocp_write(tp, 0xF8AC, 0x49AE); -+ mac_ocp_write(tp, 0xF8AE, 0xF1FE); -+ mac_ocp_write(tp, 0xF8B0, 0x0B00); -+ mac_ocp_write(tp, 0xF8B2, 0xF116); -+ mac_ocp_write(tp, 0xF8B4, 0xC71C); -+ mac_ocp_write(tp, 0xF8B6, 0xC419); -+ mac_ocp_write(tp, 0xF8B8, 0x9CE0); -+ mac_ocp_write(tp, 0xF8BA, 0x1C13); -+ mac_ocp_write(tp, 0xF8BC, 0x484F); -+ mac_ocp_write(tp, 0xF8BE, 0x9CE2); -+ mac_ocp_write(tp, 0xF8C0, 0x74E2); -+ mac_ocp_write(tp, 0xF8C2, 0x49CE); -+ mac_ocp_write(tp, 0xF8C4, 0xF1FE); -+ mac_ocp_write(tp, 0xF8C6, 0xC412); -+ mac_ocp_write(tp, 0xF8C8, 0x9CE0); -+ mac_ocp_write(tp, 0xF8CA, 0x1C13); -+ mac_ocp_write(tp, 0xF8CC, 0x484F); -+ mac_ocp_write(tp, 0xF8CE, 0x9CE2); -+ mac_ocp_write(tp, 0xF8D0, 0x74E2); -+ mac_ocp_write(tp, 0xF8D2, 0x49CE); -+ mac_ocp_write(tp, 0xF8D4, 0xF1FE); -+ mac_ocp_write(tp, 0xF8D6, 0xC70C); -+ mac_ocp_write(tp, 0xF8D8, 0x74F8); -+ mac_ocp_write(tp, 0xF8DA, 0x48C3); -+ mac_ocp_write(tp, 0xF8DC, 0x8CF8); -+ mac_ocp_write(tp, 0xF8DE, 0xB004); -+ mac_ocp_write(tp, 0xF8E0, 0xB007); -+ mac_ocp_write(tp, 0xF8E2, 0xC502); -+ mac_ocp_write(tp, 0xF8E4, 0xBD00); -+ mac_ocp_write(tp, 0xF8E6, 0x0F24); -+ mac_ocp_write(tp, 0xF8E8, 0x0481); -+ mac_ocp_write(tp, 0xF8EA, 0x0C81); -+ mac_ocp_write(tp, 0xF8EC, 0xDE24); -+ mac_ocp_write(tp, 0xF8EE, 0xE000); -+ mac_ocp_write(tp, 0xF8F0, 0xC602); -+ mac_ocp_write(tp, 0xF8F2, 0xBE00); -+ mac_ocp_write(tp, 0xF8F4, 0x0CA4); -+ mac_ocp_write(tp, 0xF8F6, 0xC502); -+ mac_ocp_write(tp, 0xF8F8, 0xBD00); -+ mac_ocp_write(tp, 0xF8FA, 0x0000); -+ mac_ocp_write(tp, 0xF8FC, 0xC602); -+ mac_ocp_write(tp, 0xF8FE, 0xBE00); -+ mac_ocp_write(tp, 0xF900, 0x0000); -+ -+ mac_ocp_write(tp, 0xFC26, 0x8000); -+ -+ mac_ocp_write(tp, 0xFC28, 0x00E2); -+ mac_ocp_write(tp, 0xFC2A, 0x0210); -+ mac_ocp_write(tp, 0xFC2C, 0x1A04); -+ mac_ocp_write(tp, 0xFC2E, 0x0B26); -+ -+ mac_ocp_write(tp, 0xFC38, 0x003F); -+ } -+} -+ -+static void -+rtl8168_hw_init(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ unsigned long flags; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ RTL_W8(Cfg9346, Cfg9346_Unlock); -+ RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0); -+ RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7); -+ RTL_W8(Cfg9346, Cfg9346_Lock); -+ RTL_W8(0xF1, RTL_R8(0xF1) & ~BIT_7); -+ break; -+ } -+ -+ //Disable UPS -+ switch (tp->mcfg) { -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ mac_ocp_write(tp, 0xD400, mac_ocp_read( tp, 0xD400) & ~(BIT_0)); -+ break; -+ } -+ -+ //Disable DMA Aggregation -+ switch (tp->mcfg) { -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ mac_ocp_write(tp, 0xE63E, mac_ocp_read( tp, 0xE63E) & ~(BIT_3 | BIT_2 | BIT_1)); -+ mac_ocp_write(tp, 0xE63E, mac_ocp_read( tp, 0xE63E) | (BIT_0)); -+ mac_ocp_write(tp, 0xE63E, mac_ocp_read( tp, 0xE63E) & ~(BIT_0)); -+ mac_ocp_write(tp, 0xC094, 0x0); -+ mac_ocp_write(tp, 0xC09E, 0x0); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_9: -+ case CFG_METHOD_10: -+ RTL_W8(DBG_reg, RTL_R8(DBG_reg) | BIT_1 | BIT_7); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ RTL_W8(0xF2, (RTL_R8(0xF2) & ~(BIT_2 | BIT_1 | BIT_0))); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ if (aspm) { -+ RTL_W8(0x6E, RTL_R8(0x6E) | BIT_6); -+ rtl8168_eri_write(ioaddr, 0x1AE, 2, 0x0403, ERIAR_ExGMAC); -+ } -+ break; -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ if (aspm) { -+ if ((mac_ocp_read(tp, 0xDC00) & BIT_3) || (RTL_R8(Config0) & 0x07)) { -+ RTL_W8(0x6E, RTL_R8(0x6E) | BIT_6); -+ rtl8168_eri_write(ioaddr, 0x1AE, 2, 0x0403, ERIAR_ExGMAC); -+ } -+ } -+ break; -+ } -+ -+ if (tp->mcfg == CFG_METHOD_10 || tp->mcfg == CFG_METHOD_14 || tp->mcfg == CFG_METHOD_15) -+ RTL_W8(0xF3, RTL_R8(0xF3) | BIT_2); -+ -+ rtl8168_hw_mac_mcu_config(dev); -+ -+ /*disable ocp phy power saving*/ -+ if (tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 || -+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 || -+ tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write_phy_ocp(tp, 0x0C41, 0x13, 0x0000); -+ mdio_write_phy_ocp(tp, 0x0C41, 0x13, 0x0500); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ } -+} -+ -+static void -+rtl8168_hw_ephy_config(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ u16 ephy_data; -+ -+ -+ if (tp->mcfg == CFG_METHOD_4) { -+ /*Set EPHY registers begin*/ -+ /*Set EPHY register offset 0x02 bit 11 to 0 and bit 12 to 1*/ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x02); -+ ephy_data &= ~BIT_11; -+ ephy_data |= BIT_12; -+ rtl8168_ephy_write(ioaddr, 0x02, ephy_data); -+ -+ /*Set EPHY register offset 0x03 bit 1 to 1*/ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x03); -+ ephy_data |= (1 << 1); -+ rtl8168_ephy_write(ioaddr, 0x03, ephy_data); -+ -+ /*Set EPHY register offset 0x06 bit 7 to 0*/ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x06); -+ ephy_data &= ~(1 << 7); -+ rtl8168_ephy_write(ioaddr, 0x06, ephy_data); -+ /*Set EPHY registers end*/ -+ } else if (tp->mcfg == CFG_METHOD_5) { -+ /* set EPHY registers */ -+ SetPCIePhyBit(tp, 0x01, BIT_0); -+ -+ ClearAndSetPCIePhyBit(tp, -+ 0x03, -+ BIT_10, -+ BIT_5 -+ ); -+ } else if (tp->mcfg == CFG_METHOD_9) { -+ /* set EPHY registers */ -+ rtl8168_ephy_write(ioaddr, 0x01, 0x7C7F); -+ rtl8168_ephy_write(ioaddr, 0x02, 0x011F); -+ if(tp->eeprom_type != EEPROM_TYPE_NONE) { -+ ClearAndSetPCIePhyBit(tp, -+ 0x03, -+ 0xFFB0, -+ 0x05B0 -+ ); -+ } else { -+ ClearAndSetPCIePhyBit(tp, -+ 0x03, -+ 0xFFF0, -+ 0x05F0 -+ ); -+ } -+ rtl8168_ephy_write(ioaddr, 0x06, 0xB271); -+ rtl8168_ephy_write(ioaddr, 0x07, 0xCE00); -+ } else if (tp->mcfg == CFG_METHOD_10) { -+ /* set EPHY registers */ -+ rtl8168_ephy_write(ioaddr, 0x01, 0x6C7F); -+ rtl8168_ephy_write(ioaddr, 0x02, 0x011F); -+ ClearAndSetPCIePhyBit(tp, -+ 0x03, -+ 0xFFF0, -+ 0x01B0 -+ ); -+ rtl8168_ephy_write(ioaddr, 0x1A, 0x0546); -+ rtl8168_ephy_write(ioaddr, 0x1C, 0x80C4); -+ rtl8168_ephy_write(ioaddr, 0x1D, 0x78E5); -+ rtl8168_ephy_write(ioaddr, 0x0A, 0x8100); -+ } else if (tp->mcfg == CFG_METHOD_12) { -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0B); -+ rtl8168_ephy_write(ioaddr, 0x0B, ephy_data|0x48); -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x19); -+ ephy_data &= ~0x20; -+ rtl8168_ephy_write(ioaddr, 0x19, ephy_data|0x50); -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0C); -+ ephy_data &= ~0x100; -+ rtl8168_ephy_write(ioaddr, 0x0C, ephy_data|0x20); -+ } else if (tp->mcfg == CFG_METHOD_14 || tp->mcfg == CFG_METHOD_15) { -+ /* set EPHY registers */ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00) & ~0x0200; -+ ephy_data |= 0x0100; -+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00); -+ ephy_data |= 0x0004; -+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x06) & ~0x0002; -+ ephy_data |= 0x0001; -+ rtl8168_ephy_write(ioaddr, 0x06, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x06); -+ ephy_data |= 0x0030; -+ rtl8168_ephy_write(ioaddr, 0x06, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x07); -+ ephy_data |= 0x2000; -+ rtl8168_ephy_write(ioaddr, 0x07, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00); -+ ephy_data |= 0x0020; -+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x03) & ~0x5800; -+ ephy_data |= 0x2000; -+ rtl8168_ephy_write(ioaddr, 0x03, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x03); -+ ephy_data |= 0x0001; -+ rtl8168_ephy_write(ioaddr, 0x03, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x01) & ~0x0800; -+ ephy_data |= 0x1000; -+ rtl8168_ephy_write(ioaddr, 0x01, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x07); -+ ephy_data |= 0x4000; -+ rtl8168_ephy_write(ioaddr, 0x07, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x1E); -+ ephy_data |= 0x2000; -+ rtl8168_ephy_write(ioaddr, 0x1E, ephy_data); -+ -+ rtl8168_ephy_write(ioaddr, 0x19, 0xFE6C); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0A); -+ ephy_data |= 0x0040; -+ rtl8168_ephy_write(ioaddr, 0x0A, ephy_data); -+ } else if (tp->mcfg == CFG_METHOD_16 || tp->mcfg == CFG_METHOD_17) { -+ if (tp->mcfg == CFG_METHOD_16) { -+ rtl8168_ephy_write(ioaddr, 0x06, 0xF020); -+ rtl8168_ephy_write(ioaddr, 0x07, 0x01FF); -+ rtl8168_ephy_write(ioaddr, 0x00, 0x5027); -+ rtl8168_ephy_write(ioaddr, 0x01, 0x0003); -+ rtl8168_ephy_write(ioaddr, 0x02, 0x2D16); -+ rtl8168_ephy_write(ioaddr, 0x03, 0x6D49); -+ rtl8168_ephy_write(ioaddr, 0x08, 0x0006); -+ rtl8168_ephy_write(ioaddr, 0x0A, 0x00C8); -+ } -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x09); -+ ephy_data |= BIT_7; -+ rtl8168_ephy_write(ioaddr, 0x09, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x19); -+ ephy_data |= (BIT_2 | BIT_5 | BIT_9); -+ rtl8168_ephy_write(ioaddr, 0x19, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00); -+ ephy_data |= BIT_3; -+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data); -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0C); -+ ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4); -+ ephy_data |= BIT_9; -+ rtl8168_ephy_write(ioaddr, 0x0C, ephy_data); -+ } else if (tp->mcfg == CFG_METHOD_18 || tp->mcfg == CFG_METHOD_19) { -+ if (tp->mcfg == CFG_METHOD_18) { -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x06); -+ ephy_data |= BIT_5; -+ ephy_data &= ~(BIT_7 | BIT_6); -+ rtl8168_ephy_write(ioaddr, 0x06, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x08); -+ ephy_data |= BIT_1; -+ ephy_data &= ~BIT_0; -+ rtl8168_ephy_write(ioaddr, 0x08, ephy_data); -+ } -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x09); -+ ephy_data |= BIT_7; -+ rtl8168_ephy_write(ioaddr, 0x09, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x19); -+ ephy_data |= (BIT_2 | BIT_5 | BIT_9); -+ rtl8168_ephy_write(ioaddr, 0x19, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00); -+ ephy_data |= BIT_3; -+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data); -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0C); -+ ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4); -+ ephy_data |= BIT_9; -+ rtl8168_ephy_write(ioaddr, 0x0C, ephy_data); -+ } else if (tp->mcfg == CFG_METHOD_20) { -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x06); -+ ephy_data |= BIT_5; -+ ephy_data &= ~(BIT_7 | BIT_6); -+ rtl8168_ephy_write(ioaddr, 0x06, ephy_data); -+ -+ rtl8168_ephy_write(ioaddr, 0x0f, 0x5200); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x19); -+ ephy_data |= (BIT_2 | BIT_5 | BIT_9); -+ rtl8168_ephy_write(ioaddr, 0x19, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00); -+ ephy_data |= BIT_3; -+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data); -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0C); -+ ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4); -+ ephy_data |= BIT_9; -+ rtl8168_ephy_write(ioaddr, 0x0C, ephy_data); -+ } else if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22) { -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00); -+ ephy_data &= ~(BIT_3); -+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data); -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0C); -+ ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4); -+ ephy_data |= (BIT_5 | BIT_11); -+ rtl8168_ephy_write(ioaddr, 0x0C, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x1E); -+ ephy_data |= (BIT_0); -+ rtl8168_ephy_write(ioaddr, 0x1E, ephy_data); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x19); -+ ephy_data &= ~(BIT_15); -+ rtl8168_ephy_write(ioaddr, 0x19, ephy_data); -+ } else if (tp->mcfg == CFG_METHOD_25) { -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00); -+ ephy_data &= ~BIT_3; -+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data); -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0C); -+ ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10| BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4); -+ ephy_data |= (BIT_5 | BIT_11); -+ rtl8168_ephy_write(ioaddr, 0x0C, ephy_data); -+ -+ rtl8168_ephy_write(ioaddr, 0x19, 0x7C00); -+ rtl8168_ephy_write(ioaddr, 0x1E, 0x20EB); -+ rtl8168_ephy_write(ioaddr, 0x0D, 0x1666); -+ rtl8168_ephy_write(ioaddr, 0x00, 0x10A3); -+ rtl8168_ephy_write(ioaddr, 0x06, 0xF050); -+ } else if (tp->mcfg == CFG_METHOD_26) { -+ ClearPCIePhyBit(tp, 0x00, BIT_3); -+ ClearAndSetPCIePhyBit( tp, -+ 0x0C, -+ (BIT_13 | BIT_12 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_4), -+ (BIT_5 | BIT_11) -+ ); -+ ClearPCIePhyBit(tp, 0x1E, BIT_0); -+ ClearPCIePhyBit(tp, 0x19, BIT_15); -+ -+ ClearPCIePhyBit(tp, 0x19, (BIT_5 | BIT_0)); -+ -+ SetPCIePhyBit(tp, 0x1E, BIT_13); -+ ClearPCIePhyBit(tp, 0x0D, BIT_8); -+ SetPCIePhyBit(tp, 0x0D, BIT_9); -+ SetPCIePhyBit(tp, 0x00, BIT_7); -+ -+ SetPCIePhyBit(tp, 0x06, BIT_4); -+ } else if (tp->mcfg == CFG_METHOD_23) { -+ rtl8168_ephy_write(ioaddr, 0x00, 0x10AB); -+ rtl8168_ephy_write(ioaddr, 0x06, 0xf030); -+ rtl8168_ephy_write(ioaddr, 0x08, 0x2006); -+ rtl8168_ephy_write(ioaddr, 0x0D, 0x1666); -+ -+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0C); -+ ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4); -+ rtl8168_ephy_write(ioaddr, 0x0C, ephy_data); -+ } else if (tp->mcfg == CFG_METHOD_27) { -+ rtl8168_ephy_write(ioaddr, 0x00, 0x10A3); -+ rtl8168_ephy_write(ioaddr, 0x19, 0xFC00); -+ rtl8168_ephy_write(ioaddr, 0x1E, 0x20EA); -+ } else if (tp->mcfg == CFG_METHOD_28) { -+ SetPCIePhyBit(tp, 0x00, BIT_7); -+ ClearAndSetPCIePhyBit(tp, -+ 0x0D, -+ BIT_8, -+ BIT_9 -+ ); -+ ClearPCIePhyBit(tp, 0x19, (BIT_15 | BIT_5 | BIT_0)); -+ SetPCIePhyBit(tp, 0x1E, BIT_13); -+ -+ } else if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ ClearPCIePhyBit(tp, 0x1E, BIT_11); -+ -+ SetPCIePhyBit(tp, 0x1E, BIT_0); -+ SetPCIePhyBit(tp, 0x1D, BIT_11); -+ -+ rtl8168_ephy_write(ioaddr, 0x05, 0x2089); -+ rtl8168_ephy_write(ioaddr, 0x06, 0x5881); -+ -+ rtl8168_ephy_write(ioaddr, 0x04, 0x154A); -+ rtl8168_ephy_write(ioaddr, 0x01, 0x068B); -+ } -+} -+ -+static int -+rtl8168_check_hw_phy_mcu_code_ver(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ int ram_code_ver_match = 0; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B60); -+ tp->hw_ram_code_ver = mdio_read(tp, 0x06); -+ mdio_write(tp, 0x1F, 0x0000); -+ break; -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B30); -+ tp->hw_ram_code_ver = mdio_read(tp, 0x06); -+ mdio_write(tp, 0x1F, 0x0000); -+ break; -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x801E); -+ tp->hw_ram_code_ver = mdio_read(tp, 0x14); -+ mdio_write(tp, 0x1F, 0x0000); -+ break; -+ default: -+ tp->hw_ram_code_ver = ~0; -+ break; -+ } -+ -+ if( tp->hw_ram_code_ver == tp->sw_ram_code_ver) { -+ ram_code_ver_match = 1; -+ tp->HwHasWrRamCodeToMicroP = TRUE; -+ } -+ -+ return ram_code_ver_match; -+} -+ -+static void -+rtl8168_write_hw_phy_mcu_code_ver(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B60); -+ mdio_write(tp, 0x06, tp->sw_ram_code_ver); -+ mdio_write(tp, 0x1F, 0x0000); -+ tp->hw_ram_code_ver = tp->sw_ram_code_ver; -+ break; -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B30); -+ mdio_write(tp, 0x06, tp->sw_ram_code_ver); -+ mdio_write(tp, 0x1F, 0x0000); -+ tp->hw_ram_code_ver = tp->sw_ram_code_ver; -+ break; -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x801E); -+ mdio_write(tp, 0x14, tp->sw_ram_code_ver); -+ mdio_write(tp, 0x1F, 0x0000); -+ tp->hw_ram_code_ver = tp->sw_ram_code_ver; -+ break; -+ } -+} -+static int -+rtl8168_phy_ram_code_check(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ u16 PhyRegValue; -+ u32 WaitCnt; -+ int retval = TRUE; -+ -+ switch(tp->mcfg) { -+ case CFG_METHOD_21: -+ mdio_write(tp, 0x1f, 0x0A40); -+ PhyRegValue = mdio_read(tp, 0x10); -+ PhyRegValue &= ~(BIT_11); -+ mdio_write(tp, 0x10, PhyRegValue); -+ -+ -+ mdio_write(tp, 0x1f, 0x0A00); -+ PhyRegValue = mdio_read(tp, 0x10); -+ PhyRegValue &= ~(BIT_12 | BIT_13 | BIT_14 | BIT_15); -+ mdio_write(tp, 0x10, PhyRegValue); -+ -+ mdio_write(tp, 0x1f, 0x0A43); -+ mdio_write(tp, 0x13, 0x8010); -+ PhyRegValue = mdio_read(tp, 0x14); -+ PhyRegValue &= ~(BIT_11); -+ mdio_write(tp, 0x14, PhyRegValue); -+ -+ mdio_write(tp,0x1f, 0x0B82); -+ PhyRegValue = mdio_read(tp, 0x10); -+ PhyRegValue |= BIT_4; -+ mdio_write(tp,0x10, PhyRegValue); -+ -+ mdio_write(tp,0x1f, 0x0B80); -+ WaitCnt = 0; -+ do { -+ PhyRegValue = mdio_read(tp, 0x10); -+ PhyRegValue &= 0x0040; -+ udelay(100); -+ WaitCnt++; -+ } while(PhyRegValue != 0x0040 && WaitCnt <1000); -+ -+ if(WaitCnt == 1000) { -+ retval = FALSE ; -+ } -+ -+ mdio_write(tp, 0x1f, 0x0A40); -+ mdio_write(tp, 0x10, 0x0140); -+ -+ mdio_write(tp, 0x1f, 0x0A4A); -+ PhyRegValue = mdio_read(tp, 0x13); -+ PhyRegValue &= ~(BIT_6); -+ PhyRegValue |= (BIT_7); -+ mdio_write(tp, 0x13, PhyRegValue); -+ -+ mdio_write(tp, 0x1f, 0x0A44); -+ PhyRegValue = mdio_read(tp, 0x14); -+ PhyRegValue |= (BIT_2); -+ mdio_write(tp, 0x14, PhyRegValue); -+ -+ mdio_write(tp, 0x1f, 0x0A50); -+ PhyRegValue = mdio_read(tp, 0x11); -+ PhyRegValue |= (BIT_11|BIT_12); -+ mdio_write(tp, 0x11, PhyRegValue); -+ -+ mdio_write(tp, 0x1f, 0x0B82); -+ PhyRegValue = mdio_read(tp, 0x10); -+ PhyRegValue &= ~(BIT_4); -+ mdio_write(tp, 0x10, PhyRegValue); -+ -+ mdio_write(tp,0x1f, 0x0A22); -+ WaitCnt = 0; -+ do { -+ PhyRegValue = mdio_read(tp, 0x12); -+ PhyRegValue &= 0x0010; -+ udelay(100); -+ WaitCnt++; -+ } while(PhyRegValue != 0x0010 && WaitCnt <1000); -+ -+ if(WaitCnt == 1000) { -+ retval = FALSE; -+ } -+ -+ mdio_write(tp, 0x1f, 0x0A40); -+ mdio_write(tp, 0x10, 0x1040); -+ -+ mdio_write(tp, 0x1f, 0x0A4A); -+ PhyRegValue = mdio_read(tp, 0x13); -+ PhyRegValue &= ~(BIT_6|BIT_7); -+ mdio_write(tp, 0x13, PhyRegValue); -+ -+ mdio_write(tp, 0x1f, 0x0A44); -+ PhyRegValue = mdio_read(tp, 0x14); -+ PhyRegValue &= ~(BIT_2); -+ mdio_write(tp, 0x14, PhyRegValue); -+ -+ mdio_write(tp, 0x1f, 0x0A50); -+ PhyRegValue = mdio_read(tp, 0x11); -+ PhyRegValue &= ~(BIT_11|BIT_12); -+ mdio_write(tp, 0x11, PhyRegValue); -+ -+ mdio_write(tp, 0x1f, 0x0A43); -+ mdio_write(tp, 0x13, 0x8010); -+ PhyRegValue = mdio_read(tp, 0x14); -+ PhyRegValue |= (BIT_11); -+ mdio_write(tp, 0x14, PhyRegValue); -+ -+ mdio_write(tp,0x1f, 0x0B82); -+ PhyRegValue = mdio_read(tp, 0x10); -+ PhyRegValue |= BIT_4; -+ mdio_write(tp,0x10, PhyRegValue); -+ -+ mdio_write(tp,0x1f, 0x0B80); -+ WaitCnt = 0; -+ do { -+ PhyRegValue = mdio_read(tp, 0x10); -+ PhyRegValue &= 0x0040; -+ udelay(100); -+ WaitCnt++; -+ } while(PhyRegValue != 0x0040 && WaitCnt <1000); -+ -+ if( WaitCnt == 1000) { -+ retval = FALSE; -+ } -+ -+ mdio_write(tp, 0x1f, 0x0A20); -+ PhyRegValue = mdio_read(tp, 0x13); -+ if(PhyRegValue & BIT_11) { -+ if(PhyRegValue & BIT_10) { -+ retval = FALSE; -+ } -+ } -+ -+ mdio_write(tp, 0x1f, 0x0B82); -+ PhyRegValue = mdio_read(tp, 0x10); -+ PhyRegValue &= ~(BIT_4); -+ mdio_write(tp, 0x10, PhyRegValue); -+ -+ mdelay(2); -+ break; -+ default: -+ break; -+ } -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ return retval; -+} -+ -+static void -+rtl8168_set_phy_ram_code_check_fail_flag(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ u16 TmpUshort; -+ -+ switch(tp->mcfg) { -+ case CFG_METHOD_21: -+ TmpUshort = mac_ocp_read(tp, 0xD3C0); -+ TmpUshort |= BIT_0; -+ mac_ocp_write(tp, 0xD3C0, TmpUshort); -+ break; -+ } -+} -+ -+static void -+rtl8168_set_phy_mcu_8168e_1(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned int gphy_val,i; -+ -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x00, 0x1800); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ mdio_write(tp, 0x17, 0x0117); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1E, 0x002C); -+ mdio_write(tp, 0x1B, 0x5000); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x16, 0x4104); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x1E); -+ gphy_val &= 0x03FF; -+ if (gphy_val == 0x000C) -+ break; -+ } -+ mdio_write(tp, 0x1f, 0x0005); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x07); -+ if ((gphy_val & BIT_5) == 0) -+ break; -+ } -+ gphy_val = mdio_read(tp, 0x07); -+ if (gphy_val & BIT_5) { -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x00a1); -+ mdio_write(tp, 0x17, 0x1000); -+ mdio_write(tp, 0x17, 0x0000); -+ mdio_write(tp, 0x17, 0x2000); -+ mdio_write(tp, 0x1e, 0x002f); -+ mdio_write(tp, 0x18, 0x9bfb); -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x07, 0x0000); -+ mdio_write(tp, 0x1f, 0x0000); -+ } -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ gphy_val = mdio_read(tp, 0x00); -+ gphy_val &= ~(BIT_7); -+ mdio_write(tp, 0x00, gphy_val); -+ mdio_write(tp, 0x1f, 0x0002); -+ gphy_val = mdio_read(tp, 0x08); -+ gphy_val &= ~(BIT_7); -+ mdio_write(tp, 0x08, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0307); -+ mdio_write(tp, 0x15, 0x000e); -+ mdio_write(tp, 0x19, 0x000a); -+ mdio_write(tp, 0x15, 0x0010); -+ mdio_write(tp, 0x19, 0x0008); -+ mdio_write(tp, 0x15, 0x0018); -+ mdio_write(tp, 0x19, 0x4801); -+ mdio_write(tp, 0x15, 0x0019); -+ mdio_write(tp, 0x19, 0x6801); -+ mdio_write(tp, 0x15, 0x001a); -+ mdio_write(tp, 0x19, 0x66a1); -+ mdio_write(tp, 0x15, 0x001f); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0020); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0021); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0022); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0023); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0024); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0025); -+ mdio_write(tp, 0x19, 0x64a1); -+ mdio_write(tp, 0x15, 0x0026); -+ mdio_write(tp, 0x19, 0x40ea); -+ mdio_write(tp, 0x15, 0x0027); -+ mdio_write(tp, 0x19, 0x4503); -+ mdio_write(tp, 0x15, 0x0028); -+ mdio_write(tp, 0x19, 0x9f00); -+ mdio_write(tp, 0x15, 0x0029); -+ mdio_write(tp, 0x19, 0xa631); -+ mdio_write(tp, 0x15, 0x002a); -+ mdio_write(tp, 0x19, 0x9717); -+ mdio_write(tp, 0x15, 0x002b); -+ mdio_write(tp, 0x19, 0x302c); -+ mdio_write(tp, 0x15, 0x002c); -+ mdio_write(tp, 0x19, 0x4802); -+ mdio_write(tp, 0x15, 0x002d); -+ mdio_write(tp, 0x19, 0x58da); -+ mdio_write(tp, 0x15, 0x002e); -+ mdio_write(tp, 0x19, 0x400d); -+ mdio_write(tp, 0x15, 0x002f); -+ mdio_write(tp, 0x19, 0x4488); -+ mdio_write(tp, 0x15, 0x0030); -+ mdio_write(tp, 0x19, 0x9e00); -+ mdio_write(tp, 0x15, 0x0031); -+ mdio_write(tp, 0x19, 0x63c8); -+ mdio_write(tp, 0x15, 0x0032); -+ mdio_write(tp, 0x19, 0x6481); -+ mdio_write(tp, 0x15, 0x0033); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0034); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0035); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0036); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0037); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0038); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0039); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x003a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x003b); -+ mdio_write(tp, 0x19, 0x63e8); -+ mdio_write(tp, 0x15, 0x003c); -+ mdio_write(tp, 0x19, 0x7d00); -+ mdio_write(tp, 0x15, 0x003d); -+ mdio_write(tp, 0x19, 0x59d4); -+ mdio_write(tp, 0x15, 0x003e); -+ mdio_write(tp, 0x19, 0x63f8); -+ mdio_write(tp, 0x15, 0x0040); -+ mdio_write(tp, 0x19, 0x64a1); -+ mdio_write(tp, 0x15, 0x0041); -+ mdio_write(tp, 0x19, 0x30de); -+ mdio_write(tp, 0x15, 0x0044); -+ mdio_write(tp, 0x19, 0x480f); -+ mdio_write(tp, 0x15, 0x0045); -+ mdio_write(tp, 0x19, 0x6800); -+ mdio_write(tp, 0x15, 0x0046); -+ mdio_write(tp, 0x19, 0x6680); -+ mdio_write(tp, 0x15, 0x0047); -+ mdio_write(tp, 0x19, 0x7c10); -+ mdio_write(tp, 0x15, 0x0048); -+ mdio_write(tp, 0x19, 0x63c8); -+ mdio_write(tp, 0x15, 0x0049); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004b); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004c); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004d); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004e); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004f); -+ mdio_write(tp, 0x19, 0x40ea); -+ mdio_write(tp, 0x15, 0x0050); -+ mdio_write(tp, 0x19, 0x4503); -+ mdio_write(tp, 0x15, 0x0051); -+ mdio_write(tp, 0x19, 0x58ca); -+ mdio_write(tp, 0x15, 0x0052); -+ mdio_write(tp, 0x19, 0x63c8); -+ mdio_write(tp, 0x15, 0x0053); -+ mdio_write(tp, 0x19, 0x63d8); -+ mdio_write(tp, 0x15, 0x0054); -+ mdio_write(tp, 0x19, 0x66a0); -+ mdio_write(tp, 0x15, 0x0055); -+ mdio_write(tp, 0x19, 0x9f00); -+ mdio_write(tp, 0x15, 0x0056); -+ mdio_write(tp, 0x19, 0x3000); -+ mdio_write(tp, 0x15, 0x006E); -+ mdio_write(tp, 0x19, 0x9afa); -+ mdio_write(tp, 0x15, 0x00a1); -+ mdio_write(tp, 0x19, 0x3044); -+ mdio_write(tp, 0x15, 0x00ab); -+ mdio_write(tp, 0x19, 0x5820); -+ mdio_write(tp, 0x15, 0x00ac); -+ mdio_write(tp, 0x19, 0x5e04); -+ mdio_write(tp, 0x15, 0x00ad); -+ mdio_write(tp, 0x19, 0xb60c); -+ mdio_write(tp, 0x15, 0x00af); -+ mdio_write(tp, 0x19, 0x000a); -+ mdio_write(tp, 0x15, 0x00b2); -+ mdio_write(tp, 0x19, 0x30b9); -+ mdio_write(tp, 0x15, 0x00b9); -+ mdio_write(tp, 0x19, 0x4408); -+ mdio_write(tp, 0x15, 0x00ba); -+ mdio_write(tp, 0x19, 0x480b); -+ mdio_write(tp, 0x15, 0x00bb); -+ mdio_write(tp, 0x19, 0x5e00); -+ mdio_write(tp, 0x15, 0x00bc); -+ mdio_write(tp, 0x19, 0x405f); -+ mdio_write(tp, 0x15, 0x00bd); -+ mdio_write(tp, 0x19, 0x4448); -+ mdio_write(tp, 0x15, 0x00be); -+ mdio_write(tp, 0x19, 0x4020); -+ mdio_write(tp, 0x15, 0x00bf); -+ mdio_write(tp, 0x19, 0x4468); -+ mdio_write(tp, 0x15, 0x00c0); -+ mdio_write(tp, 0x19, 0x9c02); -+ mdio_write(tp, 0x15, 0x00c1); -+ mdio_write(tp, 0x19, 0x58a0); -+ mdio_write(tp, 0x15, 0x00c2); -+ mdio_write(tp, 0x19, 0xb605); -+ mdio_write(tp, 0x15, 0x00c3); -+ mdio_write(tp, 0x19, 0xc0d3); -+ mdio_write(tp, 0x15, 0x00c4); -+ mdio_write(tp, 0x19, 0x00e6); -+ mdio_write(tp, 0x15, 0x00c5); -+ mdio_write(tp, 0x19, 0xdaec); -+ mdio_write(tp, 0x15, 0x00c6); -+ mdio_write(tp, 0x19, 0x00fa); -+ mdio_write(tp, 0x15, 0x00c7); -+ mdio_write(tp, 0x19, 0x9df9); -+ mdio_write(tp, 0x15, 0x00c8); -+ mdio_write(tp, 0x19, 0x307a); -+ mdio_write(tp, 0x15, 0x0112); -+ mdio_write(tp, 0x19, 0x6421); -+ mdio_write(tp, 0x15, 0x0113); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x0114); -+ mdio_write(tp, 0x19, 0x63f0); -+ mdio_write(tp, 0x15, 0x0115); -+ mdio_write(tp, 0x19, 0x4003); -+ mdio_write(tp, 0x15, 0x0116); -+ mdio_write(tp, 0x19, 0x4418); -+ mdio_write(tp, 0x15, 0x0117); -+ mdio_write(tp, 0x19, 0x9b00); -+ mdio_write(tp, 0x15, 0x0118); -+ mdio_write(tp, 0x19, 0x6461); -+ mdio_write(tp, 0x15, 0x0119); -+ mdio_write(tp, 0x19, 0x64e1); -+ mdio_write(tp, 0x15, 0x011a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0150); -+ mdio_write(tp, 0x19, 0x7c80); -+ mdio_write(tp, 0x15, 0x0151); -+ mdio_write(tp, 0x19, 0x6461); -+ mdio_write(tp, 0x15, 0x0152); -+ mdio_write(tp, 0x19, 0x4003); -+ mdio_write(tp, 0x15, 0x0153); -+ mdio_write(tp, 0x19, 0x4540); -+ mdio_write(tp, 0x15, 0x0154); -+ mdio_write(tp, 0x19, 0x9f00); -+ mdio_write(tp, 0x15, 0x0155); -+ mdio_write(tp, 0x19, 0x9d00); -+ mdio_write(tp, 0x15, 0x0156); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x0157); -+ mdio_write(tp, 0x19, 0x6421); -+ mdio_write(tp, 0x15, 0x0158); -+ mdio_write(tp, 0x19, 0x7c80); -+ mdio_write(tp, 0x15, 0x0159); -+ mdio_write(tp, 0x19, 0x64a1); -+ mdio_write(tp, 0x15, 0x015a); -+ mdio_write(tp, 0x19, 0x30fe); -+ mdio_write(tp, 0x15, 0x021e); -+ mdio_write(tp, 0x19, 0x5410); -+ mdio_write(tp, 0x15, 0x0225); -+ mdio_write(tp, 0x19, 0x5400); -+ mdio_write(tp, 0x15, 0x023D); -+ mdio_write(tp, 0x19, 0x4050); -+ mdio_write(tp, 0x15, 0x0295); -+ mdio_write(tp, 0x19, 0x6c08); -+ mdio_write(tp, 0x15, 0x02bd); -+ mdio_write(tp, 0x19, 0xa523); -+ mdio_write(tp, 0x15, 0x02be); -+ mdio_write(tp, 0x19, 0x32ca); -+ mdio_write(tp, 0x15, 0x02ca); -+ mdio_write(tp, 0x19, 0x48b3); -+ mdio_write(tp, 0x15, 0x02cb); -+ mdio_write(tp, 0x19, 0x4020); -+ mdio_write(tp, 0x15, 0x02cc); -+ mdio_write(tp, 0x19, 0x4823); -+ mdio_write(tp, 0x15, 0x02cd); -+ mdio_write(tp, 0x19, 0x4510); -+ mdio_write(tp, 0x15, 0x02ce); -+ mdio_write(tp, 0x19, 0xb63a); -+ mdio_write(tp, 0x15, 0x02cf); -+ mdio_write(tp, 0x19, 0x7dc8); -+ mdio_write(tp, 0x15, 0x02d6); -+ mdio_write(tp, 0x19, 0x9bf8); -+ mdio_write(tp, 0x15, 0x02d8); -+ mdio_write(tp, 0x19, 0x85f6); -+ mdio_write(tp, 0x15, 0x02d9); -+ mdio_write(tp, 0x19, 0x32e0); -+ mdio_write(tp, 0x15, 0x02e0); -+ mdio_write(tp, 0x19, 0x4834); -+ mdio_write(tp, 0x15, 0x02e1); -+ mdio_write(tp, 0x19, 0x6c08); -+ mdio_write(tp, 0x15, 0x02e2); -+ mdio_write(tp, 0x19, 0x4020); -+ mdio_write(tp, 0x15, 0x02e3); -+ mdio_write(tp, 0x19, 0x4824); -+ mdio_write(tp, 0x15, 0x02e4); -+ mdio_write(tp, 0x19, 0x4520); -+ mdio_write(tp, 0x15, 0x02e5); -+ mdio_write(tp, 0x19, 0x4008); -+ mdio_write(tp, 0x15, 0x02e6); -+ mdio_write(tp, 0x19, 0x4560); -+ mdio_write(tp, 0x15, 0x02e7); -+ mdio_write(tp, 0x19, 0x9d04); -+ mdio_write(tp, 0x15, 0x02e8); -+ mdio_write(tp, 0x19, 0x48c4); -+ mdio_write(tp, 0x15, 0x02e9); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02ea); -+ mdio_write(tp, 0x19, 0x4844); -+ mdio_write(tp, 0x15, 0x02eb); -+ mdio_write(tp, 0x19, 0x7dc8); -+ mdio_write(tp, 0x15, 0x02f0); -+ mdio_write(tp, 0x19, 0x9cf7); -+ mdio_write(tp, 0x15, 0x02f1); -+ mdio_write(tp, 0x19, 0xdf94); -+ mdio_write(tp, 0x15, 0x02f2); -+ mdio_write(tp, 0x19, 0x0002); -+ mdio_write(tp, 0x15, 0x02f3); -+ mdio_write(tp, 0x19, 0x6810); -+ mdio_write(tp, 0x15, 0x02f4); -+ mdio_write(tp, 0x19, 0xb614); -+ mdio_write(tp, 0x15, 0x02f5); -+ mdio_write(tp, 0x19, 0xc42b); -+ mdio_write(tp, 0x15, 0x02f6); -+ mdio_write(tp, 0x19, 0x00d4); -+ mdio_write(tp, 0x15, 0x02f7); -+ mdio_write(tp, 0x19, 0xc455); -+ mdio_write(tp, 0x15, 0x02f8); -+ mdio_write(tp, 0x19, 0x0093); -+ mdio_write(tp, 0x15, 0x02f9); -+ mdio_write(tp, 0x19, 0x92ee); -+ mdio_write(tp, 0x15, 0x02fa); -+ mdio_write(tp, 0x19, 0xefed); -+ mdio_write(tp, 0x15, 0x02fb); -+ mdio_write(tp, 0x19, 0x3312); -+ mdio_write(tp, 0x15, 0x0312); -+ mdio_write(tp, 0x19, 0x49b5); -+ mdio_write(tp, 0x15, 0x0313); -+ mdio_write(tp, 0x19, 0x7d00); -+ mdio_write(tp, 0x15, 0x0314); -+ mdio_write(tp, 0x19, 0x4d00); -+ mdio_write(tp, 0x15, 0x0315); -+ mdio_write(tp, 0x19, 0x6810); -+ mdio_write(tp, 0x15, 0x031e); -+ mdio_write(tp, 0x19, 0x404f); -+ mdio_write(tp, 0x15, 0x031f); -+ mdio_write(tp, 0x19, 0x44c8); -+ mdio_write(tp, 0x15, 0x0320); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x0321); -+ mdio_write(tp, 0x19, 0x00e7); -+ mdio_write(tp, 0x15, 0x0322); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x0323); -+ mdio_write(tp, 0x19, 0x8203); -+ mdio_write(tp, 0x15, 0x0324); -+ mdio_write(tp, 0x19, 0x4d48); -+ mdio_write(tp, 0x15, 0x0325); -+ mdio_write(tp, 0x19, 0x3327); -+ mdio_write(tp, 0x15, 0x0326); -+ mdio_write(tp, 0x19, 0x4d40); -+ mdio_write(tp, 0x15, 0x0327); -+ mdio_write(tp, 0x19, 0xc8d7); -+ mdio_write(tp, 0x15, 0x0328); -+ mdio_write(tp, 0x19, 0x0003); -+ mdio_write(tp, 0x15, 0x0329); -+ mdio_write(tp, 0x19, 0x7c20); -+ mdio_write(tp, 0x15, 0x032a); -+ mdio_write(tp, 0x19, 0x4c20); -+ mdio_write(tp, 0x15, 0x032b); -+ mdio_write(tp, 0x19, 0xc8ed); -+ mdio_write(tp, 0x15, 0x032c); -+ mdio_write(tp, 0x19, 0x00f4); -+ mdio_write(tp, 0x15, 0x032d); -+ mdio_write(tp, 0x19, 0x82b3); -+ mdio_write(tp, 0x15, 0x032e); -+ mdio_write(tp, 0x19, 0xd11d); -+ mdio_write(tp, 0x15, 0x032f); -+ mdio_write(tp, 0x19, 0x00b1); -+ mdio_write(tp, 0x15, 0x0330); -+ mdio_write(tp, 0x19, 0xde18); -+ mdio_write(tp, 0x15, 0x0331); -+ mdio_write(tp, 0x19, 0x0008); -+ mdio_write(tp, 0x15, 0x0332); -+ mdio_write(tp, 0x19, 0x91ee); -+ mdio_write(tp, 0x15, 0x0333); -+ mdio_write(tp, 0x19, 0x3339); -+ mdio_write(tp, 0x15, 0x033a); -+ mdio_write(tp, 0x19, 0x4064); -+ mdio_write(tp, 0x15, 0x0340); -+ mdio_write(tp, 0x19, 0x9e06); -+ mdio_write(tp, 0x15, 0x0341); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x0342); -+ mdio_write(tp, 0x19, 0x8203); -+ mdio_write(tp, 0x15, 0x0343); -+ mdio_write(tp, 0x19, 0x4d48); -+ mdio_write(tp, 0x15, 0x0344); -+ mdio_write(tp, 0x19, 0x3346); -+ mdio_write(tp, 0x15, 0x0345); -+ mdio_write(tp, 0x19, 0x4d40); -+ mdio_write(tp, 0x15, 0x0346); -+ mdio_write(tp, 0x19, 0xd11d); -+ mdio_write(tp, 0x15, 0x0347); -+ mdio_write(tp, 0x19, 0x0099); -+ mdio_write(tp, 0x15, 0x0348); -+ mdio_write(tp, 0x19, 0xbb17); -+ mdio_write(tp, 0x15, 0x0349); -+ mdio_write(tp, 0x19, 0x8102); -+ mdio_write(tp, 0x15, 0x034a); -+ mdio_write(tp, 0x19, 0x334d); -+ mdio_write(tp, 0x15, 0x034b); -+ mdio_write(tp, 0x19, 0xa22c); -+ mdio_write(tp, 0x15, 0x034c); -+ mdio_write(tp, 0x19, 0x3397); -+ mdio_write(tp, 0x15, 0x034d); -+ mdio_write(tp, 0x19, 0x91f2); -+ mdio_write(tp, 0x15, 0x034e); -+ mdio_write(tp, 0x19, 0xc218); -+ mdio_write(tp, 0x15, 0x034f); -+ mdio_write(tp, 0x19, 0x00f0); -+ mdio_write(tp, 0x15, 0x0350); -+ mdio_write(tp, 0x19, 0x3397); -+ mdio_write(tp, 0x15, 0x0351); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0364); -+ mdio_write(tp, 0x19, 0xbc05); -+ mdio_write(tp, 0x15, 0x0367); -+ mdio_write(tp, 0x19, 0xa1fc); -+ mdio_write(tp, 0x15, 0x0368); -+ mdio_write(tp, 0x19, 0x3377); -+ mdio_write(tp, 0x15, 0x0369); -+ mdio_write(tp, 0x19, 0x328b); -+ mdio_write(tp, 0x15, 0x036a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0377); -+ mdio_write(tp, 0x19, 0x4b97); -+ mdio_write(tp, 0x15, 0x0378); -+ mdio_write(tp, 0x19, 0x6818); -+ mdio_write(tp, 0x15, 0x0379); -+ mdio_write(tp, 0x19, 0x4b07); -+ mdio_write(tp, 0x15, 0x037a); -+ mdio_write(tp, 0x19, 0x40ac); -+ mdio_write(tp, 0x15, 0x037b); -+ mdio_write(tp, 0x19, 0x4445); -+ mdio_write(tp, 0x15, 0x037c); -+ mdio_write(tp, 0x19, 0x404e); -+ mdio_write(tp, 0x15, 0x037d); -+ mdio_write(tp, 0x19, 0x4461); -+ mdio_write(tp, 0x15, 0x037e); -+ mdio_write(tp, 0x19, 0x9c09); -+ mdio_write(tp, 0x15, 0x037f); -+ mdio_write(tp, 0x19, 0x63da); -+ mdio_write(tp, 0x15, 0x0380); -+ mdio_write(tp, 0x19, 0x5440); -+ mdio_write(tp, 0x15, 0x0381); -+ mdio_write(tp, 0x19, 0x4b98); -+ mdio_write(tp, 0x15, 0x0382); -+ mdio_write(tp, 0x19, 0x7c60); -+ mdio_write(tp, 0x15, 0x0383); -+ mdio_write(tp, 0x19, 0x4c00); -+ mdio_write(tp, 0x15, 0x0384); -+ mdio_write(tp, 0x19, 0x4b08); -+ mdio_write(tp, 0x15, 0x0385); -+ mdio_write(tp, 0x19, 0x63d8); -+ mdio_write(tp, 0x15, 0x0386); -+ mdio_write(tp, 0x19, 0x338d); -+ mdio_write(tp, 0x15, 0x0387); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x0388); -+ mdio_write(tp, 0x19, 0x0080); -+ mdio_write(tp, 0x15, 0x0389); -+ mdio_write(tp, 0x19, 0x820c); -+ mdio_write(tp, 0x15, 0x038a); -+ mdio_write(tp, 0x19, 0xa10b); -+ mdio_write(tp, 0x15, 0x038b); -+ mdio_write(tp, 0x19, 0x9df3); -+ mdio_write(tp, 0x15, 0x038c); -+ mdio_write(tp, 0x19, 0x3395); -+ mdio_write(tp, 0x15, 0x038d); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x038e); -+ mdio_write(tp, 0x19, 0x00f9); -+ mdio_write(tp, 0x15, 0x038f); -+ mdio_write(tp, 0x19, 0xc017); -+ mdio_write(tp, 0x15, 0x0390); -+ mdio_write(tp, 0x19, 0x0005); -+ mdio_write(tp, 0x15, 0x0391); -+ mdio_write(tp, 0x19, 0x6c0b); -+ mdio_write(tp, 0x15, 0x0392); -+ mdio_write(tp, 0x19, 0xa103); -+ mdio_write(tp, 0x15, 0x0393); -+ mdio_write(tp, 0x19, 0x6c08); -+ mdio_write(tp, 0x15, 0x0394); -+ mdio_write(tp, 0x19, 0x9df9); -+ mdio_write(tp, 0x15, 0x0395); -+ mdio_write(tp, 0x19, 0x6c08); -+ mdio_write(tp, 0x15, 0x0396); -+ mdio_write(tp, 0x19, 0x3397); -+ mdio_write(tp, 0x15, 0x0399); -+ mdio_write(tp, 0x19, 0x6810); -+ mdio_write(tp, 0x15, 0x03a4); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x03a5); -+ mdio_write(tp, 0x19, 0x8203); -+ mdio_write(tp, 0x15, 0x03a6); -+ mdio_write(tp, 0x19, 0x4d08); -+ mdio_write(tp, 0x15, 0x03a7); -+ mdio_write(tp, 0x19, 0x33a9); -+ mdio_write(tp, 0x15, 0x03a8); -+ mdio_write(tp, 0x19, 0x4d00); -+ mdio_write(tp, 0x15, 0x03a9); -+ mdio_write(tp, 0x19, 0x9bfa); -+ mdio_write(tp, 0x15, 0x03aa); -+ mdio_write(tp, 0x19, 0x33b6); -+ mdio_write(tp, 0x15, 0x03bb); -+ mdio_write(tp, 0x19, 0x4056); -+ mdio_write(tp, 0x15, 0x03bc); -+ mdio_write(tp, 0x19, 0x44e9); -+ mdio_write(tp, 0x15, 0x03bd); -+ mdio_write(tp, 0x19, 0x405e); -+ mdio_write(tp, 0x15, 0x03be); -+ mdio_write(tp, 0x19, 0x44f8); -+ mdio_write(tp, 0x15, 0x03bf); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x03c0); -+ mdio_write(tp, 0x19, 0x0037); -+ mdio_write(tp, 0x15, 0x03c1); -+ mdio_write(tp, 0x19, 0xbd37); -+ mdio_write(tp, 0x15, 0x03c2); -+ mdio_write(tp, 0x19, 0x9cfd); -+ mdio_write(tp, 0x15, 0x03c3); -+ mdio_write(tp, 0x19, 0xc639); -+ mdio_write(tp, 0x15, 0x03c4); -+ mdio_write(tp, 0x19, 0x0011); -+ mdio_write(tp, 0x15, 0x03c5); -+ mdio_write(tp, 0x19, 0x9b03); -+ mdio_write(tp, 0x15, 0x03c6); -+ mdio_write(tp, 0x19, 0x7c01); -+ mdio_write(tp, 0x15, 0x03c7); -+ mdio_write(tp, 0x19, 0x4c01); -+ mdio_write(tp, 0x15, 0x03c8); -+ mdio_write(tp, 0x19, 0x9e03); -+ mdio_write(tp, 0x15, 0x03c9); -+ mdio_write(tp, 0x19, 0x7c20); -+ mdio_write(tp, 0x15, 0x03ca); -+ mdio_write(tp, 0x19, 0x4c20); -+ mdio_write(tp, 0x15, 0x03cb); -+ mdio_write(tp, 0x19, 0x9af4); -+ mdio_write(tp, 0x15, 0x03cc); -+ mdio_write(tp, 0x19, 0x7c12); -+ mdio_write(tp, 0x15, 0x03cd); -+ mdio_write(tp, 0x19, 0x4c52); -+ mdio_write(tp, 0x15, 0x03ce); -+ mdio_write(tp, 0x19, 0x4470); -+ mdio_write(tp, 0x15, 0x03cf); -+ mdio_write(tp, 0x19, 0x7c12); -+ mdio_write(tp, 0x15, 0x03d0); -+ mdio_write(tp, 0x19, 0x4c40); -+ mdio_write(tp, 0x15, 0x03d1); -+ mdio_write(tp, 0x19, 0x33bf); -+ mdio_write(tp, 0x15, 0x03d6); -+ mdio_write(tp, 0x19, 0x4047); -+ mdio_write(tp, 0x15, 0x03d7); -+ mdio_write(tp, 0x19, 0x4469); -+ mdio_write(tp, 0x15, 0x03d8); -+ mdio_write(tp, 0x19, 0x492b); -+ mdio_write(tp, 0x15, 0x03d9); -+ mdio_write(tp, 0x19, 0x4479); -+ mdio_write(tp, 0x15, 0x03da); -+ mdio_write(tp, 0x19, 0x7c09); -+ mdio_write(tp, 0x15, 0x03db); -+ mdio_write(tp, 0x19, 0x8203); -+ mdio_write(tp, 0x15, 0x03dc); -+ mdio_write(tp, 0x19, 0x4d48); -+ mdio_write(tp, 0x15, 0x03dd); -+ mdio_write(tp, 0x19, 0x33df); -+ mdio_write(tp, 0x15, 0x03de); -+ mdio_write(tp, 0x19, 0x4d40); -+ mdio_write(tp, 0x15, 0x03df); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x03e0); -+ mdio_write(tp, 0x19, 0x0017); -+ mdio_write(tp, 0x15, 0x03e1); -+ mdio_write(tp, 0x19, 0xbd17); -+ mdio_write(tp, 0x15, 0x03e2); -+ mdio_write(tp, 0x19, 0x9b03); -+ mdio_write(tp, 0x15, 0x03e3); -+ mdio_write(tp, 0x19, 0x7c20); -+ mdio_write(tp, 0x15, 0x03e4); -+ mdio_write(tp, 0x19, 0x4c20); -+ mdio_write(tp, 0x15, 0x03e5); -+ mdio_write(tp, 0x19, 0x88f5); -+ mdio_write(tp, 0x15, 0x03e6); -+ mdio_write(tp, 0x19, 0xc428); -+ mdio_write(tp, 0x15, 0x03e7); -+ mdio_write(tp, 0x19, 0x0008); -+ mdio_write(tp, 0x15, 0x03e8); -+ mdio_write(tp, 0x19, 0x9af2); -+ mdio_write(tp, 0x15, 0x03e9); -+ mdio_write(tp, 0x19, 0x7c12); -+ mdio_write(tp, 0x15, 0x03ea); -+ mdio_write(tp, 0x19, 0x4c52); -+ mdio_write(tp, 0x15, 0x03eb); -+ mdio_write(tp, 0x19, 0x4470); -+ mdio_write(tp, 0x15, 0x03ec); -+ mdio_write(tp, 0x19, 0x7c12); -+ mdio_write(tp, 0x15, 0x03ed); -+ mdio_write(tp, 0x19, 0x4c40); -+ mdio_write(tp, 0x15, 0x03ee); -+ mdio_write(tp, 0x19, 0x33da); -+ mdio_write(tp, 0x15, 0x03ef); -+ mdio_write(tp, 0x19, 0x3312); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0300); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x17, 0x2179); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0040); -+ mdio_write(tp, 0x18, 0x0645); -+ mdio_write(tp, 0x19, 0xe200); -+ mdio_write(tp, 0x18, 0x0655); -+ mdio_write(tp, 0x19, 0x9000); -+ mdio_write(tp, 0x18, 0x0d05); -+ mdio_write(tp, 0x19, 0xbe00); -+ mdio_write(tp, 0x18, 0x0d15); -+ mdio_write(tp, 0x19, 0xd300); -+ mdio_write(tp, 0x18, 0x0d25); -+ mdio_write(tp, 0x19, 0xfe00); -+ mdio_write(tp, 0x18, 0x0d35); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x18, 0x0d45); -+ mdio_write(tp, 0x19, 0x7f00); -+ mdio_write(tp, 0x18, 0x0d55); -+ mdio_write(tp, 0x19, 0x1000); -+ mdio_write(tp, 0x18, 0x0d65); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x18, 0x0d75); -+ mdio_write(tp, 0x19, 0x8200); -+ mdio_write(tp, 0x18, 0x0d85); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x18, 0x0d95); -+ mdio_write(tp, 0x19, 0x7000); -+ mdio_write(tp, 0x18, 0x0da5); -+ mdio_write(tp, 0x19, 0x0f00); -+ mdio_write(tp, 0x18, 0x0db5); -+ mdio_write(tp, 0x19, 0x0100); -+ mdio_write(tp, 0x18, 0x0dc5); -+ mdio_write(tp, 0x19, 0x9b00); -+ mdio_write(tp, 0x18, 0x0dd5); -+ mdio_write(tp, 0x19, 0x7f00); -+ mdio_write(tp, 0x18, 0x0de5); -+ mdio_write(tp, 0x19, 0xe000); -+ mdio_write(tp, 0x18, 0x0df5); -+ mdio_write(tp, 0x19, 0xef00); -+ mdio_write(tp, 0x18, 0x16d5); -+ mdio_write(tp, 0x19, 0xe200); -+ mdio_write(tp, 0x18, 0x16e5); -+ mdio_write(tp, 0x19, 0xab00); -+ mdio_write(tp, 0x18, 0x2904); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x18, 0x2914); -+ mdio_write(tp, 0x19, 0x7f00); -+ mdio_write(tp, 0x18, 0x2924); -+ mdio_write(tp, 0x19, 0x0100); -+ mdio_write(tp, 0x18, 0x2934); -+ mdio_write(tp, 0x19, 0x2000); -+ mdio_write(tp, 0x18, 0x2944); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x18, 0x2954); -+ mdio_write(tp, 0x19, 0x4600); -+ mdio_write(tp, 0x18, 0x2964); -+ mdio_write(tp, 0x19, 0xfc00); -+ mdio_write(tp, 0x18, 0x2974); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x18, 0x2984); -+ mdio_write(tp, 0x19, 0x5000); -+ mdio_write(tp, 0x18, 0x2994); -+ mdio_write(tp, 0x19, 0x9d00); -+ mdio_write(tp, 0x18, 0x29a4); -+ mdio_write(tp, 0x19, 0xff00); -+ mdio_write(tp, 0x18, 0x29b4); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x18, 0x29c4); -+ mdio_write(tp, 0x19, 0x7f00); -+ mdio_write(tp, 0x18, 0x29d4); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x18, 0x29e4); -+ mdio_write(tp, 0x19, 0x2000); -+ mdio_write(tp, 0x18, 0x29f4); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x18, 0x2a04); -+ mdio_write(tp, 0x19, 0xe600); -+ mdio_write(tp, 0x18, 0x2a14); -+ mdio_write(tp, 0x19, 0xff00); -+ mdio_write(tp, 0x18, 0x2a24); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x18, 0x2a34); -+ mdio_write(tp, 0x19, 0x5000); -+ mdio_write(tp, 0x18, 0x2a44); -+ mdio_write(tp, 0x19, 0x8500); -+ mdio_write(tp, 0x18, 0x2a54); -+ mdio_write(tp, 0x19, 0x7f00); -+ mdio_write(tp, 0x18, 0x2a64); -+ mdio_write(tp, 0x19, 0xac00); -+ mdio_write(tp, 0x18, 0x2a74); -+ mdio_write(tp, 0x19, 0x0800); -+ mdio_write(tp, 0x18, 0x2a84); -+ mdio_write(tp, 0x19, 0xfc00); -+ mdio_write(tp, 0x18, 0x2a94); -+ mdio_write(tp, 0x19, 0xe000); -+ mdio_write(tp, 0x18, 0x2aa4); -+ mdio_write(tp, 0x19, 0x7400); -+ mdio_write(tp, 0x18, 0x2ab4); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x18, 0x2ac4); -+ mdio_write(tp, 0x19, 0x7f00); -+ mdio_write(tp, 0x18, 0x2ad4); -+ mdio_write(tp, 0x19, 0x0100); -+ mdio_write(tp, 0x18, 0x2ae4); -+ mdio_write(tp, 0x19, 0xff00); -+ mdio_write(tp, 0x18, 0x2af4); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x18, 0x2b04); -+ mdio_write(tp, 0x19, 0x4400); -+ mdio_write(tp, 0x18, 0x2b14); -+ mdio_write(tp, 0x19, 0xfc00); -+ mdio_write(tp, 0x18, 0x2b24); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x18, 0x2b34); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x18, 0x2b44); -+ mdio_write(tp, 0x19, 0x9d00); -+ mdio_write(tp, 0x18, 0x2b54); -+ mdio_write(tp, 0x19, 0xff00); -+ mdio_write(tp, 0x18, 0x2b64); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x18, 0x2b74); -+ mdio_write(tp, 0x19, 0x7f00); -+ mdio_write(tp, 0x18, 0x2b84); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x18, 0x2b94); -+ mdio_write(tp, 0x19, 0xff00); -+ mdio_write(tp, 0x18, 0x2ba4); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x18, 0x2bb4); -+ mdio_write(tp, 0x19, 0xfc00); -+ mdio_write(tp, 0x18, 0x2bc4); -+ mdio_write(tp, 0x19, 0xff00); -+ mdio_write(tp, 0x18, 0x2bd4); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x18, 0x2be4); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x18, 0x2bf4); -+ mdio_write(tp, 0x19, 0x8900); -+ mdio_write(tp, 0x18, 0x2c04); -+ mdio_write(tp, 0x19, 0x8300); -+ mdio_write(tp, 0x18, 0x2c14); -+ mdio_write(tp, 0x19, 0xe000); -+ mdio_write(tp, 0x18, 0x2c24); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x18, 0x2c34); -+ mdio_write(tp, 0x19, 0xac00); -+ mdio_write(tp, 0x18, 0x2c44); -+ mdio_write(tp, 0x19, 0x0800); -+ mdio_write(tp, 0x18, 0x2c54); -+ mdio_write(tp, 0x19, 0xfa00); -+ mdio_write(tp, 0x18, 0x2c64); -+ mdio_write(tp, 0x19, 0xe100); -+ mdio_write(tp, 0x18, 0x2c74); -+ mdio_write(tp, 0x19, 0x7f00); -+ mdio_write(tp, 0x18, 0x0001); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x17, 0x2100); -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ mdio_write(tp, 0x05, 0x8b88); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x05, 0x8000); -+ mdio_write(tp, 0x06, 0xd480); -+ mdio_write(tp, 0x06, 0xc1e4); -+ mdio_write(tp, 0x06, 0x8b9a); -+ mdio_write(tp, 0x06, 0xe58b); -+ mdio_write(tp, 0x06, 0x9bee); -+ mdio_write(tp, 0x06, 0x8b83); -+ mdio_write(tp, 0x06, 0x41bf); -+ mdio_write(tp, 0x06, 0x8b88); -+ mdio_write(tp, 0x06, 0xec00); -+ mdio_write(tp, 0x06, 0x19a9); -+ mdio_write(tp, 0x06, 0x8b90); -+ mdio_write(tp, 0x06, 0xf9ee); -+ mdio_write(tp, 0x06, 0xfff6); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0xfff7); -+ mdio_write(tp, 0x06, 0xffe0); -+ mdio_write(tp, 0x06, 0xe140); -+ mdio_write(tp, 0x06, 0xe1e1); -+ mdio_write(tp, 0x06, 0x41f7); -+ mdio_write(tp, 0x06, 0x2ff6); -+ mdio_write(tp, 0x06, 0x28e4); -+ mdio_write(tp, 0x06, 0xe140); -+ mdio_write(tp, 0x06, 0xe5e1); -+ mdio_write(tp, 0x06, 0x41f7); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x020c); -+ mdio_write(tp, 0x06, 0x0202); -+ mdio_write(tp, 0x06, 0x1d02); -+ mdio_write(tp, 0x06, 0x0230); -+ mdio_write(tp, 0x06, 0x0202); -+ mdio_write(tp, 0x06, 0x4002); -+ mdio_write(tp, 0x06, 0x028b); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0x6c02); -+ mdio_write(tp, 0x06, 0x8085); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x88e1); -+ mdio_write(tp, 0x06, 0x8b89); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8a1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8b); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8c1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8e1e); -+ mdio_write(tp, 0x06, 0x01a0); -+ mdio_write(tp, 0x06, 0x00c7); -+ mdio_write(tp, 0x06, 0xaec3); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x10ee); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x1310); -+ mdio_write(tp, 0x06, 0x021f); -+ mdio_write(tp, 0x06, 0x9d02); -+ mdio_write(tp, 0x06, 0x1f0c); -+ mdio_write(tp, 0x06, 0x0227); -+ mdio_write(tp, 0x06, 0x49fc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x200b); -+ mdio_write(tp, 0x06, 0xf620); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x830e); -+ mdio_write(tp, 0x06, 0x021b); -+ mdio_write(tp, 0x06, 0x67ad); -+ mdio_write(tp, 0x06, 0x2211); -+ mdio_write(tp, 0x06, 0xf622); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x2ba5); -+ mdio_write(tp, 0x06, 0x022a); -+ mdio_write(tp, 0x06, 0x2402); -+ mdio_write(tp, 0x06, 0x80c6); -+ mdio_write(tp, 0x06, 0x022a); -+ mdio_write(tp, 0x06, 0xf0ad); -+ mdio_write(tp, 0x06, 0x2511); -+ mdio_write(tp, 0x06, 0xf625); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x8226); -+ mdio_write(tp, 0x06, 0x0204); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0x19cc); -+ mdio_write(tp, 0x06, 0x022b); -+ mdio_write(tp, 0x06, 0x5bfc); -+ mdio_write(tp, 0x06, 0x04ee); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0x0105); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b83); -+ mdio_write(tp, 0x06, 0xad24); -+ mdio_write(tp, 0x06, 0x44e0); -+ mdio_write(tp, 0x06, 0xe022); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x23ad); -+ mdio_write(tp, 0x06, 0x223b); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xbea0); -+ mdio_write(tp, 0x06, 0x0005); -+ mdio_write(tp, 0x06, 0x0228); -+ mdio_write(tp, 0x06, 0xdeae); -+ mdio_write(tp, 0x06, 0x42a0); -+ mdio_write(tp, 0x06, 0x0105); -+ mdio_write(tp, 0x06, 0x0228); -+ mdio_write(tp, 0x06, 0xf1ae); -+ mdio_write(tp, 0x06, 0x3aa0); -+ mdio_write(tp, 0x06, 0x0205); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0x25ae); -+ mdio_write(tp, 0x06, 0x32a0); -+ mdio_write(tp, 0x06, 0x0305); -+ mdio_write(tp, 0x06, 0x0229); -+ mdio_write(tp, 0x06, 0x9aae); -+ mdio_write(tp, 0x06, 0x2aa0); -+ mdio_write(tp, 0x06, 0x0405); -+ mdio_write(tp, 0x06, 0x0229); -+ mdio_write(tp, 0x06, 0xaeae); -+ mdio_write(tp, 0x06, 0x22a0); -+ mdio_write(tp, 0x06, 0x0505); -+ mdio_write(tp, 0x06, 0x0229); -+ mdio_write(tp, 0x06, 0xd7ae); -+ mdio_write(tp, 0x06, 0x1aa0); -+ mdio_write(tp, 0x06, 0x0605); -+ mdio_write(tp, 0x06, 0x0229); -+ mdio_write(tp, 0x06, 0xfeae); -+ mdio_write(tp, 0x06, 0x12ee); -+ mdio_write(tp, 0x06, 0x8ac0); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8ac1); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8ac6); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8abe); -+ mdio_write(tp, 0x06, 0x00ae); -+ mdio_write(tp, 0x06, 0x00fc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0x022a); -+ mdio_write(tp, 0x06, 0x67e0); -+ mdio_write(tp, 0x06, 0xe022); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x230d); -+ mdio_write(tp, 0x06, 0x0658); -+ mdio_write(tp, 0x06, 0x03a0); -+ mdio_write(tp, 0x06, 0x0202); -+ mdio_write(tp, 0x06, 0xae2d); -+ mdio_write(tp, 0x06, 0xa001); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x2da0); -+ mdio_write(tp, 0x06, 0x004d); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0x00e1); -+ mdio_write(tp, 0x06, 0xe201); -+ mdio_write(tp, 0x06, 0xad24); -+ mdio_write(tp, 0x06, 0x44e0); -+ mdio_write(tp, 0x06, 0x8ac2); -+ mdio_write(tp, 0x06, 0xe48a); -+ mdio_write(tp, 0x06, 0xc4e0); -+ mdio_write(tp, 0x06, 0x8ac3); -+ mdio_write(tp, 0x06, 0xe48a); -+ mdio_write(tp, 0x06, 0xc5ee); -+ mdio_write(tp, 0x06, 0x8abe); -+ mdio_write(tp, 0x06, 0x03e0); -+ mdio_write(tp, 0x06, 0x8b83); -+ mdio_write(tp, 0x06, 0xad25); -+ mdio_write(tp, 0x06, 0x3aee); -+ mdio_write(tp, 0x06, 0x8abe); -+ mdio_write(tp, 0x06, 0x05ae); -+ mdio_write(tp, 0x06, 0x34e0); -+ mdio_write(tp, 0x06, 0x8ace); -+ mdio_write(tp, 0x06, 0xae03); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xcfe1); -+ mdio_write(tp, 0x06, 0x8ac2); -+ mdio_write(tp, 0x06, 0x4905); -+ mdio_write(tp, 0x06, 0xe58a); -+ mdio_write(tp, 0x06, 0xc4e1); -+ mdio_write(tp, 0x06, 0x8ac3); -+ mdio_write(tp, 0x06, 0x4905); -+ mdio_write(tp, 0x06, 0xe58a); -+ mdio_write(tp, 0x06, 0xc5ee); -+ mdio_write(tp, 0x06, 0x8abe); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0x2ab6); -+ mdio_write(tp, 0x06, 0xac20); -+ mdio_write(tp, 0x06, 0x1202); -+ mdio_write(tp, 0x06, 0x819b); -+ mdio_write(tp, 0x06, 0xac20); -+ mdio_write(tp, 0x06, 0x0cee); -+ mdio_write(tp, 0x06, 0x8ac1); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8ac6); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8abe); -+ mdio_write(tp, 0x06, 0x02fc); -+ mdio_write(tp, 0x06, 0x04d0); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x590f); -+ mdio_write(tp, 0x06, 0x3902); -+ mdio_write(tp, 0x06, 0xaa04); -+ mdio_write(tp, 0x06, 0xd001); -+ mdio_write(tp, 0x06, 0xae02); -+ mdio_write(tp, 0x06, 0xd000); -+ mdio_write(tp, 0x06, 0x04f9); -+ mdio_write(tp, 0x06, 0xfae2); -+ mdio_write(tp, 0x06, 0xe2d2); -+ mdio_write(tp, 0x06, 0xe3e2); -+ mdio_write(tp, 0x06, 0xd3f9); -+ mdio_write(tp, 0x06, 0x5af7); -+ mdio_write(tp, 0x06, 0xe6e2); -+ mdio_write(tp, 0x06, 0xd2e7); -+ mdio_write(tp, 0x06, 0xe2d3); -+ mdio_write(tp, 0x06, 0xe2e0); -+ mdio_write(tp, 0x06, 0x2ce3); -+ mdio_write(tp, 0x06, 0xe02d); -+ mdio_write(tp, 0x06, 0xf95b); -+ mdio_write(tp, 0x06, 0xe01e); -+ mdio_write(tp, 0x06, 0x30e6); -+ mdio_write(tp, 0x06, 0xe02c); -+ mdio_write(tp, 0x06, 0xe7e0); -+ mdio_write(tp, 0x06, 0x2de2); -+ mdio_write(tp, 0x06, 0xe2cc); -+ mdio_write(tp, 0x06, 0xe3e2); -+ mdio_write(tp, 0x06, 0xcdf9); -+ mdio_write(tp, 0x06, 0x5a0f); -+ mdio_write(tp, 0x06, 0x6a50); -+ mdio_write(tp, 0x06, 0xe6e2); -+ mdio_write(tp, 0x06, 0xcce7); -+ mdio_write(tp, 0x06, 0xe2cd); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x3ce1); -+ mdio_write(tp, 0x06, 0xe03d); -+ mdio_write(tp, 0x06, 0xef64); -+ mdio_write(tp, 0x06, 0xfde0); -+ mdio_write(tp, 0x06, 0xe2cc); -+ mdio_write(tp, 0x06, 0xe1e2); -+ mdio_write(tp, 0x06, 0xcd58); -+ mdio_write(tp, 0x06, 0x0f5a); -+ mdio_write(tp, 0x06, 0xf01e); -+ mdio_write(tp, 0x06, 0x02e4); -+ mdio_write(tp, 0x06, 0xe2cc); -+ mdio_write(tp, 0x06, 0xe5e2); -+ mdio_write(tp, 0x06, 0xcdfd); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x2ce1); -+ mdio_write(tp, 0x06, 0xe02d); -+ mdio_write(tp, 0x06, 0x59e0); -+ mdio_write(tp, 0x06, 0x5b1f); -+ mdio_write(tp, 0x06, 0x1e13); -+ mdio_write(tp, 0x06, 0xe4e0); -+ mdio_write(tp, 0x06, 0x2ce5); -+ mdio_write(tp, 0x06, 0xe02d); -+ mdio_write(tp, 0x06, 0xfde0); -+ mdio_write(tp, 0x06, 0xe2d2); -+ mdio_write(tp, 0x06, 0xe1e2); -+ mdio_write(tp, 0x06, 0xd358); -+ mdio_write(tp, 0x06, 0xf75a); -+ mdio_write(tp, 0x06, 0x081e); -+ mdio_write(tp, 0x06, 0x02e4); -+ mdio_write(tp, 0x06, 0xe2d2); -+ mdio_write(tp, 0x06, 0xe5e2); -+ mdio_write(tp, 0x06, 0xd3ef); -+ mdio_write(tp, 0x06, 0x46fe); -+ mdio_write(tp, 0x06, 0xfd04); -+ mdio_write(tp, 0x06, 0xf8f9); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x69e0); -+ mdio_write(tp, 0x06, 0xe022); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x2358); -+ mdio_write(tp, 0x06, 0xc4e1); -+ mdio_write(tp, 0x06, 0x8b6e); -+ mdio_write(tp, 0x06, 0x1f10); -+ mdio_write(tp, 0x06, 0x9e58); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x6ead); -+ mdio_write(tp, 0x06, 0x2222); -+ mdio_write(tp, 0x06, 0xac27); -+ mdio_write(tp, 0x06, 0x55ac); -+ mdio_write(tp, 0x06, 0x2602); -+ mdio_write(tp, 0x06, 0xae1a); -+ mdio_write(tp, 0x06, 0xd106); -+ mdio_write(tp, 0x06, 0xbf3b); -+ mdio_write(tp, 0x06, 0xba02); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xd107); -+ mdio_write(tp, 0x06, 0xbf3b); -+ mdio_write(tp, 0x06, 0xbd02); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xd107); -+ mdio_write(tp, 0x06, 0xbf3b); -+ mdio_write(tp, 0x06, 0xc002); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xae30); -+ mdio_write(tp, 0x06, 0xd103); -+ mdio_write(tp, 0x06, 0xbf3b); -+ mdio_write(tp, 0x06, 0xc302); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf3b); -+ mdio_write(tp, 0x06, 0xc602); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xca02); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xd10f); -+ mdio_write(tp, 0x06, 0xbf3b); -+ mdio_write(tp, 0x06, 0xba02); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xbf3b); -+ mdio_write(tp, 0x06, 0xbd02); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xbf3b); -+ mdio_write(tp, 0x06, 0xc002); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf3b); -+ mdio_write(tp, 0x06, 0xc302); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xd011); -+ mdio_write(tp, 0x06, 0x022b); -+ mdio_write(tp, 0x06, 0xfb59); -+ mdio_write(tp, 0x06, 0x03ef); -+ mdio_write(tp, 0x06, 0x01d1); -+ mdio_write(tp, 0x06, 0x00a0); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xbf3b); -+ mdio_write(tp, 0x06, 0xc602); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xd111); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x020c); -+ mdio_write(tp, 0x06, 0x11ad); -+ mdio_write(tp, 0x06, 0x2102); -+ mdio_write(tp, 0x06, 0x0c12); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xca02); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xaec8); -+ mdio_write(tp, 0x06, 0x70e4); -+ mdio_write(tp, 0x06, 0x2602); -+ mdio_write(tp, 0x06, 0x82d1); -+ mdio_write(tp, 0x06, 0x05f8); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x69e0); -+ mdio_write(tp, 0x06, 0xe2fe); -+ mdio_write(tp, 0x06, 0xe1e2); -+ mdio_write(tp, 0x06, 0xffad); -+ mdio_write(tp, 0x06, 0x2d1a); -+ mdio_write(tp, 0x06, 0xe0e1); -+ mdio_write(tp, 0x06, 0x4ee1); -+ mdio_write(tp, 0x06, 0xe14f); -+ mdio_write(tp, 0x06, 0xac2d); -+ mdio_write(tp, 0x06, 0x22f6); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0x033b); -+ mdio_write(tp, 0x06, 0xf703); -+ mdio_write(tp, 0x06, 0xf706); -+ mdio_write(tp, 0x06, 0xbf84); -+ mdio_write(tp, 0x06, 0x4402); -+ mdio_write(tp, 0x06, 0x2d21); -+ mdio_write(tp, 0x06, 0xae11); -+ mdio_write(tp, 0x06, 0xe0e1); -+ mdio_write(tp, 0x06, 0x4ee1); -+ mdio_write(tp, 0x06, 0xe14f); -+ mdio_write(tp, 0x06, 0xad2d); -+ mdio_write(tp, 0x06, 0x08bf); -+ mdio_write(tp, 0x06, 0x844f); -+ mdio_write(tp, 0x06, 0x022d); -+ mdio_write(tp, 0x06, 0x21f6); -+ mdio_write(tp, 0x06, 0x06ef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0x0283); -+ mdio_write(tp, 0x06, 0x4502); -+ mdio_write(tp, 0x06, 0x83a2); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x00e1); -+ mdio_write(tp, 0x06, 0xe001); -+ mdio_write(tp, 0x06, 0xad27); -+ mdio_write(tp, 0x06, 0x1fd1); -+ mdio_write(tp, 0x06, 0x01bf); -+ mdio_write(tp, 0x06, 0x843b); -+ mdio_write(tp, 0x06, 0x022d); -+ mdio_write(tp, 0x06, 0xc1e0); -+ mdio_write(tp, 0x06, 0xe020); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x21ad); -+ mdio_write(tp, 0x06, 0x200e); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf84); -+ mdio_write(tp, 0x06, 0x3b02); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xbf3b); -+ mdio_write(tp, 0x06, 0x9602); -+ mdio_write(tp, 0x06, 0x2d21); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x204c); -+ mdio_write(tp, 0x06, 0xd200); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0x0058); -+ mdio_write(tp, 0x06, 0x010c); -+ mdio_write(tp, 0x06, 0x021e); -+ mdio_write(tp, 0x06, 0x20e0); -+ mdio_write(tp, 0x06, 0xe000); -+ mdio_write(tp, 0x06, 0x5810); -+ mdio_write(tp, 0x06, 0x1e20); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x3658); -+ mdio_write(tp, 0x06, 0x031e); -+ mdio_write(tp, 0x06, 0x20e0); -+ mdio_write(tp, 0x06, 0xe022); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x2358); -+ mdio_write(tp, 0x06, 0xe01e); -+ mdio_write(tp, 0x06, 0x20e0); -+ mdio_write(tp, 0x06, 0x8b64); -+ mdio_write(tp, 0x06, 0x1f02); -+ mdio_write(tp, 0x06, 0x9e22); -+ mdio_write(tp, 0x06, 0xe68b); -+ mdio_write(tp, 0x06, 0x64ad); -+ mdio_write(tp, 0x06, 0x3214); -+ mdio_write(tp, 0x06, 0xad34); -+ mdio_write(tp, 0x06, 0x11ef); -+ mdio_write(tp, 0x06, 0x0258); -+ mdio_write(tp, 0x06, 0x039e); -+ mdio_write(tp, 0x06, 0x07ad); -+ mdio_write(tp, 0x06, 0x3508); -+ mdio_write(tp, 0x06, 0x5ac0); -+ mdio_write(tp, 0x06, 0x9f04); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xae02); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf84); -+ mdio_write(tp, 0x06, 0x3e02); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8f9); -+ mdio_write(tp, 0x06, 0xfbe0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xad25); -+ mdio_write(tp, 0x06, 0x22e0); -+ mdio_write(tp, 0x06, 0xe022); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x23e2); -+ mdio_write(tp, 0x06, 0xe036); -+ mdio_write(tp, 0x06, 0xe3e0); -+ mdio_write(tp, 0x06, 0x375a); -+ mdio_write(tp, 0x06, 0xc40d); -+ mdio_write(tp, 0x06, 0x0158); -+ mdio_write(tp, 0x06, 0x021e); -+ mdio_write(tp, 0x06, 0x20e3); -+ mdio_write(tp, 0x06, 0x8ae7); -+ mdio_write(tp, 0x06, 0xac31); -+ mdio_write(tp, 0x06, 0x60ac); -+ mdio_write(tp, 0x06, 0x3a08); -+ mdio_write(tp, 0x06, 0xac3e); -+ mdio_write(tp, 0x06, 0x26ae); -+ mdio_write(tp, 0x06, 0x67af); -+ mdio_write(tp, 0x06, 0x8437); -+ mdio_write(tp, 0x06, 0xad37); -+ mdio_write(tp, 0x06, 0x61e0); -+ mdio_write(tp, 0x06, 0x8ae8); -+ mdio_write(tp, 0x06, 0x10e4); -+ mdio_write(tp, 0x06, 0x8ae8); -+ mdio_write(tp, 0x06, 0xe18a); -+ mdio_write(tp, 0x06, 0xe91b); -+ mdio_write(tp, 0x06, 0x109e); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x51d1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x8441); -+ mdio_write(tp, 0x06, 0x022d); -+ mdio_write(tp, 0x06, 0xc1ee); -+ mdio_write(tp, 0x06, 0x8ae8); -+ mdio_write(tp, 0x06, 0x00ae); -+ mdio_write(tp, 0x06, 0x43ad); -+ mdio_write(tp, 0x06, 0x3627); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xeee1); -+ mdio_write(tp, 0x06, 0x8aef); -+ mdio_write(tp, 0x06, 0xef74); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xeae1); -+ mdio_write(tp, 0x06, 0x8aeb); -+ mdio_write(tp, 0x06, 0x1b74); -+ mdio_write(tp, 0x06, 0x9e2e); -+ mdio_write(tp, 0x06, 0x14e4); -+ mdio_write(tp, 0x06, 0x8aea); -+ mdio_write(tp, 0x06, 0xe58a); -+ mdio_write(tp, 0x06, 0xebef); -+ mdio_write(tp, 0x06, 0x74e0); -+ mdio_write(tp, 0x06, 0x8aee); -+ mdio_write(tp, 0x06, 0xe18a); -+ mdio_write(tp, 0x06, 0xef1b); -+ mdio_write(tp, 0x06, 0x479e); -+ mdio_write(tp, 0x06, 0x0fae); -+ mdio_write(tp, 0x06, 0x19ee); -+ mdio_write(tp, 0x06, 0x8aea); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8aeb); -+ mdio_write(tp, 0x06, 0x00ae); -+ mdio_write(tp, 0x06, 0x0fac); -+ mdio_write(tp, 0x06, 0x390c); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xbf84); -+ mdio_write(tp, 0x06, 0x4102); -+ mdio_write(tp, 0x06, 0x2dc1); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xe800); -+ mdio_write(tp, 0x06, 0xe68a); -+ mdio_write(tp, 0x06, 0xe7ff); -+ mdio_write(tp, 0x06, 0xfdfc); -+ mdio_write(tp, 0x06, 0x0400); -+ mdio_write(tp, 0x06, 0xe234); -+ mdio_write(tp, 0x06, 0xcce2); -+ mdio_write(tp, 0x06, 0x0088); -+ mdio_write(tp, 0x06, 0xe200); -+ mdio_write(tp, 0x06, 0xa725); -+ mdio_write(tp, 0x06, 0xe50a); -+ mdio_write(tp, 0x06, 0x1de5); -+ mdio_write(tp, 0x06, 0x0a2c); -+ mdio_write(tp, 0x06, 0xe50a); -+ mdio_write(tp, 0x06, 0x6de5); -+ mdio_write(tp, 0x06, 0x0a1d); -+ mdio_write(tp, 0x06, 0xe50a); -+ mdio_write(tp, 0x06, 0x1ce5); -+ mdio_write(tp, 0x06, 0x0a2d); -+ mdio_write(tp, 0x06, 0xa755); -+ mdio_write(tp, 0x05, 0x8b64); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x05, 0x8b94); -+ mdio_write(tp, 0x06, 0x82cd); -+ mdio_write(tp, 0x05, 0x8b85); -+ mdio_write(tp, 0x06, 0x2000); -+ mdio_write(tp, 0x05, 0x8aee); -+ mdio_write(tp, 0x06, 0x03b8); -+ mdio_write(tp, 0x05, 0x8ae8); -+ mdio_write(tp, 0x06, 0x0002); -+ gphy_val = mdio_read(tp, 0x01); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x01, gphy_val); -+ gphy_val = mdio_read(tp, 0x00); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x00, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1f, 0x0005); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x00); -+ if (gphy_val & BIT_7) -+ break; -+ } -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ gphy_val = mdio_read(tp, 0x17); -+ gphy_val &= ~(BIT_0); -+ if (tp->RequiredSecLanDonglePatch) -+ gphy_val &= ~(BIT_2); -+ mdio_write(tp, 0x17, gphy_val); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0028); -+ mdio_write(tp, 0x15, 0x0010); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0041); -+ mdio_write(tp, 0x15, 0x0802); -+ mdio_write(tp, 0x16, 0x2185); -+ mdio_write(tp, 0x1f, 0x0000); -+} -+ -+static void -+rtl8168_set_phy_mcu_8168e_2(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned int gphy_val,i; -+ -+ if (rtl8168_efuse_read(tp, 0x22) == 0x0c) { -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x00, 0x1800); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ mdio_write(tp, 0x17, 0x0117); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1E, 0x002C); -+ mdio_write(tp, 0x1B, 0x5000); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x16, 0x4104); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x1E); -+ gphy_val &= 0x03FF; -+ if (gphy_val==0x000C) -+ break; -+ } -+ mdio_write(tp, 0x1f, 0x0005); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x07); -+ if ((gphy_val & BIT_5) == 0) -+ break; -+ } -+ gphy_val = mdio_read(tp, 0x07); -+ if (gphy_val & BIT_5) { -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x00a1); -+ mdio_write(tp, 0x17, 0x1000); -+ mdio_write(tp, 0x17, 0x0000); -+ mdio_write(tp, 0x17, 0x2000); -+ mdio_write(tp, 0x1e, 0x002f); -+ mdio_write(tp, 0x18, 0x9bfb); -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x07, 0x0000); -+ mdio_write(tp, 0x1f, 0x0000); -+ } -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ gphy_val = mdio_read(tp, 0x00); -+ gphy_val &= ~(BIT_7); -+ mdio_write(tp, 0x00, gphy_val); -+ mdio_write(tp, 0x1f, 0x0002); -+ gphy_val = mdio_read(tp, 0x08); -+ gphy_val &= ~(BIT_7); -+ mdio_write(tp, 0x08, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0307); -+ mdio_write(tp, 0x15, 0x000e); -+ mdio_write(tp, 0x19, 0x000a); -+ mdio_write(tp, 0x15, 0x0010); -+ mdio_write(tp, 0x19, 0x0008); -+ mdio_write(tp, 0x15, 0x0018); -+ mdio_write(tp, 0x19, 0x4801); -+ mdio_write(tp, 0x15, 0x0019); -+ mdio_write(tp, 0x19, 0x6801); -+ mdio_write(tp, 0x15, 0x001a); -+ mdio_write(tp, 0x19, 0x66a1); -+ mdio_write(tp, 0x15, 0x001f); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0020); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0021); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0022); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0023); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0024); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0025); -+ mdio_write(tp, 0x19, 0x64a1); -+ mdio_write(tp, 0x15, 0x0026); -+ mdio_write(tp, 0x19, 0x40ea); -+ mdio_write(tp, 0x15, 0x0027); -+ mdio_write(tp, 0x19, 0x4503); -+ mdio_write(tp, 0x15, 0x0028); -+ mdio_write(tp, 0x19, 0x9f00); -+ mdio_write(tp, 0x15, 0x0029); -+ mdio_write(tp, 0x19, 0xa631); -+ mdio_write(tp, 0x15, 0x002a); -+ mdio_write(tp, 0x19, 0x9717); -+ mdio_write(tp, 0x15, 0x002b); -+ mdio_write(tp, 0x19, 0x302c); -+ mdio_write(tp, 0x15, 0x002c); -+ mdio_write(tp, 0x19, 0x4802); -+ mdio_write(tp, 0x15, 0x002d); -+ mdio_write(tp, 0x19, 0x58da); -+ mdio_write(tp, 0x15, 0x002e); -+ mdio_write(tp, 0x19, 0x400d); -+ mdio_write(tp, 0x15, 0x002f); -+ mdio_write(tp, 0x19, 0x4488); -+ mdio_write(tp, 0x15, 0x0030); -+ mdio_write(tp, 0x19, 0x9e00); -+ mdio_write(tp, 0x15, 0x0031); -+ mdio_write(tp, 0x19, 0x63c8); -+ mdio_write(tp, 0x15, 0x0032); -+ mdio_write(tp, 0x19, 0x6481); -+ mdio_write(tp, 0x15, 0x0033); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0034); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0035); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0036); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0037); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0038); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0039); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x003a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x003b); -+ mdio_write(tp, 0x19, 0x63e8); -+ mdio_write(tp, 0x15, 0x003c); -+ mdio_write(tp, 0x19, 0x7d00); -+ mdio_write(tp, 0x15, 0x003d); -+ mdio_write(tp, 0x19, 0x59d4); -+ mdio_write(tp, 0x15, 0x003e); -+ mdio_write(tp, 0x19, 0x63f8); -+ mdio_write(tp, 0x15, 0x0040); -+ mdio_write(tp, 0x19, 0x64a1); -+ mdio_write(tp, 0x15, 0x0041); -+ mdio_write(tp, 0x19, 0x30de); -+ mdio_write(tp, 0x15, 0x0044); -+ mdio_write(tp, 0x19, 0x480f); -+ mdio_write(tp, 0x15, 0x0045); -+ mdio_write(tp, 0x19, 0x6800); -+ mdio_write(tp, 0x15, 0x0046); -+ mdio_write(tp, 0x19, 0x6680); -+ mdio_write(tp, 0x15, 0x0047); -+ mdio_write(tp, 0x19, 0x7c10); -+ mdio_write(tp, 0x15, 0x0048); -+ mdio_write(tp, 0x19, 0x63c8); -+ mdio_write(tp, 0x15, 0x0049); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004b); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004c); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004d); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004e); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004f); -+ mdio_write(tp, 0x19, 0x40ea); -+ mdio_write(tp, 0x15, 0x0050); -+ mdio_write(tp, 0x19, 0x4503); -+ mdio_write(tp, 0x15, 0x0051); -+ mdio_write(tp, 0x19, 0x58ca); -+ mdio_write(tp, 0x15, 0x0052); -+ mdio_write(tp, 0x19, 0x63c8); -+ mdio_write(tp, 0x15, 0x0053); -+ mdio_write(tp, 0x19, 0x63d8); -+ mdio_write(tp, 0x15, 0x0054); -+ mdio_write(tp, 0x19, 0x66a0); -+ mdio_write(tp, 0x15, 0x0055); -+ mdio_write(tp, 0x19, 0x9f00); -+ mdio_write(tp, 0x15, 0x0056); -+ mdio_write(tp, 0x19, 0x3000); -+ mdio_write(tp, 0x15, 0x00a1); -+ mdio_write(tp, 0x19, 0x3044); -+ mdio_write(tp, 0x15, 0x00ab); -+ mdio_write(tp, 0x19, 0x5820); -+ mdio_write(tp, 0x15, 0x00ac); -+ mdio_write(tp, 0x19, 0x5e04); -+ mdio_write(tp, 0x15, 0x00ad); -+ mdio_write(tp, 0x19, 0xb60c); -+ mdio_write(tp, 0x15, 0x00af); -+ mdio_write(tp, 0x19, 0x000a); -+ mdio_write(tp, 0x15, 0x00b2); -+ mdio_write(tp, 0x19, 0x30b9); -+ mdio_write(tp, 0x15, 0x00b9); -+ mdio_write(tp, 0x19, 0x4408); -+ mdio_write(tp, 0x15, 0x00ba); -+ mdio_write(tp, 0x19, 0x480b); -+ mdio_write(tp, 0x15, 0x00bb); -+ mdio_write(tp, 0x19, 0x5e00); -+ mdio_write(tp, 0x15, 0x00bc); -+ mdio_write(tp, 0x19, 0x405f); -+ mdio_write(tp, 0x15, 0x00bd); -+ mdio_write(tp, 0x19, 0x4448); -+ mdio_write(tp, 0x15, 0x00be); -+ mdio_write(tp, 0x19, 0x4020); -+ mdio_write(tp, 0x15, 0x00bf); -+ mdio_write(tp, 0x19, 0x4468); -+ mdio_write(tp, 0x15, 0x00c0); -+ mdio_write(tp, 0x19, 0x9c02); -+ mdio_write(tp, 0x15, 0x00c1); -+ mdio_write(tp, 0x19, 0x58a0); -+ mdio_write(tp, 0x15, 0x00c2); -+ mdio_write(tp, 0x19, 0xb605); -+ mdio_write(tp, 0x15, 0x00c3); -+ mdio_write(tp, 0x19, 0xc0d3); -+ mdio_write(tp, 0x15, 0x00c4); -+ mdio_write(tp, 0x19, 0x00e6); -+ mdio_write(tp, 0x15, 0x00c5); -+ mdio_write(tp, 0x19, 0xdaec); -+ mdio_write(tp, 0x15, 0x00c6); -+ mdio_write(tp, 0x19, 0x00fa); -+ mdio_write(tp, 0x15, 0x00c7); -+ mdio_write(tp, 0x19, 0x9df9); -+ mdio_write(tp, 0x15, 0x0112); -+ mdio_write(tp, 0x19, 0x6421); -+ mdio_write(tp, 0x15, 0x0113); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x0114); -+ mdio_write(tp, 0x19, 0x63f0); -+ mdio_write(tp, 0x15, 0x0115); -+ mdio_write(tp, 0x19, 0x4003); -+ mdio_write(tp, 0x15, 0x0116); -+ mdio_write(tp, 0x19, 0x4418); -+ mdio_write(tp, 0x15, 0x0117); -+ mdio_write(tp, 0x19, 0x9b00); -+ mdio_write(tp, 0x15, 0x0118); -+ mdio_write(tp, 0x19, 0x6461); -+ mdio_write(tp, 0x15, 0x0119); -+ mdio_write(tp, 0x19, 0x64e1); -+ mdio_write(tp, 0x15, 0x011a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0150); -+ mdio_write(tp, 0x19, 0x7c80); -+ mdio_write(tp, 0x15, 0x0151); -+ mdio_write(tp, 0x19, 0x6461); -+ mdio_write(tp, 0x15, 0x0152); -+ mdio_write(tp, 0x19, 0x4003); -+ mdio_write(tp, 0x15, 0x0153); -+ mdio_write(tp, 0x19, 0x4540); -+ mdio_write(tp, 0x15, 0x0154); -+ mdio_write(tp, 0x19, 0x9f00); -+ mdio_write(tp, 0x15, 0x0155); -+ mdio_write(tp, 0x19, 0x9d00); -+ mdio_write(tp, 0x15, 0x0156); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x0157); -+ mdio_write(tp, 0x19, 0x6421); -+ mdio_write(tp, 0x15, 0x0158); -+ mdio_write(tp, 0x19, 0x7c80); -+ mdio_write(tp, 0x15, 0x0159); -+ mdio_write(tp, 0x19, 0x64a1); -+ mdio_write(tp, 0x15, 0x015a); -+ mdio_write(tp, 0x19, 0x30fe); -+ mdio_write(tp, 0x15, 0x029c); -+ mdio_write(tp, 0x19, 0x0070); -+ mdio_write(tp, 0x15, 0x02b2); -+ mdio_write(tp, 0x19, 0x005a); -+ mdio_write(tp, 0x15, 0x02bd); -+ mdio_write(tp, 0x19, 0xa522); -+ mdio_write(tp, 0x15, 0x02ce); -+ mdio_write(tp, 0x19, 0xb63e); -+ mdio_write(tp, 0x15, 0x02d9); -+ mdio_write(tp, 0x19, 0x32df); -+ mdio_write(tp, 0x15, 0x02df); -+ mdio_write(tp, 0x19, 0x4500); -+ mdio_write(tp, 0x15, 0x02e7); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02f4); -+ mdio_write(tp, 0x19, 0xb618); -+ mdio_write(tp, 0x15, 0x02fb); -+ mdio_write(tp, 0x19, 0xb900); -+ mdio_write(tp, 0x15, 0x02fc); -+ mdio_write(tp, 0x19, 0x49b5); -+ mdio_write(tp, 0x15, 0x02fd); -+ mdio_write(tp, 0x19, 0x6812); -+ mdio_write(tp, 0x15, 0x02fe); -+ mdio_write(tp, 0x19, 0x66a0); -+ mdio_write(tp, 0x15, 0x02ff); -+ mdio_write(tp, 0x19, 0x9900); -+ mdio_write(tp, 0x15, 0x0300); -+ mdio_write(tp, 0x19, 0x64a0); -+ mdio_write(tp, 0x15, 0x0301); -+ mdio_write(tp, 0x19, 0x3316); -+ mdio_write(tp, 0x15, 0x0308); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x030c); -+ mdio_write(tp, 0x19, 0x3000); -+ mdio_write(tp, 0x15, 0x0312); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0313); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0314); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0315); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0316); -+ mdio_write(tp, 0x19, 0x49b5); -+ mdio_write(tp, 0x15, 0x0317); -+ mdio_write(tp, 0x19, 0x7d00); -+ mdio_write(tp, 0x15, 0x0318); -+ mdio_write(tp, 0x19, 0x4d00); -+ mdio_write(tp, 0x15, 0x0319); -+ mdio_write(tp, 0x19, 0x6810); -+ mdio_write(tp, 0x15, 0x031a); -+ mdio_write(tp, 0x19, 0x6c08); -+ mdio_write(tp, 0x15, 0x031b); -+ mdio_write(tp, 0x19, 0x4925); -+ mdio_write(tp, 0x15, 0x031c); -+ mdio_write(tp, 0x19, 0x403b); -+ mdio_write(tp, 0x15, 0x031d); -+ mdio_write(tp, 0x19, 0xa602); -+ mdio_write(tp, 0x15, 0x031e); -+ mdio_write(tp, 0x19, 0x402f); -+ mdio_write(tp, 0x15, 0x031f); -+ mdio_write(tp, 0x19, 0x4484); -+ mdio_write(tp, 0x15, 0x0320); -+ mdio_write(tp, 0x19, 0x40c8); -+ mdio_write(tp, 0x15, 0x0321); -+ mdio_write(tp, 0x19, 0x44c4); -+ mdio_write(tp, 0x15, 0x0322); -+ mdio_write(tp, 0x19, 0x404f); -+ mdio_write(tp, 0x15, 0x0323); -+ mdio_write(tp, 0x19, 0x44c8); -+ mdio_write(tp, 0x15, 0x0324); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x0325); -+ mdio_write(tp, 0x19, 0x00e7); -+ mdio_write(tp, 0x15, 0x0326); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x0327); -+ mdio_write(tp, 0x19, 0x8203); -+ mdio_write(tp, 0x15, 0x0328); -+ mdio_write(tp, 0x19, 0x4d48); -+ mdio_write(tp, 0x15, 0x0329); -+ mdio_write(tp, 0x19, 0x332b); -+ mdio_write(tp, 0x15, 0x032a); -+ mdio_write(tp, 0x19, 0x4d40); -+ mdio_write(tp, 0x15, 0x032c); -+ mdio_write(tp, 0x19, 0x00f8); -+ mdio_write(tp, 0x15, 0x032d); -+ mdio_write(tp, 0x19, 0x82b2); -+ mdio_write(tp, 0x15, 0x032f); -+ mdio_write(tp, 0x19, 0x00b0); -+ mdio_write(tp, 0x15, 0x0332); -+ mdio_write(tp, 0x19, 0x91f2); -+ mdio_write(tp, 0x15, 0x033f); -+ mdio_write(tp, 0x19, 0xb6cd); -+ mdio_write(tp, 0x15, 0x0340); -+ mdio_write(tp, 0x19, 0x9e01); -+ mdio_write(tp, 0x15, 0x0341); -+ mdio_write(tp, 0x19, 0xd11d); -+ mdio_write(tp, 0x15, 0x0342); -+ mdio_write(tp, 0x19, 0x009d); -+ mdio_write(tp, 0x15, 0x0343); -+ mdio_write(tp, 0x19, 0xbb1c); -+ mdio_write(tp, 0x15, 0x0344); -+ mdio_write(tp, 0x19, 0x8102); -+ mdio_write(tp, 0x15, 0x0345); -+ mdio_write(tp, 0x19, 0x3348); -+ mdio_write(tp, 0x15, 0x0346); -+ mdio_write(tp, 0x19, 0xa231); -+ mdio_write(tp, 0x15, 0x0347); -+ mdio_write(tp, 0x19, 0x335b); -+ mdio_write(tp, 0x15, 0x0348); -+ mdio_write(tp, 0x19, 0x91f7); -+ mdio_write(tp, 0x15, 0x0349); -+ mdio_write(tp, 0x19, 0xc218); -+ mdio_write(tp, 0x15, 0x034a); -+ mdio_write(tp, 0x19, 0x00f5); -+ mdio_write(tp, 0x15, 0x034b); -+ mdio_write(tp, 0x19, 0x335b); -+ mdio_write(tp, 0x15, 0x034c); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x034d); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x034e); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x034f); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0350); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x035b); -+ mdio_write(tp, 0x19, 0xa23c); -+ mdio_write(tp, 0x15, 0x035c); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x035d); -+ mdio_write(tp, 0x19, 0x4c00); -+ mdio_write(tp, 0x15, 0x035e); -+ mdio_write(tp, 0x19, 0x3397); -+ mdio_write(tp, 0x15, 0x0363); -+ mdio_write(tp, 0x19, 0xb6a9); -+ mdio_write(tp, 0x15, 0x0366); -+ mdio_write(tp, 0x19, 0x00f5); -+ mdio_write(tp, 0x15, 0x0382); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x0388); -+ mdio_write(tp, 0x19, 0x0084); -+ mdio_write(tp, 0x15, 0x0389); -+ mdio_write(tp, 0x19, 0xdd17); -+ mdio_write(tp, 0x15, 0x038a); -+ mdio_write(tp, 0x19, 0x000b); -+ mdio_write(tp, 0x15, 0x038b); -+ mdio_write(tp, 0x19, 0xa10a); -+ mdio_write(tp, 0x15, 0x038c); -+ mdio_write(tp, 0x19, 0x337e); -+ mdio_write(tp, 0x15, 0x038d); -+ mdio_write(tp, 0x19, 0x6c0b); -+ mdio_write(tp, 0x15, 0x038e); -+ mdio_write(tp, 0x19, 0xa107); -+ mdio_write(tp, 0x15, 0x038f); -+ mdio_write(tp, 0x19, 0x6c08); -+ mdio_write(tp, 0x15, 0x0390); -+ mdio_write(tp, 0x19, 0xc017); -+ mdio_write(tp, 0x15, 0x0391); -+ mdio_write(tp, 0x19, 0x0004); -+ mdio_write(tp, 0x15, 0x0392); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x0393); -+ mdio_write(tp, 0x19, 0x00f4); -+ mdio_write(tp, 0x15, 0x0397); -+ mdio_write(tp, 0x19, 0x4098); -+ mdio_write(tp, 0x15, 0x0398); -+ mdio_write(tp, 0x19, 0x4408); -+ mdio_write(tp, 0x15, 0x0399); -+ mdio_write(tp, 0x19, 0x55bf); -+ mdio_write(tp, 0x15, 0x039a); -+ mdio_write(tp, 0x19, 0x4bb9); -+ mdio_write(tp, 0x15, 0x039b); -+ mdio_write(tp, 0x19, 0x6810); -+ mdio_write(tp, 0x15, 0x039c); -+ mdio_write(tp, 0x19, 0x4b29); -+ mdio_write(tp, 0x15, 0x039d); -+ mdio_write(tp, 0x19, 0x4041); -+ mdio_write(tp, 0x15, 0x039e); -+ mdio_write(tp, 0x19, 0x442a); -+ mdio_write(tp, 0x15, 0x039f); -+ mdio_write(tp, 0x19, 0x4029); -+ mdio_write(tp, 0x15, 0x03aa); -+ mdio_write(tp, 0x19, 0x33b8); -+ mdio_write(tp, 0x15, 0x03b6); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03b7); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03b8); -+ mdio_write(tp, 0x19, 0x543f); -+ mdio_write(tp, 0x15, 0x03b9); -+ mdio_write(tp, 0x19, 0x499a); -+ mdio_write(tp, 0x15, 0x03ba); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x03bb); -+ mdio_write(tp, 0x19, 0x4c40); -+ mdio_write(tp, 0x15, 0x03bc); -+ mdio_write(tp, 0x19, 0x490a); -+ mdio_write(tp, 0x15, 0x03bd); -+ mdio_write(tp, 0x19, 0x405e); -+ mdio_write(tp, 0x15, 0x03c2); -+ mdio_write(tp, 0x19, 0x9a03); -+ mdio_write(tp, 0x15, 0x03c4); -+ mdio_write(tp, 0x19, 0x0015); -+ mdio_write(tp, 0x15, 0x03c5); -+ mdio_write(tp, 0x19, 0x9e03); -+ mdio_write(tp, 0x15, 0x03c8); -+ mdio_write(tp, 0x19, 0x9cf7); -+ mdio_write(tp, 0x15, 0x03c9); -+ mdio_write(tp, 0x19, 0x7c12); -+ mdio_write(tp, 0x15, 0x03ca); -+ mdio_write(tp, 0x19, 0x4c52); -+ mdio_write(tp, 0x15, 0x03cb); -+ mdio_write(tp, 0x19, 0x4458); -+ mdio_write(tp, 0x15, 0x03cd); -+ mdio_write(tp, 0x19, 0x4c40); -+ mdio_write(tp, 0x15, 0x03ce); -+ mdio_write(tp, 0x19, 0x33bf); -+ mdio_write(tp, 0x15, 0x03cf); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03d0); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03d1); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03d5); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03d6); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03d7); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03d8); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03d9); -+ mdio_write(tp, 0x19, 0x49bb); -+ mdio_write(tp, 0x15, 0x03da); -+ mdio_write(tp, 0x19, 0x4478); -+ mdio_write(tp, 0x15, 0x03db); -+ mdio_write(tp, 0x19, 0x492b); -+ mdio_write(tp, 0x15, 0x03dc); -+ mdio_write(tp, 0x19, 0x7c01); -+ mdio_write(tp, 0x15, 0x03dd); -+ mdio_write(tp, 0x19, 0x4c00); -+ mdio_write(tp, 0x15, 0x03de); -+ mdio_write(tp, 0x19, 0xbd1a); -+ mdio_write(tp, 0x15, 0x03df); -+ mdio_write(tp, 0x19, 0xc428); -+ mdio_write(tp, 0x15, 0x03e0); -+ mdio_write(tp, 0x19, 0x0008); -+ mdio_write(tp, 0x15, 0x03e1); -+ mdio_write(tp, 0x19, 0x9cfd); -+ mdio_write(tp, 0x15, 0x03e2); -+ mdio_write(tp, 0x19, 0x7c12); -+ mdio_write(tp, 0x15, 0x03e3); -+ mdio_write(tp, 0x19, 0x4c52); -+ mdio_write(tp, 0x15, 0x03e4); -+ mdio_write(tp, 0x19, 0x4458); -+ mdio_write(tp, 0x15, 0x03e5); -+ mdio_write(tp, 0x19, 0x7c12); -+ mdio_write(tp, 0x15, 0x03e6); -+ mdio_write(tp, 0x19, 0x4c40); -+ mdio_write(tp, 0x15, 0x03e7); -+ mdio_write(tp, 0x19, 0x33de); -+ mdio_write(tp, 0x15, 0x03e8); -+ mdio_write(tp, 0x19, 0xc218); -+ mdio_write(tp, 0x15, 0x03e9); -+ mdio_write(tp, 0x19, 0x0002); -+ mdio_write(tp, 0x15, 0x03ea); -+ mdio_write(tp, 0x19, 0x32df); -+ mdio_write(tp, 0x15, 0x03eb); -+ mdio_write(tp, 0x19, 0x3316); -+ mdio_write(tp, 0x15, 0x03ec); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03ed); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03ee); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03ef); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03f7); -+ mdio_write(tp, 0x19, 0x330c); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0300); -+ -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ mdio_write(tp, 0x05, 0x8000); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0x48f7); -+ mdio_write(tp, 0x06, 0x00e0); -+ mdio_write(tp, 0x06, 0xfff7); -+ mdio_write(tp, 0x06, 0xa080); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0xf602); -+ mdio_write(tp, 0x06, 0x0200); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0x9002); -+ mdio_write(tp, 0x06, 0x0224); -+ mdio_write(tp, 0x06, 0x0202); -+ mdio_write(tp, 0x06, 0x3402); -+ mdio_write(tp, 0x06, 0x027f); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0xa602); -+ mdio_write(tp, 0x06, 0x80bf); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x88e1); -+ mdio_write(tp, 0x06, 0x8b89); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8a1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8b); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8c1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8e1e); -+ mdio_write(tp, 0x06, 0x01a0); -+ mdio_write(tp, 0x06, 0x00c7); -+ mdio_write(tp, 0x06, 0xaebb); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xe600); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xee03); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xefb8); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xe902); -+ mdio_write(tp, 0x06, 0xee8b); -+ mdio_write(tp, 0x06, 0x8285); -+ mdio_write(tp, 0x06, 0xee8b); -+ mdio_write(tp, 0x06, 0x8520); -+ mdio_write(tp, 0x06, 0xee8b); -+ mdio_write(tp, 0x06, 0x8701); -+ mdio_write(tp, 0x06, 0xd481); -+ mdio_write(tp, 0x06, 0x35e4); -+ mdio_write(tp, 0x06, 0x8b94); -+ mdio_write(tp, 0x06, 0xe58b); -+ mdio_write(tp, 0x06, 0x95bf); -+ mdio_write(tp, 0x06, 0x8b88); -+ mdio_write(tp, 0x06, 0xec00); -+ mdio_write(tp, 0x06, 0x19a9); -+ mdio_write(tp, 0x06, 0x8b90); -+ mdio_write(tp, 0x06, 0xf9ee); -+ mdio_write(tp, 0x06, 0xfff6); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0xfff7); -+ mdio_write(tp, 0x06, 0xffe0); -+ mdio_write(tp, 0x06, 0xe140); -+ mdio_write(tp, 0x06, 0xe1e1); -+ mdio_write(tp, 0x06, 0x41f7); -+ mdio_write(tp, 0x06, 0x2ff6); -+ mdio_write(tp, 0x06, 0x28e4); -+ mdio_write(tp, 0x06, 0xe140); -+ mdio_write(tp, 0x06, 0xe5e1); -+ mdio_write(tp, 0x06, 0x4104); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b89); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x0dee); -+ mdio_write(tp, 0x06, 0x8b89); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x82f4); -+ mdio_write(tp, 0x06, 0x021f); -+ mdio_write(tp, 0x06, 0x4102); -+ mdio_write(tp, 0x06, 0x2812); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x10ee); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x139d); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0xd602); -+ mdio_write(tp, 0x06, 0x1f99); -+ mdio_write(tp, 0x06, 0x0227); -+ mdio_write(tp, 0x06, 0xeafc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2014); -+ mdio_write(tp, 0x06, 0xf620); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x8104); -+ mdio_write(tp, 0x06, 0x021b); -+ mdio_write(tp, 0x06, 0xf402); -+ mdio_write(tp, 0x06, 0x2c9c); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0x7902); -+ mdio_write(tp, 0x06, 0x8443); -+ mdio_write(tp, 0x06, 0xad22); -+ mdio_write(tp, 0x06, 0x11f6); -+ mdio_write(tp, 0x06, 0x22e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x022c); -+ mdio_write(tp, 0x06, 0x4602); -+ mdio_write(tp, 0x06, 0x2ac5); -+ mdio_write(tp, 0x06, 0x0229); -+ mdio_write(tp, 0x06, 0x2002); -+ mdio_write(tp, 0x06, 0x2b91); -+ mdio_write(tp, 0x06, 0xad25); -+ mdio_write(tp, 0x06, 0x11f6); -+ mdio_write(tp, 0x06, 0x25e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x0284); -+ mdio_write(tp, 0x06, 0xe202); -+ mdio_write(tp, 0x06, 0x043a); -+ mdio_write(tp, 0x06, 0x021a); -+ mdio_write(tp, 0x06, 0x5902); -+ mdio_write(tp, 0x06, 0x2bfc); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x00e1); -+ mdio_write(tp, 0x06, 0xe001); -+ mdio_write(tp, 0x06, 0xad27); -+ mdio_write(tp, 0x06, 0x1fd1); -+ mdio_write(tp, 0x06, 0x01bf); -+ mdio_write(tp, 0x06, 0x8638); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x50e0); -+ mdio_write(tp, 0x06, 0xe020); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x21ad); -+ mdio_write(tp, 0x06, 0x200e); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x3802); -+ mdio_write(tp, 0x06, 0x2f50); -+ mdio_write(tp, 0x06, 0xbf3d); -+ mdio_write(tp, 0x06, 0x3902); -+ mdio_write(tp, 0x06, 0x2eb0); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefc); -+ mdio_write(tp, 0x06, 0x0402); -+ mdio_write(tp, 0x06, 0x8591); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0x3c05); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0xfee1); -+ mdio_write(tp, 0x06, 0xe2ff); -+ mdio_write(tp, 0x06, 0xad2d); -+ mdio_write(tp, 0x06, 0x1ae0); -+ mdio_write(tp, 0x06, 0xe14e); -+ mdio_write(tp, 0x06, 0xe1e1); -+ mdio_write(tp, 0x06, 0x4fac); -+ mdio_write(tp, 0x06, 0x2d22); -+ mdio_write(tp, 0x06, 0xf603); -+ mdio_write(tp, 0x06, 0x0203); -+ mdio_write(tp, 0x06, 0x36f7); -+ mdio_write(tp, 0x06, 0x03f7); -+ mdio_write(tp, 0x06, 0x06bf); -+ mdio_write(tp, 0x06, 0x8622); -+ mdio_write(tp, 0x06, 0x022e); -+ mdio_write(tp, 0x06, 0xb0ae); -+ mdio_write(tp, 0x06, 0x11e0); -+ mdio_write(tp, 0x06, 0xe14e); -+ mdio_write(tp, 0x06, 0xe1e1); -+ mdio_write(tp, 0x06, 0x4fad); -+ mdio_write(tp, 0x06, 0x2d08); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x2d02); -+ mdio_write(tp, 0x06, 0x2eb0); -+ mdio_write(tp, 0x06, 0xf606); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x204c); -+ mdio_write(tp, 0x06, 0xd200); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0x0058); -+ mdio_write(tp, 0x06, 0x010c); -+ mdio_write(tp, 0x06, 0x021e); -+ mdio_write(tp, 0x06, 0x20e0); -+ mdio_write(tp, 0x06, 0xe000); -+ mdio_write(tp, 0x06, 0x5810); -+ mdio_write(tp, 0x06, 0x1e20); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x3658); -+ mdio_write(tp, 0x06, 0x031e); -+ mdio_write(tp, 0x06, 0x20e0); -+ mdio_write(tp, 0x06, 0xe022); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x2358); -+ mdio_write(tp, 0x06, 0xe01e); -+ mdio_write(tp, 0x06, 0x20e0); -+ mdio_write(tp, 0x06, 0x8ae6); -+ mdio_write(tp, 0x06, 0x1f02); -+ mdio_write(tp, 0x06, 0x9e22); -+ mdio_write(tp, 0x06, 0xe68a); -+ mdio_write(tp, 0x06, 0xe6ad); -+ mdio_write(tp, 0x06, 0x3214); -+ mdio_write(tp, 0x06, 0xad34); -+ mdio_write(tp, 0x06, 0x11ef); -+ mdio_write(tp, 0x06, 0x0258); -+ mdio_write(tp, 0x06, 0x039e); -+ mdio_write(tp, 0x06, 0x07ad); -+ mdio_write(tp, 0x06, 0x3508); -+ mdio_write(tp, 0x06, 0x5ac0); -+ mdio_write(tp, 0x06, 0x9f04); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xae02); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x3e02); -+ mdio_write(tp, 0x06, 0x2f50); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8f9); -+ mdio_write(tp, 0x06, 0xfae0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xac26); -+ mdio_write(tp, 0x06, 0x0ee0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xac21); -+ mdio_write(tp, 0x06, 0x08e0); -+ mdio_write(tp, 0x06, 0x8b87); -+ mdio_write(tp, 0x06, 0xac24); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x6bee); -+ mdio_write(tp, 0x06, 0xe0ea); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0xe0eb); -+ mdio_write(tp, 0x06, 0x00e2); -+ mdio_write(tp, 0x06, 0xe07c); -+ mdio_write(tp, 0x06, 0xe3e0); -+ mdio_write(tp, 0x06, 0x7da5); -+ mdio_write(tp, 0x06, 0x1111); -+ mdio_write(tp, 0x06, 0x15d2); -+ mdio_write(tp, 0x06, 0x60d6); -+ mdio_write(tp, 0x06, 0x6666); -+ mdio_write(tp, 0x06, 0x0207); -+ mdio_write(tp, 0x06, 0xf9d2); -+ mdio_write(tp, 0x06, 0xa0d6); -+ mdio_write(tp, 0x06, 0xaaaa); -+ mdio_write(tp, 0x06, 0x0207); -+ mdio_write(tp, 0x06, 0xf902); -+ mdio_write(tp, 0x06, 0x825c); -+ mdio_write(tp, 0x06, 0xae44); -+ mdio_write(tp, 0x06, 0xa566); -+ mdio_write(tp, 0x06, 0x6602); -+ mdio_write(tp, 0x06, 0xae38); -+ mdio_write(tp, 0x06, 0xa5aa); -+ mdio_write(tp, 0x06, 0xaa02); -+ mdio_write(tp, 0x06, 0xae32); -+ mdio_write(tp, 0x06, 0xeee0); -+ mdio_write(tp, 0x06, 0xea04); -+ mdio_write(tp, 0x06, 0xeee0); -+ mdio_write(tp, 0x06, 0xeb06); -+ mdio_write(tp, 0x06, 0xe2e0); -+ mdio_write(tp, 0x06, 0x7ce3); -+ mdio_write(tp, 0x06, 0xe07d); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x38e1); -+ mdio_write(tp, 0x06, 0xe039); -+ mdio_write(tp, 0x06, 0xad2e); -+ mdio_write(tp, 0x06, 0x21ad); -+ mdio_write(tp, 0x06, 0x3f13); -+ mdio_write(tp, 0x06, 0xe0e4); -+ mdio_write(tp, 0x06, 0x14e1); -+ mdio_write(tp, 0x06, 0xe415); -+ mdio_write(tp, 0x06, 0x6880); -+ mdio_write(tp, 0x06, 0xe4e4); -+ mdio_write(tp, 0x06, 0x14e5); -+ mdio_write(tp, 0x06, 0xe415); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0x5cae); -+ mdio_write(tp, 0x06, 0x0bac); -+ mdio_write(tp, 0x06, 0x3e02); -+ mdio_write(tp, 0x06, 0xae06); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0x8602); -+ mdio_write(tp, 0x06, 0x82b0); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e1); -+ mdio_write(tp, 0x06, 0x8b2e); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x2605); -+ mdio_write(tp, 0x06, 0x0221); -+ mdio_write(tp, 0x06, 0xf3f7); -+ mdio_write(tp, 0x06, 0x28e0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xad21); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0x22f8); -+ mdio_write(tp, 0x06, 0xf729); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x2405); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0xebf7); -+ mdio_write(tp, 0x06, 0x2ae5); -+ mdio_write(tp, 0x06, 0x8b2e); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xad26); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0x2134); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x2109); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x2eac); -+ mdio_write(tp, 0x06, 0x2003); -+ mdio_write(tp, 0x06, 0x0283); -+ mdio_write(tp, 0x06, 0x52e0); -+ mdio_write(tp, 0x06, 0x8b87); -+ mdio_write(tp, 0x06, 0xad24); -+ mdio_write(tp, 0x06, 0x09e0); -+ mdio_write(tp, 0x06, 0x8b2e); -+ mdio_write(tp, 0x06, 0xac21); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0x8337); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e1); -+ mdio_write(tp, 0x06, 0x8b2e); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x2608); -+ mdio_write(tp, 0x06, 0xe085); -+ mdio_write(tp, 0x06, 0xd2ad); -+ mdio_write(tp, 0x06, 0x2502); -+ mdio_write(tp, 0x06, 0xf628); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x210a); -+ mdio_write(tp, 0x06, 0xe086); -+ mdio_write(tp, 0x06, 0x0af6); -+ mdio_write(tp, 0x06, 0x27a0); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0xf629); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x2408); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xedad); -+ mdio_write(tp, 0x06, 0x2002); -+ mdio_write(tp, 0x06, 0xf62a); -+ mdio_write(tp, 0x06, 0xe58b); -+ mdio_write(tp, 0x06, 0x2ea1); -+ mdio_write(tp, 0x06, 0x0003); -+ mdio_write(tp, 0x06, 0x0221); -+ mdio_write(tp, 0x06, 0x11fc); -+ mdio_write(tp, 0x06, 0x04ee); -+ mdio_write(tp, 0x06, 0x8aed); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8aec); -+ mdio_write(tp, 0x06, 0x0004); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b87); -+ mdio_write(tp, 0x06, 0xad24); -+ mdio_write(tp, 0x06, 0x3ae0); -+ mdio_write(tp, 0x06, 0xe0ea); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0xeb58); -+ mdio_write(tp, 0x06, 0xf8d1); -+ mdio_write(tp, 0x06, 0x01e4); -+ mdio_write(tp, 0x06, 0xe0ea); -+ mdio_write(tp, 0x06, 0xe5e0); -+ mdio_write(tp, 0x06, 0xebe0); -+ mdio_write(tp, 0x06, 0xe07c); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x7d5c); -+ mdio_write(tp, 0x06, 0x00ff); -+ mdio_write(tp, 0x06, 0x3c00); -+ mdio_write(tp, 0x06, 0x1eab); -+ mdio_write(tp, 0x06, 0x1ce0); -+ mdio_write(tp, 0x06, 0xe04c); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x4d58); -+ mdio_write(tp, 0x06, 0xc1e4); -+ mdio_write(tp, 0x06, 0xe04c); -+ mdio_write(tp, 0x06, 0xe5e0); -+ mdio_write(tp, 0x06, 0x4de0); -+ mdio_write(tp, 0x06, 0xe0ee); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0x3ce4); -+ mdio_write(tp, 0x06, 0xe0ee); -+ mdio_write(tp, 0x06, 0xe5e0); -+ mdio_write(tp, 0x06, 0xeffc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x2412); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0xeee1); -+ mdio_write(tp, 0x06, 0xe0ef); -+ mdio_write(tp, 0x06, 0x59c3); -+ mdio_write(tp, 0x06, 0xe4e0); -+ mdio_write(tp, 0x06, 0xeee5); -+ mdio_write(tp, 0x06, 0xe0ef); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xed01); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xac25); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0x8363); -+ mdio_write(tp, 0x06, 0xae03); -+ mdio_write(tp, 0x06, 0x0225); -+ mdio_write(tp, 0x06, 0x16fc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xfae0); -+ mdio_write(tp, 0x06, 0x860a); -+ mdio_write(tp, 0x06, 0xa000); -+ mdio_write(tp, 0x06, 0x19e0); -+ mdio_write(tp, 0x06, 0x860b); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x331b); -+ mdio_write(tp, 0x06, 0x109e); -+ mdio_write(tp, 0x06, 0x04aa); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x06ee); -+ mdio_write(tp, 0x06, 0x860a); -+ mdio_write(tp, 0x06, 0x01ae); -+ mdio_write(tp, 0x06, 0xe602); -+ mdio_write(tp, 0x06, 0x241e); -+ mdio_write(tp, 0x06, 0xae14); -+ mdio_write(tp, 0x06, 0xa001); -+ mdio_write(tp, 0x06, 0x1402); -+ mdio_write(tp, 0x06, 0x2426); -+ mdio_write(tp, 0x06, 0xbf26); -+ mdio_write(tp, 0x06, 0x6d02); -+ mdio_write(tp, 0x06, 0x2eb0); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0b00); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0a02); -+ mdio_write(tp, 0x06, 0xaf84); -+ mdio_write(tp, 0x06, 0x3ca0); -+ mdio_write(tp, 0x06, 0x0252); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0400); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0500); -+ mdio_write(tp, 0x06, 0xe086); -+ mdio_write(tp, 0x06, 0x0be1); -+ mdio_write(tp, 0x06, 0x8b32); -+ mdio_write(tp, 0x06, 0x1b10); -+ mdio_write(tp, 0x06, 0x9e04); -+ mdio_write(tp, 0x06, 0xaa02); -+ mdio_write(tp, 0x06, 0xaecb); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0b00); -+ mdio_write(tp, 0x06, 0x0224); -+ mdio_write(tp, 0x06, 0x3ae2); -+ mdio_write(tp, 0x06, 0x8604); -+ mdio_write(tp, 0x06, 0xe386); -+ mdio_write(tp, 0x06, 0x05ef); -+ mdio_write(tp, 0x06, 0x65e2); -+ mdio_write(tp, 0x06, 0x8606); -+ mdio_write(tp, 0x06, 0xe386); -+ mdio_write(tp, 0x06, 0x071b); -+ mdio_write(tp, 0x06, 0x56aa); -+ mdio_write(tp, 0x06, 0x0eef); -+ mdio_write(tp, 0x06, 0x56e6); -+ mdio_write(tp, 0x06, 0x8606); -+ mdio_write(tp, 0x06, 0xe786); -+ mdio_write(tp, 0x06, 0x07e2); -+ mdio_write(tp, 0x06, 0x8609); -+ mdio_write(tp, 0x06, 0xe686); -+ mdio_write(tp, 0x06, 0x08e0); -+ mdio_write(tp, 0x06, 0x8609); -+ mdio_write(tp, 0x06, 0xa000); -+ mdio_write(tp, 0x06, 0x07ee); -+ mdio_write(tp, 0x06, 0x860a); -+ mdio_write(tp, 0x06, 0x03af); -+ mdio_write(tp, 0x06, 0x8369); -+ mdio_write(tp, 0x06, 0x0224); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x2426); -+ mdio_write(tp, 0x06, 0xae48); -+ mdio_write(tp, 0x06, 0xa003); -+ mdio_write(tp, 0x06, 0x21e0); -+ mdio_write(tp, 0x06, 0x8608); -+ mdio_write(tp, 0x06, 0xe186); -+ mdio_write(tp, 0x06, 0x091b); -+ mdio_write(tp, 0x06, 0x019e); -+ mdio_write(tp, 0x06, 0x0caa); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0x249d); -+ mdio_write(tp, 0x06, 0xaee7); -+ mdio_write(tp, 0x06, 0x0224); -+ mdio_write(tp, 0x06, 0x8eae); -+ mdio_write(tp, 0x06, 0xe2ee); -+ mdio_write(tp, 0x06, 0x860a); -+ mdio_write(tp, 0x06, 0x04ee); -+ mdio_write(tp, 0x06, 0x860b); -+ mdio_write(tp, 0x06, 0x00af); -+ mdio_write(tp, 0x06, 0x8369); -+ mdio_write(tp, 0x06, 0xa004); -+ mdio_write(tp, 0x06, 0x15e0); -+ mdio_write(tp, 0x06, 0x860b); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x341b); -+ mdio_write(tp, 0x06, 0x109e); -+ mdio_write(tp, 0x06, 0x05aa); -+ mdio_write(tp, 0x06, 0x03af); -+ mdio_write(tp, 0x06, 0x8383); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0a05); -+ mdio_write(tp, 0x06, 0xae0c); -+ mdio_write(tp, 0x06, 0xa005); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x0702); -+ mdio_write(tp, 0x06, 0x2309); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0a00); -+ mdio_write(tp, 0x06, 0xfeef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfdfc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xfbe0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xad25); -+ mdio_write(tp, 0x06, 0x22e0); -+ mdio_write(tp, 0x06, 0xe022); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x23e2); -+ mdio_write(tp, 0x06, 0xe036); -+ mdio_write(tp, 0x06, 0xe3e0); -+ mdio_write(tp, 0x06, 0x375a); -+ mdio_write(tp, 0x06, 0xc40d); -+ mdio_write(tp, 0x06, 0x0158); -+ mdio_write(tp, 0x06, 0x021e); -+ mdio_write(tp, 0x06, 0x20e3); -+ mdio_write(tp, 0x06, 0x8ae7); -+ mdio_write(tp, 0x06, 0xac31); -+ mdio_write(tp, 0x06, 0x60ac); -+ mdio_write(tp, 0x06, 0x3a08); -+ mdio_write(tp, 0x06, 0xac3e); -+ mdio_write(tp, 0x06, 0x26ae); -+ mdio_write(tp, 0x06, 0x67af); -+ mdio_write(tp, 0x06, 0x84db); -+ mdio_write(tp, 0x06, 0xad37); -+ mdio_write(tp, 0x06, 0x61e0); -+ mdio_write(tp, 0x06, 0x8ae8); -+ mdio_write(tp, 0x06, 0x10e4); -+ mdio_write(tp, 0x06, 0x8ae8); -+ mdio_write(tp, 0x06, 0xe18a); -+ mdio_write(tp, 0x06, 0xe91b); -+ mdio_write(tp, 0x06, 0x109e); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x51d1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x863b); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x50ee); -+ mdio_write(tp, 0x06, 0x8ae8); -+ mdio_write(tp, 0x06, 0x00ae); -+ mdio_write(tp, 0x06, 0x43ad); -+ mdio_write(tp, 0x06, 0x3627); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xeee1); -+ mdio_write(tp, 0x06, 0x8aef); -+ mdio_write(tp, 0x06, 0xef74); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xeae1); -+ mdio_write(tp, 0x06, 0x8aeb); -+ mdio_write(tp, 0x06, 0x1b74); -+ mdio_write(tp, 0x06, 0x9e2e); -+ mdio_write(tp, 0x06, 0x14e4); -+ mdio_write(tp, 0x06, 0x8aea); -+ mdio_write(tp, 0x06, 0xe58a); -+ mdio_write(tp, 0x06, 0xebef); -+ mdio_write(tp, 0x06, 0x74e0); -+ mdio_write(tp, 0x06, 0x8aee); -+ mdio_write(tp, 0x06, 0xe18a); -+ mdio_write(tp, 0x06, 0xef1b); -+ mdio_write(tp, 0x06, 0x479e); -+ mdio_write(tp, 0x06, 0x0fae); -+ mdio_write(tp, 0x06, 0x19ee); -+ mdio_write(tp, 0x06, 0x8aea); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8aeb); -+ mdio_write(tp, 0x06, 0x00ae); -+ mdio_write(tp, 0x06, 0x0fac); -+ mdio_write(tp, 0x06, 0x390c); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x3b02); -+ mdio_write(tp, 0x06, 0x2f50); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xe800); -+ mdio_write(tp, 0x06, 0xe68a); -+ mdio_write(tp, 0x06, 0xe7ff); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8f9); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x69e0); -+ mdio_write(tp, 0x06, 0xe022); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x2358); -+ mdio_write(tp, 0x06, 0xc4e1); -+ mdio_write(tp, 0x06, 0x8b6e); -+ mdio_write(tp, 0x06, 0x1f10); -+ mdio_write(tp, 0x06, 0x9e24); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x6ead); -+ mdio_write(tp, 0x06, 0x2218); -+ mdio_write(tp, 0x06, 0xac27); -+ mdio_write(tp, 0x06, 0x0dac); -+ mdio_write(tp, 0x06, 0x2605); -+ mdio_write(tp, 0x06, 0x0203); -+ mdio_write(tp, 0x06, 0x8fae); -+ mdio_write(tp, 0x06, 0x1302); -+ mdio_write(tp, 0x06, 0x03c8); -+ mdio_write(tp, 0x06, 0xae0e); -+ mdio_write(tp, 0x06, 0x0203); -+ mdio_write(tp, 0x06, 0xe102); -+ mdio_write(tp, 0x06, 0x8520); -+ mdio_write(tp, 0x06, 0xae06); -+ mdio_write(tp, 0x06, 0x0203); -+ mdio_write(tp, 0x06, 0x8f02); -+ mdio_write(tp, 0x06, 0x8566); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x82ad); -+ mdio_write(tp, 0x06, 0x2737); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x4402); -+ mdio_write(tp, 0x06, 0x2f23); -+ mdio_write(tp, 0x06, 0xac28); -+ mdio_write(tp, 0x06, 0x2ed1); -+ mdio_write(tp, 0x06, 0x01bf); -+ mdio_write(tp, 0x06, 0x8647); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x50bf); -+ mdio_write(tp, 0x06, 0x8641); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x23e5); -+ mdio_write(tp, 0x06, 0x8af0); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x22e1); -+ mdio_write(tp, 0x06, 0xe023); -+ mdio_write(tp, 0x06, 0xac2e); -+ mdio_write(tp, 0x06, 0x04d1); -+ mdio_write(tp, 0x06, 0x01ae); -+ mdio_write(tp, 0x06, 0x02d1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x8641); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x50d1); -+ mdio_write(tp, 0x06, 0x01bf); -+ mdio_write(tp, 0x06, 0x8644); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x50ef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x4702); -+ mdio_write(tp, 0x06, 0x2f23); -+ mdio_write(tp, 0x06, 0xad28); -+ mdio_write(tp, 0x06, 0x19d1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x8644); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x50e1); -+ mdio_write(tp, 0x06, 0x8af0); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x4102); -+ mdio_write(tp, 0x06, 0x2f50); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x4702); -+ mdio_write(tp, 0x06, 0x2f50); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0xfee1); -+ mdio_write(tp, 0x06, 0xe2ff); -+ mdio_write(tp, 0x06, 0xad2e); -+ mdio_write(tp, 0x06, 0x63e0); -+ mdio_write(tp, 0x06, 0xe038); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x39ad); -+ mdio_write(tp, 0x06, 0x2f10); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x34e1); -+ mdio_write(tp, 0x06, 0xe035); -+ mdio_write(tp, 0x06, 0xf726); -+ mdio_write(tp, 0x06, 0xe4e0); -+ mdio_write(tp, 0x06, 0x34e5); -+ mdio_write(tp, 0x06, 0xe035); -+ mdio_write(tp, 0x06, 0xae0e); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0xd6e1); -+ mdio_write(tp, 0x06, 0xe2d7); -+ mdio_write(tp, 0x06, 0xf728); -+ mdio_write(tp, 0x06, 0xe4e2); -+ mdio_write(tp, 0x06, 0xd6e5); -+ mdio_write(tp, 0x06, 0xe2d7); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0x34e1); -+ mdio_write(tp, 0x06, 0xe235); -+ mdio_write(tp, 0x06, 0xf72b); -+ mdio_write(tp, 0x06, 0xe4e2); -+ mdio_write(tp, 0x06, 0x34e5); -+ mdio_write(tp, 0x06, 0xe235); -+ mdio_write(tp, 0x06, 0xd07d); -+ mdio_write(tp, 0x06, 0xb0fe); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0x34e1); -+ mdio_write(tp, 0x06, 0xe235); -+ mdio_write(tp, 0x06, 0xf62b); -+ mdio_write(tp, 0x06, 0xe4e2); -+ mdio_write(tp, 0x06, 0x34e5); -+ mdio_write(tp, 0x06, 0xe235); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x34e1); -+ mdio_write(tp, 0x06, 0xe035); -+ mdio_write(tp, 0x06, 0xf626); -+ mdio_write(tp, 0x06, 0xe4e0); -+ mdio_write(tp, 0x06, 0x34e5); -+ mdio_write(tp, 0x06, 0xe035); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0xd6e1); -+ mdio_write(tp, 0x06, 0xe2d7); -+ mdio_write(tp, 0x06, 0xf628); -+ mdio_write(tp, 0x06, 0xe4e2); -+ mdio_write(tp, 0x06, 0xd6e5); -+ mdio_write(tp, 0x06, 0xe2d7); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xae20); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0xa725); -+ mdio_write(tp, 0x06, 0xe50a); -+ mdio_write(tp, 0x06, 0x1de5); -+ mdio_write(tp, 0x06, 0x0a2c); -+ mdio_write(tp, 0x06, 0xe50a); -+ mdio_write(tp, 0x06, 0x6de5); -+ mdio_write(tp, 0x06, 0x0a1d); -+ mdio_write(tp, 0x06, 0xe50a); -+ mdio_write(tp, 0x06, 0x1ce5); -+ mdio_write(tp, 0x06, 0x0a2d); -+ mdio_write(tp, 0x06, 0xa755); -+ mdio_write(tp, 0x06, 0x00e2); -+ mdio_write(tp, 0x06, 0x3488); -+ mdio_write(tp, 0x06, 0xe200); -+ mdio_write(tp, 0x06, 0xcce2); -+ mdio_write(tp, 0x06, 0x0055); -+ mdio_write(tp, 0x06, 0xe020); -+ mdio_write(tp, 0x06, 0x55e2); -+ mdio_write(tp, 0x06, 0xd600); -+ mdio_write(tp, 0x06, 0xe24a); -+ gphy_val = mdio_read(tp, 0x01); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x01, gphy_val); -+ gphy_val = mdio_read(tp, 0x00); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x00, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x17, 0x2179); -+ mdio_write(tp, 0x1f, 0x0001); -+ mdio_write(tp, 0x10, 0xf274); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0042); -+ mdio_write(tp, 0x15, 0x0f00); -+ mdio_write(tp, 0x15, 0x0f00); -+ mdio_write(tp, 0x16, 0x7408); -+ mdio_write(tp, 0x15, 0x0e00); -+ mdio_write(tp, 0x15, 0x0f00); -+ mdio_write(tp, 0x15, 0x0f01); -+ mdio_write(tp, 0x16, 0x4000); -+ mdio_write(tp, 0x15, 0x0e01); -+ mdio_write(tp, 0x15, 0x0f01); -+ mdio_write(tp, 0x15, 0x0f02); -+ mdio_write(tp, 0x16, 0x9400); -+ mdio_write(tp, 0x15, 0x0e02); -+ mdio_write(tp, 0x15, 0x0f02); -+ mdio_write(tp, 0x15, 0x0f03); -+ mdio_write(tp, 0x16, 0x7408); -+ mdio_write(tp, 0x15, 0x0e03); -+ mdio_write(tp, 0x15, 0x0f03); -+ mdio_write(tp, 0x15, 0x0f04); -+ mdio_write(tp, 0x16, 0x4008); -+ mdio_write(tp, 0x15, 0x0e04); -+ mdio_write(tp, 0x15, 0x0f04); -+ mdio_write(tp, 0x15, 0x0f05); -+ mdio_write(tp, 0x16, 0x9400); -+ mdio_write(tp, 0x15, 0x0e05); -+ mdio_write(tp, 0x15, 0x0f05); -+ mdio_write(tp, 0x15, 0x0f06); -+ mdio_write(tp, 0x16, 0x0803); -+ mdio_write(tp, 0x15, 0x0e06); -+ mdio_write(tp, 0x15, 0x0f06); -+ mdio_write(tp, 0x15, 0x0d00); -+ mdio_write(tp, 0x15, 0x0100); -+ mdio_write(tp, 0x1f, 0x0001); -+ mdio_write(tp, 0x10, 0xf074); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x17, 0x2149); -+ -+ mdio_write(tp, 0x1f, 0x0005); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x00); -+ if (gphy_val & BIT_7) -+ break; -+ } -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ gphy_val = mdio_read(tp, 0x17); -+ gphy_val &= ~(BIT_0); -+ if (tp->RequiredSecLanDonglePatch) -+ gphy_val &= ~(BIT_2); -+ mdio_write(tp, 0x17, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ gphy_val = mdio_read(tp, 0x17); -+ gphy_val |= BIT_14; -+ mdio_write(tp, 0x17, gphy_val); -+ mdio_write(tp, 0x1e, 0x0020); -+ gphy_val = mdio_read(tp, 0x1b); -+ gphy_val |= BIT_7; -+ mdio_write(tp, 0x1b, gphy_val); -+ mdio_write(tp, 0x1e, 0x0041); -+ mdio_write(tp, 0x15, 0x0e02); -+ mdio_write(tp, 0x1e, 0x0028); -+ gphy_val = mdio_read(tp, 0x19); -+ gphy_val |= BIT_15; -+ mdio_write(tp, 0x19, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ } else { -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x00, 0x1800); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ mdio_write(tp, 0x17, 0x0117); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1E, 0x002C); -+ mdio_write(tp, 0x1B, 0x5000); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x16, 0x4104); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x1E); -+ gphy_val &= 0x03FF; -+ if (gphy_val==0x000C) -+ break; -+ } -+ mdio_write(tp, 0x1f, 0x0005); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x07); -+ if ((gphy_val & BIT_5) == 0) -+ break; -+ } -+ gphy_val = mdio_read(tp, 0x07); -+ if (gphy_val & BIT_5) { -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x00a1); -+ mdio_write(tp, 0x17, 0x1000); -+ mdio_write(tp, 0x17, 0x0000); -+ mdio_write(tp, 0x17, 0x2000); -+ mdio_write(tp, 0x1e, 0x002f); -+ mdio_write(tp, 0x18, 0x9bfb); -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x07, 0x0000); -+ mdio_write(tp, 0x1f, 0x0000); -+ } -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ gphy_val = mdio_read(tp, 0x00); -+ gphy_val &= ~(BIT_7); -+ mdio_write(tp, 0x00, gphy_val); -+ mdio_write(tp, 0x1f, 0x0002); -+ gphy_val = mdio_read(tp, 0x08); -+ gphy_val &= ~(BIT_7); -+ mdio_write(tp, 0x08, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0307); -+ mdio_write(tp, 0x15, 0x000e); -+ mdio_write(tp, 0x19, 0x000a); -+ mdio_write(tp, 0x15, 0x0010); -+ mdio_write(tp, 0x19, 0x0008); -+ mdio_write(tp, 0x15, 0x0018); -+ mdio_write(tp, 0x19, 0x4801); -+ mdio_write(tp, 0x15, 0x0019); -+ mdio_write(tp, 0x19, 0x6801); -+ mdio_write(tp, 0x15, 0x001a); -+ mdio_write(tp, 0x19, 0x66a1); -+ mdio_write(tp, 0x15, 0x001f); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0020); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0021); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0022); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0023); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0024); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0025); -+ mdio_write(tp, 0x19, 0x64a1); -+ mdio_write(tp, 0x15, 0x0026); -+ mdio_write(tp, 0x19, 0x40ea); -+ mdio_write(tp, 0x15, 0x0027); -+ mdio_write(tp, 0x19, 0x4503); -+ mdio_write(tp, 0x15, 0x0028); -+ mdio_write(tp, 0x19, 0x9f00); -+ mdio_write(tp, 0x15, 0x0029); -+ mdio_write(tp, 0x19, 0xa631); -+ mdio_write(tp, 0x15, 0x002a); -+ mdio_write(tp, 0x19, 0x9717); -+ mdio_write(tp, 0x15, 0x002b); -+ mdio_write(tp, 0x19, 0x302c); -+ mdio_write(tp, 0x15, 0x002c); -+ mdio_write(tp, 0x19, 0x4802); -+ mdio_write(tp, 0x15, 0x002d); -+ mdio_write(tp, 0x19, 0x58da); -+ mdio_write(tp, 0x15, 0x002e); -+ mdio_write(tp, 0x19, 0x400d); -+ mdio_write(tp, 0x15, 0x002f); -+ mdio_write(tp, 0x19, 0x4488); -+ mdio_write(tp, 0x15, 0x0030); -+ mdio_write(tp, 0x19, 0x9e00); -+ mdio_write(tp, 0x15, 0x0031); -+ mdio_write(tp, 0x19, 0x63c8); -+ mdio_write(tp, 0x15, 0x0032); -+ mdio_write(tp, 0x19, 0x6481); -+ mdio_write(tp, 0x15, 0x0033); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0034); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0035); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0036); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0037); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0038); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0039); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x003a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x003b); -+ mdio_write(tp, 0x19, 0x63e8); -+ mdio_write(tp, 0x15, 0x003c); -+ mdio_write(tp, 0x19, 0x7d00); -+ mdio_write(tp, 0x15, 0x003d); -+ mdio_write(tp, 0x19, 0x59d4); -+ mdio_write(tp, 0x15, 0x003e); -+ mdio_write(tp, 0x19, 0x63f8); -+ mdio_write(tp, 0x15, 0x0040); -+ mdio_write(tp, 0x19, 0x64a1); -+ mdio_write(tp, 0x15, 0x0041); -+ mdio_write(tp, 0x19, 0x30de); -+ mdio_write(tp, 0x15, 0x0044); -+ mdio_write(tp, 0x19, 0x480f); -+ mdio_write(tp, 0x15, 0x0045); -+ mdio_write(tp, 0x19, 0x6800); -+ mdio_write(tp, 0x15, 0x0046); -+ mdio_write(tp, 0x19, 0x6680); -+ mdio_write(tp, 0x15, 0x0047); -+ mdio_write(tp, 0x19, 0x7c10); -+ mdio_write(tp, 0x15, 0x0048); -+ mdio_write(tp, 0x19, 0x63c8); -+ mdio_write(tp, 0x15, 0x0049); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004b); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004c); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004d); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004e); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004f); -+ mdio_write(tp, 0x19, 0x40ea); -+ mdio_write(tp, 0x15, 0x0050); -+ mdio_write(tp, 0x19, 0x4503); -+ mdio_write(tp, 0x15, 0x0051); -+ mdio_write(tp, 0x19, 0x58ca); -+ mdio_write(tp, 0x15, 0x0052); -+ mdio_write(tp, 0x19, 0x63c8); -+ mdio_write(tp, 0x15, 0x0053); -+ mdio_write(tp, 0x19, 0x63d8); -+ mdio_write(tp, 0x15, 0x0054); -+ mdio_write(tp, 0x19, 0x66a0); -+ mdio_write(tp, 0x15, 0x0055); -+ mdio_write(tp, 0x19, 0x9f00); -+ mdio_write(tp, 0x15, 0x0056); -+ mdio_write(tp, 0x19, 0x3000); -+ mdio_write(tp, 0x15, 0x00a1); -+ mdio_write(tp, 0x19, 0x3044); -+ mdio_write(tp, 0x15, 0x00ab); -+ mdio_write(tp, 0x19, 0x5820); -+ mdio_write(tp, 0x15, 0x00ac); -+ mdio_write(tp, 0x19, 0x5e04); -+ mdio_write(tp, 0x15, 0x00ad); -+ mdio_write(tp, 0x19, 0xb60c); -+ mdio_write(tp, 0x15, 0x00af); -+ mdio_write(tp, 0x19, 0x000a); -+ mdio_write(tp, 0x15, 0x00b2); -+ mdio_write(tp, 0x19, 0x30b9); -+ mdio_write(tp, 0x15, 0x00b9); -+ mdio_write(tp, 0x19, 0x4408); -+ mdio_write(tp, 0x15, 0x00ba); -+ mdio_write(tp, 0x19, 0x480b); -+ mdio_write(tp, 0x15, 0x00bb); -+ mdio_write(tp, 0x19, 0x5e00); -+ mdio_write(tp, 0x15, 0x00bc); -+ mdio_write(tp, 0x19, 0x405f); -+ mdio_write(tp, 0x15, 0x00bd); -+ mdio_write(tp, 0x19, 0x4448); -+ mdio_write(tp, 0x15, 0x00be); -+ mdio_write(tp, 0x19, 0x4020); -+ mdio_write(tp, 0x15, 0x00bf); -+ mdio_write(tp, 0x19, 0x4468); -+ mdio_write(tp, 0x15, 0x00c0); -+ mdio_write(tp, 0x19, 0x9c02); -+ mdio_write(tp, 0x15, 0x00c1); -+ mdio_write(tp, 0x19, 0x58a0); -+ mdio_write(tp, 0x15, 0x00c2); -+ mdio_write(tp, 0x19, 0xb605); -+ mdio_write(tp, 0x15, 0x00c3); -+ mdio_write(tp, 0x19, 0xc0d3); -+ mdio_write(tp, 0x15, 0x00c4); -+ mdio_write(tp, 0x19, 0x00e6); -+ mdio_write(tp, 0x15, 0x00c5); -+ mdio_write(tp, 0x19, 0xdaec); -+ mdio_write(tp, 0x15, 0x00c6); -+ mdio_write(tp, 0x19, 0x00fa); -+ mdio_write(tp, 0x15, 0x00c7); -+ mdio_write(tp, 0x19, 0x9df9); -+ mdio_write(tp, 0x15, 0x0112); -+ mdio_write(tp, 0x19, 0x6421); -+ mdio_write(tp, 0x15, 0x0113); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x0114); -+ mdio_write(tp, 0x19, 0x63f0); -+ mdio_write(tp, 0x15, 0x0115); -+ mdio_write(tp, 0x19, 0x4003); -+ mdio_write(tp, 0x15, 0x0116); -+ mdio_write(tp, 0x19, 0x4418); -+ mdio_write(tp, 0x15, 0x0117); -+ mdio_write(tp, 0x19, 0x9b00); -+ mdio_write(tp, 0x15, 0x0118); -+ mdio_write(tp, 0x19, 0x6461); -+ mdio_write(tp, 0x15, 0x0119); -+ mdio_write(tp, 0x19, 0x64e1); -+ mdio_write(tp, 0x15, 0x011a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0150); -+ mdio_write(tp, 0x19, 0x7c80); -+ mdio_write(tp, 0x15, 0x0151); -+ mdio_write(tp, 0x19, 0x6461); -+ mdio_write(tp, 0x15, 0x0152); -+ mdio_write(tp, 0x19, 0x4003); -+ mdio_write(tp, 0x15, 0x0153); -+ mdio_write(tp, 0x19, 0x4540); -+ mdio_write(tp, 0x15, 0x0154); -+ mdio_write(tp, 0x19, 0x9f00); -+ mdio_write(tp, 0x15, 0x0155); -+ mdio_write(tp, 0x19, 0x9d00); -+ mdio_write(tp, 0x15, 0x0156); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x0157); -+ mdio_write(tp, 0x19, 0x6421); -+ mdio_write(tp, 0x15, 0x0158); -+ mdio_write(tp, 0x19, 0x7c80); -+ mdio_write(tp, 0x15, 0x0159); -+ mdio_write(tp, 0x19, 0x64a1); -+ mdio_write(tp, 0x15, 0x015a); -+ mdio_write(tp, 0x19, 0x30fe); -+ mdio_write(tp, 0x15, 0x029c); -+ mdio_write(tp, 0x19, 0x0070); -+ mdio_write(tp, 0x15, 0x02b2); -+ mdio_write(tp, 0x19, 0x005a); -+ mdio_write(tp, 0x15, 0x02bd); -+ mdio_write(tp, 0x19, 0xa522); -+ mdio_write(tp, 0x15, 0x02ce); -+ mdio_write(tp, 0x19, 0xb63e); -+ mdio_write(tp, 0x15, 0x02d9); -+ mdio_write(tp, 0x19, 0x32df); -+ mdio_write(tp, 0x15, 0x02df); -+ mdio_write(tp, 0x19, 0x4500); -+ mdio_write(tp, 0x15, 0x02f4); -+ mdio_write(tp, 0x19, 0xb618); -+ mdio_write(tp, 0x15, 0x02fb); -+ mdio_write(tp, 0x19, 0xb900); -+ mdio_write(tp, 0x15, 0x02fc); -+ mdio_write(tp, 0x19, 0x49b5); -+ mdio_write(tp, 0x15, 0x02fd); -+ mdio_write(tp, 0x19, 0x6812); -+ mdio_write(tp, 0x15, 0x02fe); -+ mdio_write(tp, 0x19, 0x66a0); -+ mdio_write(tp, 0x15, 0x02ff); -+ mdio_write(tp, 0x19, 0x9900); -+ mdio_write(tp, 0x15, 0x0300); -+ mdio_write(tp, 0x19, 0x64a0); -+ mdio_write(tp, 0x15, 0x0301); -+ mdio_write(tp, 0x19, 0x3316); -+ mdio_write(tp, 0x15, 0x0308); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x030c); -+ mdio_write(tp, 0x19, 0x3000); -+ mdio_write(tp, 0x15, 0x0312); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0313); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0314); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0315); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0316); -+ mdio_write(tp, 0x19, 0x49b5); -+ mdio_write(tp, 0x15, 0x0317); -+ mdio_write(tp, 0x19, 0x7d00); -+ mdio_write(tp, 0x15, 0x0318); -+ mdio_write(tp, 0x19, 0x4d00); -+ mdio_write(tp, 0x15, 0x0319); -+ mdio_write(tp, 0x19, 0x6810); -+ mdio_write(tp, 0x15, 0x031a); -+ mdio_write(tp, 0x19, 0x6c08); -+ mdio_write(tp, 0x15, 0x031b); -+ mdio_write(tp, 0x19, 0x4925); -+ mdio_write(tp, 0x15, 0x031c); -+ mdio_write(tp, 0x19, 0x403b); -+ mdio_write(tp, 0x15, 0x031d); -+ mdio_write(tp, 0x19, 0xa602); -+ mdio_write(tp, 0x15, 0x031e); -+ mdio_write(tp, 0x19, 0x402f); -+ mdio_write(tp, 0x15, 0x031f); -+ mdio_write(tp, 0x19, 0x4484); -+ mdio_write(tp, 0x15, 0x0320); -+ mdio_write(tp, 0x19, 0x40c8); -+ mdio_write(tp, 0x15, 0x0321); -+ mdio_write(tp, 0x19, 0x44c4); -+ mdio_write(tp, 0x15, 0x0322); -+ mdio_write(tp, 0x19, 0x404f); -+ mdio_write(tp, 0x15, 0x0323); -+ mdio_write(tp, 0x19, 0x44c8); -+ mdio_write(tp, 0x15, 0x0324); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x0325); -+ mdio_write(tp, 0x19, 0x00e7); -+ mdio_write(tp, 0x15, 0x0326); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x0327); -+ mdio_write(tp, 0x19, 0x8203); -+ mdio_write(tp, 0x15, 0x0328); -+ mdio_write(tp, 0x19, 0x4d48); -+ mdio_write(tp, 0x15, 0x0329); -+ mdio_write(tp, 0x19, 0x332b); -+ mdio_write(tp, 0x15, 0x032a); -+ mdio_write(tp, 0x19, 0x4d40); -+ mdio_write(tp, 0x15, 0x032c); -+ mdio_write(tp, 0x19, 0x00f8); -+ mdio_write(tp, 0x15, 0x032d); -+ mdio_write(tp, 0x19, 0x82b2); -+ mdio_write(tp, 0x15, 0x032f); -+ mdio_write(tp, 0x19, 0x00b0); -+ mdio_write(tp, 0x15, 0x0332); -+ mdio_write(tp, 0x19, 0x91f2); -+ mdio_write(tp, 0x15, 0x033f); -+ mdio_write(tp, 0x19, 0xb6cd); -+ mdio_write(tp, 0x15, 0x0340); -+ mdio_write(tp, 0x19, 0x9e01); -+ mdio_write(tp, 0x15, 0x0341); -+ mdio_write(tp, 0x19, 0xd11d); -+ mdio_write(tp, 0x15, 0x0342); -+ mdio_write(tp, 0x19, 0x009d); -+ mdio_write(tp, 0x15, 0x0343); -+ mdio_write(tp, 0x19, 0xbb1c); -+ mdio_write(tp, 0x15, 0x0344); -+ mdio_write(tp, 0x19, 0x8102); -+ mdio_write(tp, 0x15, 0x0345); -+ mdio_write(tp, 0x19, 0x3348); -+ mdio_write(tp, 0x15, 0x0346); -+ mdio_write(tp, 0x19, 0xa231); -+ mdio_write(tp, 0x15, 0x0347); -+ mdio_write(tp, 0x19, 0x335b); -+ mdio_write(tp, 0x15, 0x0348); -+ mdio_write(tp, 0x19, 0x91f7); -+ mdio_write(tp, 0x15, 0x0349); -+ mdio_write(tp, 0x19, 0xc218); -+ mdio_write(tp, 0x15, 0x034a); -+ mdio_write(tp, 0x19, 0x00f5); -+ mdio_write(tp, 0x15, 0x034b); -+ mdio_write(tp, 0x19, 0x335b); -+ mdio_write(tp, 0x15, 0x034c); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x034d); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x034e); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x034f); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0350); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x035b); -+ mdio_write(tp, 0x19, 0xa23c); -+ mdio_write(tp, 0x15, 0x035c); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x035d); -+ mdio_write(tp, 0x19, 0x4c00); -+ mdio_write(tp, 0x15, 0x035e); -+ mdio_write(tp, 0x19, 0x3397); -+ mdio_write(tp, 0x15, 0x0363); -+ mdio_write(tp, 0x19, 0xb6a9); -+ mdio_write(tp, 0x15, 0x0366); -+ mdio_write(tp, 0x19, 0x00f5); -+ mdio_write(tp, 0x15, 0x0382); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x0388); -+ mdio_write(tp, 0x19, 0x0084); -+ mdio_write(tp, 0x15, 0x0389); -+ mdio_write(tp, 0x19, 0xdd17); -+ mdio_write(tp, 0x15, 0x038a); -+ mdio_write(tp, 0x19, 0x000b); -+ mdio_write(tp, 0x15, 0x038b); -+ mdio_write(tp, 0x19, 0xa10a); -+ mdio_write(tp, 0x15, 0x038c); -+ mdio_write(tp, 0x19, 0x337e); -+ mdio_write(tp, 0x15, 0x038d); -+ mdio_write(tp, 0x19, 0x6c0b); -+ mdio_write(tp, 0x15, 0x038e); -+ mdio_write(tp, 0x19, 0xa107); -+ mdio_write(tp, 0x15, 0x038f); -+ mdio_write(tp, 0x19, 0x6c08); -+ mdio_write(tp, 0x15, 0x0390); -+ mdio_write(tp, 0x19, 0xc017); -+ mdio_write(tp, 0x15, 0x0391); -+ mdio_write(tp, 0x19, 0x0004); -+ mdio_write(tp, 0x15, 0x0392); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x0393); -+ mdio_write(tp, 0x19, 0x00f4); -+ mdio_write(tp, 0x15, 0x0397); -+ mdio_write(tp, 0x19, 0x4098); -+ mdio_write(tp, 0x15, 0x0398); -+ mdio_write(tp, 0x19, 0x4408); -+ mdio_write(tp, 0x15, 0x0399); -+ mdio_write(tp, 0x19, 0x55bf); -+ mdio_write(tp, 0x15, 0x039a); -+ mdio_write(tp, 0x19, 0x4bb9); -+ mdio_write(tp, 0x15, 0x039b); -+ mdio_write(tp, 0x19, 0x6810); -+ mdio_write(tp, 0x15, 0x039c); -+ mdio_write(tp, 0x19, 0x4b29); -+ mdio_write(tp, 0x15, 0x039d); -+ mdio_write(tp, 0x19, 0x4041); -+ mdio_write(tp, 0x15, 0x039e); -+ mdio_write(tp, 0x19, 0x442a); -+ mdio_write(tp, 0x15, 0x039f); -+ mdio_write(tp, 0x19, 0x4029); -+ mdio_write(tp, 0x15, 0x03aa); -+ mdio_write(tp, 0x19, 0x33b8); -+ mdio_write(tp, 0x15, 0x03b6); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03b7); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03b8); -+ mdio_write(tp, 0x19, 0x543f); -+ mdio_write(tp, 0x15, 0x03b9); -+ mdio_write(tp, 0x19, 0x499a); -+ mdio_write(tp, 0x15, 0x03ba); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x03bb); -+ mdio_write(tp, 0x19, 0x4c40); -+ mdio_write(tp, 0x15, 0x03bc); -+ mdio_write(tp, 0x19, 0x490a); -+ mdio_write(tp, 0x15, 0x03bd); -+ mdio_write(tp, 0x19, 0x405e); -+ mdio_write(tp, 0x15, 0x03c2); -+ mdio_write(tp, 0x19, 0x9a03); -+ mdio_write(tp, 0x15, 0x03c4); -+ mdio_write(tp, 0x19, 0x0015); -+ mdio_write(tp, 0x15, 0x03c5); -+ mdio_write(tp, 0x19, 0x9e03); -+ mdio_write(tp, 0x15, 0x03c8); -+ mdio_write(tp, 0x19, 0x9cf7); -+ mdio_write(tp, 0x15, 0x03c9); -+ mdio_write(tp, 0x19, 0x7c12); -+ mdio_write(tp, 0x15, 0x03ca); -+ mdio_write(tp, 0x19, 0x4c52); -+ mdio_write(tp, 0x15, 0x03cb); -+ mdio_write(tp, 0x19, 0x4458); -+ mdio_write(tp, 0x15, 0x03cd); -+ mdio_write(tp, 0x19, 0x4c40); -+ mdio_write(tp, 0x15, 0x03ce); -+ mdio_write(tp, 0x19, 0x33bf); -+ mdio_write(tp, 0x15, 0x03cf); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03d0); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03d1); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03d5); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03d6); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03d7); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03d8); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03d9); -+ mdio_write(tp, 0x19, 0x49bb); -+ mdio_write(tp, 0x15, 0x03da); -+ mdio_write(tp, 0x19, 0x4478); -+ mdio_write(tp, 0x15, 0x03db); -+ mdio_write(tp, 0x19, 0x492b); -+ mdio_write(tp, 0x15, 0x03dc); -+ mdio_write(tp, 0x19, 0x7c01); -+ mdio_write(tp, 0x15, 0x03dd); -+ mdio_write(tp, 0x19, 0x4c00); -+ mdio_write(tp, 0x15, 0x03de); -+ mdio_write(tp, 0x19, 0xbd1a); -+ mdio_write(tp, 0x15, 0x03df); -+ mdio_write(tp, 0x19, 0xc428); -+ mdio_write(tp, 0x15, 0x03e0); -+ mdio_write(tp, 0x19, 0x0008); -+ mdio_write(tp, 0x15, 0x03e1); -+ mdio_write(tp, 0x19, 0x9cfd); -+ mdio_write(tp, 0x15, 0x03e2); -+ mdio_write(tp, 0x19, 0x7c12); -+ mdio_write(tp, 0x15, 0x03e3); -+ mdio_write(tp, 0x19, 0x4c52); -+ mdio_write(tp, 0x15, 0x03e4); -+ mdio_write(tp, 0x19, 0x4458); -+ mdio_write(tp, 0x15, 0x03e5); -+ mdio_write(tp, 0x19, 0x7c12); -+ mdio_write(tp, 0x15, 0x03e6); -+ mdio_write(tp, 0x19, 0x4c40); -+ mdio_write(tp, 0x15, 0x03e7); -+ mdio_write(tp, 0x19, 0x33de); -+ mdio_write(tp, 0x15, 0x03e8); -+ mdio_write(tp, 0x19, 0xc218); -+ mdio_write(tp, 0x15, 0x03e9); -+ mdio_write(tp, 0x19, 0x0002); -+ mdio_write(tp, 0x15, 0x03ea); -+ mdio_write(tp, 0x19, 0x32df); -+ mdio_write(tp, 0x15, 0x03eb); -+ mdio_write(tp, 0x19, 0x3316); -+ mdio_write(tp, 0x15, 0x03ec); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03ed); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03ee); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03ef); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03f7); -+ mdio_write(tp, 0x19, 0x330c); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0300); -+ -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ mdio_write(tp, 0x05, 0x8000); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0x48f7); -+ mdio_write(tp, 0x06, 0x00e0); -+ mdio_write(tp, 0x06, 0xfff7); -+ mdio_write(tp, 0x06, 0xa080); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0xf602); -+ mdio_write(tp, 0x06, 0x0200); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0x9002); -+ mdio_write(tp, 0x06, 0x0224); -+ mdio_write(tp, 0x06, 0x0202); -+ mdio_write(tp, 0x06, 0x3402); -+ mdio_write(tp, 0x06, 0x027f); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0xa602); -+ mdio_write(tp, 0x06, 0x80bf); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x88e1); -+ mdio_write(tp, 0x06, 0x8b89); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8a1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8b); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8c1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8e1e); -+ mdio_write(tp, 0x06, 0x01a0); -+ mdio_write(tp, 0x06, 0x00c7); -+ mdio_write(tp, 0x06, 0xaebb); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xe600); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xee03); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xefb8); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xe902); -+ mdio_write(tp, 0x06, 0xee8b); -+ mdio_write(tp, 0x06, 0x8285); -+ mdio_write(tp, 0x06, 0xee8b); -+ mdio_write(tp, 0x06, 0x8520); -+ mdio_write(tp, 0x06, 0xee8b); -+ mdio_write(tp, 0x06, 0x8701); -+ mdio_write(tp, 0x06, 0xd481); -+ mdio_write(tp, 0x06, 0x35e4); -+ mdio_write(tp, 0x06, 0x8b94); -+ mdio_write(tp, 0x06, 0xe58b); -+ mdio_write(tp, 0x06, 0x95bf); -+ mdio_write(tp, 0x06, 0x8b88); -+ mdio_write(tp, 0x06, 0xec00); -+ mdio_write(tp, 0x06, 0x19a9); -+ mdio_write(tp, 0x06, 0x8b90); -+ mdio_write(tp, 0x06, 0xf9ee); -+ mdio_write(tp, 0x06, 0xfff6); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0xfff7); -+ mdio_write(tp, 0x06, 0xffe0); -+ mdio_write(tp, 0x06, 0xe140); -+ mdio_write(tp, 0x06, 0xe1e1); -+ mdio_write(tp, 0x06, 0x41f7); -+ mdio_write(tp, 0x06, 0x2ff6); -+ mdio_write(tp, 0x06, 0x28e4); -+ mdio_write(tp, 0x06, 0xe140); -+ mdio_write(tp, 0x06, 0xe5e1); -+ mdio_write(tp, 0x06, 0x4104); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b89); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x0dee); -+ mdio_write(tp, 0x06, 0x8b89); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x82f4); -+ mdio_write(tp, 0x06, 0x021f); -+ mdio_write(tp, 0x06, 0x4102); -+ mdio_write(tp, 0x06, 0x2812); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x10ee); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x139d); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0xd602); -+ mdio_write(tp, 0x06, 0x1f99); -+ mdio_write(tp, 0x06, 0x0227); -+ mdio_write(tp, 0x06, 0xeafc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2014); -+ mdio_write(tp, 0x06, 0xf620); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x8104); -+ mdio_write(tp, 0x06, 0x021b); -+ mdio_write(tp, 0x06, 0xf402); -+ mdio_write(tp, 0x06, 0x2c9c); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0x7902); -+ mdio_write(tp, 0x06, 0x8443); -+ mdio_write(tp, 0x06, 0xad22); -+ mdio_write(tp, 0x06, 0x11f6); -+ mdio_write(tp, 0x06, 0x22e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x022c); -+ mdio_write(tp, 0x06, 0x4602); -+ mdio_write(tp, 0x06, 0x2ac5); -+ mdio_write(tp, 0x06, 0x0229); -+ mdio_write(tp, 0x06, 0x2002); -+ mdio_write(tp, 0x06, 0x2b91); -+ mdio_write(tp, 0x06, 0xad25); -+ mdio_write(tp, 0x06, 0x11f6); -+ mdio_write(tp, 0x06, 0x25e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x0284); -+ mdio_write(tp, 0x06, 0xe202); -+ mdio_write(tp, 0x06, 0x043a); -+ mdio_write(tp, 0x06, 0x021a); -+ mdio_write(tp, 0x06, 0x5902); -+ mdio_write(tp, 0x06, 0x2bfc); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x00e1); -+ mdio_write(tp, 0x06, 0xe001); -+ mdio_write(tp, 0x06, 0xad27); -+ mdio_write(tp, 0x06, 0x1fd1); -+ mdio_write(tp, 0x06, 0x01bf); -+ mdio_write(tp, 0x06, 0x8638); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x50e0); -+ mdio_write(tp, 0x06, 0xe020); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x21ad); -+ mdio_write(tp, 0x06, 0x200e); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x3802); -+ mdio_write(tp, 0x06, 0x2f50); -+ mdio_write(tp, 0x06, 0xbf3d); -+ mdio_write(tp, 0x06, 0x3902); -+ mdio_write(tp, 0x06, 0x2eb0); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefc); -+ mdio_write(tp, 0x06, 0x0402); -+ mdio_write(tp, 0x06, 0x8591); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0x3c05); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0xfee1); -+ mdio_write(tp, 0x06, 0xe2ff); -+ mdio_write(tp, 0x06, 0xad2d); -+ mdio_write(tp, 0x06, 0x1ae0); -+ mdio_write(tp, 0x06, 0xe14e); -+ mdio_write(tp, 0x06, 0xe1e1); -+ mdio_write(tp, 0x06, 0x4fac); -+ mdio_write(tp, 0x06, 0x2d22); -+ mdio_write(tp, 0x06, 0xf603); -+ mdio_write(tp, 0x06, 0x0203); -+ mdio_write(tp, 0x06, 0x36f7); -+ mdio_write(tp, 0x06, 0x03f7); -+ mdio_write(tp, 0x06, 0x06bf); -+ mdio_write(tp, 0x06, 0x8622); -+ mdio_write(tp, 0x06, 0x022e); -+ mdio_write(tp, 0x06, 0xb0ae); -+ mdio_write(tp, 0x06, 0x11e0); -+ mdio_write(tp, 0x06, 0xe14e); -+ mdio_write(tp, 0x06, 0xe1e1); -+ mdio_write(tp, 0x06, 0x4fad); -+ mdio_write(tp, 0x06, 0x2d08); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x2d02); -+ mdio_write(tp, 0x06, 0x2eb0); -+ mdio_write(tp, 0x06, 0xf606); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x204c); -+ mdio_write(tp, 0x06, 0xd200); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0x0058); -+ mdio_write(tp, 0x06, 0x010c); -+ mdio_write(tp, 0x06, 0x021e); -+ mdio_write(tp, 0x06, 0x20e0); -+ mdio_write(tp, 0x06, 0xe000); -+ mdio_write(tp, 0x06, 0x5810); -+ mdio_write(tp, 0x06, 0x1e20); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x3658); -+ mdio_write(tp, 0x06, 0x031e); -+ mdio_write(tp, 0x06, 0x20e0); -+ mdio_write(tp, 0x06, 0xe022); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x2358); -+ mdio_write(tp, 0x06, 0xe01e); -+ mdio_write(tp, 0x06, 0x20e0); -+ mdio_write(tp, 0x06, 0x8ae6); -+ mdio_write(tp, 0x06, 0x1f02); -+ mdio_write(tp, 0x06, 0x9e22); -+ mdio_write(tp, 0x06, 0xe68a); -+ mdio_write(tp, 0x06, 0xe6ad); -+ mdio_write(tp, 0x06, 0x3214); -+ mdio_write(tp, 0x06, 0xad34); -+ mdio_write(tp, 0x06, 0x11ef); -+ mdio_write(tp, 0x06, 0x0258); -+ mdio_write(tp, 0x06, 0x039e); -+ mdio_write(tp, 0x06, 0x07ad); -+ mdio_write(tp, 0x06, 0x3508); -+ mdio_write(tp, 0x06, 0x5ac0); -+ mdio_write(tp, 0x06, 0x9f04); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xae02); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x3e02); -+ mdio_write(tp, 0x06, 0x2f50); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8f9); -+ mdio_write(tp, 0x06, 0xfae0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xac26); -+ mdio_write(tp, 0x06, 0x0ee0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xac21); -+ mdio_write(tp, 0x06, 0x08e0); -+ mdio_write(tp, 0x06, 0x8b87); -+ mdio_write(tp, 0x06, 0xac24); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x6bee); -+ mdio_write(tp, 0x06, 0xe0ea); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0xe0eb); -+ mdio_write(tp, 0x06, 0x00e2); -+ mdio_write(tp, 0x06, 0xe07c); -+ mdio_write(tp, 0x06, 0xe3e0); -+ mdio_write(tp, 0x06, 0x7da5); -+ mdio_write(tp, 0x06, 0x1111); -+ mdio_write(tp, 0x06, 0x15d2); -+ mdio_write(tp, 0x06, 0x60d6); -+ mdio_write(tp, 0x06, 0x6666); -+ mdio_write(tp, 0x06, 0x0207); -+ mdio_write(tp, 0x06, 0xf9d2); -+ mdio_write(tp, 0x06, 0xa0d6); -+ mdio_write(tp, 0x06, 0xaaaa); -+ mdio_write(tp, 0x06, 0x0207); -+ mdio_write(tp, 0x06, 0xf902); -+ mdio_write(tp, 0x06, 0x825c); -+ mdio_write(tp, 0x06, 0xae44); -+ mdio_write(tp, 0x06, 0xa566); -+ mdio_write(tp, 0x06, 0x6602); -+ mdio_write(tp, 0x06, 0xae38); -+ mdio_write(tp, 0x06, 0xa5aa); -+ mdio_write(tp, 0x06, 0xaa02); -+ mdio_write(tp, 0x06, 0xae32); -+ mdio_write(tp, 0x06, 0xeee0); -+ mdio_write(tp, 0x06, 0xea04); -+ mdio_write(tp, 0x06, 0xeee0); -+ mdio_write(tp, 0x06, 0xeb06); -+ mdio_write(tp, 0x06, 0xe2e0); -+ mdio_write(tp, 0x06, 0x7ce3); -+ mdio_write(tp, 0x06, 0xe07d); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x38e1); -+ mdio_write(tp, 0x06, 0xe039); -+ mdio_write(tp, 0x06, 0xad2e); -+ mdio_write(tp, 0x06, 0x21ad); -+ mdio_write(tp, 0x06, 0x3f13); -+ mdio_write(tp, 0x06, 0xe0e4); -+ mdio_write(tp, 0x06, 0x14e1); -+ mdio_write(tp, 0x06, 0xe415); -+ mdio_write(tp, 0x06, 0x6880); -+ mdio_write(tp, 0x06, 0xe4e4); -+ mdio_write(tp, 0x06, 0x14e5); -+ mdio_write(tp, 0x06, 0xe415); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0x5cae); -+ mdio_write(tp, 0x06, 0x0bac); -+ mdio_write(tp, 0x06, 0x3e02); -+ mdio_write(tp, 0x06, 0xae06); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0x8602); -+ mdio_write(tp, 0x06, 0x82b0); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e1); -+ mdio_write(tp, 0x06, 0x8b2e); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x2605); -+ mdio_write(tp, 0x06, 0x0221); -+ mdio_write(tp, 0x06, 0xf3f7); -+ mdio_write(tp, 0x06, 0x28e0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xad21); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0x22f8); -+ mdio_write(tp, 0x06, 0xf729); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x2405); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0xebf7); -+ mdio_write(tp, 0x06, 0x2ae5); -+ mdio_write(tp, 0x06, 0x8b2e); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xad26); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0x2134); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x2109); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x2eac); -+ mdio_write(tp, 0x06, 0x2003); -+ mdio_write(tp, 0x06, 0x0283); -+ mdio_write(tp, 0x06, 0x52e0); -+ mdio_write(tp, 0x06, 0x8b87); -+ mdio_write(tp, 0x06, 0xad24); -+ mdio_write(tp, 0x06, 0x09e0); -+ mdio_write(tp, 0x06, 0x8b2e); -+ mdio_write(tp, 0x06, 0xac21); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0x8337); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e1); -+ mdio_write(tp, 0x06, 0x8b2e); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x2608); -+ mdio_write(tp, 0x06, 0xe085); -+ mdio_write(tp, 0x06, 0xd2ad); -+ mdio_write(tp, 0x06, 0x2502); -+ mdio_write(tp, 0x06, 0xf628); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x210a); -+ mdio_write(tp, 0x06, 0xe086); -+ mdio_write(tp, 0x06, 0x0af6); -+ mdio_write(tp, 0x06, 0x27a0); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0xf629); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x2408); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xedad); -+ mdio_write(tp, 0x06, 0x2002); -+ mdio_write(tp, 0x06, 0xf62a); -+ mdio_write(tp, 0x06, 0xe58b); -+ mdio_write(tp, 0x06, 0x2ea1); -+ mdio_write(tp, 0x06, 0x0003); -+ mdio_write(tp, 0x06, 0x0221); -+ mdio_write(tp, 0x06, 0x11fc); -+ mdio_write(tp, 0x06, 0x04ee); -+ mdio_write(tp, 0x06, 0x8aed); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8aec); -+ mdio_write(tp, 0x06, 0x0004); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b87); -+ mdio_write(tp, 0x06, 0xad24); -+ mdio_write(tp, 0x06, 0x3ae0); -+ mdio_write(tp, 0x06, 0xe0ea); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0xeb58); -+ mdio_write(tp, 0x06, 0xf8d1); -+ mdio_write(tp, 0x06, 0x01e4); -+ mdio_write(tp, 0x06, 0xe0ea); -+ mdio_write(tp, 0x06, 0xe5e0); -+ mdio_write(tp, 0x06, 0xebe0); -+ mdio_write(tp, 0x06, 0xe07c); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x7d5c); -+ mdio_write(tp, 0x06, 0x00ff); -+ mdio_write(tp, 0x06, 0x3c00); -+ mdio_write(tp, 0x06, 0x1eab); -+ mdio_write(tp, 0x06, 0x1ce0); -+ mdio_write(tp, 0x06, 0xe04c); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x4d58); -+ mdio_write(tp, 0x06, 0xc1e4); -+ mdio_write(tp, 0x06, 0xe04c); -+ mdio_write(tp, 0x06, 0xe5e0); -+ mdio_write(tp, 0x06, 0x4de0); -+ mdio_write(tp, 0x06, 0xe0ee); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0x3ce4); -+ mdio_write(tp, 0x06, 0xe0ee); -+ mdio_write(tp, 0x06, 0xe5e0); -+ mdio_write(tp, 0x06, 0xeffc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x2412); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0xeee1); -+ mdio_write(tp, 0x06, 0xe0ef); -+ mdio_write(tp, 0x06, 0x59c3); -+ mdio_write(tp, 0x06, 0xe4e0); -+ mdio_write(tp, 0x06, 0xeee5); -+ mdio_write(tp, 0x06, 0xe0ef); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xed01); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xac25); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0x8363); -+ mdio_write(tp, 0x06, 0xae03); -+ mdio_write(tp, 0x06, 0x0225); -+ mdio_write(tp, 0x06, 0x16fc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xfae0); -+ mdio_write(tp, 0x06, 0x860a); -+ mdio_write(tp, 0x06, 0xa000); -+ mdio_write(tp, 0x06, 0x19e0); -+ mdio_write(tp, 0x06, 0x860b); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x331b); -+ mdio_write(tp, 0x06, 0x109e); -+ mdio_write(tp, 0x06, 0x04aa); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x06ee); -+ mdio_write(tp, 0x06, 0x860a); -+ mdio_write(tp, 0x06, 0x01ae); -+ mdio_write(tp, 0x06, 0xe602); -+ mdio_write(tp, 0x06, 0x241e); -+ mdio_write(tp, 0x06, 0xae14); -+ mdio_write(tp, 0x06, 0xa001); -+ mdio_write(tp, 0x06, 0x1402); -+ mdio_write(tp, 0x06, 0x2426); -+ mdio_write(tp, 0x06, 0xbf26); -+ mdio_write(tp, 0x06, 0x6d02); -+ mdio_write(tp, 0x06, 0x2eb0); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0b00); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0a02); -+ mdio_write(tp, 0x06, 0xaf84); -+ mdio_write(tp, 0x06, 0x3ca0); -+ mdio_write(tp, 0x06, 0x0252); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0400); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0500); -+ mdio_write(tp, 0x06, 0xe086); -+ mdio_write(tp, 0x06, 0x0be1); -+ mdio_write(tp, 0x06, 0x8b32); -+ mdio_write(tp, 0x06, 0x1b10); -+ mdio_write(tp, 0x06, 0x9e04); -+ mdio_write(tp, 0x06, 0xaa02); -+ mdio_write(tp, 0x06, 0xaecb); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0b00); -+ mdio_write(tp, 0x06, 0x0224); -+ mdio_write(tp, 0x06, 0x3ae2); -+ mdio_write(tp, 0x06, 0x8604); -+ mdio_write(tp, 0x06, 0xe386); -+ mdio_write(tp, 0x06, 0x05ef); -+ mdio_write(tp, 0x06, 0x65e2); -+ mdio_write(tp, 0x06, 0x8606); -+ mdio_write(tp, 0x06, 0xe386); -+ mdio_write(tp, 0x06, 0x071b); -+ mdio_write(tp, 0x06, 0x56aa); -+ mdio_write(tp, 0x06, 0x0eef); -+ mdio_write(tp, 0x06, 0x56e6); -+ mdio_write(tp, 0x06, 0x8606); -+ mdio_write(tp, 0x06, 0xe786); -+ mdio_write(tp, 0x06, 0x07e2); -+ mdio_write(tp, 0x06, 0x8609); -+ mdio_write(tp, 0x06, 0xe686); -+ mdio_write(tp, 0x06, 0x08e0); -+ mdio_write(tp, 0x06, 0x8609); -+ mdio_write(tp, 0x06, 0xa000); -+ mdio_write(tp, 0x06, 0x07ee); -+ mdio_write(tp, 0x06, 0x860a); -+ mdio_write(tp, 0x06, 0x03af); -+ mdio_write(tp, 0x06, 0x8369); -+ mdio_write(tp, 0x06, 0x0224); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x2426); -+ mdio_write(tp, 0x06, 0xae48); -+ mdio_write(tp, 0x06, 0xa003); -+ mdio_write(tp, 0x06, 0x21e0); -+ mdio_write(tp, 0x06, 0x8608); -+ mdio_write(tp, 0x06, 0xe186); -+ mdio_write(tp, 0x06, 0x091b); -+ mdio_write(tp, 0x06, 0x019e); -+ mdio_write(tp, 0x06, 0x0caa); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0x249d); -+ mdio_write(tp, 0x06, 0xaee7); -+ mdio_write(tp, 0x06, 0x0224); -+ mdio_write(tp, 0x06, 0x8eae); -+ mdio_write(tp, 0x06, 0xe2ee); -+ mdio_write(tp, 0x06, 0x860a); -+ mdio_write(tp, 0x06, 0x04ee); -+ mdio_write(tp, 0x06, 0x860b); -+ mdio_write(tp, 0x06, 0x00af); -+ mdio_write(tp, 0x06, 0x8369); -+ mdio_write(tp, 0x06, 0xa004); -+ mdio_write(tp, 0x06, 0x15e0); -+ mdio_write(tp, 0x06, 0x860b); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x341b); -+ mdio_write(tp, 0x06, 0x109e); -+ mdio_write(tp, 0x06, 0x05aa); -+ mdio_write(tp, 0x06, 0x03af); -+ mdio_write(tp, 0x06, 0x8383); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0a05); -+ mdio_write(tp, 0x06, 0xae0c); -+ mdio_write(tp, 0x06, 0xa005); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x0702); -+ mdio_write(tp, 0x06, 0x2309); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0a00); -+ mdio_write(tp, 0x06, 0xfeef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfdfc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xfbe0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xad25); -+ mdio_write(tp, 0x06, 0x22e0); -+ mdio_write(tp, 0x06, 0xe022); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x23e2); -+ mdio_write(tp, 0x06, 0xe036); -+ mdio_write(tp, 0x06, 0xe3e0); -+ mdio_write(tp, 0x06, 0x375a); -+ mdio_write(tp, 0x06, 0xc40d); -+ mdio_write(tp, 0x06, 0x0158); -+ mdio_write(tp, 0x06, 0x021e); -+ mdio_write(tp, 0x06, 0x20e3); -+ mdio_write(tp, 0x06, 0x8ae7); -+ mdio_write(tp, 0x06, 0xac31); -+ mdio_write(tp, 0x06, 0x60ac); -+ mdio_write(tp, 0x06, 0x3a08); -+ mdio_write(tp, 0x06, 0xac3e); -+ mdio_write(tp, 0x06, 0x26ae); -+ mdio_write(tp, 0x06, 0x67af); -+ mdio_write(tp, 0x06, 0x84db); -+ mdio_write(tp, 0x06, 0xad37); -+ mdio_write(tp, 0x06, 0x61e0); -+ mdio_write(tp, 0x06, 0x8ae8); -+ mdio_write(tp, 0x06, 0x10e4); -+ mdio_write(tp, 0x06, 0x8ae8); -+ mdio_write(tp, 0x06, 0xe18a); -+ mdio_write(tp, 0x06, 0xe91b); -+ mdio_write(tp, 0x06, 0x109e); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x51d1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x863b); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x50ee); -+ mdio_write(tp, 0x06, 0x8ae8); -+ mdio_write(tp, 0x06, 0x00ae); -+ mdio_write(tp, 0x06, 0x43ad); -+ mdio_write(tp, 0x06, 0x3627); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xeee1); -+ mdio_write(tp, 0x06, 0x8aef); -+ mdio_write(tp, 0x06, 0xef74); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xeae1); -+ mdio_write(tp, 0x06, 0x8aeb); -+ mdio_write(tp, 0x06, 0x1b74); -+ mdio_write(tp, 0x06, 0x9e2e); -+ mdio_write(tp, 0x06, 0x14e4); -+ mdio_write(tp, 0x06, 0x8aea); -+ mdio_write(tp, 0x06, 0xe58a); -+ mdio_write(tp, 0x06, 0xebef); -+ mdio_write(tp, 0x06, 0x74e0); -+ mdio_write(tp, 0x06, 0x8aee); -+ mdio_write(tp, 0x06, 0xe18a); -+ mdio_write(tp, 0x06, 0xef1b); -+ mdio_write(tp, 0x06, 0x479e); -+ mdio_write(tp, 0x06, 0x0fae); -+ mdio_write(tp, 0x06, 0x19ee); -+ mdio_write(tp, 0x06, 0x8aea); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8aeb); -+ mdio_write(tp, 0x06, 0x00ae); -+ mdio_write(tp, 0x06, 0x0fac); -+ mdio_write(tp, 0x06, 0x390c); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x3b02); -+ mdio_write(tp, 0x06, 0x2f50); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xe800); -+ mdio_write(tp, 0x06, 0xe68a); -+ mdio_write(tp, 0x06, 0xe7ff); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8f9); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x69e0); -+ mdio_write(tp, 0x06, 0xe022); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x2358); -+ mdio_write(tp, 0x06, 0xc4e1); -+ mdio_write(tp, 0x06, 0x8b6e); -+ mdio_write(tp, 0x06, 0x1f10); -+ mdio_write(tp, 0x06, 0x9e24); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x6ead); -+ mdio_write(tp, 0x06, 0x2218); -+ mdio_write(tp, 0x06, 0xac27); -+ mdio_write(tp, 0x06, 0x0dac); -+ mdio_write(tp, 0x06, 0x2605); -+ mdio_write(tp, 0x06, 0x0203); -+ mdio_write(tp, 0x06, 0x8fae); -+ mdio_write(tp, 0x06, 0x1302); -+ mdio_write(tp, 0x06, 0x03c8); -+ mdio_write(tp, 0x06, 0xae0e); -+ mdio_write(tp, 0x06, 0x0203); -+ mdio_write(tp, 0x06, 0xe102); -+ mdio_write(tp, 0x06, 0x8520); -+ mdio_write(tp, 0x06, 0xae06); -+ mdio_write(tp, 0x06, 0x0203); -+ mdio_write(tp, 0x06, 0x8f02); -+ mdio_write(tp, 0x06, 0x8566); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x82ad); -+ mdio_write(tp, 0x06, 0x2737); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x4402); -+ mdio_write(tp, 0x06, 0x2f23); -+ mdio_write(tp, 0x06, 0xac28); -+ mdio_write(tp, 0x06, 0x2ed1); -+ mdio_write(tp, 0x06, 0x01bf); -+ mdio_write(tp, 0x06, 0x8647); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x50bf); -+ mdio_write(tp, 0x06, 0x8641); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x23e5); -+ mdio_write(tp, 0x06, 0x8af0); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x22e1); -+ mdio_write(tp, 0x06, 0xe023); -+ mdio_write(tp, 0x06, 0xac2e); -+ mdio_write(tp, 0x06, 0x04d1); -+ mdio_write(tp, 0x06, 0x01ae); -+ mdio_write(tp, 0x06, 0x02d1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x8641); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x50d1); -+ mdio_write(tp, 0x06, 0x01bf); -+ mdio_write(tp, 0x06, 0x8644); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x50ef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x4702); -+ mdio_write(tp, 0x06, 0x2f23); -+ mdio_write(tp, 0x06, 0xad28); -+ mdio_write(tp, 0x06, 0x19d1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x8644); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x50e1); -+ mdio_write(tp, 0x06, 0x8af0); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x4102); -+ mdio_write(tp, 0x06, 0x2f50); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x4702); -+ mdio_write(tp, 0x06, 0x2f50); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0xfee1); -+ mdio_write(tp, 0x06, 0xe2ff); -+ mdio_write(tp, 0x06, 0xad2e); -+ mdio_write(tp, 0x06, 0x63e0); -+ mdio_write(tp, 0x06, 0xe038); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x39ad); -+ mdio_write(tp, 0x06, 0x2f10); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x34e1); -+ mdio_write(tp, 0x06, 0xe035); -+ mdio_write(tp, 0x06, 0xf726); -+ mdio_write(tp, 0x06, 0xe4e0); -+ mdio_write(tp, 0x06, 0x34e5); -+ mdio_write(tp, 0x06, 0xe035); -+ mdio_write(tp, 0x06, 0xae0e); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0xd6e1); -+ mdio_write(tp, 0x06, 0xe2d7); -+ mdio_write(tp, 0x06, 0xf728); -+ mdio_write(tp, 0x06, 0xe4e2); -+ mdio_write(tp, 0x06, 0xd6e5); -+ mdio_write(tp, 0x06, 0xe2d7); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0x34e1); -+ mdio_write(tp, 0x06, 0xe235); -+ mdio_write(tp, 0x06, 0xf72b); -+ mdio_write(tp, 0x06, 0xe4e2); -+ mdio_write(tp, 0x06, 0x34e5); -+ mdio_write(tp, 0x06, 0xe235); -+ mdio_write(tp, 0x06, 0xd07d); -+ mdio_write(tp, 0x06, 0xb0fe); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0x34e1); -+ mdio_write(tp, 0x06, 0xe235); -+ mdio_write(tp, 0x06, 0xf62b); -+ mdio_write(tp, 0x06, 0xe4e2); -+ mdio_write(tp, 0x06, 0x34e5); -+ mdio_write(tp, 0x06, 0xe235); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x34e1); -+ mdio_write(tp, 0x06, 0xe035); -+ mdio_write(tp, 0x06, 0xf626); -+ mdio_write(tp, 0x06, 0xe4e0); -+ mdio_write(tp, 0x06, 0x34e5); -+ mdio_write(tp, 0x06, 0xe035); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0xd6e1); -+ mdio_write(tp, 0x06, 0xe2d7); -+ mdio_write(tp, 0x06, 0xf628); -+ mdio_write(tp, 0x06, 0xe4e2); -+ mdio_write(tp, 0x06, 0xd6e5); -+ mdio_write(tp, 0x06, 0xe2d7); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xae20); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0xa725); -+ mdio_write(tp, 0x06, 0xe50a); -+ mdio_write(tp, 0x06, 0x1de5); -+ mdio_write(tp, 0x06, 0x0a2c); -+ mdio_write(tp, 0x06, 0xe50a); -+ mdio_write(tp, 0x06, 0x6de5); -+ mdio_write(tp, 0x06, 0x0a1d); -+ mdio_write(tp, 0x06, 0xe50a); -+ mdio_write(tp, 0x06, 0x1ce5); -+ mdio_write(tp, 0x06, 0x0a2d); -+ mdio_write(tp, 0x06, 0xa755); -+ mdio_write(tp, 0x06, 0x00e2); -+ mdio_write(tp, 0x06, 0x3488); -+ mdio_write(tp, 0x06, 0xe200); -+ mdio_write(tp, 0x06, 0xcce2); -+ mdio_write(tp, 0x06, 0x0055); -+ mdio_write(tp, 0x06, 0xe020); -+ mdio_write(tp, 0x06, 0x55e2); -+ mdio_write(tp, 0x06, 0xd600); -+ mdio_write(tp, 0x06, 0xe24a); -+ gphy_val = mdio_read(tp, 0x01); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x01, gphy_val); -+ gphy_val = mdio_read(tp, 0x00); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x00, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1f, 0x0005); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x00); -+ if (gphy_val & BIT_7) -+ break; -+ } -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ gphy_val = mdio_read(tp, 0x17); -+ gphy_val &= ~(BIT_0); -+ if (tp->RequiredSecLanDonglePatch) -+ gphy_val &= ~(BIT_2); -+ mdio_write(tp, 0x17, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ } -+} -+ -+static void -+rtl8168_set_phy_mcu_8168evl_1(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned int gphy_val,i; -+ -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x00, 0x1800); -+ gphy_val = mdio_read(tp, 0x15); -+ gphy_val &= ~(BIT_12); -+ mdio_write(tp, 0x15, gphy_val); -+ mdelay(20); -+ mdio_write(tp, 0x1f, 0x0004); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ gphy_val = mdio_read(tp, 0x17); -+ if ((gphy_val & BIT_11) == 0x0000) { -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x17, gphy_val); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x17); -+ if (gphy_val & BIT_11) -+ break; -+ } -+ } -+ gphy_val = mdio_read(tp, 0x17); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x17, gphy_val); -+ mdio_write(tp, 0x1f, 0x0004); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1E, 0x002C); -+ mdio_write(tp, 0x1B, 0x5000); -+ mdio_write(tp, 0x1E, 0x002d); -+ mdio_write(tp, 0x19, 0x0004); -+ mdio_write(tp, 0x1f, 0x0002); -+ mdio_write(tp, 0x1f, 0x0000); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x1E); -+ if ((gphy_val & 0x03FF) == 0x0014) -+ break; -+ } -+ mdio_write(tp, 0x1f, 0x0005); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x07); -+ if ((gphy_val & BIT_5) == 0) -+ break; -+ } -+ gphy_val = mdio_read(tp, 0x07); -+ if (gphy_val & BIT_5) { -+ mdio_write(tp, 0x1f, 0x0004); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x00a1); -+ mdio_write(tp, 0x17, 0x1000); -+ mdio_write(tp, 0x17, 0x0000); -+ mdio_write(tp, 0x17, 0x2000); -+ mdio_write(tp, 0x1e, 0x002f); -+ mdio_write(tp, 0x18, 0x9bfb); -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x07, 0x0000); -+ mdio_write(tp, 0x1f, 0x0002); -+ mdio_write(tp, 0x1f, 0x0000); -+ } -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ gphy_val = mdio_read(tp, 0x00); -+ gphy_val &= ~(BIT_7); -+ mdio_write(tp, 0x00, gphy_val); -+ mdio_write(tp, 0x1f, 0x0004); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0307); -+ mdio_write(tp, 0x15, 0x0000); -+ mdio_write(tp, 0x19, 0x407d); -+ mdio_write(tp, 0x15, 0x0001); -+ mdio_write(tp, 0x19, 0x440f); -+ mdio_write(tp, 0x15, 0x0002); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x0003); -+ mdio_write(tp, 0x19, 0x6c03); -+ mdio_write(tp, 0x15, 0x0004); -+ mdio_write(tp, 0x19, 0xc4d5); -+ mdio_write(tp, 0x15, 0x0005); -+ mdio_write(tp, 0x19, 0x00ff); -+ mdio_write(tp, 0x15, 0x0006); -+ mdio_write(tp, 0x19, 0x74f0); -+ mdio_write(tp, 0x15, 0x0007); -+ mdio_write(tp, 0x19, 0x4880); -+ mdio_write(tp, 0x15, 0x0008); -+ mdio_write(tp, 0x19, 0x4c00); -+ mdio_write(tp, 0x15, 0x0009); -+ mdio_write(tp, 0x19, 0x4800); -+ mdio_write(tp, 0x15, 0x000a); -+ mdio_write(tp, 0x19, 0x5000); -+ mdio_write(tp, 0x15, 0x000b); -+ mdio_write(tp, 0x19, 0x4400); -+ mdio_write(tp, 0x15, 0x000c); -+ mdio_write(tp, 0x19, 0x7801); -+ mdio_write(tp, 0x15, 0x000d); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x15, 0x000e); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x000f); -+ mdio_write(tp, 0x19, 0x7010); -+ mdio_write(tp, 0x15, 0x0010); -+ mdio_write(tp, 0x19, 0x6804); -+ mdio_write(tp, 0x15, 0x0011); -+ mdio_write(tp, 0x19, 0x64a0); -+ mdio_write(tp, 0x15, 0x0012); -+ mdio_write(tp, 0x19, 0x63da); -+ mdio_write(tp, 0x15, 0x0013); -+ mdio_write(tp, 0x19, 0x63d8); -+ mdio_write(tp, 0x15, 0x0014); -+ mdio_write(tp, 0x19, 0x6f05); -+ mdio_write(tp, 0x15, 0x0015); -+ mdio_write(tp, 0x19, 0x5420); -+ mdio_write(tp, 0x15, 0x0016); -+ mdio_write(tp, 0x19, 0x58ce); -+ mdio_write(tp, 0x15, 0x0017); -+ mdio_write(tp, 0x19, 0x5cf3); -+ mdio_write(tp, 0x15, 0x0018); -+ mdio_write(tp, 0x19, 0xb600); -+ mdio_write(tp, 0x15, 0x0019); -+ mdio_write(tp, 0x19, 0xc659); -+ mdio_write(tp, 0x15, 0x001a); -+ mdio_write(tp, 0x19, 0x0018); -+ mdio_write(tp, 0x15, 0x001b); -+ mdio_write(tp, 0x19, 0xc403); -+ mdio_write(tp, 0x15, 0x001c); -+ mdio_write(tp, 0x19, 0x0016); -+ mdio_write(tp, 0x15, 0x001d); -+ mdio_write(tp, 0x19, 0xaa05); -+ mdio_write(tp, 0x15, 0x001e); -+ mdio_write(tp, 0x19, 0xc503); -+ mdio_write(tp, 0x15, 0x001f); -+ mdio_write(tp, 0x19, 0x0003); -+ mdio_write(tp, 0x15, 0x0020); -+ mdio_write(tp, 0x19, 0x89f8); -+ mdio_write(tp, 0x15, 0x0021); -+ mdio_write(tp, 0x19, 0x32ae); -+ mdio_write(tp, 0x15, 0x0022); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x0023); -+ mdio_write(tp, 0x19, 0x6c03); -+ mdio_write(tp, 0x15, 0x0024); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x0025); -+ mdio_write(tp, 0x19, 0x6801); -+ mdio_write(tp, 0x15, 0x0026); -+ mdio_write(tp, 0x19, 0x66a0); -+ mdio_write(tp, 0x15, 0x0027); -+ mdio_write(tp, 0x19, 0xa300); -+ mdio_write(tp, 0x15, 0x0028); -+ mdio_write(tp, 0x19, 0x64a0); -+ mdio_write(tp, 0x15, 0x0029); -+ mdio_write(tp, 0x19, 0x76f0); -+ mdio_write(tp, 0x15, 0x002a); -+ mdio_write(tp, 0x19, 0x7670); -+ mdio_write(tp, 0x15, 0x002b); -+ mdio_write(tp, 0x19, 0x7630); -+ mdio_write(tp, 0x15, 0x002c); -+ mdio_write(tp, 0x19, 0x31a6); -+ mdio_write(tp, 0x15, 0x002d); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x002e); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x002f); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0030); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0031); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0032); -+ mdio_write(tp, 0x19, 0x4801); -+ mdio_write(tp, 0x15, 0x0033); -+ mdio_write(tp, 0x19, 0x6803); -+ mdio_write(tp, 0x15, 0x0034); -+ mdio_write(tp, 0x19, 0x66a1); -+ mdio_write(tp, 0x15, 0x0035); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x0036); -+ mdio_write(tp, 0x19, 0x6c03); -+ mdio_write(tp, 0x15, 0x0037); -+ mdio_write(tp, 0x19, 0xa300); -+ mdio_write(tp, 0x15, 0x0038); -+ mdio_write(tp, 0x19, 0x64a1); -+ mdio_write(tp, 0x15, 0x0039); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x003a); -+ mdio_write(tp, 0x19, 0x74f8); -+ mdio_write(tp, 0x15, 0x003b); -+ mdio_write(tp, 0x19, 0x63d0); -+ mdio_write(tp, 0x15, 0x003c); -+ mdio_write(tp, 0x19, 0x7ff0); -+ mdio_write(tp, 0x15, 0x003d); -+ mdio_write(tp, 0x19, 0x77f0); -+ mdio_write(tp, 0x15, 0x003e); -+ mdio_write(tp, 0x19, 0x7ff0); -+ mdio_write(tp, 0x15, 0x003f); -+ mdio_write(tp, 0x19, 0x7750); -+ mdio_write(tp, 0x15, 0x0040); -+ mdio_write(tp, 0x19, 0x63d8); -+ mdio_write(tp, 0x15, 0x0041); -+ mdio_write(tp, 0x19, 0x7cf0); -+ mdio_write(tp, 0x15, 0x0042); -+ mdio_write(tp, 0x19, 0x7708); -+ mdio_write(tp, 0x15, 0x0043); -+ mdio_write(tp, 0x19, 0xa654); -+ mdio_write(tp, 0x15, 0x0044); -+ mdio_write(tp, 0x19, 0x304a); -+ mdio_write(tp, 0x15, 0x0045); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0046); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0047); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0048); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0049); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x004a); -+ mdio_write(tp, 0x19, 0x4802); -+ mdio_write(tp, 0x15, 0x004b); -+ mdio_write(tp, 0x19, 0x4003); -+ mdio_write(tp, 0x15, 0x004c); -+ mdio_write(tp, 0x19, 0x4440); -+ mdio_write(tp, 0x15, 0x004d); -+ mdio_write(tp, 0x19, 0x63c8); -+ mdio_write(tp, 0x15, 0x004e); -+ mdio_write(tp, 0x19, 0x6481); -+ mdio_write(tp, 0x15, 0x004f); -+ mdio_write(tp, 0x19, 0x9d00); -+ mdio_write(tp, 0x15, 0x0050); -+ mdio_write(tp, 0x19, 0x63e8); -+ mdio_write(tp, 0x15, 0x0051); -+ mdio_write(tp, 0x19, 0x7d00); -+ mdio_write(tp, 0x15, 0x0052); -+ mdio_write(tp, 0x19, 0x5900); -+ mdio_write(tp, 0x15, 0x0053); -+ mdio_write(tp, 0x19, 0x63f8); -+ mdio_write(tp, 0x15, 0x0054); -+ mdio_write(tp, 0x19, 0x64a1); -+ mdio_write(tp, 0x15, 0x0055); -+ mdio_write(tp, 0x19, 0x3116); -+ mdio_write(tp, 0x15, 0x0056); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0057); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0058); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0059); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x005a); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x005b); -+ mdio_write(tp, 0x19, 0x6c03); -+ mdio_write(tp, 0x15, 0x005c); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x005d); -+ mdio_write(tp, 0x19, 0x6000); -+ mdio_write(tp, 0x15, 0x005e); -+ mdio_write(tp, 0x19, 0x59ce); -+ mdio_write(tp, 0x15, 0x005f); -+ mdio_write(tp, 0x19, 0x4400); -+ mdio_write(tp, 0x15, 0x0060); -+ mdio_write(tp, 0x19, 0x7d00); -+ mdio_write(tp, 0x15, 0x0061); -+ mdio_write(tp, 0x19, 0x72b0); -+ mdio_write(tp, 0x15, 0x0062); -+ mdio_write(tp, 0x19, 0x400e); -+ mdio_write(tp, 0x15, 0x0063); -+ mdio_write(tp, 0x19, 0x4440); -+ mdio_write(tp, 0x15, 0x0064); -+ mdio_write(tp, 0x19, 0x9d00); -+ mdio_write(tp, 0x15, 0x0065); -+ mdio_write(tp, 0x19, 0x7f00); -+ mdio_write(tp, 0x15, 0x0066); -+ mdio_write(tp, 0x19, 0x70b0); -+ mdio_write(tp, 0x15, 0x0067); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x0068); -+ mdio_write(tp, 0x19, 0x6008); -+ mdio_write(tp, 0x15, 0x0069); -+ mdio_write(tp, 0x19, 0x7cf0); -+ mdio_write(tp, 0x15, 0x006a); -+ mdio_write(tp, 0x19, 0x7750); -+ mdio_write(tp, 0x15, 0x006b); -+ mdio_write(tp, 0x19, 0x4007); -+ mdio_write(tp, 0x15, 0x006c); -+ mdio_write(tp, 0x19, 0x4500); -+ mdio_write(tp, 0x15, 0x006d); -+ mdio_write(tp, 0x19, 0x4023); -+ mdio_write(tp, 0x15, 0x006e); -+ mdio_write(tp, 0x19, 0x4580); -+ mdio_write(tp, 0x15, 0x006f); -+ mdio_write(tp, 0x19, 0x9f00); -+ mdio_write(tp, 0x15, 0x0070); -+ mdio_write(tp, 0x19, 0xcd78); -+ mdio_write(tp, 0x15, 0x0071); -+ mdio_write(tp, 0x19, 0x0003); -+ mdio_write(tp, 0x15, 0x0072); -+ mdio_write(tp, 0x19, 0xbe02); -+ mdio_write(tp, 0x15, 0x0073); -+ mdio_write(tp, 0x19, 0x3070); -+ mdio_write(tp, 0x15, 0x0074); -+ mdio_write(tp, 0x19, 0x7cf0); -+ mdio_write(tp, 0x15, 0x0075); -+ mdio_write(tp, 0x19, 0x77f0); -+ mdio_write(tp, 0x15, 0x0076); -+ mdio_write(tp, 0x19, 0x4400); -+ mdio_write(tp, 0x15, 0x0077); -+ mdio_write(tp, 0x19, 0x4007); -+ mdio_write(tp, 0x15, 0x0078); -+ mdio_write(tp, 0x19, 0x4500); -+ mdio_write(tp, 0x15, 0x0079); -+ mdio_write(tp, 0x19, 0x4023); -+ mdio_write(tp, 0x15, 0x007a); -+ mdio_write(tp, 0x19, 0x4580); -+ mdio_write(tp, 0x15, 0x007b); -+ mdio_write(tp, 0x19, 0x9f00); -+ mdio_write(tp, 0x15, 0x007c); -+ mdio_write(tp, 0x19, 0xce80); -+ mdio_write(tp, 0x15, 0x007d); -+ mdio_write(tp, 0x19, 0x0004); -+ mdio_write(tp, 0x15, 0x007e); -+ mdio_write(tp, 0x19, 0xce80); -+ mdio_write(tp, 0x15, 0x007f); -+ mdio_write(tp, 0x19, 0x0002); -+ mdio_write(tp, 0x15, 0x0080); -+ mdio_write(tp, 0x19, 0x307c); -+ mdio_write(tp, 0x15, 0x0081); -+ mdio_write(tp, 0x19, 0x4400); -+ mdio_write(tp, 0x15, 0x0082); -+ mdio_write(tp, 0x19, 0x480f); -+ mdio_write(tp, 0x15, 0x0083); -+ mdio_write(tp, 0x19, 0x6802); -+ mdio_write(tp, 0x15, 0x0084); -+ mdio_write(tp, 0x19, 0x6680); -+ mdio_write(tp, 0x15, 0x0085); -+ mdio_write(tp, 0x19, 0x7c10); -+ mdio_write(tp, 0x15, 0x0086); -+ mdio_write(tp, 0x19, 0x6010); -+ mdio_write(tp, 0x15, 0x0087); -+ mdio_write(tp, 0x19, 0x400a); -+ mdio_write(tp, 0x15, 0x0088); -+ mdio_write(tp, 0x19, 0x4580); -+ mdio_write(tp, 0x15, 0x0089); -+ mdio_write(tp, 0x19, 0x9e00); -+ mdio_write(tp, 0x15, 0x008a); -+ mdio_write(tp, 0x19, 0x7d00); -+ mdio_write(tp, 0x15, 0x008b); -+ mdio_write(tp, 0x19, 0x5800); -+ mdio_write(tp, 0x15, 0x008c); -+ mdio_write(tp, 0x19, 0x63c8); -+ mdio_write(tp, 0x15, 0x008d); -+ mdio_write(tp, 0x19, 0x63d8); -+ mdio_write(tp, 0x15, 0x008e); -+ mdio_write(tp, 0x19, 0x66a0); -+ mdio_write(tp, 0x15, 0x008f); -+ mdio_write(tp, 0x19, 0x8300); -+ mdio_write(tp, 0x15, 0x0090); -+ mdio_write(tp, 0x19, 0x7ff0); -+ mdio_write(tp, 0x15, 0x0091); -+ mdio_write(tp, 0x19, 0x74f0); -+ mdio_write(tp, 0x15, 0x0092); -+ mdio_write(tp, 0x19, 0x3006); -+ mdio_write(tp, 0x15, 0x0093); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0094); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0095); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0096); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0097); -+ mdio_write(tp, 0x19, 0x4803); -+ mdio_write(tp, 0x15, 0x0098); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x0099); -+ mdio_write(tp, 0x19, 0x6c03); -+ mdio_write(tp, 0x15, 0x009a); -+ mdio_write(tp, 0x19, 0xa203); -+ mdio_write(tp, 0x15, 0x009b); -+ mdio_write(tp, 0x19, 0x64b1); -+ mdio_write(tp, 0x15, 0x009c); -+ mdio_write(tp, 0x19, 0x309e); -+ mdio_write(tp, 0x15, 0x009d); -+ mdio_write(tp, 0x19, 0x64b3); -+ mdio_write(tp, 0x15, 0x009e); -+ mdio_write(tp, 0x19, 0x4030); -+ mdio_write(tp, 0x15, 0x009f); -+ mdio_write(tp, 0x19, 0x440e); -+ mdio_write(tp, 0x15, 0x00a0); -+ mdio_write(tp, 0x19, 0x4020); -+ mdio_write(tp, 0x15, 0x00a1); -+ mdio_write(tp, 0x19, 0x4419); -+ mdio_write(tp, 0x15, 0x00a2); -+ mdio_write(tp, 0x19, 0x7801); -+ mdio_write(tp, 0x15, 0x00a3); -+ mdio_write(tp, 0x19, 0xc520); -+ mdio_write(tp, 0x15, 0x00a4); -+ mdio_write(tp, 0x19, 0x000b); -+ mdio_write(tp, 0x15, 0x00a5); -+ mdio_write(tp, 0x19, 0x4020); -+ mdio_write(tp, 0x15, 0x00a6); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x00a7); -+ mdio_write(tp, 0x19, 0x58a4); -+ mdio_write(tp, 0x15, 0x00a8); -+ mdio_write(tp, 0x19, 0x63da); -+ mdio_write(tp, 0x15, 0x00a9); -+ mdio_write(tp, 0x19, 0x5cb0); -+ mdio_write(tp, 0x15, 0x00aa); -+ mdio_write(tp, 0x19, 0x7d00); -+ mdio_write(tp, 0x15, 0x00ab); -+ mdio_write(tp, 0x19, 0x72b0); -+ mdio_write(tp, 0x15, 0x00ac); -+ mdio_write(tp, 0x19, 0x7f00); -+ mdio_write(tp, 0x15, 0x00ad); -+ mdio_write(tp, 0x19, 0x70b0); -+ mdio_write(tp, 0x15, 0x00ae); -+ mdio_write(tp, 0x19, 0x30b8); -+ mdio_write(tp, 0x15, 0x00AF); -+ mdio_write(tp, 0x19, 0x4060); -+ mdio_write(tp, 0x15, 0x00B0); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x00B1); -+ mdio_write(tp, 0x19, 0x7e00); -+ mdio_write(tp, 0x15, 0x00B2); -+ mdio_write(tp, 0x19, 0x72B0); -+ mdio_write(tp, 0x15, 0x00B3); -+ mdio_write(tp, 0x19, 0x7F00); -+ mdio_write(tp, 0x15, 0x00B4); -+ mdio_write(tp, 0x19, 0x73B0); -+ mdio_write(tp, 0x15, 0x00b5); -+ mdio_write(tp, 0x19, 0x58a0); -+ mdio_write(tp, 0x15, 0x00b6); -+ mdio_write(tp, 0x19, 0x63d2); -+ mdio_write(tp, 0x15, 0x00b7); -+ mdio_write(tp, 0x19, 0x5c00); -+ mdio_write(tp, 0x15, 0x00b8); -+ mdio_write(tp, 0x19, 0x5780); -+ mdio_write(tp, 0x15, 0x00b9); -+ mdio_write(tp, 0x19, 0xb60d); -+ mdio_write(tp, 0x15, 0x00ba); -+ mdio_write(tp, 0x19, 0x9bff); -+ mdio_write(tp, 0x15, 0x00bb); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x00bc); -+ mdio_write(tp, 0x19, 0x6001); -+ mdio_write(tp, 0x15, 0x00bd); -+ mdio_write(tp, 0x19, 0xc020); -+ mdio_write(tp, 0x15, 0x00be); -+ mdio_write(tp, 0x19, 0x002b); -+ mdio_write(tp, 0x15, 0x00bf); -+ mdio_write(tp, 0x19, 0xc137); -+ mdio_write(tp, 0x15, 0x00c0); -+ mdio_write(tp, 0x19, 0x0006); -+ mdio_write(tp, 0x15, 0x00c1); -+ mdio_write(tp, 0x19, 0x9af8); -+ mdio_write(tp, 0x15, 0x00c2); -+ mdio_write(tp, 0x19, 0x30c6); -+ mdio_write(tp, 0x15, 0x00c3); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00c4); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00c5); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00c6); -+ mdio_write(tp, 0x19, 0x7d00); -+ mdio_write(tp, 0x15, 0x00c7); -+ mdio_write(tp, 0x19, 0x70b0); -+ mdio_write(tp, 0x15, 0x00c8); -+ mdio_write(tp, 0x19, 0x4400); -+ mdio_write(tp, 0x15, 0x00c9); -+ mdio_write(tp, 0x19, 0x4804); -+ mdio_write(tp, 0x15, 0x00ca); -+ mdio_write(tp, 0x19, 0x7c80); -+ mdio_write(tp, 0x15, 0x00cb); -+ mdio_write(tp, 0x19, 0x5c80); -+ mdio_write(tp, 0x15, 0x00cc); -+ mdio_write(tp, 0x19, 0x4010); -+ mdio_write(tp, 0x15, 0x00cd); -+ mdio_write(tp, 0x19, 0x4415); -+ mdio_write(tp, 0x15, 0x00ce); -+ mdio_write(tp, 0x19, 0x9b00); -+ mdio_write(tp, 0x15, 0x00cf); -+ mdio_write(tp, 0x19, 0x7f00); -+ mdio_write(tp, 0x15, 0x00d0); -+ mdio_write(tp, 0x19, 0x70b0); -+ mdio_write(tp, 0x15, 0x00d1); -+ mdio_write(tp, 0x19, 0x3177); -+ mdio_write(tp, 0x15, 0x00d2); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00d3); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00d4); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00d5); -+ mdio_write(tp, 0x19, 0x4808); -+ mdio_write(tp, 0x15, 0x00d6); -+ mdio_write(tp, 0x19, 0x4007); -+ mdio_write(tp, 0x15, 0x00d7); -+ mdio_write(tp, 0x19, 0x4420); -+ mdio_write(tp, 0x15, 0x00d8); -+ mdio_write(tp, 0x19, 0x63d8); -+ mdio_write(tp, 0x15, 0x00d9); -+ mdio_write(tp, 0x19, 0xb608); -+ mdio_write(tp, 0x15, 0x00da); -+ mdio_write(tp, 0x19, 0xbcbd); -+ mdio_write(tp, 0x15, 0x00db); -+ mdio_write(tp, 0x19, 0xc60b); -+ mdio_write(tp, 0x15, 0x00dc); -+ mdio_write(tp, 0x19, 0x00fd); -+ mdio_write(tp, 0x15, 0x00dd); -+ mdio_write(tp, 0x19, 0x30e1); -+ mdio_write(tp, 0x15, 0x00de); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00df); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00e0); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00e1); -+ mdio_write(tp, 0x19, 0x4809); -+ mdio_write(tp, 0x15, 0x00e2); -+ mdio_write(tp, 0x19, 0x7e40); -+ mdio_write(tp, 0x15, 0x00e3); -+ mdio_write(tp, 0x19, 0x5a40); -+ mdio_write(tp, 0x15, 0x00e4); -+ mdio_write(tp, 0x19, 0x305a); -+ mdio_write(tp, 0x15, 0x00e5); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00e6); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00e7); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00e8); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00e9); -+ mdio_write(tp, 0x19, 0x480a); -+ mdio_write(tp, 0x15, 0x00ea); -+ mdio_write(tp, 0x19, 0x5820); -+ mdio_write(tp, 0x15, 0x00eb); -+ mdio_write(tp, 0x19, 0x6c03); -+ mdio_write(tp, 0x15, 0x00ec); -+ mdio_write(tp, 0x19, 0xb60a); -+ mdio_write(tp, 0x15, 0x00ed); -+ mdio_write(tp, 0x19, 0xda07); -+ mdio_write(tp, 0x15, 0x00ee); -+ mdio_write(tp, 0x19, 0x0008); -+ mdio_write(tp, 0x15, 0x00ef); -+ mdio_write(tp, 0x19, 0xc60b); -+ mdio_write(tp, 0x15, 0x00f0); -+ mdio_write(tp, 0x19, 0x00fc); -+ mdio_write(tp, 0x15, 0x00f1); -+ mdio_write(tp, 0x19, 0x30f6); -+ mdio_write(tp, 0x15, 0x00f2); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00f3); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00f4); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00f5); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x00f6); -+ mdio_write(tp, 0x19, 0x4408); -+ mdio_write(tp, 0x15, 0x00f7); -+ mdio_write(tp, 0x19, 0x480b); -+ mdio_write(tp, 0x15, 0x00f8); -+ mdio_write(tp, 0x19, 0x6f03); -+ mdio_write(tp, 0x15, 0x00f9); -+ mdio_write(tp, 0x19, 0x405f); -+ mdio_write(tp, 0x15, 0x00fa); -+ mdio_write(tp, 0x19, 0x4448); -+ mdio_write(tp, 0x15, 0x00fb); -+ mdio_write(tp, 0x19, 0x4020); -+ mdio_write(tp, 0x15, 0x00fc); -+ mdio_write(tp, 0x19, 0x4468); -+ mdio_write(tp, 0x15, 0x00fd); -+ mdio_write(tp, 0x19, 0x9c03); -+ mdio_write(tp, 0x15, 0x00fe); -+ mdio_write(tp, 0x19, 0x6f07); -+ mdio_write(tp, 0x15, 0x00ff); -+ mdio_write(tp, 0x19, 0x58a0); -+ mdio_write(tp, 0x15, 0x0100); -+ mdio_write(tp, 0x19, 0xd6d1); -+ mdio_write(tp, 0x15, 0x0101); -+ mdio_write(tp, 0x19, 0x0004); -+ mdio_write(tp, 0x15, 0x0102); -+ mdio_write(tp, 0x19, 0xc137); -+ mdio_write(tp, 0x15, 0x0103); -+ mdio_write(tp, 0x19, 0x0002); -+ mdio_write(tp, 0x15, 0x0104); -+ mdio_write(tp, 0x19, 0xa0e5); -+ mdio_write(tp, 0x15, 0x0105); -+ mdio_write(tp, 0x19, 0x9df8); -+ mdio_write(tp, 0x15, 0x0106); -+ mdio_write(tp, 0x19, 0x30c6); -+ mdio_write(tp, 0x15, 0x0107); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0108); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0109); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x010a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x010b); -+ mdio_write(tp, 0x19, 0x4808); -+ mdio_write(tp, 0x15, 0x010c); -+ mdio_write(tp, 0x19, 0xc32d); -+ mdio_write(tp, 0x15, 0x010d); -+ mdio_write(tp, 0x19, 0x0003); -+ mdio_write(tp, 0x15, 0x010e); -+ mdio_write(tp, 0x19, 0xc8b3); -+ mdio_write(tp, 0x15, 0x010f); -+ mdio_write(tp, 0x19, 0x00fc); -+ mdio_write(tp, 0x15, 0x0110); -+ mdio_write(tp, 0x19, 0x4400); -+ mdio_write(tp, 0x15, 0x0111); -+ mdio_write(tp, 0x19, 0x3116); -+ mdio_write(tp, 0x15, 0x0112); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0113); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0114); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0115); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0116); -+ mdio_write(tp, 0x19, 0x4803); -+ mdio_write(tp, 0x15, 0x0117); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x0118); -+ mdio_write(tp, 0x19, 0x6c02); -+ mdio_write(tp, 0x15, 0x0119); -+ mdio_write(tp, 0x19, 0x7c04); -+ mdio_write(tp, 0x15, 0x011a); -+ mdio_write(tp, 0x19, 0x6000); -+ mdio_write(tp, 0x15, 0x011b); -+ mdio_write(tp, 0x19, 0x5cf7); -+ mdio_write(tp, 0x15, 0x011c); -+ mdio_write(tp, 0x19, 0x7c2a); -+ mdio_write(tp, 0x15, 0x011d); -+ mdio_write(tp, 0x19, 0x5800); -+ mdio_write(tp, 0x15, 0x011e); -+ mdio_write(tp, 0x19, 0x5400); -+ mdio_write(tp, 0x15, 0x011f); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x0120); -+ mdio_write(tp, 0x19, 0x74f0); -+ mdio_write(tp, 0x15, 0x0121); -+ mdio_write(tp, 0x19, 0x4019); -+ mdio_write(tp, 0x15, 0x0122); -+ mdio_write(tp, 0x19, 0x440d); -+ mdio_write(tp, 0x15, 0x0123); -+ mdio_write(tp, 0x19, 0xb6c1); -+ mdio_write(tp, 0x15, 0x0124); -+ mdio_write(tp, 0x19, 0xc05b); -+ mdio_write(tp, 0x15, 0x0125); -+ mdio_write(tp, 0x19, 0x00bf); -+ mdio_write(tp, 0x15, 0x0126); -+ mdio_write(tp, 0x19, 0xc025); -+ mdio_write(tp, 0x15, 0x0127); -+ mdio_write(tp, 0x19, 0x00bd); -+ mdio_write(tp, 0x15, 0x0128); -+ mdio_write(tp, 0x19, 0xc603); -+ mdio_write(tp, 0x15, 0x0129); -+ mdio_write(tp, 0x19, 0x00bb); -+ mdio_write(tp, 0x15, 0x012a); -+ mdio_write(tp, 0x19, 0x8805); -+ mdio_write(tp, 0x15, 0x012b); -+ mdio_write(tp, 0x19, 0x7801); -+ mdio_write(tp, 0x15, 0x012c); -+ mdio_write(tp, 0x19, 0x4001); -+ mdio_write(tp, 0x15, 0x012d); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x012e); -+ mdio_write(tp, 0x19, 0xa3dd); -+ mdio_write(tp, 0x15, 0x012f); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x0130); -+ mdio_write(tp, 0x19, 0x6c03); -+ mdio_write(tp, 0x15, 0x0131); -+ mdio_write(tp, 0x19, 0x8407); -+ mdio_write(tp, 0x15, 0x0132); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x0133); -+ mdio_write(tp, 0x19, 0x6c02); -+ mdio_write(tp, 0x15, 0x0134); -+ mdio_write(tp, 0x19, 0xd9b8); -+ mdio_write(tp, 0x15, 0x0135); -+ mdio_write(tp, 0x19, 0x0003); -+ mdio_write(tp, 0x15, 0x0136); -+ mdio_write(tp, 0x19, 0xc240); -+ mdio_write(tp, 0x15, 0x0137); -+ mdio_write(tp, 0x19, 0x0015); -+ mdio_write(tp, 0x15, 0x0138); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x0139); -+ mdio_write(tp, 0x19, 0x6c02); -+ mdio_write(tp, 0x15, 0x013a); -+ mdio_write(tp, 0x19, 0x9ae9); -+ mdio_write(tp, 0x15, 0x013b); -+ mdio_write(tp, 0x19, 0x3140); -+ mdio_write(tp, 0x15, 0x013c); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x013d); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x013e); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x013f); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0140); -+ mdio_write(tp, 0x19, 0x4807); -+ mdio_write(tp, 0x15, 0x0141); -+ mdio_write(tp, 0x19, 0x4004); -+ mdio_write(tp, 0x15, 0x0142); -+ mdio_write(tp, 0x19, 0x4410); -+ mdio_write(tp, 0x15, 0x0143); -+ mdio_write(tp, 0x19, 0x7c0c); -+ mdio_write(tp, 0x15, 0x0144); -+ mdio_write(tp, 0x19, 0x600c); -+ mdio_write(tp, 0x15, 0x0145); -+ mdio_write(tp, 0x19, 0x9b00); -+ mdio_write(tp, 0x15, 0x0146); -+ mdio_write(tp, 0x19, 0xa68f); -+ mdio_write(tp, 0x15, 0x0147); -+ mdio_write(tp, 0x19, 0x3116); -+ mdio_write(tp, 0x15, 0x0148); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0149); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x014a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x014b); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x014c); -+ mdio_write(tp, 0x19, 0x4804); -+ mdio_write(tp, 0x15, 0x014d); -+ mdio_write(tp, 0x19, 0x54c0); -+ mdio_write(tp, 0x15, 0x014e); -+ mdio_write(tp, 0x19, 0xb703); -+ mdio_write(tp, 0x15, 0x014f); -+ mdio_write(tp, 0x19, 0x5cff); -+ mdio_write(tp, 0x15, 0x0150); -+ mdio_write(tp, 0x19, 0x315f); -+ mdio_write(tp, 0x15, 0x0151); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x0152); -+ mdio_write(tp, 0x19, 0x74f8); -+ mdio_write(tp, 0x15, 0x0153); -+ mdio_write(tp, 0x19, 0x6421); -+ mdio_write(tp, 0x15, 0x0154); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x0155); -+ mdio_write(tp, 0x19, 0x6000); -+ mdio_write(tp, 0x15, 0x0156); -+ mdio_write(tp, 0x19, 0x4003); -+ mdio_write(tp, 0x15, 0x0157); -+ mdio_write(tp, 0x19, 0x4418); -+ mdio_write(tp, 0x15, 0x0158); -+ mdio_write(tp, 0x19, 0x9b00); -+ mdio_write(tp, 0x15, 0x0159); -+ mdio_write(tp, 0x19, 0x6461); -+ mdio_write(tp, 0x15, 0x015a); -+ mdio_write(tp, 0x19, 0x64e1); -+ mdio_write(tp, 0x15, 0x015b); -+ mdio_write(tp, 0x19, 0x7c20); -+ mdio_write(tp, 0x15, 0x015c); -+ mdio_write(tp, 0x19, 0x5820); -+ mdio_write(tp, 0x15, 0x015d); -+ mdio_write(tp, 0x19, 0x5ccf); -+ mdio_write(tp, 0x15, 0x015e); -+ mdio_write(tp, 0x19, 0x7050); -+ mdio_write(tp, 0x15, 0x015f); -+ mdio_write(tp, 0x19, 0xd9b8); -+ mdio_write(tp, 0x15, 0x0160); -+ mdio_write(tp, 0x19, 0x0008); -+ mdio_write(tp, 0x15, 0x0161); -+ mdio_write(tp, 0x19, 0xdab1); -+ mdio_write(tp, 0x15, 0x0162); -+ mdio_write(tp, 0x19, 0x0015); -+ mdio_write(tp, 0x15, 0x0163); -+ mdio_write(tp, 0x19, 0xc244); -+ mdio_write(tp, 0x15, 0x0164); -+ mdio_write(tp, 0x19, 0x0013); -+ mdio_write(tp, 0x15, 0x0165); -+ mdio_write(tp, 0x19, 0xc021); -+ mdio_write(tp, 0x15, 0x0166); -+ mdio_write(tp, 0x19, 0x00f9); -+ mdio_write(tp, 0x15, 0x0167); -+ mdio_write(tp, 0x19, 0x3177); -+ mdio_write(tp, 0x15, 0x0168); -+ mdio_write(tp, 0x19, 0x5cf7); -+ mdio_write(tp, 0x15, 0x0169); -+ mdio_write(tp, 0x19, 0x4010); -+ mdio_write(tp, 0x15, 0x016a); -+ mdio_write(tp, 0x19, 0x4428); -+ mdio_write(tp, 0x15, 0x016b); -+ mdio_write(tp, 0x19, 0x9c00); -+ mdio_write(tp, 0x15, 0x016c); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x016d); -+ mdio_write(tp, 0x19, 0x6008); -+ mdio_write(tp, 0x15, 0x016e); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x016f); -+ mdio_write(tp, 0x19, 0x74f0); -+ mdio_write(tp, 0x15, 0x0170); -+ mdio_write(tp, 0x19, 0x6461); -+ mdio_write(tp, 0x15, 0x0171); -+ mdio_write(tp, 0x19, 0x6421); -+ mdio_write(tp, 0x15, 0x0172); -+ mdio_write(tp, 0x19, 0x64a1); -+ mdio_write(tp, 0x15, 0x0173); -+ mdio_write(tp, 0x19, 0x3116); -+ mdio_write(tp, 0x15, 0x0174); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0175); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0176); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0177); -+ mdio_write(tp, 0x19, 0x4805); -+ mdio_write(tp, 0x15, 0x0178); -+ mdio_write(tp, 0x19, 0xa103); -+ mdio_write(tp, 0x15, 0x0179); -+ mdio_write(tp, 0x19, 0x7c02); -+ mdio_write(tp, 0x15, 0x017a); -+ mdio_write(tp, 0x19, 0x6002); -+ mdio_write(tp, 0x15, 0x017b); -+ mdio_write(tp, 0x19, 0x7e00); -+ mdio_write(tp, 0x15, 0x017c); -+ mdio_write(tp, 0x19, 0x5400); -+ mdio_write(tp, 0x15, 0x017d); -+ mdio_write(tp, 0x19, 0x7c6b); -+ mdio_write(tp, 0x15, 0x017e); -+ mdio_write(tp, 0x19, 0x5c63); -+ mdio_write(tp, 0x15, 0x017f); -+ mdio_write(tp, 0x19, 0x407d); -+ mdio_write(tp, 0x15, 0x0180); -+ mdio_write(tp, 0x19, 0xa602); -+ mdio_write(tp, 0x15, 0x0181); -+ mdio_write(tp, 0x19, 0x4001); -+ mdio_write(tp, 0x15, 0x0182); -+ mdio_write(tp, 0x19, 0x4420); -+ mdio_write(tp, 0x15, 0x0183); -+ mdio_write(tp, 0x19, 0x4020); -+ mdio_write(tp, 0x15, 0x0184); -+ mdio_write(tp, 0x19, 0x44a1); -+ mdio_write(tp, 0x15, 0x0185); -+ mdio_write(tp, 0x19, 0xd6e0); -+ mdio_write(tp, 0x15, 0x0186); -+ mdio_write(tp, 0x19, 0x0009); -+ mdio_write(tp, 0x15, 0x0187); -+ mdio_write(tp, 0x19, 0x9efe); -+ mdio_write(tp, 0x15, 0x0188); -+ mdio_write(tp, 0x19, 0x7c02); -+ mdio_write(tp, 0x15, 0x0189); -+ mdio_write(tp, 0x19, 0x6000); -+ mdio_write(tp, 0x15, 0x018a); -+ mdio_write(tp, 0x19, 0x9c00); -+ mdio_write(tp, 0x15, 0x018b); -+ mdio_write(tp, 0x19, 0x318f); -+ mdio_write(tp, 0x15, 0x018c); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x018d); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x018e); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x018f); -+ mdio_write(tp, 0x19, 0x4806); -+ mdio_write(tp, 0x15, 0x0190); -+ mdio_write(tp, 0x19, 0x7c10); -+ mdio_write(tp, 0x15, 0x0191); -+ mdio_write(tp, 0x19, 0x5c10); -+ mdio_write(tp, 0x15, 0x0192); -+ mdio_write(tp, 0x19, 0x40fa); -+ mdio_write(tp, 0x15, 0x0193); -+ mdio_write(tp, 0x19, 0xa602); -+ mdio_write(tp, 0x15, 0x0194); -+ mdio_write(tp, 0x19, 0x4010); -+ mdio_write(tp, 0x15, 0x0195); -+ mdio_write(tp, 0x19, 0x4440); -+ mdio_write(tp, 0x15, 0x0196); -+ mdio_write(tp, 0x19, 0x9d00); -+ mdio_write(tp, 0x15, 0x0197); -+ mdio_write(tp, 0x19, 0x7c80); -+ mdio_write(tp, 0x15, 0x0198); -+ mdio_write(tp, 0x19, 0x6400); -+ mdio_write(tp, 0x15, 0x0199); -+ mdio_write(tp, 0x19, 0x4003); -+ mdio_write(tp, 0x15, 0x019a); -+ mdio_write(tp, 0x19, 0x4540); -+ mdio_write(tp, 0x15, 0x019b); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x019c); -+ mdio_write(tp, 0x19, 0x6008); -+ mdio_write(tp, 0x15, 0x019d); -+ mdio_write(tp, 0x19, 0x9f00); -+ mdio_write(tp, 0x15, 0x019e); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x019f); -+ mdio_write(tp, 0x19, 0x6400); -+ mdio_write(tp, 0x15, 0x01a0); -+ mdio_write(tp, 0x19, 0x7c80); -+ mdio_write(tp, 0x15, 0x01a1); -+ mdio_write(tp, 0x19, 0x6480); -+ mdio_write(tp, 0x15, 0x01a2); -+ mdio_write(tp, 0x19, 0x3140); -+ mdio_write(tp, 0x15, 0x01a3); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01a4); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01a5); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01a6); -+ mdio_write(tp, 0x19, 0x4400); -+ mdio_write(tp, 0x15, 0x01a7); -+ mdio_write(tp, 0x19, 0x7c0b); -+ mdio_write(tp, 0x15, 0x01a8); -+ mdio_write(tp, 0x19, 0x6c01); -+ mdio_write(tp, 0x15, 0x01a9); -+ mdio_write(tp, 0x19, 0x64a8); -+ mdio_write(tp, 0x15, 0x01aa); -+ mdio_write(tp, 0x19, 0x6800); -+ mdio_write(tp, 0x15, 0x01ab); -+ mdio_write(tp, 0x19, 0x5cf0); -+ mdio_write(tp, 0x15, 0x01ac); -+ mdio_write(tp, 0x19, 0x588f); -+ mdio_write(tp, 0x15, 0x01ad); -+ mdio_write(tp, 0x19, 0xb628); -+ mdio_write(tp, 0x15, 0x01ae); -+ mdio_write(tp, 0x19, 0xc053); -+ mdio_write(tp, 0x15, 0x01af); -+ mdio_write(tp, 0x19, 0x0026); -+ mdio_write(tp, 0x15, 0x01b0); -+ mdio_write(tp, 0x19, 0xc02d); -+ mdio_write(tp, 0x15, 0x01b1); -+ mdio_write(tp, 0x19, 0x0024); -+ mdio_write(tp, 0x15, 0x01b2); -+ mdio_write(tp, 0x19, 0xc603); -+ mdio_write(tp, 0x15, 0x01b3); -+ mdio_write(tp, 0x19, 0x0022); -+ mdio_write(tp, 0x15, 0x01b4); -+ mdio_write(tp, 0x19, 0x8cf9); -+ mdio_write(tp, 0x15, 0x01b5); -+ mdio_write(tp, 0x19, 0x31ba); -+ mdio_write(tp, 0x15, 0x01b6); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01b7); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01b8); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01b9); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01ba); -+ mdio_write(tp, 0x19, 0x4400); -+ mdio_write(tp, 0x15, 0x01bb); -+ mdio_write(tp, 0x19, 0x5420); -+ mdio_write(tp, 0x15, 0x01bc); -+ mdio_write(tp, 0x19, 0x4811); -+ mdio_write(tp, 0x15, 0x01bd); -+ mdio_write(tp, 0x19, 0x5000); -+ mdio_write(tp, 0x15, 0x01be); -+ mdio_write(tp, 0x19, 0x4801); -+ mdio_write(tp, 0x15, 0x01bf); -+ mdio_write(tp, 0x19, 0x6800); -+ mdio_write(tp, 0x15, 0x01c0); -+ mdio_write(tp, 0x19, 0x31f5); -+ mdio_write(tp, 0x15, 0x01c1); -+ mdio_write(tp, 0x19, 0xb614); -+ mdio_write(tp, 0x15, 0x01c2); -+ mdio_write(tp, 0x19, 0x8ce4); -+ mdio_write(tp, 0x15, 0x01c3); -+ mdio_write(tp, 0x19, 0xb30c); -+ mdio_write(tp, 0x15, 0x01c4); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x01c5); -+ mdio_write(tp, 0x19, 0x6c02); -+ mdio_write(tp, 0x15, 0x01c6); -+ mdio_write(tp, 0x19, 0x8206); -+ mdio_write(tp, 0x15, 0x01c7); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x01c8); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x01c9); -+ mdio_write(tp, 0x19, 0x7c04); -+ mdio_write(tp, 0x15, 0x01ca); -+ mdio_write(tp, 0x19, 0x7404); -+ mdio_write(tp, 0x15, 0x01cb); -+ mdio_write(tp, 0x19, 0x31c0); -+ mdio_write(tp, 0x15, 0x01cc); -+ mdio_write(tp, 0x19, 0x7c04); -+ mdio_write(tp, 0x15, 0x01cd); -+ mdio_write(tp, 0x19, 0x7400); -+ mdio_write(tp, 0x15, 0x01ce); -+ mdio_write(tp, 0x19, 0x31c0); -+ mdio_write(tp, 0x15, 0x01cf); -+ mdio_write(tp, 0x19, 0x8df1); -+ mdio_write(tp, 0x15, 0x01d0); -+ mdio_write(tp, 0x19, 0x3248); -+ mdio_write(tp, 0x15, 0x01d1); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01d2); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01d3); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01d4); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01d5); -+ mdio_write(tp, 0x19, 0x4400); -+ mdio_write(tp, 0x15, 0x01d6); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x01d7); -+ mdio_write(tp, 0x19, 0x6c03); -+ mdio_write(tp, 0x15, 0x01d8); -+ mdio_write(tp, 0x19, 0x7670); -+ mdio_write(tp, 0x15, 0x01d9); -+ mdio_write(tp, 0x19, 0x4023); -+ mdio_write(tp, 0x15, 0x01da); -+ mdio_write(tp, 0x19, 0x4500); -+ mdio_write(tp, 0x15, 0x01db); -+ mdio_write(tp, 0x19, 0x4069); -+ mdio_write(tp, 0x15, 0x01dc); -+ mdio_write(tp, 0x19, 0x4580); -+ mdio_write(tp, 0x15, 0x01dd); -+ mdio_write(tp, 0x19, 0x9f00); -+ mdio_write(tp, 0x15, 0x01de); -+ mdio_write(tp, 0x19, 0xcff5); -+ mdio_write(tp, 0x15, 0x01df); -+ mdio_write(tp, 0x19, 0x00ff); -+ mdio_write(tp, 0x15, 0x01e0); -+ mdio_write(tp, 0x19, 0x76f0); -+ mdio_write(tp, 0x15, 0x01e1); -+ mdio_write(tp, 0x19, 0x4400); -+ mdio_write(tp, 0x15, 0x01e2); -+ mdio_write(tp, 0x19, 0x4023); -+ mdio_write(tp, 0x15, 0x01e3); -+ mdio_write(tp, 0x19, 0x4500); -+ mdio_write(tp, 0x15, 0x01e4); -+ mdio_write(tp, 0x19, 0x4069); -+ mdio_write(tp, 0x15, 0x01e5); -+ mdio_write(tp, 0x19, 0x4580); -+ mdio_write(tp, 0x15, 0x01e6); -+ mdio_write(tp, 0x19, 0x9f00); -+ mdio_write(tp, 0x15, 0x01e7); -+ mdio_write(tp, 0x19, 0xd0f5); -+ mdio_write(tp, 0x15, 0x01e8); -+ mdio_write(tp, 0x19, 0x00ff); -+ mdio_write(tp, 0x15, 0x01e9); -+ mdio_write(tp, 0x19, 0x4400); -+ mdio_write(tp, 0x15, 0x01ea); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x01eb); -+ mdio_write(tp, 0x19, 0x6800); -+ mdio_write(tp, 0x15, 0x01ec); -+ mdio_write(tp, 0x19, 0x66a0); -+ mdio_write(tp, 0x15, 0x01ed); -+ mdio_write(tp, 0x19, 0x8300); -+ mdio_write(tp, 0x15, 0x01ee); -+ mdio_write(tp, 0x19, 0x74f0); -+ mdio_write(tp, 0x15, 0x01ef); -+ mdio_write(tp, 0x19, 0x3006); -+ mdio_write(tp, 0x15, 0x01f0); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01f1); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01f2); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01f3); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01f4); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x01f5); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x01f6); -+ mdio_write(tp, 0x19, 0x6c02); -+ mdio_write(tp, 0x15, 0x01f7); -+ mdio_write(tp, 0x19, 0x409d); -+ mdio_write(tp, 0x15, 0x01f8); -+ mdio_write(tp, 0x19, 0x7c87); -+ mdio_write(tp, 0x15, 0x01f9); -+ mdio_write(tp, 0x19, 0xae14); -+ mdio_write(tp, 0x15, 0x01fa); -+ mdio_write(tp, 0x19, 0x4400); -+ mdio_write(tp, 0x15, 0x01fb); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x01fc); -+ mdio_write(tp, 0x19, 0x6800); -+ mdio_write(tp, 0x15, 0x01fd); -+ mdio_write(tp, 0x19, 0x7801); -+ mdio_write(tp, 0x15, 0x01fe); -+ mdio_write(tp, 0x19, 0x980e); -+ mdio_write(tp, 0x15, 0x01ff); -+ mdio_write(tp, 0x19, 0x930c); -+ mdio_write(tp, 0x15, 0x0200); -+ mdio_write(tp, 0x19, 0x9206); -+ mdio_write(tp, 0x15, 0x0201); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x0202); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0203); -+ mdio_write(tp, 0x19, 0x588f); -+ mdio_write(tp, 0x15, 0x0204); -+ mdio_write(tp, 0x19, 0x5520); -+ mdio_write(tp, 0x15, 0x0205); -+ mdio_write(tp, 0x19, 0x320c); -+ mdio_write(tp, 0x15, 0x0206); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x15, 0x0207); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0208); -+ mdio_write(tp, 0x19, 0x588d); -+ mdio_write(tp, 0x15, 0x0209); -+ mdio_write(tp, 0x19, 0x5500); -+ mdio_write(tp, 0x15, 0x020a); -+ mdio_write(tp, 0x19, 0x320c); -+ mdio_write(tp, 0x15, 0x020b); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x020c); -+ mdio_write(tp, 0x19, 0x3220); -+ mdio_write(tp, 0x15, 0x020d); -+ mdio_write(tp, 0x19, 0x4480); -+ mdio_write(tp, 0x15, 0x020e); -+ mdio_write(tp, 0x19, 0x9e03); -+ mdio_write(tp, 0x15, 0x020f); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x0210); -+ mdio_write(tp, 0x19, 0x6840); -+ mdio_write(tp, 0x15, 0x0211); -+ mdio_write(tp, 0x19, 0x7801); -+ mdio_write(tp, 0x15, 0x0212); -+ mdio_write(tp, 0x19, 0x980e); -+ mdio_write(tp, 0x15, 0x0213); -+ mdio_write(tp, 0x19, 0x930c); -+ mdio_write(tp, 0x15, 0x0214); -+ mdio_write(tp, 0x19, 0x9206); -+ mdio_write(tp, 0x15, 0x0215); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x15, 0x0216); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0217); -+ mdio_write(tp, 0x19, 0x588f); -+ mdio_write(tp, 0x15, 0x0218); -+ mdio_write(tp, 0x19, 0x5520); -+ mdio_write(tp, 0x15, 0x0219); -+ mdio_write(tp, 0x19, 0x3220); -+ mdio_write(tp, 0x15, 0x021a); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x021b); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x021c); -+ mdio_write(tp, 0x19, 0x588d); -+ mdio_write(tp, 0x15, 0x021d); -+ mdio_write(tp, 0x19, 0x5540); -+ mdio_write(tp, 0x15, 0x021e); -+ mdio_write(tp, 0x19, 0x3220); -+ mdio_write(tp, 0x15, 0x021f); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x15, 0x0220); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0221); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x0222); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x0223); -+ mdio_write(tp, 0x19, 0x3231); -+ mdio_write(tp, 0x15, 0x0224); -+ mdio_write(tp, 0x19, 0xab06); -+ mdio_write(tp, 0x15, 0x0225); -+ mdio_write(tp, 0x19, 0xbf08); -+ mdio_write(tp, 0x15, 0x0226); -+ mdio_write(tp, 0x19, 0x4076); -+ mdio_write(tp, 0x15, 0x0227); -+ mdio_write(tp, 0x19, 0x7d07); -+ mdio_write(tp, 0x15, 0x0228); -+ mdio_write(tp, 0x19, 0x4502); -+ mdio_write(tp, 0x15, 0x0229); -+ mdio_write(tp, 0x19, 0x3231); -+ mdio_write(tp, 0x15, 0x022a); -+ mdio_write(tp, 0x19, 0x7d80); -+ mdio_write(tp, 0x15, 0x022b); -+ mdio_write(tp, 0x19, 0x5180); -+ mdio_write(tp, 0x15, 0x022c); -+ mdio_write(tp, 0x19, 0x322f); -+ mdio_write(tp, 0x15, 0x022d); -+ mdio_write(tp, 0x19, 0x7d80); -+ mdio_write(tp, 0x15, 0x022e); -+ mdio_write(tp, 0x19, 0x5000); -+ mdio_write(tp, 0x15, 0x022f); -+ mdio_write(tp, 0x19, 0x7d07); -+ mdio_write(tp, 0x15, 0x0230); -+ mdio_write(tp, 0x19, 0x4402); -+ mdio_write(tp, 0x15, 0x0231); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x0232); -+ mdio_write(tp, 0x19, 0x6c02); -+ mdio_write(tp, 0x15, 0x0233); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x0234); -+ mdio_write(tp, 0x19, 0xb309); -+ mdio_write(tp, 0x15, 0x0235); -+ mdio_write(tp, 0x19, 0xb204); -+ mdio_write(tp, 0x15, 0x0236); -+ mdio_write(tp, 0x19, 0xb105); -+ mdio_write(tp, 0x15, 0x0237); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x0238); -+ mdio_write(tp, 0x19, 0x31c1); -+ mdio_write(tp, 0x15, 0x0239); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x023a); -+ mdio_write(tp, 0x19, 0x3261); -+ mdio_write(tp, 0x15, 0x023b); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x023c); -+ mdio_write(tp, 0x19, 0x3250); -+ mdio_write(tp, 0x15, 0x023d); -+ mdio_write(tp, 0x19, 0xb203); -+ mdio_write(tp, 0x15, 0x023e); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x023f); -+ mdio_write(tp, 0x19, 0x327a); -+ mdio_write(tp, 0x15, 0x0240); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x0241); -+ mdio_write(tp, 0x19, 0x3293); -+ mdio_write(tp, 0x15, 0x0242); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0243); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0244); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0245); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0246); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0247); -+ mdio_write(tp, 0x19, 0x32a3); -+ mdio_write(tp, 0x15, 0x0248); -+ mdio_write(tp, 0x19, 0x5520); -+ mdio_write(tp, 0x15, 0x0249); -+ mdio_write(tp, 0x19, 0x403d); -+ mdio_write(tp, 0x15, 0x024a); -+ mdio_write(tp, 0x19, 0x440c); -+ mdio_write(tp, 0x15, 0x024b); -+ mdio_write(tp, 0x19, 0x4812); -+ mdio_write(tp, 0x15, 0x024c); -+ mdio_write(tp, 0x19, 0x5001); -+ mdio_write(tp, 0x15, 0x024d); -+ mdio_write(tp, 0x19, 0x4802); -+ mdio_write(tp, 0x15, 0x024e); -+ mdio_write(tp, 0x19, 0x6880); -+ mdio_write(tp, 0x15, 0x024f); -+ mdio_write(tp, 0x19, 0x31f5); -+ mdio_write(tp, 0x15, 0x0250); -+ mdio_write(tp, 0x19, 0xb685); -+ mdio_write(tp, 0x15, 0x0251); -+ mdio_write(tp, 0x19, 0x801c); -+ mdio_write(tp, 0x15, 0x0252); -+ mdio_write(tp, 0x19, 0xbaf5); -+ mdio_write(tp, 0x15, 0x0253); -+ mdio_write(tp, 0x19, 0xc07c); -+ mdio_write(tp, 0x15, 0x0254); -+ mdio_write(tp, 0x19, 0x00fb); -+ mdio_write(tp, 0x15, 0x0255); -+ mdio_write(tp, 0x19, 0x325a); -+ mdio_write(tp, 0x15, 0x0256); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0257); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0258); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0259); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x025a); -+ mdio_write(tp, 0x19, 0x481a); -+ mdio_write(tp, 0x15, 0x025b); -+ mdio_write(tp, 0x19, 0x5001); -+ mdio_write(tp, 0x15, 0x025c); -+ mdio_write(tp, 0x19, 0x401b); -+ mdio_write(tp, 0x15, 0x025d); -+ mdio_write(tp, 0x19, 0x480a); -+ mdio_write(tp, 0x15, 0x025e); -+ mdio_write(tp, 0x19, 0x4418); -+ mdio_write(tp, 0x15, 0x025f); -+ mdio_write(tp, 0x19, 0x6900); -+ mdio_write(tp, 0x15, 0x0260); -+ mdio_write(tp, 0x19, 0x31f5); -+ mdio_write(tp, 0x15, 0x0261); -+ mdio_write(tp, 0x19, 0xb64b); -+ mdio_write(tp, 0x15, 0x0262); -+ mdio_write(tp, 0x19, 0xdb00); -+ mdio_write(tp, 0x15, 0x0263); -+ mdio_write(tp, 0x19, 0x0048); -+ mdio_write(tp, 0x15, 0x0264); -+ mdio_write(tp, 0x19, 0xdb7d); -+ mdio_write(tp, 0x15, 0x0265); -+ mdio_write(tp, 0x19, 0x0002); -+ mdio_write(tp, 0x15, 0x0266); -+ mdio_write(tp, 0x19, 0xa0fa); -+ mdio_write(tp, 0x15, 0x0267); -+ mdio_write(tp, 0x19, 0x4408); -+ mdio_write(tp, 0x15, 0x0268); -+ mdio_write(tp, 0x19, 0x3248); -+ mdio_write(tp, 0x15, 0x0269); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x026a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x026b); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x026c); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x026d); -+ mdio_write(tp, 0x19, 0xb806); -+ mdio_write(tp, 0x15, 0x026e); -+ mdio_write(tp, 0x19, 0x588d); -+ mdio_write(tp, 0x15, 0x026f); -+ mdio_write(tp, 0x19, 0x5500); -+ mdio_write(tp, 0x15, 0x0270); -+ mdio_write(tp, 0x19, 0x7801); -+ mdio_write(tp, 0x15, 0x0271); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x0272); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0273); -+ mdio_write(tp, 0x19, 0x4814); -+ mdio_write(tp, 0x15, 0x0274); -+ mdio_write(tp, 0x19, 0x500b); -+ mdio_write(tp, 0x15, 0x0275); -+ mdio_write(tp, 0x19, 0x4804); -+ mdio_write(tp, 0x15, 0x0276); -+ mdio_write(tp, 0x19, 0x40c4); -+ mdio_write(tp, 0x15, 0x0277); -+ mdio_write(tp, 0x19, 0x4425); -+ mdio_write(tp, 0x15, 0x0278); -+ mdio_write(tp, 0x19, 0x6a00); -+ mdio_write(tp, 0x15, 0x0279); -+ mdio_write(tp, 0x19, 0x31f5); -+ mdio_write(tp, 0x15, 0x027a); -+ mdio_write(tp, 0x19, 0xb632); -+ mdio_write(tp, 0x15, 0x027b); -+ mdio_write(tp, 0x19, 0xdc03); -+ mdio_write(tp, 0x15, 0x027c); -+ mdio_write(tp, 0x19, 0x0027); -+ mdio_write(tp, 0x15, 0x027d); -+ mdio_write(tp, 0x19, 0x80fc); -+ mdio_write(tp, 0x15, 0x027e); -+ mdio_write(tp, 0x19, 0x3283); -+ mdio_write(tp, 0x15, 0x027f); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0280); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0281); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0282); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0283); -+ mdio_write(tp, 0x19, 0xb806); -+ mdio_write(tp, 0x15, 0x0284); -+ mdio_write(tp, 0x19, 0x588f); -+ mdio_write(tp, 0x15, 0x0285); -+ mdio_write(tp, 0x19, 0x5520); -+ mdio_write(tp, 0x15, 0x0286); -+ mdio_write(tp, 0x19, 0x7801); -+ mdio_write(tp, 0x15, 0x0287); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x15, 0x0288); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0289); -+ mdio_write(tp, 0x19, 0x4818); -+ mdio_write(tp, 0x15, 0x028a); -+ mdio_write(tp, 0x19, 0x5051); -+ mdio_write(tp, 0x15, 0x028b); -+ mdio_write(tp, 0x19, 0x4808); -+ mdio_write(tp, 0x15, 0x028c); -+ mdio_write(tp, 0x19, 0x4050); -+ mdio_write(tp, 0x15, 0x028d); -+ mdio_write(tp, 0x19, 0x4462); -+ mdio_write(tp, 0x15, 0x028e); -+ mdio_write(tp, 0x19, 0x40c4); -+ mdio_write(tp, 0x15, 0x028f); -+ mdio_write(tp, 0x19, 0x4473); -+ mdio_write(tp, 0x15, 0x0290); -+ mdio_write(tp, 0x19, 0x5041); -+ mdio_write(tp, 0x15, 0x0291); -+ mdio_write(tp, 0x19, 0x6b00); -+ mdio_write(tp, 0x15, 0x0292); -+ mdio_write(tp, 0x19, 0x31f5); -+ mdio_write(tp, 0x15, 0x0293); -+ mdio_write(tp, 0x19, 0xb619); -+ mdio_write(tp, 0x15, 0x0294); -+ mdio_write(tp, 0x19, 0x80d9); -+ mdio_write(tp, 0x15, 0x0295); -+ mdio_write(tp, 0x19, 0xbd06); -+ mdio_write(tp, 0x15, 0x0296); -+ mdio_write(tp, 0x19, 0xbb0d); -+ mdio_write(tp, 0x15, 0x0297); -+ mdio_write(tp, 0x19, 0xaf14); -+ mdio_write(tp, 0x15, 0x0298); -+ mdio_write(tp, 0x19, 0x8efa); -+ mdio_write(tp, 0x15, 0x0299); -+ mdio_write(tp, 0x19, 0x5049); -+ mdio_write(tp, 0x15, 0x029a); -+ mdio_write(tp, 0x19, 0x3248); -+ mdio_write(tp, 0x15, 0x029b); -+ mdio_write(tp, 0x19, 0x4c10); -+ mdio_write(tp, 0x15, 0x029c); -+ mdio_write(tp, 0x19, 0x44b0); -+ mdio_write(tp, 0x15, 0x029d); -+ mdio_write(tp, 0x19, 0x4c00); -+ mdio_write(tp, 0x15, 0x029e); -+ mdio_write(tp, 0x19, 0x3292); -+ mdio_write(tp, 0x15, 0x029f); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02a0); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02a1); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02a2); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02a3); -+ mdio_write(tp, 0x19, 0x481f); -+ mdio_write(tp, 0x15, 0x02a4); -+ mdio_write(tp, 0x19, 0x5005); -+ mdio_write(tp, 0x15, 0x02a5); -+ mdio_write(tp, 0x19, 0x480f); -+ mdio_write(tp, 0x15, 0x02a6); -+ mdio_write(tp, 0x19, 0xac00); -+ mdio_write(tp, 0x15, 0x02a7); -+ mdio_write(tp, 0x19, 0x31a6); -+ mdio_write(tp, 0x15, 0x02a8); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02a9); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02aa); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02ab); -+ mdio_write(tp, 0x19, 0x31ba); -+ mdio_write(tp, 0x15, 0x02ac); -+ mdio_write(tp, 0x19, 0x31d5); -+ mdio_write(tp, 0x15, 0x02ad); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02ae); -+ mdio_write(tp, 0x19, 0x5cf0); -+ mdio_write(tp, 0x15, 0x02af); -+ mdio_write(tp, 0x19, 0x588c); -+ mdio_write(tp, 0x15, 0x02b0); -+ mdio_write(tp, 0x19, 0x542f); -+ mdio_write(tp, 0x15, 0x02b1); -+ mdio_write(tp, 0x19, 0x7ffb); -+ mdio_write(tp, 0x15, 0x02b2); -+ mdio_write(tp, 0x19, 0x6ff8); -+ mdio_write(tp, 0x15, 0x02b3); -+ mdio_write(tp, 0x19, 0x64a4); -+ mdio_write(tp, 0x15, 0x02b4); -+ mdio_write(tp, 0x19, 0x64a0); -+ mdio_write(tp, 0x15, 0x02b5); -+ mdio_write(tp, 0x19, 0x6800); -+ mdio_write(tp, 0x15, 0x02b6); -+ mdio_write(tp, 0x19, 0x4400); -+ mdio_write(tp, 0x15, 0x02b7); -+ mdio_write(tp, 0x19, 0x4020); -+ mdio_write(tp, 0x15, 0x02b8); -+ mdio_write(tp, 0x19, 0x4480); -+ mdio_write(tp, 0x15, 0x02b9); -+ mdio_write(tp, 0x19, 0x9e00); -+ mdio_write(tp, 0x15, 0x02ba); -+ mdio_write(tp, 0x19, 0x4891); -+ mdio_write(tp, 0x15, 0x02bb); -+ mdio_write(tp, 0x19, 0x4cc0); -+ mdio_write(tp, 0x15, 0x02bc); -+ mdio_write(tp, 0x19, 0x4801); -+ mdio_write(tp, 0x15, 0x02bd); -+ mdio_write(tp, 0x19, 0xa609); -+ mdio_write(tp, 0x15, 0x02be); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x02bf); -+ mdio_write(tp, 0x19, 0x004e); -+ mdio_write(tp, 0x15, 0x02c0); -+ mdio_write(tp, 0x19, 0x87fe); -+ mdio_write(tp, 0x15, 0x02c1); -+ mdio_write(tp, 0x19, 0x32c6); -+ mdio_write(tp, 0x15, 0x02c2); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02c3); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02c4); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02c5); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02c6); -+ mdio_write(tp, 0x19, 0x48b2); -+ mdio_write(tp, 0x15, 0x02c7); -+ mdio_write(tp, 0x19, 0x4020); -+ mdio_write(tp, 0x15, 0x02c8); -+ mdio_write(tp, 0x19, 0x4822); -+ mdio_write(tp, 0x15, 0x02c9); -+ mdio_write(tp, 0x19, 0x4488); -+ mdio_write(tp, 0x15, 0x02ca); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x02cb); -+ mdio_write(tp, 0x19, 0x0042); -+ mdio_write(tp, 0x15, 0x02cc); -+ mdio_write(tp, 0x19, 0x8203); -+ mdio_write(tp, 0x15, 0x02cd); -+ mdio_write(tp, 0x19, 0x4cc8); -+ mdio_write(tp, 0x15, 0x02ce); -+ mdio_write(tp, 0x19, 0x32d0); -+ mdio_write(tp, 0x15, 0x02cf); -+ mdio_write(tp, 0x19, 0x4cc0); -+ mdio_write(tp, 0x15, 0x02d0); -+ mdio_write(tp, 0x19, 0xc4d4); -+ mdio_write(tp, 0x15, 0x02d1); -+ mdio_write(tp, 0x19, 0x00f9); -+ mdio_write(tp, 0x15, 0x02d2); -+ mdio_write(tp, 0x19, 0xa51a); -+ mdio_write(tp, 0x15, 0x02d3); -+ mdio_write(tp, 0x19, 0x32d9); -+ mdio_write(tp, 0x15, 0x02d4); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02d5); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02d6); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02d7); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02d8); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02d9); -+ mdio_write(tp, 0x19, 0x48b3); -+ mdio_write(tp, 0x15, 0x02da); -+ mdio_write(tp, 0x19, 0x4020); -+ mdio_write(tp, 0x15, 0x02db); -+ mdio_write(tp, 0x19, 0x4823); -+ mdio_write(tp, 0x15, 0x02dc); -+ mdio_write(tp, 0x19, 0x4410); -+ mdio_write(tp, 0x15, 0x02dd); -+ mdio_write(tp, 0x19, 0xb630); -+ mdio_write(tp, 0x15, 0x02de); -+ mdio_write(tp, 0x19, 0x7dc8); -+ mdio_write(tp, 0x15, 0x02df); -+ mdio_write(tp, 0x19, 0x8203); -+ mdio_write(tp, 0x15, 0x02e0); -+ mdio_write(tp, 0x19, 0x4c48); -+ mdio_write(tp, 0x15, 0x02e1); -+ mdio_write(tp, 0x19, 0x32e3); -+ mdio_write(tp, 0x15, 0x02e2); -+ mdio_write(tp, 0x19, 0x4c40); -+ mdio_write(tp, 0x15, 0x02e3); -+ mdio_write(tp, 0x19, 0x9bfa); -+ mdio_write(tp, 0x15, 0x02e4); -+ mdio_write(tp, 0x19, 0x84ca); -+ mdio_write(tp, 0x15, 0x02e5); -+ mdio_write(tp, 0x19, 0x85f8); -+ mdio_write(tp, 0x15, 0x02e6); -+ mdio_write(tp, 0x19, 0x32ec); -+ mdio_write(tp, 0x15, 0x02e7); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02e8); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02e9); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02ea); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02eb); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x02ec); -+ mdio_write(tp, 0x19, 0x48d4); -+ mdio_write(tp, 0x15, 0x02ed); -+ mdio_write(tp, 0x19, 0x4020); -+ mdio_write(tp, 0x15, 0x02ee); -+ mdio_write(tp, 0x19, 0x4844); -+ mdio_write(tp, 0x15, 0x02ef); -+ mdio_write(tp, 0x19, 0x4420); -+ mdio_write(tp, 0x15, 0x02f0); -+ mdio_write(tp, 0x19, 0x6800); -+ mdio_write(tp, 0x15, 0x02f1); -+ mdio_write(tp, 0x19, 0x7dc0); -+ mdio_write(tp, 0x15, 0x02f2); -+ mdio_write(tp, 0x19, 0x4c40); -+ mdio_write(tp, 0x15, 0x02f3); -+ mdio_write(tp, 0x19, 0x7c0b); -+ mdio_write(tp, 0x15, 0x02f4); -+ mdio_write(tp, 0x19, 0x6c08); -+ mdio_write(tp, 0x15, 0x02f5); -+ mdio_write(tp, 0x19, 0x3311); -+ mdio_write(tp, 0x15, 0x02f6); -+ mdio_write(tp, 0x19, 0x9cfd); -+ mdio_write(tp, 0x15, 0x02f7); -+ mdio_write(tp, 0x19, 0xb616); -+ mdio_write(tp, 0x15, 0x02f8); -+ mdio_write(tp, 0x19, 0xc42b); -+ mdio_write(tp, 0x15, 0x02f9); -+ mdio_write(tp, 0x19, 0x00e0); -+ mdio_write(tp, 0x15, 0x02fa); -+ mdio_write(tp, 0x19, 0xc455); -+ mdio_write(tp, 0x15, 0x02fb); -+ mdio_write(tp, 0x19, 0x00b3); -+ mdio_write(tp, 0x15, 0x02fc); -+ mdio_write(tp, 0x19, 0xb20a); -+ mdio_write(tp, 0x15, 0x02fd); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x02fe); -+ mdio_write(tp, 0x19, 0x6c02); -+ mdio_write(tp, 0x15, 0x02ff); -+ mdio_write(tp, 0x19, 0x8204); -+ mdio_write(tp, 0x15, 0x0300); -+ mdio_write(tp, 0x19, 0x7c04); -+ mdio_write(tp, 0x15, 0x0301); -+ mdio_write(tp, 0x19, 0x7404); -+ mdio_write(tp, 0x15, 0x0302); -+ mdio_write(tp, 0x19, 0x32f3); -+ mdio_write(tp, 0x15, 0x0303); -+ mdio_write(tp, 0x19, 0x7c04); -+ mdio_write(tp, 0x15, 0x0304); -+ mdio_write(tp, 0x19, 0x7400); -+ mdio_write(tp, 0x15, 0x0305); -+ mdio_write(tp, 0x19, 0x32f3); -+ mdio_write(tp, 0x15, 0x0306); -+ mdio_write(tp, 0x19, 0xefed); -+ mdio_write(tp, 0x15, 0x0307); -+ mdio_write(tp, 0x19, 0x3342); -+ mdio_write(tp, 0x15, 0x0308); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0309); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x030a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x030b); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x030c); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x030d); -+ mdio_write(tp, 0x19, 0x3006); -+ mdio_write(tp, 0x15, 0x030e); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x030f); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0310); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0311); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x0312); -+ mdio_write(tp, 0x19, 0xa207); -+ mdio_write(tp, 0x15, 0x0313); -+ mdio_write(tp, 0x19, 0x4c00); -+ mdio_write(tp, 0x15, 0x0314); -+ mdio_write(tp, 0x19, 0x3322); -+ mdio_write(tp, 0x15, 0x0315); -+ mdio_write(tp, 0x19, 0x4041); -+ mdio_write(tp, 0x15, 0x0316); -+ mdio_write(tp, 0x19, 0x7d07); -+ mdio_write(tp, 0x15, 0x0317); -+ mdio_write(tp, 0x19, 0x4502); -+ mdio_write(tp, 0x15, 0x0318); -+ mdio_write(tp, 0x19, 0x3322); -+ mdio_write(tp, 0x15, 0x0319); -+ mdio_write(tp, 0x19, 0x4c08); -+ mdio_write(tp, 0x15, 0x031a); -+ mdio_write(tp, 0x19, 0x3322); -+ mdio_write(tp, 0x15, 0x031b); -+ mdio_write(tp, 0x19, 0x7d80); -+ mdio_write(tp, 0x15, 0x031c); -+ mdio_write(tp, 0x19, 0x5180); -+ mdio_write(tp, 0x15, 0x031d); -+ mdio_write(tp, 0x19, 0x3320); -+ mdio_write(tp, 0x15, 0x031e); -+ mdio_write(tp, 0x19, 0x7d80); -+ mdio_write(tp, 0x15, 0x031f); -+ mdio_write(tp, 0x19, 0x5000); -+ mdio_write(tp, 0x15, 0x0320); -+ mdio_write(tp, 0x19, 0x7d07); -+ mdio_write(tp, 0x15, 0x0321); -+ mdio_write(tp, 0x19, 0x4402); -+ mdio_write(tp, 0x15, 0x0322); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x0323); -+ mdio_write(tp, 0x19, 0x6c02); -+ mdio_write(tp, 0x15, 0x0324); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x0325); -+ mdio_write(tp, 0x19, 0xb30c); -+ mdio_write(tp, 0x15, 0x0326); -+ mdio_write(tp, 0x19, 0xb206); -+ mdio_write(tp, 0x15, 0x0327); -+ mdio_write(tp, 0x19, 0xb103); -+ mdio_write(tp, 0x15, 0x0328); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x0329); -+ mdio_write(tp, 0x19, 0x32f6); -+ mdio_write(tp, 0x15, 0x032a); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x032b); -+ mdio_write(tp, 0x19, 0x3352); -+ mdio_write(tp, 0x15, 0x032c); -+ mdio_write(tp, 0x19, 0xb103); -+ mdio_write(tp, 0x15, 0x032d); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x032e); -+ mdio_write(tp, 0x19, 0x336a); -+ mdio_write(tp, 0x15, 0x032f); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x0330); -+ mdio_write(tp, 0x19, 0x3382); -+ mdio_write(tp, 0x15, 0x0331); -+ mdio_write(tp, 0x19, 0xb206); -+ mdio_write(tp, 0x15, 0x0332); -+ mdio_write(tp, 0x19, 0xb103); -+ mdio_write(tp, 0x15, 0x0333); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x0334); -+ mdio_write(tp, 0x19, 0x3395); -+ mdio_write(tp, 0x15, 0x0335); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x0336); -+ mdio_write(tp, 0x19, 0x33c6); -+ mdio_write(tp, 0x15, 0x0337); -+ mdio_write(tp, 0x19, 0xb103); -+ mdio_write(tp, 0x15, 0x0338); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x0339); -+ mdio_write(tp, 0x19, 0x33d7); -+ mdio_write(tp, 0x15, 0x033a); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x033b); -+ mdio_write(tp, 0x19, 0x33f2); -+ mdio_write(tp, 0x15, 0x033c); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x033d); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x033e); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x033f); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0340); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0341); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0342); -+ mdio_write(tp, 0x19, 0x49b5); -+ mdio_write(tp, 0x15, 0x0343); -+ mdio_write(tp, 0x19, 0x7d00); -+ mdio_write(tp, 0x15, 0x0344); -+ mdio_write(tp, 0x19, 0x4d00); -+ mdio_write(tp, 0x15, 0x0345); -+ mdio_write(tp, 0x19, 0x6880); -+ mdio_write(tp, 0x15, 0x0346); -+ mdio_write(tp, 0x19, 0x7c08); -+ mdio_write(tp, 0x15, 0x0347); -+ mdio_write(tp, 0x19, 0x6c08); -+ mdio_write(tp, 0x15, 0x0348); -+ mdio_write(tp, 0x19, 0x4925); -+ mdio_write(tp, 0x15, 0x0349); -+ mdio_write(tp, 0x19, 0x403b); -+ mdio_write(tp, 0x15, 0x034a); -+ mdio_write(tp, 0x19, 0xa602); -+ mdio_write(tp, 0x15, 0x034b); -+ mdio_write(tp, 0x19, 0x402f); -+ mdio_write(tp, 0x15, 0x034c); -+ mdio_write(tp, 0x19, 0x4484); -+ mdio_write(tp, 0x15, 0x034d); -+ mdio_write(tp, 0x19, 0x40c8); -+ mdio_write(tp, 0x15, 0x034e); -+ mdio_write(tp, 0x19, 0x44c4); -+ mdio_write(tp, 0x15, 0x034f); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x0350); -+ mdio_write(tp, 0x19, 0x00bd); -+ mdio_write(tp, 0x15, 0x0351); -+ mdio_write(tp, 0x19, 0x3311); -+ mdio_write(tp, 0x15, 0x0352); -+ mdio_write(tp, 0x19, 0xc8ed); -+ mdio_write(tp, 0x15, 0x0353); -+ mdio_write(tp, 0x19, 0x00fc); -+ mdio_write(tp, 0x15, 0x0354); -+ mdio_write(tp, 0x19, 0x8221); -+ mdio_write(tp, 0x15, 0x0355); -+ mdio_write(tp, 0x19, 0xd11d); -+ mdio_write(tp, 0x15, 0x0356); -+ mdio_write(tp, 0x19, 0x001f); -+ mdio_write(tp, 0x15, 0x0357); -+ mdio_write(tp, 0x19, 0xde18); -+ mdio_write(tp, 0x15, 0x0358); -+ mdio_write(tp, 0x19, 0x0008); -+ mdio_write(tp, 0x15, 0x0359); -+ mdio_write(tp, 0x19, 0x91f6); -+ mdio_write(tp, 0x15, 0x035a); -+ mdio_write(tp, 0x19, 0x3360); -+ mdio_write(tp, 0x15, 0x035b); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x035c); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x035d); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x035e); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x035f); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0360); -+ mdio_write(tp, 0x19, 0x4bb6); -+ mdio_write(tp, 0x15, 0x0361); -+ mdio_write(tp, 0x19, 0x4064); -+ mdio_write(tp, 0x15, 0x0362); -+ mdio_write(tp, 0x19, 0x4b26); -+ mdio_write(tp, 0x15, 0x0363); -+ mdio_write(tp, 0x19, 0x4410); -+ mdio_write(tp, 0x15, 0x0364); -+ mdio_write(tp, 0x19, 0x4006); -+ mdio_write(tp, 0x15, 0x0365); -+ mdio_write(tp, 0x19, 0x4490); -+ mdio_write(tp, 0x15, 0x0366); -+ mdio_write(tp, 0x19, 0x6900); -+ mdio_write(tp, 0x15, 0x0367); -+ mdio_write(tp, 0x19, 0xb6a6); -+ mdio_write(tp, 0x15, 0x0368); -+ mdio_write(tp, 0x19, 0x9e02); -+ mdio_write(tp, 0x15, 0x0369); -+ mdio_write(tp, 0x19, 0x3311); -+ mdio_write(tp, 0x15, 0x036a); -+ mdio_write(tp, 0x19, 0xd11d); -+ mdio_write(tp, 0x15, 0x036b); -+ mdio_write(tp, 0x19, 0x000a); -+ mdio_write(tp, 0x15, 0x036c); -+ mdio_write(tp, 0x19, 0xbb0f); -+ mdio_write(tp, 0x15, 0x036d); -+ mdio_write(tp, 0x19, 0x8102); -+ mdio_write(tp, 0x15, 0x036e); -+ mdio_write(tp, 0x19, 0x3371); -+ mdio_write(tp, 0x15, 0x036f); -+ mdio_write(tp, 0x19, 0xa21e); -+ mdio_write(tp, 0x15, 0x0370); -+ mdio_write(tp, 0x19, 0x33b6); -+ mdio_write(tp, 0x15, 0x0371); -+ mdio_write(tp, 0x19, 0x91f6); -+ mdio_write(tp, 0x15, 0x0372); -+ mdio_write(tp, 0x19, 0xc218); -+ mdio_write(tp, 0x15, 0x0373); -+ mdio_write(tp, 0x19, 0x00f4); -+ mdio_write(tp, 0x15, 0x0374); -+ mdio_write(tp, 0x19, 0x33b6); -+ mdio_write(tp, 0x15, 0x0375); -+ mdio_write(tp, 0x19, 0x32ec); -+ mdio_write(tp, 0x15, 0x0376); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0377); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0378); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x0379); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x037a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x037b); -+ mdio_write(tp, 0x19, 0x4b97); -+ mdio_write(tp, 0x15, 0x037c); -+ mdio_write(tp, 0x19, 0x402b); -+ mdio_write(tp, 0x15, 0x037d); -+ mdio_write(tp, 0x19, 0x4b07); -+ mdio_write(tp, 0x15, 0x037e); -+ mdio_write(tp, 0x19, 0x4422); -+ mdio_write(tp, 0x15, 0x037f); -+ mdio_write(tp, 0x19, 0x6980); -+ mdio_write(tp, 0x15, 0x0380); -+ mdio_write(tp, 0x19, 0xb608); -+ mdio_write(tp, 0x15, 0x0381); -+ mdio_write(tp, 0x19, 0x3311); -+ mdio_write(tp, 0x15, 0x0382); -+ mdio_write(tp, 0x19, 0xbc05); -+ mdio_write(tp, 0x15, 0x0383); -+ mdio_write(tp, 0x19, 0xc21c); -+ mdio_write(tp, 0x15, 0x0384); -+ mdio_write(tp, 0x19, 0x0032); -+ mdio_write(tp, 0x15, 0x0385); -+ mdio_write(tp, 0x19, 0xa1fb); -+ mdio_write(tp, 0x15, 0x0386); -+ mdio_write(tp, 0x19, 0x338d); -+ mdio_write(tp, 0x15, 0x0387); -+ mdio_write(tp, 0x19, 0x32ae); -+ mdio_write(tp, 0x15, 0x0388); -+ mdio_write(tp, 0x19, 0x330d); -+ mdio_write(tp, 0x15, 0x0389); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x038a); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x038b); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x038c); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x038d); -+ mdio_write(tp, 0x19, 0x4b97); -+ mdio_write(tp, 0x15, 0x038e); -+ mdio_write(tp, 0x19, 0x6a08); -+ mdio_write(tp, 0x15, 0x038f); -+ mdio_write(tp, 0x19, 0x4b07); -+ mdio_write(tp, 0x15, 0x0390); -+ mdio_write(tp, 0x19, 0x40ac); -+ mdio_write(tp, 0x15, 0x0391); -+ mdio_write(tp, 0x19, 0x4445); -+ mdio_write(tp, 0x15, 0x0392); -+ mdio_write(tp, 0x19, 0x404e); -+ mdio_write(tp, 0x15, 0x0393); -+ mdio_write(tp, 0x19, 0x4461); -+ mdio_write(tp, 0x15, 0x0394); -+ mdio_write(tp, 0x19, 0x3311); -+ mdio_write(tp, 0x15, 0x0395); -+ mdio_write(tp, 0x19, 0x9c0a); -+ mdio_write(tp, 0x15, 0x0396); -+ mdio_write(tp, 0x19, 0x63da); -+ mdio_write(tp, 0x15, 0x0397); -+ mdio_write(tp, 0x19, 0x6f0c); -+ mdio_write(tp, 0x15, 0x0398); -+ mdio_write(tp, 0x19, 0x5440); -+ mdio_write(tp, 0x15, 0x0399); -+ mdio_write(tp, 0x19, 0x4b98); -+ mdio_write(tp, 0x15, 0x039a); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x039b); -+ mdio_write(tp, 0x19, 0x4c00); -+ mdio_write(tp, 0x15, 0x039c); -+ mdio_write(tp, 0x19, 0x4b08); -+ mdio_write(tp, 0x15, 0x039d); -+ mdio_write(tp, 0x19, 0x63d8); -+ mdio_write(tp, 0x15, 0x039e); -+ mdio_write(tp, 0x19, 0x33a5); -+ mdio_write(tp, 0x15, 0x039f); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x03a0); -+ mdio_write(tp, 0x19, 0x00e8); -+ mdio_write(tp, 0x15, 0x03a1); -+ mdio_write(tp, 0x19, 0x820e); -+ mdio_write(tp, 0x15, 0x03a2); -+ mdio_write(tp, 0x19, 0xa10d); -+ mdio_write(tp, 0x15, 0x03a3); -+ mdio_write(tp, 0x19, 0x9df1); -+ mdio_write(tp, 0x15, 0x03a4); -+ mdio_write(tp, 0x19, 0x33af); -+ mdio_write(tp, 0x15, 0x03a5); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x03a6); -+ mdio_write(tp, 0x19, 0x00f9); -+ mdio_write(tp, 0x15, 0x03a7); -+ mdio_write(tp, 0x19, 0xc017); -+ mdio_write(tp, 0x15, 0x03a8); -+ mdio_write(tp, 0x19, 0x0007); -+ mdio_write(tp, 0x15, 0x03a9); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x03aa); -+ mdio_write(tp, 0x19, 0x6c03); -+ mdio_write(tp, 0x15, 0x03ab); -+ mdio_write(tp, 0x19, 0xa104); -+ mdio_write(tp, 0x15, 0x03ac); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x03ad); -+ mdio_write(tp, 0x19, 0x6c00); -+ mdio_write(tp, 0x15, 0x03ae); -+ mdio_write(tp, 0x19, 0x9df7); -+ mdio_write(tp, 0x15, 0x03af); -+ mdio_write(tp, 0x19, 0x7c03); -+ mdio_write(tp, 0x15, 0x03b0); -+ mdio_write(tp, 0x19, 0x6c08); -+ mdio_write(tp, 0x15, 0x03b1); -+ mdio_write(tp, 0x19, 0x33b6); -+ mdio_write(tp, 0x15, 0x03b2); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03b3); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03b4); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03b5); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03b6); -+ mdio_write(tp, 0x19, 0x55af); -+ mdio_write(tp, 0x15, 0x03b7); -+ mdio_write(tp, 0x19, 0x7ff0); -+ mdio_write(tp, 0x15, 0x03b8); -+ mdio_write(tp, 0x19, 0x6ff0); -+ mdio_write(tp, 0x15, 0x03b9); -+ mdio_write(tp, 0x19, 0x4bb9); -+ mdio_write(tp, 0x15, 0x03ba); -+ mdio_write(tp, 0x19, 0x6a80); -+ mdio_write(tp, 0x15, 0x03bb); -+ mdio_write(tp, 0x19, 0x4b29); -+ mdio_write(tp, 0x15, 0x03bc); -+ mdio_write(tp, 0x19, 0x4041); -+ mdio_write(tp, 0x15, 0x03bd); -+ mdio_write(tp, 0x19, 0x440a); -+ mdio_write(tp, 0x15, 0x03be); -+ mdio_write(tp, 0x19, 0x4029); -+ mdio_write(tp, 0x15, 0x03bf); -+ mdio_write(tp, 0x19, 0x4418); -+ mdio_write(tp, 0x15, 0x03c0); -+ mdio_write(tp, 0x19, 0x4090); -+ mdio_write(tp, 0x15, 0x03c1); -+ mdio_write(tp, 0x19, 0x4438); -+ mdio_write(tp, 0x15, 0x03c2); -+ mdio_write(tp, 0x19, 0x40c4); -+ mdio_write(tp, 0x15, 0x03c3); -+ mdio_write(tp, 0x19, 0x447b); -+ mdio_write(tp, 0x15, 0x03c4); -+ mdio_write(tp, 0x19, 0xb6c4); -+ mdio_write(tp, 0x15, 0x03c5); -+ mdio_write(tp, 0x19, 0x3311); -+ mdio_write(tp, 0x15, 0x03c6); -+ mdio_write(tp, 0x19, 0x9bfe); -+ mdio_write(tp, 0x15, 0x03c7); -+ mdio_write(tp, 0x19, 0x33cc); -+ mdio_write(tp, 0x15, 0x03c8); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03c9); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03ca); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03cb); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03cc); -+ mdio_write(tp, 0x19, 0x542f); -+ mdio_write(tp, 0x15, 0x03cd); -+ mdio_write(tp, 0x19, 0x499a); -+ mdio_write(tp, 0x15, 0x03ce); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x03cf); -+ mdio_write(tp, 0x19, 0x4c40); -+ mdio_write(tp, 0x15, 0x03d0); -+ mdio_write(tp, 0x19, 0x490a); -+ mdio_write(tp, 0x15, 0x03d1); -+ mdio_write(tp, 0x19, 0x405e); -+ mdio_write(tp, 0x15, 0x03d2); -+ mdio_write(tp, 0x19, 0x44f8); -+ mdio_write(tp, 0x15, 0x03d3); -+ mdio_write(tp, 0x19, 0x6b00); -+ mdio_write(tp, 0x15, 0x03d4); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x03d5); -+ mdio_write(tp, 0x19, 0x0028); -+ mdio_write(tp, 0x15, 0x03d6); -+ mdio_write(tp, 0x19, 0x3311); -+ mdio_write(tp, 0x15, 0x03d7); -+ mdio_write(tp, 0x19, 0xbd27); -+ mdio_write(tp, 0x15, 0x03d8); -+ mdio_write(tp, 0x19, 0x9cfc); -+ mdio_write(tp, 0x15, 0x03d9); -+ mdio_write(tp, 0x19, 0xc639); -+ mdio_write(tp, 0x15, 0x03da); -+ mdio_write(tp, 0x19, 0x000f); -+ mdio_write(tp, 0x15, 0x03db); -+ mdio_write(tp, 0x19, 0x9e03); -+ mdio_write(tp, 0x15, 0x03dc); -+ mdio_write(tp, 0x19, 0x7c01); -+ mdio_write(tp, 0x15, 0x03dd); -+ mdio_write(tp, 0x19, 0x4c01); -+ mdio_write(tp, 0x15, 0x03de); -+ mdio_write(tp, 0x19, 0x9af6); -+ mdio_write(tp, 0x15, 0x03df); -+ mdio_write(tp, 0x19, 0x7c12); -+ mdio_write(tp, 0x15, 0x03e0); -+ mdio_write(tp, 0x19, 0x4c52); -+ mdio_write(tp, 0x15, 0x03e1); -+ mdio_write(tp, 0x19, 0x4470); -+ mdio_write(tp, 0x15, 0x03e2); -+ mdio_write(tp, 0x19, 0x7c12); -+ mdio_write(tp, 0x15, 0x03e3); -+ mdio_write(tp, 0x19, 0x4c40); -+ mdio_write(tp, 0x15, 0x03e4); -+ mdio_write(tp, 0x19, 0x33d4); -+ mdio_write(tp, 0x15, 0x03e5); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03e6); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03e7); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03e8); -+ mdio_write(tp, 0x19, 0x0000); -+ mdio_write(tp, 0x15, 0x03e9); -+ mdio_write(tp, 0x19, 0x49bb); -+ mdio_write(tp, 0x15, 0x03ea); -+ mdio_write(tp, 0x19, 0x4478); -+ mdio_write(tp, 0x15, 0x03eb); -+ mdio_write(tp, 0x19, 0x492b); -+ mdio_write(tp, 0x15, 0x03ec); -+ mdio_write(tp, 0x19, 0x6b80); -+ mdio_write(tp, 0x15, 0x03ed); -+ mdio_write(tp, 0x19, 0x7c01); -+ mdio_write(tp, 0x15, 0x03ee); -+ mdio_write(tp, 0x19, 0x4c00); -+ mdio_write(tp, 0x15, 0x03ef); -+ mdio_write(tp, 0x19, 0xd64f); -+ mdio_write(tp, 0x15, 0x03f0); -+ mdio_write(tp, 0x19, 0x000d); -+ mdio_write(tp, 0x15, 0x03f1); -+ mdio_write(tp, 0x19, 0x3311); -+ mdio_write(tp, 0x15, 0x03f2); -+ mdio_write(tp, 0x19, 0xbd0c); -+ mdio_write(tp, 0x15, 0x03f3); -+ mdio_write(tp, 0x19, 0xc428); -+ mdio_write(tp, 0x15, 0x03f4); -+ mdio_write(tp, 0x19, 0x0008); -+ mdio_write(tp, 0x15, 0x03f5); -+ mdio_write(tp, 0x19, 0x9afa); -+ mdio_write(tp, 0x15, 0x03f6); -+ mdio_write(tp, 0x19, 0x7c12); -+ mdio_write(tp, 0x15, 0x03f7); -+ mdio_write(tp, 0x19, 0x4c52); -+ mdio_write(tp, 0x15, 0x03f8); -+ mdio_write(tp, 0x19, 0x4470); -+ mdio_write(tp, 0x15, 0x03f9); -+ mdio_write(tp, 0x19, 0x7c12); -+ mdio_write(tp, 0x15, 0x03fa); -+ mdio_write(tp, 0x19, 0x4c40); -+ mdio_write(tp, 0x15, 0x03fb); -+ mdio_write(tp, 0x19, 0x33ef); -+ mdio_write(tp, 0x15, 0x03fc); -+ mdio_write(tp, 0x19, 0x3342); -+ mdio_write(tp, 0x15, 0x03fd); -+ mdio_write(tp, 0x19, 0x330d); -+ mdio_write(tp, 0x15, 0x03fe); -+ mdio_write(tp, 0x19, 0x32ae); -+ mdio_write(tp, 0x15, 0x0000); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0300); -+ mdio_write(tp, 0x1f, 0x0002); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ mdio_write(tp, 0x05, 0x8000); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0x48f7); -+ mdio_write(tp, 0x06, 0x00e0); -+ mdio_write(tp, 0x06, 0xfff7); -+ mdio_write(tp, 0x06, 0xa080); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0xf602); -+ mdio_write(tp, 0x06, 0x0112); -+ mdio_write(tp, 0x06, 0x0201); -+ mdio_write(tp, 0x06, 0x1f02); -+ mdio_write(tp, 0x06, 0x012c); -+ mdio_write(tp, 0x06, 0x0201); -+ mdio_write(tp, 0x06, 0x3c02); -+ mdio_write(tp, 0x06, 0x0156); -+ mdio_write(tp, 0x06, 0x0201); -+ mdio_write(tp, 0x06, 0x6d02); -+ mdio_write(tp, 0x06, 0x809d); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x88e1); -+ mdio_write(tp, 0x06, 0x8b89); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8a1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8b); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8c1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8e1e); -+ mdio_write(tp, 0x06, 0x01a0); -+ mdio_write(tp, 0x06, 0x00c7); -+ mdio_write(tp, 0x06, 0xaebb); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xc702); -+ mdio_write(tp, 0x06, 0x320a); -+ mdio_write(tp, 0x06, 0xd105); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xcd02); -+ mdio_write(tp, 0x06, 0x320a); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xca02); -+ mdio_write(tp, 0x06, 0x320a); -+ mdio_write(tp, 0x06, 0xd105); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xd002); -+ mdio_write(tp, 0x06, 0x320a); -+ mdio_write(tp, 0x06, 0xd481); -+ mdio_write(tp, 0x06, 0xc9e4); -+ mdio_write(tp, 0x06, 0x8b90); -+ mdio_write(tp, 0x06, 0xe58b); -+ mdio_write(tp, 0x06, 0x91d4); -+ mdio_write(tp, 0x06, 0x81b8); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x92e5); -+ mdio_write(tp, 0x06, 0x8b93); -+ mdio_write(tp, 0x06, 0xbf8b); -+ mdio_write(tp, 0x06, 0x88ec); -+ mdio_write(tp, 0x06, 0x0019); -+ mdio_write(tp, 0x06, 0xa98b); -+ mdio_write(tp, 0x06, 0x90f9); -+ mdio_write(tp, 0x06, 0xeeff); -+ mdio_write(tp, 0x06, 0xf600); -+ mdio_write(tp, 0x06, 0xeeff); -+ mdio_write(tp, 0x06, 0xf7fc); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xc102); -+ mdio_write(tp, 0x06, 0x320a); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xc402); -+ mdio_write(tp, 0x06, 0x320a); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x201a); -+ mdio_write(tp, 0x06, 0xf620); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x824b); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0x1902); -+ mdio_write(tp, 0x06, 0x2c9d); -+ mdio_write(tp, 0x06, 0x0203); -+ mdio_write(tp, 0x06, 0x9602); -+ mdio_write(tp, 0x06, 0x0473); -+ mdio_write(tp, 0x06, 0x022e); -+ mdio_write(tp, 0x06, 0x3902); -+ mdio_write(tp, 0x06, 0x044d); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x210b); -+ mdio_write(tp, 0x06, 0xf621); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x0416); -+ mdio_write(tp, 0x06, 0x021b); -+ mdio_write(tp, 0x06, 0xa4e0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad22); -+ mdio_write(tp, 0x06, 0x05f6); -+ mdio_write(tp, 0x06, 0x22e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2305); -+ mdio_write(tp, 0x06, 0xf623); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8ee0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad24); -+ mdio_write(tp, 0x06, 0x05f6); -+ mdio_write(tp, 0x06, 0x24e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2505); -+ mdio_write(tp, 0x06, 0xf625); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8ee0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad26); -+ mdio_write(tp, 0x06, 0x08f6); -+ mdio_write(tp, 0x06, 0x26e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0xdae0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad27); -+ mdio_write(tp, 0x06, 0x05f6); -+ mdio_write(tp, 0x06, 0x27e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x0203); -+ mdio_write(tp, 0x06, 0x5cfc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x69e0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xad21); -+ mdio_write(tp, 0x06, 0x57e0); -+ mdio_write(tp, 0x06, 0xe022); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x2358); -+ mdio_write(tp, 0x06, 0xc059); -+ mdio_write(tp, 0x06, 0x021e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b3c); -+ mdio_write(tp, 0x06, 0x1f10); -+ mdio_write(tp, 0x06, 0x9e44); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x3cad); -+ mdio_write(tp, 0x06, 0x211d); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x84f7); -+ mdio_write(tp, 0x06, 0x29e5); -+ mdio_write(tp, 0x06, 0x8b84); -+ mdio_write(tp, 0x06, 0xac27); -+ mdio_write(tp, 0x06, 0x0dac); -+ mdio_write(tp, 0x06, 0x2605); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0x7fae); -+ mdio_write(tp, 0x06, 0x2b02); -+ mdio_write(tp, 0x06, 0x2c23); -+ mdio_write(tp, 0x06, 0xae26); -+ mdio_write(tp, 0x06, 0x022c); -+ mdio_write(tp, 0x06, 0x41ae); -+ mdio_write(tp, 0x06, 0x21e0); -+ mdio_write(tp, 0x06, 0x8b87); -+ mdio_write(tp, 0x06, 0xad22); -+ mdio_write(tp, 0x06, 0x18e0); -+ mdio_write(tp, 0x06, 0xfff7); -+ mdio_write(tp, 0x06, 0x58fc); -+ mdio_write(tp, 0x06, 0xe4ff); -+ mdio_write(tp, 0x06, 0xf7d1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x2eee); -+ mdio_write(tp, 0x06, 0x0232); -+ mdio_write(tp, 0x06, 0x0ad1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x82e8); -+ mdio_write(tp, 0x06, 0x0232); -+ mdio_write(tp, 0x06, 0x0a02); -+ mdio_write(tp, 0x06, 0x2bdf); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefc); -+ mdio_write(tp, 0x06, 0x04d0); -+ mdio_write(tp, 0x06, 0x0202); -+ mdio_write(tp, 0x06, 0x1e97); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x2228); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xd302); -+ mdio_write(tp, 0x06, 0x320a); -+ mdio_write(tp, 0x06, 0xd10c); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xd602); -+ mdio_write(tp, 0x06, 0x320a); -+ mdio_write(tp, 0x06, 0xd104); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xd902); -+ mdio_write(tp, 0x06, 0x320a); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xe802); -+ mdio_write(tp, 0x06, 0x320a); -+ mdio_write(tp, 0x06, 0xe0ff); -+ mdio_write(tp, 0x06, 0xf768); -+ mdio_write(tp, 0x06, 0x03e4); -+ mdio_write(tp, 0x06, 0xfff7); -+ mdio_write(tp, 0x06, 0xd004); -+ mdio_write(tp, 0x06, 0x0228); -+ mdio_write(tp, 0x06, 0x7a04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0xe234); -+ mdio_write(tp, 0x06, 0xe1e2); -+ mdio_write(tp, 0x06, 0x35f6); -+ mdio_write(tp, 0x06, 0x2be4); -+ mdio_write(tp, 0x06, 0xe234); -+ mdio_write(tp, 0x06, 0xe5e2); -+ mdio_write(tp, 0x06, 0x35fc); -+ mdio_write(tp, 0x06, 0x05f8); -+ mdio_write(tp, 0x06, 0xe0e2); -+ mdio_write(tp, 0x06, 0x34e1); -+ mdio_write(tp, 0x06, 0xe235); -+ mdio_write(tp, 0x06, 0xf72b); -+ mdio_write(tp, 0x06, 0xe4e2); -+ mdio_write(tp, 0x06, 0x34e5); -+ mdio_write(tp, 0x06, 0xe235); -+ mdio_write(tp, 0x06, 0xfc05); -+ mdio_write(tp, 0x06, 0xf8f9); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x69ac); -+ mdio_write(tp, 0x06, 0x1b4c); -+ mdio_write(tp, 0x06, 0xbf2e); -+ mdio_write(tp, 0x06, 0x3002); -+ mdio_write(tp, 0x06, 0x31dd); -+ mdio_write(tp, 0x06, 0xef01); -+ mdio_write(tp, 0x06, 0xe28a); -+ mdio_write(tp, 0x06, 0x76e4); -+ mdio_write(tp, 0x06, 0x8a76); -+ mdio_write(tp, 0x06, 0x1f12); -+ mdio_write(tp, 0x06, 0x9e3a); -+ mdio_write(tp, 0x06, 0xef12); -+ mdio_write(tp, 0x06, 0x5907); -+ mdio_write(tp, 0x06, 0x9f12); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b40); -+ mdio_write(tp, 0x06, 0xf721); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x40d0); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0x287a); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0x34fc); -+ mdio_write(tp, 0x06, 0xa000); -+ mdio_write(tp, 0x06, 0x1002); -+ mdio_write(tp, 0x06, 0x2dc3); -+ mdio_write(tp, 0x06, 0x022e); -+ mdio_write(tp, 0x06, 0x21e0); -+ mdio_write(tp, 0x06, 0x8b40); -+ mdio_write(tp, 0x06, 0xf621); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x40ae); -+ mdio_write(tp, 0x06, 0x0fbf); -+ mdio_write(tp, 0x06, 0x3fa5); -+ mdio_write(tp, 0x06, 0x0231); -+ mdio_write(tp, 0x06, 0x6cbf); -+ mdio_write(tp, 0x06, 0x3fa2); -+ mdio_write(tp, 0x06, 0x0231); -+ mdio_write(tp, 0x06, 0x6c02); -+ mdio_write(tp, 0x06, 0x2dc3); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0xe2f4); -+ mdio_write(tp, 0x06, 0xe1e2); -+ mdio_write(tp, 0x06, 0xf5e4); -+ mdio_write(tp, 0x06, 0x8a78); -+ mdio_write(tp, 0x06, 0xe58a); -+ mdio_write(tp, 0x06, 0x79ee); -+ mdio_write(tp, 0x06, 0xe2f4); -+ mdio_write(tp, 0x06, 0xd8ee); -+ mdio_write(tp, 0x06, 0xe2f5); -+ mdio_write(tp, 0x06, 0x20fc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x2065); -+ mdio_write(tp, 0x06, 0xd200); -+ mdio_write(tp, 0x06, 0xbf2e); -+ mdio_write(tp, 0x06, 0xe802); -+ mdio_write(tp, 0x06, 0x31dd); -+ mdio_write(tp, 0x06, 0x1e21); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xdf02); -+ mdio_write(tp, 0x06, 0x31dd); -+ mdio_write(tp, 0x06, 0x0c11); -+ mdio_write(tp, 0x06, 0x1e21); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xe202); -+ mdio_write(tp, 0x06, 0x31dd); -+ mdio_write(tp, 0x06, 0x0c12); -+ mdio_write(tp, 0x06, 0x1e21); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xe502); -+ mdio_write(tp, 0x06, 0x31dd); -+ mdio_write(tp, 0x06, 0x0c13); -+ mdio_write(tp, 0x06, 0x1e21); -+ mdio_write(tp, 0x06, 0xbf1f); -+ mdio_write(tp, 0x06, 0x5302); -+ mdio_write(tp, 0x06, 0x31dd); -+ mdio_write(tp, 0x06, 0x0c14); -+ mdio_write(tp, 0x06, 0x1e21); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0xeb02); -+ mdio_write(tp, 0x06, 0x31dd); -+ mdio_write(tp, 0x06, 0x0c16); -+ mdio_write(tp, 0x06, 0x1e21); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0xe01f); -+ mdio_write(tp, 0x06, 0x029e); -+ mdio_write(tp, 0x06, 0x22e6); -+ mdio_write(tp, 0x06, 0x83e0); -+ mdio_write(tp, 0x06, 0xad31); -+ mdio_write(tp, 0x06, 0x14ad); -+ mdio_write(tp, 0x06, 0x3011); -+ mdio_write(tp, 0x06, 0xef02); -+ mdio_write(tp, 0x06, 0x580c); -+ mdio_write(tp, 0x06, 0x9e07); -+ mdio_write(tp, 0x06, 0xad36); -+ mdio_write(tp, 0x06, 0x085a); -+ mdio_write(tp, 0x06, 0x309f); -+ mdio_write(tp, 0x06, 0x04d1); -+ mdio_write(tp, 0x06, 0x01ae); -+ mdio_write(tp, 0x06, 0x02d1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x82dc); -+ mdio_write(tp, 0x06, 0x0232); -+ mdio_write(tp, 0x06, 0x0aef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfdfc); -+ mdio_write(tp, 0x06, 0x0400); -+ mdio_write(tp, 0x06, 0xe140); -+ mdio_write(tp, 0x06, 0x77e1); -+ mdio_write(tp, 0x06, 0x4010); -+ mdio_write(tp, 0x06, 0xe150); -+ mdio_write(tp, 0x06, 0x32e1); -+ mdio_write(tp, 0x06, 0x5030); -+ mdio_write(tp, 0x06, 0xe144); -+ mdio_write(tp, 0x06, 0x74e1); -+ mdio_write(tp, 0x06, 0x44bb); -+ mdio_write(tp, 0x06, 0xe2d2); -+ mdio_write(tp, 0x06, 0x40e0); -+ mdio_write(tp, 0x06, 0x2cfc); -+ mdio_write(tp, 0x06, 0xe2cc); -+ mdio_write(tp, 0x06, 0xcce2); -+ mdio_write(tp, 0x06, 0x00cc); -+ mdio_write(tp, 0x06, 0xe000); -+ mdio_write(tp, 0x06, 0x99e0); -+ mdio_write(tp, 0x06, 0x3688); -+ mdio_write(tp, 0x06, 0xe036); -+ mdio_write(tp, 0x06, 0x99e1); -+ mdio_write(tp, 0x06, 0x40dd); -+ mdio_write(tp, 0x06, 0xe022); -+ mdio_write(tp, 0x05, 0xe142); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x05, 0xe140); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1f, 0x0005); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x00); -+ if (gphy_val & BIT_7) -+ break; -+ } -+ mdio_write(tp, 0x1f, 0x0004); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ gphy_val = mdio_read(tp, 0x17); -+ gphy_val &= ~(BIT_0); -+ gphy_val |= BIT_2; -+ mdio_write(tp, 0x17, gphy_val); -+ mdio_write(tp, 0x1f, 0x0002); -+ mdio_write(tp, 0x1f, 0x0000); -+} -+ -+static void -+rtl8168_set_phy_mcu_8168evl_2(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ struct pci_dev *pdev = tp->pci_dev; -+ unsigned int gphy_val,i; -+ -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x00, 0x1800); -+ gphy_val = mdio_read(tp, 0x15); -+ gphy_val &= ~(BIT_12); -+ mdio_write(tp, 0x15, gphy_val); -+ mdio_write(tp, 0x00, 0x4800); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x002f); -+ for (i = 0; i < 1000; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x1c); -+ if ((gphy_val & 0x0080) == 0x0080) -+ break; -+ } -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x00, 0x1800); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x17); -+ if (!(gphy_val & 0x0001)) -+ break; -+ } -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0307); -+ mdio_write(tp, 0x15, 0x00AF); -+ mdio_write(tp, 0x19, 0x4060); -+ mdio_write(tp, 0x15, 0x00B0); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x00B1); -+ mdio_write(tp, 0x19, 0x7e00); -+ mdio_write(tp, 0x15, 0x00B2); -+ mdio_write(tp, 0x19, 0x72B0); -+ mdio_write(tp, 0x15, 0x00B3); -+ mdio_write(tp, 0x19, 0x7F00); -+ mdio_write(tp, 0x15, 0x00B4); -+ mdio_write(tp, 0x19, 0x73B0); -+ mdio_write(tp, 0x15, 0x0101); -+ mdio_write(tp, 0x19, 0x0005); -+ mdio_write(tp, 0x15, 0x0103); -+ mdio_write(tp, 0x19, 0x0003); -+ mdio_write(tp, 0x15, 0x0105); -+ mdio_write(tp, 0x19, 0x30FD); -+ mdio_write(tp, 0x15, 0x0106); -+ mdio_write(tp, 0x19, 0x9DF7); -+ mdio_write(tp, 0x15, 0x0107); -+ mdio_write(tp, 0x19, 0x30C6); -+ mdio_write(tp, 0x15, 0x0098); -+ mdio_write(tp, 0x19, 0x7c0b); -+ mdio_write(tp, 0x15, 0x0099); -+ mdio_write(tp, 0x19, 0x6c0b); -+ mdio_write(tp, 0x15, 0x00eb); -+ mdio_write(tp, 0x19, 0x6c0b); -+ mdio_write(tp, 0x15, 0x00f8); -+ mdio_write(tp, 0x19, 0x6f0b); -+ mdio_write(tp, 0x15, 0x00fe); -+ mdio_write(tp, 0x19, 0x6f0f); -+ mdio_write(tp, 0x15, 0x00db); -+ mdio_write(tp, 0x19, 0x6f09); -+ mdio_write(tp, 0x15, 0x00dc); -+ mdio_write(tp, 0x19, 0xaefd); -+ mdio_write(tp, 0x15, 0x00dd); -+ mdio_write(tp, 0x19, 0x6f0b); -+ mdio_write(tp, 0x15, 0x00de); -+ mdio_write(tp, 0x19, 0xc60b); -+ mdio_write(tp, 0x15, 0x00df); -+ mdio_write(tp, 0x19, 0x00fa); -+ mdio_write(tp, 0x15, 0x00e0); -+ mdio_write(tp, 0x19, 0x30e1); -+ mdio_write(tp, 0x15, 0x020c); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x020e); -+ mdio_write(tp, 0x19, 0x9813); -+ mdio_write(tp, 0x15, 0x020f); -+ mdio_write(tp, 0x19, 0x7801); -+ mdio_write(tp, 0x15, 0x0210); -+ mdio_write(tp, 0x19, 0x930f); -+ mdio_write(tp, 0x15, 0x0211); -+ mdio_write(tp, 0x19, 0x9206); -+ mdio_write(tp, 0x15, 0x0212); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x0213); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0214); -+ mdio_write(tp, 0x19, 0x588f); -+ mdio_write(tp, 0x15, 0x0215); -+ mdio_write(tp, 0x19, 0x5520); -+ mdio_write(tp, 0x15, 0x0216); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x0217); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x0218); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0219); -+ mdio_write(tp, 0x19, 0x588d); -+ mdio_write(tp, 0x15, 0x021a); -+ mdio_write(tp, 0x19, 0x5540); -+ mdio_write(tp, 0x15, 0x021b); -+ mdio_write(tp, 0x19, 0x9e03); -+ mdio_write(tp, 0x15, 0x021c); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x021d); -+ mdio_write(tp, 0x19, 0x6840); -+ mdio_write(tp, 0x15, 0x021e); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x021f); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x0220); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x0221); -+ mdio_write(tp, 0x19, 0x9e03); -+ mdio_write(tp, 0x15, 0x0222); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x0223); -+ mdio_write(tp, 0x19, 0x6840); -+ mdio_write(tp, 0x15, 0x0224); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0225); -+ mdio_write(tp, 0x19, 0x3231); -+ mdio_write(tp, 0x15, 0x0000); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0300); -+ mdio_write(tp, 0x1f, 0x0002); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x17, 0x2160); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0040); -+ mdio_write(tp, 0x18, 0x0004); -+ if (pdev->subsystem_vendor == 0x144d && -+ pdev->subsystem_device == 0xc0a6) { -+ mdio_write(tp, 0x18, 0x0724); -+ mdio_write(tp, 0x19, 0xfe00); -+ mdio_write(tp, 0x18, 0x0734); -+ mdio_write(tp, 0x19, 0xfd00); -+ mdio_write(tp, 0x18, 0x1824); -+ mdio_write(tp, 0x19, 0xfc00); -+ mdio_write(tp, 0x18, 0x1834); -+ mdio_write(tp, 0x19, 0xfd00); -+ } -+ mdio_write(tp, 0x18, 0x09d4); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x18, 0x09e4); -+ mdio_write(tp, 0x19, 0x0800); -+ mdio_write(tp, 0x18, 0x09f4); -+ mdio_write(tp, 0x19, 0xff00); -+ mdio_write(tp, 0x18, 0x0a04); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x18, 0x0a14); -+ mdio_write(tp, 0x19, 0x0c00); -+ mdio_write(tp, 0x18, 0x0a24); -+ mdio_write(tp, 0x19, 0xff00); -+ mdio_write(tp, 0x18, 0x0a74); -+ mdio_write(tp, 0x19, 0xf600); -+ mdio_write(tp, 0x18, 0x1a24); -+ mdio_write(tp, 0x19, 0x7d00); -+ mdio_write(tp, 0x18, 0x1a64); -+ mdio_write(tp, 0x19, 0x0500); -+ mdio_write(tp, 0x18, 0x1a74); -+ mdio_write(tp, 0x19, 0x9500); -+ mdio_write(tp, 0x18, 0x1a84); -+ mdio_write(tp, 0x19, 0x8000); -+ mdio_write(tp, 0x18, 0x1a94); -+ mdio_write(tp, 0x19, 0x7d00); -+ mdio_write(tp, 0x18, 0x1aa4); -+ mdio_write(tp, 0x19, 0x9600); -+ mdio_write(tp, 0x18, 0x1ac4); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x18, 0x1ad4); -+ mdio_write(tp, 0x19, 0x0800); -+ mdio_write(tp, 0x18, 0x1af4); -+ mdio_write(tp, 0x19, 0xc400); -+ mdio_write(tp, 0x18, 0x1b04); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x18, 0x1b14); -+ mdio_write(tp, 0x19, 0x0800); -+ mdio_write(tp, 0x18, 0x1b24); -+ mdio_write(tp, 0x19, 0xfd00); -+ mdio_write(tp, 0x18, 0x1b34); -+ mdio_write(tp, 0x19, 0x4000); -+ mdio_write(tp, 0x18, 0x1b44); -+ mdio_write(tp, 0x19, 0x0400); -+ mdio_write(tp, 0x18, 0x1b94); -+ mdio_write(tp, 0x19, 0xf100); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x17, 0x2100); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0040); -+ mdio_write(tp, 0x18, 0x0000); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ mdio_write(tp, 0x05, 0x8000); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0x48f7); -+ mdio_write(tp, 0x06, 0x00e0); -+ mdio_write(tp, 0x06, 0xfff7); -+ mdio_write(tp, 0x06, 0xa080); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0xf602); -+ mdio_write(tp, 0x06, 0x0115); -+ mdio_write(tp, 0x06, 0x0201); -+ mdio_write(tp, 0x06, 0x2202); -+ mdio_write(tp, 0x06, 0x80a0); -+ mdio_write(tp, 0x06, 0x0201); -+ mdio_write(tp, 0x06, 0x3f02); -+ mdio_write(tp, 0x06, 0x0159); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0xbd02); -+ mdio_write(tp, 0x06, 0x80da); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x88e1); -+ mdio_write(tp, 0x06, 0x8b89); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8a1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8b); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8c1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8e1e); -+ mdio_write(tp, 0x06, 0x01a0); -+ mdio_write(tp, 0x06, 0x00c7); -+ mdio_write(tp, 0x06, 0xaebb); -+ mdio_write(tp, 0x06, 0xd481); -+ mdio_write(tp, 0x06, 0xd2e4); -+ mdio_write(tp, 0x06, 0x8b92); -+ mdio_write(tp, 0x06, 0xe58b); -+ mdio_write(tp, 0x06, 0x93d1); -+ mdio_write(tp, 0x06, 0x03bf); -+ mdio_write(tp, 0x06, 0x859e); -+ mdio_write(tp, 0x06, 0x0237); -+ mdio_write(tp, 0x06, 0x23d1); -+ mdio_write(tp, 0x06, 0x02bf); -+ mdio_write(tp, 0x06, 0x85a1); -+ mdio_write(tp, 0x06, 0x0237); -+ mdio_write(tp, 0x06, 0x23ee); -+ mdio_write(tp, 0x06, 0x8608); -+ mdio_write(tp, 0x06, 0x03ee); -+ mdio_write(tp, 0x06, 0x860a); -+ mdio_write(tp, 0x06, 0x60ee); -+ mdio_write(tp, 0x06, 0x8610); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8611); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8abe); -+ mdio_write(tp, 0x06, 0x07ee); -+ mdio_write(tp, 0x06, 0x8abf); -+ mdio_write(tp, 0x06, 0x73ee); -+ mdio_write(tp, 0x06, 0x8a95); -+ mdio_write(tp, 0x06, 0x02bf); -+ mdio_write(tp, 0x06, 0x8b88); -+ mdio_write(tp, 0x06, 0xec00); -+ mdio_write(tp, 0x06, 0x19a9); -+ mdio_write(tp, 0x06, 0x8b90); -+ mdio_write(tp, 0x06, 0xf9ee); -+ mdio_write(tp, 0x06, 0xfff6); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0xfff7); -+ mdio_write(tp, 0x06, 0xfed1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x8595); -+ mdio_write(tp, 0x06, 0x0237); -+ mdio_write(tp, 0x06, 0x23d1); -+ mdio_write(tp, 0x06, 0x01bf); -+ mdio_write(tp, 0x06, 0x8598); -+ mdio_write(tp, 0x06, 0x0237); -+ mdio_write(tp, 0x06, 0x2304); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b8a); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x14ee); -+ mdio_write(tp, 0x06, 0x8b8a); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x1f9a); -+ mdio_write(tp, 0x06, 0xe0e4); -+ mdio_write(tp, 0x06, 0x26e1); -+ mdio_write(tp, 0x06, 0xe427); -+ mdio_write(tp, 0x06, 0xeee4); -+ mdio_write(tp, 0x06, 0x2623); -+ mdio_write(tp, 0x06, 0xe5e4); -+ mdio_write(tp, 0x06, 0x27fc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8dad); -+ mdio_write(tp, 0x06, 0x2014); -+ mdio_write(tp, 0x06, 0xee8b); -+ mdio_write(tp, 0x06, 0x8d00); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0x5a78); -+ mdio_write(tp, 0x06, 0x039e); -+ mdio_write(tp, 0x06, 0x0902); -+ mdio_write(tp, 0x06, 0x05db); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0x7b02); -+ mdio_write(tp, 0x06, 0x3231); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x1df6); -+ mdio_write(tp, 0x06, 0x20e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0x5c02); -+ mdio_write(tp, 0x06, 0x2bcb); -+ mdio_write(tp, 0x06, 0x022d); -+ mdio_write(tp, 0x06, 0x2902); -+ mdio_write(tp, 0x06, 0x03b4); -+ mdio_write(tp, 0x06, 0x0285); -+ mdio_write(tp, 0x06, 0x6402); -+ mdio_write(tp, 0x06, 0x2eca); -+ mdio_write(tp, 0x06, 0x0284); -+ mdio_write(tp, 0x06, 0xcd02); -+ mdio_write(tp, 0x06, 0x046f); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x210b); -+ mdio_write(tp, 0x06, 0xf621); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x8520); -+ mdio_write(tp, 0x06, 0x021b); -+ mdio_write(tp, 0x06, 0xe8e0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad22); -+ mdio_write(tp, 0x06, 0x05f6); -+ mdio_write(tp, 0x06, 0x22e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2308); -+ mdio_write(tp, 0x06, 0xf623); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x311c); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2405); -+ mdio_write(tp, 0x06, 0xf624); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8ee0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad25); -+ mdio_write(tp, 0x06, 0x05f6); -+ mdio_write(tp, 0x06, 0x25e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2608); -+ mdio_write(tp, 0x06, 0xf626); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x2df5); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2705); -+ mdio_write(tp, 0x06, 0xf627); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x037a); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8f9); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x69e0); -+ mdio_write(tp, 0x06, 0x8b87); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x65d2); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x2fe9); -+ mdio_write(tp, 0x06, 0x0236); -+ mdio_write(tp, 0x06, 0xf61e); -+ mdio_write(tp, 0x06, 0x21bf); -+ mdio_write(tp, 0x06, 0x2ff5); -+ mdio_write(tp, 0x06, 0x0236); -+ mdio_write(tp, 0x06, 0xf60c); -+ mdio_write(tp, 0x06, 0x111e); -+ mdio_write(tp, 0x06, 0x21bf); -+ mdio_write(tp, 0x06, 0x2ff8); -+ mdio_write(tp, 0x06, 0x0236); -+ mdio_write(tp, 0x06, 0xf60c); -+ mdio_write(tp, 0x06, 0x121e); -+ mdio_write(tp, 0x06, 0x21bf); -+ mdio_write(tp, 0x06, 0x2ffb); -+ mdio_write(tp, 0x06, 0x0236); -+ mdio_write(tp, 0x06, 0xf60c); -+ mdio_write(tp, 0x06, 0x131e); -+ mdio_write(tp, 0x06, 0x21bf); -+ mdio_write(tp, 0x06, 0x1f97); -+ mdio_write(tp, 0x06, 0x0236); -+ mdio_write(tp, 0x06, 0xf60c); -+ mdio_write(tp, 0x06, 0x141e); -+ mdio_write(tp, 0x06, 0x21bf); -+ mdio_write(tp, 0x06, 0x859b); -+ mdio_write(tp, 0x06, 0x0236); -+ mdio_write(tp, 0x06, 0xf60c); -+ mdio_write(tp, 0x06, 0x161e); -+ mdio_write(tp, 0x06, 0x21e0); -+ mdio_write(tp, 0x06, 0x8a8c); -+ mdio_write(tp, 0x06, 0x1f02); -+ mdio_write(tp, 0x06, 0x9e22); -+ mdio_write(tp, 0x06, 0xe68a); -+ mdio_write(tp, 0x06, 0x8cad); -+ mdio_write(tp, 0x06, 0x3114); -+ mdio_write(tp, 0x06, 0xad30); -+ mdio_write(tp, 0x06, 0x11ef); -+ mdio_write(tp, 0x06, 0x0258); -+ mdio_write(tp, 0x06, 0x0c9e); -+ mdio_write(tp, 0x06, 0x07ad); -+ mdio_write(tp, 0x06, 0x3608); -+ mdio_write(tp, 0x06, 0x5a30); -+ mdio_write(tp, 0x06, 0x9f04); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xae02); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf2f); -+ mdio_write(tp, 0x06, 0xf202); -+ mdio_write(tp, 0x06, 0x3723); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8f9); -+ mdio_write(tp, 0x06, 0xface); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x69fa); -+ mdio_write(tp, 0x06, 0xd401); -+ mdio_write(tp, 0x06, 0x55b4); -+ mdio_write(tp, 0x06, 0xfebf); -+ mdio_write(tp, 0x06, 0x85a7); -+ mdio_write(tp, 0x06, 0x0236); -+ mdio_write(tp, 0x06, 0xf6ac); -+ mdio_write(tp, 0x06, 0x280b); -+ mdio_write(tp, 0x06, 0xbf85); -+ mdio_write(tp, 0x06, 0xa402); -+ mdio_write(tp, 0x06, 0x36f6); -+ mdio_write(tp, 0x06, 0xac28); -+ mdio_write(tp, 0x06, 0x49ae); -+ mdio_write(tp, 0x06, 0x64bf); -+ mdio_write(tp, 0x06, 0x85a4); -+ mdio_write(tp, 0x06, 0x0236); -+ mdio_write(tp, 0x06, 0xf6ac); -+ mdio_write(tp, 0x06, 0x285b); -+ mdio_write(tp, 0x06, 0xd000); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0x60ac); -+ mdio_write(tp, 0x06, 0x2105); -+ mdio_write(tp, 0x06, 0xac22); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x4ebf); -+ mdio_write(tp, 0x06, 0xe0c4); -+ mdio_write(tp, 0x06, 0xbe86); -+ mdio_write(tp, 0x06, 0x14d2); -+ mdio_write(tp, 0x06, 0x04d8); -+ mdio_write(tp, 0x06, 0x19d9); -+ mdio_write(tp, 0x06, 0x1907); -+ mdio_write(tp, 0x06, 0xdc19); -+ mdio_write(tp, 0x06, 0xdd19); -+ mdio_write(tp, 0x06, 0x0789); -+ mdio_write(tp, 0x06, 0x89ef); -+ mdio_write(tp, 0x06, 0x645e); -+ mdio_write(tp, 0x06, 0x07ff); -+ mdio_write(tp, 0x06, 0x0d65); -+ mdio_write(tp, 0x06, 0x5cf8); -+ mdio_write(tp, 0x06, 0x001e); -+ mdio_write(tp, 0x06, 0x46dc); -+ mdio_write(tp, 0x06, 0x19dd); -+ mdio_write(tp, 0x06, 0x19b2); -+ mdio_write(tp, 0x06, 0xe2d4); -+ mdio_write(tp, 0x06, 0x0001); -+ mdio_write(tp, 0x06, 0xbf85); -+ mdio_write(tp, 0x06, 0xa402); -+ mdio_write(tp, 0x06, 0x3723); -+ mdio_write(tp, 0x06, 0xae1d); -+ mdio_write(tp, 0x06, 0xbee0); -+ mdio_write(tp, 0x06, 0xc4bf); -+ mdio_write(tp, 0x06, 0x8614); -+ mdio_write(tp, 0x06, 0xd204); -+ mdio_write(tp, 0x06, 0xd819); -+ mdio_write(tp, 0x06, 0xd919); -+ mdio_write(tp, 0x06, 0x07dc); -+ mdio_write(tp, 0x06, 0x19dd); -+ mdio_write(tp, 0x06, 0x1907); -+ mdio_write(tp, 0x06, 0xb2f4); -+ mdio_write(tp, 0x06, 0xd400); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x85a4); -+ mdio_write(tp, 0x06, 0x0237); -+ mdio_write(tp, 0x06, 0x23fe); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfec6); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc05); -+ mdio_write(tp, 0x06, 0xf9e2); -+ mdio_write(tp, 0x06, 0xe0ea); -+ mdio_write(tp, 0x06, 0xe3e0); -+ mdio_write(tp, 0x06, 0xeb5a); -+ mdio_write(tp, 0x06, 0x070c); -+ mdio_write(tp, 0x06, 0x031e); -+ mdio_write(tp, 0x06, 0x20e6); -+ mdio_write(tp, 0x06, 0xe0ea); -+ mdio_write(tp, 0x06, 0xe7e0); -+ mdio_write(tp, 0x06, 0xebe0); -+ mdio_write(tp, 0x06, 0xe0fc); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0xfdfd); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9e0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xac26); -+ mdio_write(tp, 0x06, 0x1ae0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xac21); -+ mdio_write(tp, 0x06, 0x14e0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xac20); -+ mdio_write(tp, 0x06, 0x0ee0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xac23); -+ mdio_write(tp, 0x06, 0x08e0); -+ mdio_write(tp, 0x06, 0x8b87); -+ mdio_write(tp, 0x06, 0xac24); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x3802); -+ mdio_write(tp, 0x06, 0x1ab5); -+ mdio_write(tp, 0x06, 0xeee4); -+ mdio_write(tp, 0x06, 0x1c04); -+ mdio_write(tp, 0x06, 0xeee4); -+ mdio_write(tp, 0x06, 0x1d04); -+ mdio_write(tp, 0x06, 0xe2e0); -+ mdio_write(tp, 0x06, 0x7ce3); -+ mdio_write(tp, 0x06, 0xe07d); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x38e1); -+ mdio_write(tp, 0x06, 0xe039); -+ mdio_write(tp, 0x06, 0xad2e); -+ mdio_write(tp, 0x06, 0x1bad); -+ mdio_write(tp, 0x06, 0x390d); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xbf21); -+ mdio_write(tp, 0x06, 0xd502); -+ mdio_write(tp, 0x06, 0x3723); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0xd8ae); -+ mdio_write(tp, 0x06, 0x0bac); -+ mdio_write(tp, 0x06, 0x3802); -+ mdio_write(tp, 0x06, 0xae06); -+ mdio_write(tp, 0x06, 0x0283); -+ mdio_write(tp, 0x06, 0x1802); -+ mdio_write(tp, 0x06, 0x8360); -+ mdio_write(tp, 0x06, 0x021a); -+ mdio_write(tp, 0x06, 0xc6fd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e1); -+ mdio_write(tp, 0x06, 0x8af4); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x2605); -+ mdio_write(tp, 0x06, 0x0222); -+ mdio_write(tp, 0x06, 0xa4f7); -+ mdio_write(tp, 0x06, 0x28e0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xad21); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0x23a9); -+ mdio_write(tp, 0x06, 0xf729); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x85ad); -+ mdio_write(tp, 0x06, 0x2005); -+ mdio_write(tp, 0x06, 0x0214); -+ mdio_write(tp, 0x06, 0xabf7); -+ mdio_write(tp, 0x06, 0x2ae0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xad23); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0x12e7); -+ mdio_write(tp, 0x06, 0xf72b); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x2405); -+ mdio_write(tp, 0x06, 0x0283); -+ mdio_write(tp, 0x06, 0xbcf7); -+ mdio_write(tp, 0x06, 0x2ce5); -+ mdio_write(tp, 0x06, 0x8af4); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xad26); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0x21e5); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x2109); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xf4ac); -+ mdio_write(tp, 0x06, 0x2003); -+ mdio_write(tp, 0x06, 0x0223); -+ mdio_write(tp, 0x06, 0x98e0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x09e0); -+ mdio_write(tp, 0x06, 0x8af4); -+ mdio_write(tp, 0x06, 0xac21); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0x13fb); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x85ad); -+ mdio_write(tp, 0x06, 0x2309); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xf4ac); -+ mdio_write(tp, 0x06, 0x2203); -+ mdio_write(tp, 0x06, 0x0212); -+ mdio_write(tp, 0x06, 0xfae0); -+ mdio_write(tp, 0x06, 0x8b87); -+ mdio_write(tp, 0x06, 0xad24); -+ mdio_write(tp, 0x06, 0x09e0); -+ mdio_write(tp, 0x06, 0x8af4); -+ mdio_write(tp, 0x06, 0xac23); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0x83c1); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e1); -+ mdio_write(tp, 0x06, 0x8af4); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x2608); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0xd2ad); -+ mdio_write(tp, 0x06, 0x2502); -+ mdio_write(tp, 0x06, 0xf628); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x210a); -+ mdio_write(tp, 0x06, 0xe084); -+ mdio_write(tp, 0x06, 0x0af6); -+ mdio_write(tp, 0x06, 0x27a0); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0xf629); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x85ad); -+ mdio_write(tp, 0x06, 0x2008); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xe8ad); -+ mdio_write(tp, 0x06, 0x2102); -+ mdio_write(tp, 0x06, 0xf62a); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x85ad); -+ mdio_write(tp, 0x06, 0x2308); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x20a0); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0xf62b); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x2408); -+ mdio_write(tp, 0x06, 0xe086); -+ mdio_write(tp, 0x06, 0x02a0); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0xf62c); -+ mdio_write(tp, 0x06, 0xe58a); -+ mdio_write(tp, 0x06, 0xf4a1); -+ mdio_write(tp, 0x06, 0x0008); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf21); -+ mdio_write(tp, 0x06, 0xd502); -+ mdio_write(tp, 0x06, 0x3723); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x0200); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x241e); -+ mdio_write(tp, 0x06, 0xe086); -+ mdio_write(tp, 0x06, 0x02a0); -+ mdio_write(tp, 0x06, 0x0005); -+ mdio_write(tp, 0x06, 0x0283); -+ mdio_write(tp, 0x06, 0xe8ae); -+ mdio_write(tp, 0x06, 0xf5a0); -+ mdio_write(tp, 0x06, 0x0105); -+ mdio_write(tp, 0x06, 0x0283); -+ mdio_write(tp, 0x06, 0xf8ae); -+ mdio_write(tp, 0x06, 0x0ba0); -+ mdio_write(tp, 0x06, 0x0205); -+ mdio_write(tp, 0x06, 0x0284); -+ mdio_write(tp, 0x06, 0x14ae); -+ mdio_write(tp, 0x06, 0x03a0); -+ mdio_write(tp, 0x06, 0x0300); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0x0284); -+ mdio_write(tp, 0x06, 0x2bee); -+ mdio_write(tp, 0x06, 0x8602); -+ mdio_write(tp, 0x06, 0x01ef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8ee); -+ mdio_write(tp, 0x06, 0x8609); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x8461); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xae10); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8608); -+ mdio_write(tp, 0x06, 0xe186); -+ mdio_write(tp, 0x06, 0x091f); -+ mdio_write(tp, 0x06, 0x019e); -+ mdio_write(tp, 0x06, 0x0611); -+ mdio_write(tp, 0x06, 0xe586); -+ mdio_write(tp, 0x06, 0x09ae); -+ mdio_write(tp, 0x06, 0x04ee); -+ mdio_write(tp, 0x06, 0x8602); -+ mdio_write(tp, 0x06, 0x01fc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xfbbf); -+ mdio_write(tp, 0x06, 0x8604); -+ mdio_write(tp, 0x06, 0xef79); -+ mdio_write(tp, 0x06, 0xd200); -+ mdio_write(tp, 0x06, 0xd400); -+ mdio_write(tp, 0x06, 0x221e); -+ mdio_write(tp, 0x06, 0x02bf); -+ mdio_write(tp, 0x06, 0x2fec); -+ mdio_write(tp, 0x06, 0x0237); -+ mdio_write(tp, 0x06, 0x23bf); -+ mdio_write(tp, 0x06, 0x13f2); -+ mdio_write(tp, 0x06, 0x0236); -+ mdio_write(tp, 0x06, 0xf60d); -+ mdio_write(tp, 0x06, 0x4559); -+ mdio_write(tp, 0x06, 0x1fef); -+ mdio_write(tp, 0x06, 0x97dd); -+ mdio_write(tp, 0x06, 0xd308); -+ mdio_write(tp, 0x06, 0x1a93); -+ mdio_write(tp, 0x06, 0xdd12); -+ mdio_write(tp, 0x06, 0x17a2); -+ mdio_write(tp, 0x06, 0x04de); -+ mdio_write(tp, 0x06, 0xffef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfdfc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xfbee); -+ mdio_write(tp, 0x06, 0x8602); -+ mdio_write(tp, 0x06, 0x03d5); -+ mdio_write(tp, 0x06, 0x0080); -+ mdio_write(tp, 0x06, 0xbf86); -+ mdio_write(tp, 0x06, 0x04ef); -+ mdio_write(tp, 0x06, 0x79ef); -+ mdio_write(tp, 0x06, 0x45bf); -+ mdio_write(tp, 0x06, 0x2fec); -+ mdio_write(tp, 0x06, 0x0237); -+ mdio_write(tp, 0x06, 0x23bf); -+ mdio_write(tp, 0x06, 0x13f2); -+ mdio_write(tp, 0x06, 0x0236); -+ mdio_write(tp, 0x06, 0xf6ad); -+ mdio_write(tp, 0x06, 0x2702); -+ mdio_write(tp, 0x06, 0x78ff); -+ mdio_write(tp, 0x06, 0xe186); -+ mdio_write(tp, 0x06, 0x0a1b); -+ mdio_write(tp, 0x06, 0x01aa); -+ mdio_write(tp, 0x06, 0x2eef); -+ mdio_write(tp, 0x06, 0x97d9); -+ mdio_write(tp, 0x06, 0x7900); -+ mdio_write(tp, 0x06, 0x9e2b); -+ mdio_write(tp, 0x06, 0x81dd); -+ mdio_write(tp, 0x06, 0xbf85); -+ mdio_write(tp, 0x06, 0xad02); -+ mdio_write(tp, 0x06, 0x3723); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xef02); -+ mdio_write(tp, 0x06, 0x100c); -+ mdio_write(tp, 0x06, 0x11b0); -+ mdio_write(tp, 0x06, 0xfc0d); -+ mdio_write(tp, 0x06, 0x11bf); -+ mdio_write(tp, 0x06, 0x85aa); -+ mdio_write(tp, 0x06, 0x0237); -+ mdio_write(tp, 0x06, 0x23d1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x85aa); -+ mdio_write(tp, 0x06, 0x0237); -+ mdio_write(tp, 0x06, 0x23ee); -+ mdio_write(tp, 0x06, 0x8602); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x0413); -+ mdio_write(tp, 0x06, 0xa38b); -+ mdio_write(tp, 0x06, 0xb4d3); -+ mdio_write(tp, 0x06, 0x8012); -+ mdio_write(tp, 0x06, 0x17a2); -+ mdio_write(tp, 0x06, 0x04ad); -+ mdio_write(tp, 0x06, 0xffef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfdfc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9e0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xad25); -+ mdio_write(tp, 0x06, 0x48e0); -+ mdio_write(tp, 0x06, 0x8a96); -+ mdio_write(tp, 0x06, 0xe18a); -+ mdio_write(tp, 0x06, 0x977c); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x9e35); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0x9600); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0x9700); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xbee1); -+ mdio_write(tp, 0x06, 0x8abf); -+ mdio_write(tp, 0x06, 0xe286); -+ mdio_write(tp, 0x06, 0x10e3); -+ mdio_write(tp, 0x06, 0x8611); -+ mdio_write(tp, 0x06, 0x0236); -+ mdio_write(tp, 0x06, 0x1aad); -+ mdio_write(tp, 0x06, 0x2012); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0x9603); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0x97b7); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x1000); -+ mdio_write(tp, 0x06, 0xee86); -+ mdio_write(tp, 0x06, 0x1100); -+ mdio_write(tp, 0x06, 0xae11); -+ mdio_write(tp, 0x06, 0x15e6); -+ mdio_write(tp, 0x06, 0x8610); -+ mdio_write(tp, 0x06, 0xe786); -+ mdio_write(tp, 0x06, 0x11ae); -+ mdio_write(tp, 0x06, 0x08ee); -+ mdio_write(tp, 0x06, 0x8610); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8611); -+ mdio_write(tp, 0x06, 0x00fd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x00e1); -+ mdio_write(tp, 0x06, 0xe001); -+ mdio_write(tp, 0x06, 0xad27); -+ mdio_write(tp, 0x06, 0x32e0); -+ mdio_write(tp, 0x06, 0x8b40); -+ mdio_write(tp, 0x06, 0xf720); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x40bf); -+ mdio_write(tp, 0x06, 0x31f5); -+ mdio_write(tp, 0x06, 0x0236); -+ mdio_write(tp, 0x06, 0xf6ad); -+ mdio_write(tp, 0x06, 0x2821); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x20e1); -+ mdio_write(tp, 0x06, 0xe021); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x18e0); -+ mdio_write(tp, 0x06, 0x8b40); -+ mdio_write(tp, 0x06, 0xf620); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x40ee); -+ mdio_write(tp, 0x06, 0x8b3b); -+ mdio_write(tp, 0x06, 0xffe0); -+ mdio_write(tp, 0x06, 0x8a8a); -+ mdio_write(tp, 0x06, 0xe18a); -+ mdio_write(tp, 0x06, 0x8be4); -+ mdio_write(tp, 0x06, 0xe000); -+ mdio_write(tp, 0x06, 0xe5e0); -+ mdio_write(tp, 0x06, 0x01ef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x80ad); -+ mdio_write(tp, 0x06, 0x2722); -+ mdio_write(tp, 0x06, 0xbf44); -+ mdio_write(tp, 0x06, 0xfc02); -+ mdio_write(tp, 0x06, 0x36f6); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x441f); -+ mdio_write(tp, 0x06, 0x019e); -+ mdio_write(tp, 0x06, 0x15e5); -+ mdio_write(tp, 0x06, 0x8b44); -+ mdio_write(tp, 0x06, 0xad29); -+ mdio_write(tp, 0x06, 0x07ac); -+ mdio_write(tp, 0x06, 0x2804); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xae02); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf85); -+ mdio_write(tp, 0x06, 0xb002); -+ mdio_write(tp, 0x06, 0x3723); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfefc); -+ mdio_write(tp, 0x06, 0x0400); -+ mdio_write(tp, 0x06, 0xe140); -+ mdio_write(tp, 0x06, 0x77e1); -+ mdio_write(tp, 0x06, 0x40dd); -+ mdio_write(tp, 0x06, 0xe022); -+ mdio_write(tp, 0x06, 0x32e1); -+ mdio_write(tp, 0x06, 0x5074); -+ mdio_write(tp, 0x06, 0xe144); -+ mdio_write(tp, 0x06, 0xffe0); -+ mdio_write(tp, 0x06, 0xdaff); -+ mdio_write(tp, 0x06, 0xe0c0); -+ mdio_write(tp, 0x06, 0x52e0); -+ mdio_write(tp, 0x06, 0xeed9); -+ mdio_write(tp, 0x06, 0xe04c); -+ mdio_write(tp, 0x06, 0xbbe0); -+ mdio_write(tp, 0x06, 0x2a00); -+ mdio_write(tp, 0x05, 0xe142); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x05, 0xe140); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1f, 0x0005); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x00); -+ if (gphy_val & BIT_7) -+ break; -+ } -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0042); -+ mdio_write(tp, 0x18, 0x2300); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ if (tp->RequiredSecLanDonglePatch) { -+ gphy_val = mdio_read(tp, 0x17); -+ gphy_val &= ~BIT_2; -+ mdio_write(tp, 0x17, gphy_val); -+ } -+ -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x00, 0x9200); -+} -+ -+static void -+rtl8168_set_phy_mcu_8168f_1(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned int gphy_val,i; -+ -+ mdio_write(tp,0x1f, 0x0000); -+ mdio_write(tp,0x00, 0x1800); -+ gphy_val = mdio_read(tp, 0x15); -+ gphy_val &= ~(BIT_12); -+ mdio_write(tp,0x15, gphy_val); -+ mdio_write(tp,0x00, 0x4800); -+ mdio_write(tp,0x1f, 0x0007); -+ mdio_write(tp,0x1e, 0x002f); -+ for (i = 0; i < 1000; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x1c); -+ if (gphy_val & 0x0080) -+ break; -+ } -+ mdio_write(tp,0x1f, 0x0000); -+ mdio_write(tp,0x00, 0x1800); -+ mdio_write(tp,0x1f, 0x0007); -+ mdio_write(tp,0x1e, 0x0023); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x18); -+ if (!(gphy_val & 0x0001)) -+ break; -+ } -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0307); -+ mdio_write(tp, 0x15, 0x0194); -+ mdio_write(tp, 0x19, 0x407D); -+ mdio_write(tp, 0x15, 0x0098); -+ mdio_write(tp, 0x19, 0x7c0b); -+ mdio_write(tp, 0x15, 0x0099); -+ mdio_write(tp, 0x19, 0x6c0b); -+ mdio_write(tp, 0x15, 0x00eb); -+ mdio_write(tp, 0x19, 0x6c0b); -+ mdio_write(tp, 0x15, 0x00f8); -+ mdio_write(tp, 0x19, 0x6f0b); -+ mdio_write(tp, 0x15, 0x00fe); -+ mdio_write(tp, 0x19, 0x6f0f); -+ mdio_write(tp, 0x15, 0x00db); -+ mdio_write(tp, 0x19, 0x6f09); -+ mdio_write(tp, 0x15, 0x00dc); -+ mdio_write(tp, 0x19, 0xaefd); -+ mdio_write(tp, 0x15, 0x00dd); -+ mdio_write(tp, 0x19, 0x6f0b); -+ mdio_write(tp, 0x15, 0x00de); -+ mdio_write(tp, 0x19, 0xc60b); -+ mdio_write(tp, 0x15, 0x00df); -+ mdio_write(tp, 0x19, 0x00fa); -+ mdio_write(tp, 0x15, 0x00e0); -+ mdio_write(tp, 0x19, 0x30e1); -+ mdio_write(tp, 0x15, 0x020c); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x020e); -+ mdio_write(tp, 0x19, 0x9813); -+ mdio_write(tp, 0x15, 0x020f); -+ mdio_write(tp, 0x19, 0x7801); -+ mdio_write(tp, 0x15, 0x0210); -+ mdio_write(tp, 0x19, 0x930f); -+ mdio_write(tp, 0x15, 0x0211); -+ mdio_write(tp, 0x19, 0x9206); -+ mdio_write(tp, 0x15, 0x0212); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x0213); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0214); -+ mdio_write(tp, 0x19, 0x588f); -+ mdio_write(tp, 0x15, 0x0215); -+ mdio_write(tp, 0x19, 0x5520); -+ mdio_write(tp, 0x15, 0x0216); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x0217); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x0218); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0219); -+ mdio_write(tp, 0x19, 0x588d); -+ mdio_write(tp, 0x15, 0x021a); -+ mdio_write(tp, 0x19, 0x5540); -+ mdio_write(tp, 0x15, 0x021b); -+ mdio_write(tp, 0x19, 0x9e03); -+ mdio_write(tp, 0x15, 0x021c); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x021d); -+ mdio_write(tp, 0x19, 0x6840); -+ mdio_write(tp, 0x15, 0x021e); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x021f); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x0220); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x0221); -+ mdio_write(tp, 0x19, 0x9e03); -+ mdio_write(tp, 0x15, 0x0222); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x0223); -+ mdio_write(tp, 0x19, 0x6840); -+ mdio_write(tp, 0x15, 0x0224); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0225); -+ mdio_write(tp, 0x19, 0x3231); -+ mdio_write(tp, 0x15, 0x0000); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0300); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ mdio_write(tp, 0x05, 0x8000); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0x48f7); -+ mdio_write(tp, 0x06, 0x00e0); -+ mdio_write(tp, 0x06, 0xfff7); -+ mdio_write(tp, 0x06, 0xa080); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0xf602); -+ mdio_write(tp, 0x06, 0x0118); -+ mdio_write(tp, 0x06, 0x0201); -+ mdio_write(tp, 0x06, 0x2502); -+ mdio_write(tp, 0x06, 0x8090); -+ mdio_write(tp, 0x06, 0x0201); -+ mdio_write(tp, 0x06, 0x4202); -+ mdio_write(tp, 0x06, 0x015c); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0xad02); -+ mdio_write(tp, 0x06, 0x80ca); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x88e1); -+ mdio_write(tp, 0x06, 0x8b89); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8a1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8b); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8c1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8e1e); -+ mdio_write(tp, 0x06, 0x01a0); -+ mdio_write(tp, 0x06, 0x00c7); -+ mdio_write(tp, 0x06, 0xaebb); -+ mdio_write(tp, 0x06, 0xd484); -+ mdio_write(tp, 0x06, 0x3ce4); -+ mdio_write(tp, 0x06, 0x8b92); -+ mdio_write(tp, 0x06, 0xe58b); -+ mdio_write(tp, 0x06, 0x93ee); -+ mdio_write(tp, 0x06, 0x8ac8); -+ mdio_write(tp, 0x06, 0x03ee); -+ mdio_write(tp, 0x06, 0x8aca); -+ mdio_write(tp, 0x06, 0x60ee); -+ mdio_write(tp, 0x06, 0x8ac0); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8ac1); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8abe); -+ mdio_write(tp, 0x06, 0x07ee); -+ mdio_write(tp, 0x06, 0x8abf); -+ mdio_write(tp, 0x06, 0x73ee); -+ mdio_write(tp, 0x06, 0x8a95); -+ mdio_write(tp, 0x06, 0x02bf); -+ mdio_write(tp, 0x06, 0x8b88); -+ mdio_write(tp, 0x06, 0xec00); -+ mdio_write(tp, 0x06, 0x19a9); -+ mdio_write(tp, 0x06, 0x8b90); -+ mdio_write(tp, 0x06, 0xf9ee); -+ mdio_write(tp, 0x06, 0xfff6); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0xfff7); -+ mdio_write(tp, 0x06, 0xfed1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x85a4); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x7dd1); -+ mdio_write(tp, 0x06, 0x01bf); -+ mdio_write(tp, 0x06, 0x85a7); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x7d04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b8a); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x14ee); -+ mdio_write(tp, 0x06, 0x8b8a); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x204b); -+ mdio_write(tp, 0x06, 0xe0e4); -+ mdio_write(tp, 0x06, 0x26e1); -+ mdio_write(tp, 0x06, 0xe427); -+ mdio_write(tp, 0x06, 0xeee4); -+ mdio_write(tp, 0x06, 0x2623); -+ mdio_write(tp, 0x06, 0xe5e4); -+ mdio_write(tp, 0x06, 0x27fc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8dad); -+ mdio_write(tp, 0x06, 0x2014); -+ mdio_write(tp, 0x06, 0xee8b); -+ mdio_write(tp, 0x06, 0x8d00); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0x5a78); -+ mdio_write(tp, 0x06, 0x039e); -+ mdio_write(tp, 0x06, 0x0902); -+ mdio_write(tp, 0x06, 0x05e8); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0x4f02); -+ mdio_write(tp, 0x06, 0x326c); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x1df6); -+ mdio_write(tp, 0x06, 0x20e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x0902); -+ mdio_write(tp, 0x06, 0x2ab0); -+ mdio_write(tp, 0x06, 0x0285); -+ mdio_write(tp, 0x06, 0x1602); -+ mdio_write(tp, 0x06, 0x03ba); -+ mdio_write(tp, 0x06, 0x0284); -+ mdio_write(tp, 0x06, 0xe502); -+ mdio_write(tp, 0x06, 0x2df1); -+ mdio_write(tp, 0x06, 0x0283); -+ mdio_write(tp, 0x06, 0x8302); -+ mdio_write(tp, 0x06, 0x0475); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x210b); -+ mdio_write(tp, 0x06, 0xf621); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x83f8); -+ mdio_write(tp, 0x06, 0x021c); -+ mdio_write(tp, 0x06, 0x99e0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad22); -+ mdio_write(tp, 0x06, 0x08f6); -+ mdio_write(tp, 0x06, 0x22e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x0235); -+ mdio_write(tp, 0x06, 0x63e0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad23); -+ mdio_write(tp, 0x06, 0x08f6); -+ mdio_write(tp, 0x06, 0x23e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x0231); -+ mdio_write(tp, 0x06, 0x57e0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad24); -+ mdio_write(tp, 0x06, 0x05f6); -+ mdio_write(tp, 0x06, 0x24e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2505); -+ mdio_write(tp, 0x06, 0xf625); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8ee0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad26); -+ mdio_write(tp, 0x06, 0x08f6); -+ mdio_write(tp, 0x06, 0x26e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x022d); -+ mdio_write(tp, 0x06, 0x1ce0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad27); -+ mdio_write(tp, 0x06, 0x05f6); -+ mdio_write(tp, 0x06, 0x27e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x0203); -+ mdio_write(tp, 0x06, 0x80fc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9e0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xac26); -+ mdio_write(tp, 0x06, 0x1ae0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xac21); -+ mdio_write(tp, 0x06, 0x14e0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xac20); -+ mdio_write(tp, 0x06, 0x0ee0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xac23); -+ mdio_write(tp, 0x06, 0x08e0); -+ mdio_write(tp, 0x06, 0x8b87); -+ mdio_write(tp, 0x06, 0xac24); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x3802); -+ mdio_write(tp, 0x06, 0x1ac2); -+ mdio_write(tp, 0x06, 0xeee4); -+ mdio_write(tp, 0x06, 0x1c04); -+ mdio_write(tp, 0x06, 0xeee4); -+ mdio_write(tp, 0x06, 0x1d04); -+ mdio_write(tp, 0x06, 0xe2e0); -+ mdio_write(tp, 0x06, 0x7ce3); -+ mdio_write(tp, 0x06, 0xe07d); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x38e1); -+ mdio_write(tp, 0x06, 0xe039); -+ mdio_write(tp, 0x06, 0xad2e); -+ mdio_write(tp, 0x06, 0x1bad); -+ mdio_write(tp, 0x06, 0x390d); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xbf22); -+ mdio_write(tp, 0x06, 0x7a02); -+ mdio_write(tp, 0x06, 0x387d); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0xacae); -+ mdio_write(tp, 0x06, 0x0bac); -+ mdio_write(tp, 0x06, 0x3802); -+ mdio_write(tp, 0x06, 0xae06); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0xe902); -+ mdio_write(tp, 0x06, 0x822e); -+ mdio_write(tp, 0x06, 0x021a); -+ mdio_write(tp, 0x06, 0xd3fd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e1); -+ mdio_write(tp, 0x06, 0x8af4); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x2602); -+ mdio_write(tp, 0x06, 0xf728); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x2105); -+ mdio_write(tp, 0x06, 0x0222); -+ mdio_write(tp, 0x06, 0x8ef7); -+ mdio_write(tp, 0x06, 0x29e0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0x14b8); -+ mdio_write(tp, 0x06, 0xf72a); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x85ad); -+ mdio_write(tp, 0x06, 0x2305); -+ mdio_write(tp, 0x06, 0x0212); -+ mdio_write(tp, 0x06, 0xf4f7); -+ mdio_write(tp, 0x06, 0x2be0); -+ mdio_write(tp, 0x06, 0x8b87); -+ mdio_write(tp, 0x06, 0xad24); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0x8284); -+ mdio_write(tp, 0x06, 0xf72c); -+ mdio_write(tp, 0x06, 0xe58a); -+ mdio_write(tp, 0x06, 0xf4fc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x2600); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x2109); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xf4ac); -+ mdio_write(tp, 0x06, 0x2003); -+ mdio_write(tp, 0x06, 0x0222); -+ mdio_write(tp, 0x06, 0x7de0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x09e0); -+ mdio_write(tp, 0x06, 0x8af4); -+ mdio_write(tp, 0x06, 0xac21); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0x1408); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x85ad); -+ mdio_write(tp, 0x06, 0x2309); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xf4ac); -+ mdio_write(tp, 0x06, 0x2203); -+ mdio_write(tp, 0x06, 0x0213); -+ mdio_write(tp, 0x06, 0x07e0); -+ mdio_write(tp, 0x06, 0x8b87); -+ mdio_write(tp, 0x06, 0xad24); -+ mdio_write(tp, 0x06, 0x09e0); -+ mdio_write(tp, 0x06, 0x8af4); -+ mdio_write(tp, 0x06, 0xac23); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0x8289); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e1); -+ mdio_write(tp, 0x06, 0x8af4); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x2602); -+ mdio_write(tp, 0x06, 0xf628); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ad); -+ mdio_write(tp, 0x06, 0x210a); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0xecf6); -+ mdio_write(tp, 0x06, 0x27a0); -+ mdio_write(tp, 0x06, 0x0502); -+ mdio_write(tp, 0x06, 0xf629); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x85ad); -+ mdio_write(tp, 0x06, 0x2008); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xe8ad); -+ mdio_write(tp, 0x06, 0x2102); -+ mdio_write(tp, 0x06, 0xf62a); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x85ad); -+ mdio_write(tp, 0x06, 0x2308); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x20a0); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0xf62b); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x2408); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xc2a0); -+ mdio_write(tp, 0x06, 0x0302); -+ mdio_write(tp, 0x06, 0xf62c); -+ mdio_write(tp, 0x06, 0xe58a); -+ mdio_write(tp, 0x06, 0xf4a1); -+ mdio_write(tp, 0x06, 0x0008); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf22); -+ mdio_write(tp, 0x06, 0x7a02); -+ mdio_write(tp, 0x06, 0x387d); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xc200); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ad); -+ mdio_write(tp, 0x06, 0x241e); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xc2a0); -+ mdio_write(tp, 0x06, 0x0005); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0xb0ae); -+ mdio_write(tp, 0x06, 0xf5a0); -+ mdio_write(tp, 0x06, 0x0105); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0xc0ae); -+ mdio_write(tp, 0x06, 0x0ba0); -+ mdio_write(tp, 0x06, 0x0205); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0xcaae); -+ mdio_write(tp, 0x06, 0x03a0); -+ mdio_write(tp, 0x06, 0x0300); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0xe1ee); -+ mdio_write(tp, 0x06, 0x8ac2); -+ mdio_write(tp, 0x06, 0x01ef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8ee); -+ mdio_write(tp, 0x06, 0x8ac9); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x8317); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8ac8); -+ mdio_write(tp, 0x06, 0xe18a); -+ mdio_write(tp, 0x06, 0xc91f); -+ mdio_write(tp, 0x06, 0x019e); -+ mdio_write(tp, 0x06, 0x0611); -+ mdio_write(tp, 0x06, 0xe58a); -+ mdio_write(tp, 0x06, 0xc9ae); -+ mdio_write(tp, 0x06, 0x04ee); -+ mdio_write(tp, 0x06, 0x8ac2); -+ mdio_write(tp, 0x06, 0x01fc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xfbbf); -+ mdio_write(tp, 0x06, 0x8ac4); -+ mdio_write(tp, 0x06, 0xef79); -+ mdio_write(tp, 0x06, 0xd200); -+ mdio_write(tp, 0x06, 0xd400); -+ mdio_write(tp, 0x06, 0x221e); -+ mdio_write(tp, 0x06, 0x02bf); -+ mdio_write(tp, 0x06, 0x3024); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x7dbf); -+ mdio_write(tp, 0x06, 0x13ff); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x500d); -+ mdio_write(tp, 0x06, 0x4559); -+ mdio_write(tp, 0x06, 0x1fef); -+ mdio_write(tp, 0x06, 0x97dd); -+ mdio_write(tp, 0x06, 0xd308); -+ mdio_write(tp, 0x06, 0x1a93); -+ mdio_write(tp, 0x06, 0xdd12); -+ mdio_write(tp, 0x06, 0x17a2); -+ mdio_write(tp, 0x06, 0x04de); -+ mdio_write(tp, 0x06, 0xffef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfdfc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xfbee); -+ mdio_write(tp, 0x06, 0x8ac2); -+ mdio_write(tp, 0x06, 0x03d5); -+ mdio_write(tp, 0x06, 0x0080); -+ mdio_write(tp, 0x06, 0xbf8a); -+ mdio_write(tp, 0x06, 0xc4ef); -+ mdio_write(tp, 0x06, 0x79ef); -+ mdio_write(tp, 0x06, 0x45bf); -+ mdio_write(tp, 0x06, 0x3024); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x7dbf); -+ mdio_write(tp, 0x06, 0x13ff); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x50ad); -+ mdio_write(tp, 0x06, 0x2702); -+ mdio_write(tp, 0x06, 0x78ff); -+ mdio_write(tp, 0x06, 0xe18a); -+ mdio_write(tp, 0x06, 0xca1b); -+ mdio_write(tp, 0x06, 0x01aa); -+ mdio_write(tp, 0x06, 0x2eef); -+ mdio_write(tp, 0x06, 0x97d9); -+ mdio_write(tp, 0x06, 0x7900); -+ mdio_write(tp, 0x06, 0x9e2b); -+ mdio_write(tp, 0x06, 0x81dd); -+ mdio_write(tp, 0x06, 0xbf85); -+ mdio_write(tp, 0x06, 0xad02); -+ mdio_write(tp, 0x06, 0x387d); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xef02); -+ mdio_write(tp, 0x06, 0x100c); -+ mdio_write(tp, 0x06, 0x11b0); -+ mdio_write(tp, 0x06, 0xfc0d); -+ mdio_write(tp, 0x06, 0x11bf); -+ mdio_write(tp, 0x06, 0x85aa); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x7dd1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x85aa); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x7dee); -+ mdio_write(tp, 0x06, 0x8ac2); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x0413); -+ mdio_write(tp, 0x06, 0xa38b); -+ mdio_write(tp, 0x06, 0xb4d3); -+ mdio_write(tp, 0x06, 0x8012); -+ mdio_write(tp, 0x06, 0x17a2); -+ mdio_write(tp, 0x06, 0x04ad); -+ mdio_write(tp, 0x06, 0xffef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfdfc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9e0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xad25); -+ mdio_write(tp, 0x06, 0x48e0); -+ mdio_write(tp, 0x06, 0x8a96); -+ mdio_write(tp, 0x06, 0xe18a); -+ mdio_write(tp, 0x06, 0x977c); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x9e35); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0x9600); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0x9700); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0xbee1); -+ mdio_write(tp, 0x06, 0x8abf); -+ mdio_write(tp, 0x06, 0xe28a); -+ mdio_write(tp, 0x06, 0xc0e3); -+ mdio_write(tp, 0x06, 0x8ac1); -+ mdio_write(tp, 0x06, 0x0237); -+ mdio_write(tp, 0x06, 0x74ad); -+ mdio_write(tp, 0x06, 0x2012); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0x9603); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0x97b7); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xc000); -+ mdio_write(tp, 0x06, 0xee8a); -+ mdio_write(tp, 0x06, 0xc100); -+ mdio_write(tp, 0x06, 0xae11); -+ mdio_write(tp, 0x06, 0x15e6); -+ mdio_write(tp, 0x06, 0x8ac0); -+ mdio_write(tp, 0x06, 0xe78a); -+ mdio_write(tp, 0x06, 0xc1ae); -+ mdio_write(tp, 0x06, 0x08ee); -+ mdio_write(tp, 0x06, 0x8ac0); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8ac1); -+ mdio_write(tp, 0x06, 0x00fd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xae20); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x00e1); -+ mdio_write(tp, 0x06, 0xe001); -+ mdio_write(tp, 0x06, 0xad27); -+ mdio_write(tp, 0x06, 0x32e0); -+ mdio_write(tp, 0x06, 0x8b40); -+ mdio_write(tp, 0x06, 0xf720); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x40bf); -+ mdio_write(tp, 0x06, 0x3230); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x50ad); -+ mdio_write(tp, 0x06, 0x2821); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x20e1); -+ mdio_write(tp, 0x06, 0xe021); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x18e0); -+ mdio_write(tp, 0x06, 0x8b40); -+ mdio_write(tp, 0x06, 0xf620); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x40ee); -+ mdio_write(tp, 0x06, 0x8b3b); -+ mdio_write(tp, 0x06, 0xffe0); -+ mdio_write(tp, 0x06, 0x8a8a); -+ mdio_write(tp, 0x06, 0xe18a); -+ mdio_write(tp, 0x06, 0x8be4); -+ mdio_write(tp, 0x06, 0xe000); -+ mdio_write(tp, 0x06, 0xe5e0); -+ mdio_write(tp, 0x06, 0x01ef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8f9); -+ mdio_write(tp, 0x06, 0xface); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x69fa); -+ mdio_write(tp, 0x06, 0xd401); -+ mdio_write(tp, 0x06, 0x55b4); -+ mdio_write(tp, 0x06, 0xfebf); -+ mdio_write(tp, 0x06, 0x1c1e); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x50ac); -+ mdio_write(tp, 0x06, 0x280b); -+ mdio_write(tp, 0x06, 0xbf1c); -+ mdio_write(tp, 0x06, 0x1b02); -+ mdio_write(tp, 0x06, 0x3850); -+ mdio_write(tp, 0x06, 0xac28); -+ mdio_write(tp, 0x06, 0x49ae); -+ mdio_write(tp, 0x06, 0x64bf); -+ mdio_write(tp, 0x06, 0x1c1b); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x50ac); -+ mdio_write(tp, 0x06, 0x285b); -+ mdio_write(tp, 0x06, 0xd000); -+ mdio_write(tp, 0x06, 0x0284); -+ mdio_write(tp, 0x06, 0xcaac); -+ mdio_write(tp, 0x06, 0x2105); -+ mdio_write(tp, 0x06, 0xac22); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x4ebf); -+ mdio_write(tp, 0x06, 0xe0c4); -+ mdio_write(tp, 0x06, 0xbe85); -+ mdio_write(tp, 0x06, 0xf6d2); -+ mdio_write(tp, 0x06, 0x04d8); -+ mdio_write(tp, 0x06, 0x19d9); -+ mdio_write(tp, 0x06, 0x1907); -+ mdio_write(tp, 0x06, 0xdc19); -+ mdio_write(tp, 0x06, 0xdd19); -+ mdio_write(tp, 0x06, 0x0789); -+ mdio_write(tp, 0x06, 0x89ef); -+ mdio_write(tp, 0x06, 0x645e); -+ mdio_write(tp, 0x06, 0x07ff); -+ mdio_write(tp, 0x06, 0x0d65); -+ mdio_write(tp, 0x06, 0x5cf8); -+ mdio_write(tp, 0x06, 0x001e); -+ mdio_write(tp, 0x06, 0x46dc); -+ mdio_write(tp, 0x06, 0x19dd); -+ mdio_write(tp, 0x06, 0x19b2); -+ mdio_write(tp, 0x06, 0xe2d4); -+ mdio_write(tp, 0x06, 0x0001); -+ mdio_write(tp, 0x06, 0xbf1c); -+ mdio_write(tp, 0x06, 0x1b02); -+ mdio_write(tp, 0x06, 0x387d); -+ mdio_write(tp, 0x06, 0xae1d); -+ mdio_write(tp, 0x06, 0xbee0); -+ mdio_write(tp, 0x06, 0xc4bf); -+ mdio_write(tp, 0x06, 0x85f6); -+ mdio_write(tp, 0x06, 0xd204); -+ mdio_write(tp, 0x06, 0xd819); -+ mdio_write(tp, 0x06, 0xd919); -+ mdio_write(tp, 0x06, 0x07dc); -+ mdio_write(tp, 0x06, 0x19dd); -+ mdio_write(tp, 0x06, 0x1907); -+ mdio_write(tp, 0x06, 0xb2f4); -+ mdio_write(tp, 0x06, 0xd400); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x1c1b); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x7dfe); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfec6); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc05); -+ mdio_write(tp, 0x06, 0xf9e2); -+ mdio_write(tp, 0x06, 0xe0ea); -+ mdio_write(tp, 0x06, 0xe3e0); -+ mdio_write(tp, 0x06, 0xeb5a); -+ mdio_write(tp, 0x06, 0x070c); -+ mdio_write(tp, 0x06, 0x031e); -+ mdio_write(tp, 0x06, 0x20e6); -+ mdio_write(tp, 0x06, 0xe0ea); -+ mdio_write(tp, 0x06, 0xe7e0); -+ mdio_write(tp, 0x06, 0xebe0); -+ mdio_write(tp, 0x06, 0xe0fc); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0xfdfd); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x69e0); -+ mdio_write(tp, 0x06, 0x8b80); -+ mdio_write(tp, 0x06, 0xad27); -+ mdio_write(tp, 0x06, 0x22bf); -+ mdio_write(tp, 0x06, 0x4616); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x50e0); -+ mdio_write(tp, 0x06, 0x8b44); -+ mdio_write(tp, 0x06, 0x1f01); -+ mdio_write(tp, 0x06, 0x9e15); -+ mdio_write(tp, 0x06, 0xe58b); -+ mdio_write(tp, 0x06, 0x44ad); -+ mdio_write(tp, 0x06, 0x2907); -+ mdio_write(tp, 0x06, 0xac28); -+ mdio_write(tp, 0x06, 0x04d1); -+ mdio_write(tp, 0x06, 0x01ae); -+ mdio_write(tp, 0x06, 0x02d1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x85b0); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x7def); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xad26); -+ mdio_write(tp, 0x06, 0x30e0); -+ mdio_write(tp, 0x06, 0xe036); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x37e1); -+ mdio_write(tp, 0x06, 0x8b3f); -+ mdio_write(tp, 0x06, 0x1f10); -+ mdio_write(tp, 0x06, 0x9e23); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x3fac); -+ mdio_write(tp, 0x06, 0x200b); -+ mdio_write(tp, 0x06, 0xac21); -+ mdio_write(tp, 0x06, 0x0dac); -+ mdio_write(tp, 0x06, 0x250f); -+ mdio_write(tp, 0x06, 0xac27); -+ mdio_write(tp, 0x06, 0x11ae); -+ mdio_write(tp, 0x06, 0x1202); -+ mdio_write(tp, 0x06, 0x2c47); -+ mdio_write(tp, 0x06, 0xae0d); -+ mdio_write(tp, 0x06, 0x0285); -+ mdio_write(tp, 0x06, 0x4fae); -+ mdio_write(tp, 0x06, 0x0802); -+ mdio_write(tp, 0x06, 0x2c69); -+ mdio_write(tp, 0x06, 0xae03); -+ mdio_write(tp, 0x06, 0x022c); -+ mdio_write(tp, 0x06, 0x7cfc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x6902); -+ mdio_write(tp, 0x06, 0x856c); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x14e1); -+ mdio_write(tp, 0x06, 0xe015); -+ mdio_write(tp, 0x06, 0xad26); -+ mdio_write(tp, 0x06, 0x08d1); -+ mdio_write(tp, 0x06, 0x1ebf); -+ mdio_write(tp, 0x06, 0x2cd9); -+ mdio_write(tp, 0x06, 0x0238); -+ mdio_write(tp, 0x06, 0x7def); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xad27); -+ mdio_write(tp, 0x06, 0x2fd0); -+ mdio_write(tp, 0x06, 0x0b02); -+ mdio_write(tp, 0x06, 0x3682); -+ mdio_write(tp, 0x06, 0x5882); -+ mdio_write(tp, 0x06, 0x7882); -+ mdio_write(tp, 0x06, 0x9f24); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x32e1); -+ mdio_write(tp, 0x06, 0x8b33); -+ mdio_write(tp, 0x06, 0x1f10); -+ mdio_write(tp, 0x06, 0x9e1a); -+ mdio_write(tp, 0x06, 0x10e4); -+ mdio_write(tp, 0x06, 0x8b32); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x28e1); -+ mdio_write(tp, 0x06, 0xe029); -+ mdio_write(tp, 0x06, 0xf72c); -+ mdio_write(tp, 0x06, 0xe4e0); -+ mdio_write(tp, 0x06, 0x28e5); -+ mdio_write(tp, 0x06, 0xe029); -+ mdio_write(tp, 0x06, 0xf62c); -+ mdio_write(tp, 0x06, 0xe4e0); -+ mdio_write(tp, 0x06, 0x28e5); -+ mdio_write(tp, 0x06, 0xe029); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0x00e1); -+ mdio_write(tp, 0x06, 0x4077); -+ mdio_write(tp, 0x06, 0xe140); -+ mdio_write(tp, 0x06, 0x52e0); -+ mdio_write(tp, 0x06, 0xeed9); -+ mdio_write(tp, 0x06, 0xe04c); -+ mdio_write(tp, 0x06, 0xbbe0); -+ mdio_write(tp, 0x06, 0x2a00); -+ mdio_write(tp, 0x05, 0xe142); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp,0x06, gphy_val); -+ mdio_write(tp, 0x05, 0xe140); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp,0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp,0x1f, 0x0005); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x00); -+ if (gphy_val & BIT_7) -+ break; -+ } -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ gphy_val = mdio_read(tp, 0x17); -+ gphy_val |= BIT_1; -+ if (tp->RequiredSecLanDonglePatch) -+ gphy_val &= ~BIT_2; -+ mdio_write(tp, 0x17, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x09, 0xA20F); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x1f, 0x0003); -+ mdio_write(tp, 0x01, 0x328A); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x00, 0x9200); -+} -+ -+static void -+rtl8168_set_phy_mcu_8168f_2(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned int gphy_val,i; -+ -+ mdio_write(tp,0x1f, 0x0000); -+ mdio_write(tp,0x00, 0x1800); -+ gphy_val = mdio_read(tp, 0x15); -+ gphy_val &= ~(BIT_12); -+ mdio_write(tp,0x15, gphy_val); -+ mdio_write(tp,0x00, 0x9800); -+ mdio_write(tp,0x1f, 0x0007); -+ mdio_write(tp,0x1e, 0x002f); -+ for (i = 0; i < 1000; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x1c); -+ if (gphy_val & 0x0080) -+ break; -+ } -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0307); -+ mdio_write(tp, 0x15, 0x0098); -+ mdio_write(tp, 0x19, 0x7c0b); -+ mdio_write(tp, 0x15, 0x0099); -+ mdio_write(tp, 0x19, 0x6c0b); -+ mdio_write(tp, 0x15, 0x00eb); -+ mdio_write(tp, 0x19, 0x6c0b); -+ mdio_write(tp, 0x15, 0x00f8); -+ mdio_write(tp, 0x19, 0x6f0b); -+ mdio_write(tp, 0x15, 0x00fe); -+ mdio_write(tp, 0x19, 0x6f0f); -+ mdio_write(tp, 0x15, 0x00db); -+ mdio_write(tp, 0x19, 0x6f09); -+ mdio_write(tp, 0x15, 0x00dc); -+ mdio_write(tp, 0x19, 0xaefd); -+ mdio_write(tp, 0x15, 0x00dd); -+ mdio_write(tp, 0x19, 0x6f0b); -+ mdio_write(tp, 0x15, 0x00de); -+ mdio_write(tp, 0x19, 0xc60b); -+ mdio_write(tp, 0x15, 0x00df); -+ mdio_write(tp, 0x19, 0x00fa); -+ mdio_write(tp, 0x15, 0x00e0); -+ mdio_write(tp, 0x19, 0x30e1); -+ mdio_write(tp, 0x15, 0x020c); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x020e); -+ mdio_write(tp, 0x19, 0x9813); -+ mdio_write(tp, 0x15, 0x020f); -+ mdio_write(tp, 0x19, 0x7801); -+ mdio_write(tp, 0x15, 0x0210); -+ mdio_write(tp, 0x19, 0x930f); -+ mdio_write(tp, 0x15, 0x0211); -+ mdio_write(tp, 0x19, 0x9206); -+ mdio_write(tp, 0x15, 0x0212); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x0213); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0214); -+ mdio_write(tp, 0x19, 0x588f); -+ mdio_write(tp, 0x15, 0x0215); -+ mdio_write(tp, 0x19, 0x5520); -+ mdio_write(tp, 0x15, 0x0216); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x0217); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x0218); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0219); -+ mdio_write(tp, 0x19, 0x588d); -+ mdio_write(tp, 0x15, 0x021a); -+ mdio_write(tp, 0x19, 0x5540); -+ mdio_write(tp, 0x15, 0x021b); -+ mdio_write(tp, 0x19, 0x9e03); -+ mdio_write(tp, 0x15, 0x021c); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x021d); -+ mdio_write(tp, 0x19, 0x6840); -+ mdio_write(tp, 0x15, 0x021e); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x021f); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x0220); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x0221); -+ mdio_write(tp, 0x19, 0x9e03); -+ mdio_write(tp, 0x15, 0x0222); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x0223); -+ mdio_write(tp, 0x19, 0x6840); -+ mdio_write(tp, 0x15, 0x0224); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0225); -+ mdio_write(tp, 0x19, 0x3231); -+ mdio_write(tp, 0x15, 0x0000); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0300); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ mdio_write(tp, 0x05, 0x8000); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0x48f7); -+ mdio_write(tp, 0x06, 0x00e0); -+ mdio_write(tp, 0x06, 0xfff7); -+ mdio_write(tp, 0x06, 0xa080); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0xf602); -+ mdio_write(tp, 0x06, 0x011b); -+ mdio_write(tp, 0x06, 0x0201); -+ mdio_write(tp, 0x06, 0x2802); -+ mdio_write(tp, 0x06, 0x0135); -+ mdio_write(tp, 0x06, 0x0201); -+ mdio_write(tp, 0x06, 0x4502); -+ mdio_write(tp, 0x06, 0x015f); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0x6b02); -+ mdio_write(tp, 0x06, 0x80e5); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x88e1); -+ mdio_write(tp, 0x06, 0x8b89); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8a1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8b); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8c1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8e1e); -+ mdio_write(tp, 0x06, 0x01a0); -+ mdio_write(tp, 0x06, 0x00c7); -+ mdio_write(tp, 0x06, 0xaebb); -+ mdio_write(tp, 0x06, 0xbf8b); -+ mdio_write(tp, 0x06, 0x88ec); -+ mdio_write(tp, 0x06, 0x0019); -+ mdio_write(tp, 0x06, 0xa98b); -+ mdio_write(tp, 0x06, 0x90f9); -+ mdio_write(tp, 0x06, 0xeeff); -+ mdio_write(tp, 0x06, 0xf600); -+ mdio_write(tp, 0x06, 0xeeff); -+ mdio_write(tp, 0x06, 0xf7fe); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf81); -+ mdio_write(tp, 0x06, 0x9802); -+ mdio_write(tp, 0x06, 0x39f3); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xbf81); -+ mdio_write(tp, 0x06, 0x9b02); -+ mdio_write(tp, 0x06, 0x39f3); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8dad); -+ mdio_write(tp, 0x06, 0x2014); -+ mdio_write(tp, 0x06, 0xee8b); -+ mdio_write(tp, 0x06, 0x8d00); -+ mdio_write(tp, 0x06, 0xe08a); -+ mdio_write(tp, 0x06, 0x5a78); -+ mdio_write(tp, 0x06, 0x039e); -+ mdio_write(tp, 0x06, 0x0902); -+ mdio_write(tp, 0x06, 0x05fc); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0x8802); -+ mdio_write(tp, 0x06, 0x32dd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8f9); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ac); -+ mdio_write(tp, 0x06, 0x261a); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x81ac); -+ mdio_write(tp, 0x06, 0x2114); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x85ac); -+ mdio_write(tp, 0x06, 0x200e); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x85ac); -+ mdio_write(tp, 0x06, 0x2308); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x87ac); -+ mdio_write(tp, 0x06, 0x2402); -+ mdio_write(tp, 0x06, 0xae38); -+ mdio_write(tp, 0x06, 0x021a); -+ mdio_write(tp, 0x06, 0xd6ee); -+ mdio_write(tp, 0x06, 0xe41c); -+ mdio_write(tp, 0x06, 0x04ee); -+ mdio_write(tp, 0x06, 0xe41d); -+ mdio_write(tp, 0x06, 0x04e2); -+ mdio_write(tp, 0x06, 0xe07c); -+ mdio_write(tp, 0x06, 0xe3e0); -+ mdio_write(tp, 0x06, 0x7de0); -+ mdio_write(tp, 0x06, 0xe038); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x39ad); -+ mdio_write(tp, 0x06, 0x2e1b); -+ mdio_write(tp, 0x06, 0xad39); -+ mdio_write(tp, 0x06, 0x0dd1); -+ mdio_write(tp, 0x06, 0x01bf); -+ mdio_write(tp, 0x06, 0x22c8); -+ mdio_write(tp, 0x06, 0x0239); -+ mdio_write(tp, 0x06, 0xf302); -+ mdio_write(tp, 0x06, 0x21f0); -+ mdio_write(tp, 0x06, 0xae0b); -+ mdio_write(tp, 0x06, 0xac38); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x0602); -+ mdio_write(tp, 0x06, 0x222d); -+ mdio_write(tp, 0x06, 0x0222); -+ mdio_write(tp, 0x06, 0x7202); -+ mdio_write(tp, 0x06, 0x1ae7); -+ mdio_write(tp, 0x06, 0xfdfc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x201a); -+ mdio_write(tp, 0x06, 0xf620); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x2afe); -+ mdio_write(tp, 0x06, 0x022c); -+ mdio_write(tp, 0x06, 0x5c02); -+ mdio_write(tp, 0x06, 0x03c5); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0x6702); -+ mdio_write(tp, 0x06, 0x2e4f); -+ mdio_write(tp, 0x06, 0x0204); -+ mdio_write(tp, 0x06, 0x8902); -+ mdio_write(tp, 0x06, 0x2f7a); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x210b); -+ mdio_write(tp, 0x06, 0xf621); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x0445); -+ mdio_write(tp, 0x06, 0x021c); -+ mdio_write(tp, 0x06, 0xb8e0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad22); -+ mdio_write(tp, 0x06, 0x08f6); -+ mdio_write(tp, 0x06, 0x22e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x0235); -+ mdio_write(tp, 0x06, 0xd4e0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad23); -+ mdio_write(tp, 0x06, 0x08f6); -+ mdio_write(tp, 0x06, 0x23e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x0231); -+ mdio_write(tp, 0x06, 0xc8e0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad24); -+ mdio_write(tp, 0x06, 0x05f6); -+ mdio_write(tp, 0x06, 0x24e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2505); -+ mdio_write(tp, 0x06, 0xf625); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8ee0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad26); -+ mdio_write(tp, 0x06, 0x08f6); -+ mdio_write(tp, 0x06, 0x26e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x022d); -+ mdio_write(tp, 0x06, 0x6ae0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad27); -+ mdio_write(tp, 0x06, 0x05f6); -+ mdio_write(tp, 0x06, 0x27e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x0203); -+ mdio_write(tp, 0x06, 0x8bfc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x69e0); -+ mdio_write(tp, 0x06, 0x8b80); -+ mdio_write(tp, 0x06, 0xad27); -+ mdio_write(tp, 0x06, 0x22bf); -+ mdio_write(tp, 0x06, 0x479a); -+ mdio_write(tp, 0x06, 0x0239); -+ mdio_write(tp, 0x06, 0xc6e0); -+ mdio_write(tp, 0x06, 0x8b44); -+ mdio_write(tp, 0x06, 0x1f01); -+ mdio_write(tp, 0x06, 0x9e15); -+ mdio_write(tp, 0x06, 0xe58b); -+ mdio_write(tp, 0x06, 0x44ad); -+ mdio_write(tp, 0x06, 0x2907); -+ mdio_write(tp, 0x06, 0xac28); -+ mdio_write(tp, 0x06, 0x04d1); -+ mdio_write(tp, 0x06, 0x01ae); -+ mdio_write(tp, 0x06, 0x02d1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x819e); -+ mdio_write(tp, 0x06, 0x0239); -+ mdio_write(tp, 0x06, 0xf3ef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0x00e1); -+ mdio_write(tp, 0x06, 0x4077); -+ mdio_write(tp, 0x06, 0xe140); -+ mdio_write(tp, 0x06, 0xbbe0); -+ mdio_write(tp, 0x06, 0x2a00); -+ mdio_write(tp, 0x05, 0xe142); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x05, 0xe140); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ gphy_val = mdio_read(tp, 0x17); -+ gphy_val |= BIT_1; -+ if (tp->RequiredSecLanDonglePatch) -+ gphy_val &= ~BIT_2; -+ mdio_write(tp, 0x17, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x00, 0x9200); -+} -+ -+static void -+rtl8168_set_phy_mcu_8411_1(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned int gphy_val,i; -+ -+ mdio_write(tp,0x1f, 0x0000); -+ mdio_write(tp,0x00, 0x1800); -+ gphy_val = mdio_read(tp, 0x15); -+ gphy_val &= ~(BIT_12); -+ mdio_write(tp,0x15, gphy_val); -+ mdio_write(tp,0x00, 0x4800); -+ mdio_write(tp,0x1f, 0x0007); -+ mdio_write(tp,0x1e, 0x002f); -+ for (i = 0; i < 1000; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x1c); -+ if (gphy_val & 0x0080) -+ break; -+ } -+ mdio_write(tp,0x1f, 0x0000); -+ mdio_write(tp,0x00, 0x1800); -+ mdio_write(tp,0x1f, 0x0007); -+ mdio_write(tp,0x1e, 0x0023); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x18); -+ if (!(gphy_val & 0x0001)) -+ break; -+ } -+ mdio_write(tp,0x1f, 0x0005); -+ mdio_write(tp,0x05, 0xfff6); -+ mdio_write(tp,0x06, 0x0080); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x0023); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0307); -+ mdio_write(tp, 0x15, 0x0098); -+ mdio_write(tp, 0x19, 0x7c0b); -+ mdio_write(tp, 0x15, 0x0099); -+ mdio_write(tp, 0x19, 0x6c0b); -+ mdio_write(tp, 0x15, 0x00eb); -+ mdio_write(tp, 0x19, 0x6c0b); -+ mdio_write(tp, 0x15, 0x00f8); -+ mdio_write(tp, 0x19, 0x6f0b); -+ mdio_write(tp, 0x15, 0x00fe); -+ mdio_write(tp, 0x19, 0x6f0f); -+ mdio_write(tp, 0x15, 0x00db); -+ mdio_write(tp, 0x19, 0x6f09); -+ mdio_write(tp, 0x15, 0x00dc); -+ mdio_write(tp, 0x19, 0xaefd); -+ mdio_write(tp, 0x15, 0x00dd); -+ mdio_write(tp, 0x19, 0x6f0b); -+ mdio_write(tp, 0x15, 0x00de); -+ mdio_write(tp, 0x19, 0xc60b); -+ mdio_write(tp, 0x15, 0x00df); -+ mdio_write(tp, 0x19, 0x00fa); -+ mdio_write(tp, 0x15, 0x00e0); -+ mdio_write(tp, 0x19, 0x30e1); -+ mdio_write(tp, 0x15, 0x020c); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x020e); -+ mdio_write(tp, 0x19, 0x9813); -+ mdio_write(tp, 0x15, 0x020f); -+ mdio_write(tp, 0x19, 0x7801); -+ mdio_write(tp, 0x15, 0x0210); -+ mdio_write(tp, 0x19, 0x930f); -+ mdio_write(tp, 0x15, 0x0211); -+ mdio_write(tp, 0x19, 0x9206); -+ mdio_write(tp, 0x15, 0x0212); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x0213); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0214); -+ mdio_write(tp, 0x19, 0x588f); -+ mdio_write(tp, 0x15, 0x0215); -+ mdio_write(tp, 0x19, 0x5520); -+ mdio_write(tp, 0x15, 0x0216); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x0217); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x0218); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0219); -+ mdio_write(tp, 0x19, 0x588d); -+ mdio_write(tp, 0x15, 0x021a); -+ mdio_write(tp, 0x19, 0x5540); -+ mdio_write(tp, 0x15, 0x021b); -+ mdio_write(tp, 0x19, 0x9e03); -+ mdio_write(tp, 0x15, 0x021c); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x021d); -+ mdio_write(tp, 0x19, 0x6840); -+ mdio_write(tp, 0x15, 0x021e); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x021f); -+ mdio_write(tp, 0x19, 0x4002); -+ mdio_write(tp, 0x15, 0x0220); -+ mdio_write(tp, 0x19, 0x3224); -+ mdio_write(tp, 0x15, 0x0221); -+ mdio_write(tp, 0x19, 0x9e03); -+ mdio_write(tp, 0x15, 0x0222); -+ mdio_write(tp, 0x19, 0x7c40); -+ mdio_write(tp, 0x15, 0x0223); -+ mdio_write(tp, 0x19, 0x6840); -+ mdio_write(tp, 0x15, 0x0224); -+ mdio_write(tp, 0x19, 0x7800); -+ mdio_write(tp, 0x15, 0x0225); -+ mdio_write(tp, 0x19, 0x3231); -+ mdio_write(tp, 0x15, 0x0000); -+ mdio_write(tp, 0x16, 0x0306); -+ mdio_write(tp, 0x16, 0x0300); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ mdio_write(tp, 0x05, 0x8000); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0x48f7); -+ mdio_write(tp, 0x06, 0x00e0); -+ mdio_write(tp, 0x06, 0xfff7); -+ mdio_write(tp, 0x06, 0xa080); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0xf602); -+ mdio_write(tp, 0x06, 0x011e); -+ mdio_write(tp, 0x06, 0x0201); -+ mdio_write(tp, 0x06, 0x2b02); -+ mdio_write(tp, 0x06, 0x8077); -+ mdio_write(tp, 0x06, 0x0201); -+ mdio_write(tp, 0x06, 0x4802); -+ mdio_write(tp, 0x06, 0x0162); -+ mdio_write(tp, 0x06, 0x0280); -+ mdio_write(tp, 0x06, 0x9402); -+ mdio_write(tp, 0x06, 0x810e); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x88e1); -+ mdio_write(tp, 0x06, 0x8b89); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8a1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8b); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8c1e); -+ mdio_write(tp, 0x06, 0x01e1); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0x1e01); -+ mdio_write(tp, 0x06, 0xe18b); -+ mdio_write(tp, 0x06, 0x8e1e); -+ mdio_write(tp, 0x06, 0x01a0); -+ mdio_write(tp, 0x06, 0x00c7); -+ mdio_write(tp, 0x06, 0xaebb); -+ mdio_write(tp, 0x06, 0xd481); -+ mdio_write(tp, 0x06, 0xd4e4); -+ mdio_write(tp, 0x06, 0x8b92); -+ mdio_write(tp, 0x06, 0xe58b); -+ mdio_write(tp, 0x06, 0x9302); -+ mdio_write(tp, 0x06, 0x2e5a); -+ mdio_write(tp, 0x06, 0xbf8b); -+ mdio_write(tp, 0x06, 0x88ec); -+ mdio_write(tp, 0x06, 0x0019); -+ mdio_write(tp, 0x06, 0xa98b); -+ mdio_write(tp, 0x06, 0x90f9); -+ mdio_write(tp, 0x06, 0xeeff); -+ mdio_write(tp, 0x06, 0xf600); -+ mdio_write(tp, 0x06, 0xeeff); -+ mdio_write(tp, 0x06, 0xf7fc); -+ mdio_write(tp, 0x06, 0xd100); -+ mdio_write(tp, 0x06, 0xbf83); -+ mdio_write(tp, 0x06, 0x3c02); -+ mdio_write(tp, 0x06, 0x3a21); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xbf83); -+ mdio_write(tp, 0x06, 0x3f02); -+ mdio_write(tp, 0x06, 0x3a21); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8aad); -+ mdio_write(tp, 0x06, 0x2014); -+ mdio_write(tp, 0x06, 0xee8b); -+ mdio_write(tp, 0x06, 0x8a00); -+ mdio_write(tp, 0x06, 0x0220); -+ mdio_write(tp, 0x06, 0x8be0); -+ mdio_write(tp, 0x06, 0xe426); -+ mdio_write(tp, 0x06, 0xe1e4); -+ mdio_write(tp, 0x06, 0x27ee); -+ mdio_write(tp, 0x06, 0xe426); -+ mdio_write(tp, 0x06, 0x23e5); -+ mdio_write(tp, 0x06, 0xe427); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x14ee); -+ mdio_write(tp, 0x06, 0x8b8d); -+ mdio_write(tp, 0x06, 0x00e0); -+ mdio_write(tp, 0x06, 0x8a5a); -+ mdio_write(tp, 0x06, 0x7803); -+ mdio_write(tp, 0x06, 0x9e09); -+ mdio_write(tp, 0x06, 0x0206); -+ mdio_write(tp, 0x06, 0x2802); -+ mdio_write(tp, 0x06, 0x80b1); -+ mdio_write(tp, 0x06, 0x0232); -+ mdio_write(tp, 0x06, 0xfdfc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xf9e0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xac26); -+ mdio_write(tp, 0x06, 0x1ae0); -+ mdio_write(tp, 0x06, 0x8b81); -+ mdio_write(tp, 0x06, 0xac21); -+ mdio_write(tp, 0x06, 0x14e0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xac20); -+ mdio_write(tp, 0x06, 0x0ee0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xac23); -+ mdio_write(tp, 0x06, 0x08e0); -+ mdio_write(tp, 0x06, 0x8b87); -+ mdio_write(tp, 0x06, 0xac24); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x3802); -+ mdio_write(tp, 0x06, 0x1b02); -+ mdio_write(tp, 0x06, 0xeee4); -+ mdio_write(tp, 0x06, 0x1c04); -+ mdio_write(tp, 0x06, 0xeee4); -+ mdio_write(tp, 0x06, 0x1d04); -+ mdio_write(tp, 0x06, 0xe2e0); -+ mdio_write(tp, 0x06, 0x7ce3); -+ mdio_write(tp, 0x06, 0xe07d); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x38e1); -+ mdio_write(tp, 0x06, 0xe039); -+ mdio_write(tp, 0x06, 0xad2e); -+ mdio_write(tp, 0x06, 0x1bad); -+ mdio_write(tp, 0x06, 0x390d); -+ mdio_write(tp, 0x06, 0xd101); -+ mdio_write(tp, 0x06, 0xbf22); -+ mdio_write(tp, 0x06, 0xe802); -+ mdio_write(tp, 0x06, 0x3a21); -+ mdio_write(tp, 0x06, 0x0222); -+ mdio_write(tp, 0x06, 0x10ae); -+ mdio_write(tp, 0x06, 0x0bac); -+ mdio_write(tp, 0x06, 0x3802); -+ mdio_write(tp, 0x06, 0xae06); -+ mdio_write(tp, 0x06, 0x0222); -+ mdio_write(tp, 0x06, 0x4d02); -+ mdio_write(tp, 0x06, 0x2292); -+ mdio_write(tp, 0x06, 0x021b); -+ mdio_write(tp, 0x06, 0x13fd); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x1af6); -+ mdio_write(tp, 0x06, 0x20e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x022b); -+ mdio_write(tp, 0x06, 0x1e02); -+ mdio_write(tp, 0x06, 0x82ae); -+ mdio_write(tp, 0x06, 0x0203); -+ mdio_write(tp, 0x06, 0xc002); -+ mdio_write(tp, 0x06, 0x827d); -+ mdio_write(tp, 0x06, 0x022e); -+ mdio_write(tp, 0x06, 0x6f02); -+ mdio_write(tp, 0x06, 0x047b); -+ mdio_write(tp, 0x06, 0x022f); -+ mdio_write(tp, 0x06, 0x9ae0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad21); -+ mdio_write(tp, 0x06, 0x0bf6); -+ mdio_write(tp, 0x06, 0x21e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0x9002); -+ mdio_write(tp, 0x06, 0x1cd9); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2208); -+ mdio_write(tp, 0x06, 0xf622); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x35f4); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2308); -+ mdio_write(tp, 0x06, 0xf623); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x31e8); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2405); -+ mdio_write(tp, 0x06, 0xf624); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8ee0); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xad25); -+ mdio_write(tp, 0x06, 0x05f6); -+ mdio_write(tp, 0x06, 0x25e4); -+ mdio_write(tp, 0x06, 0x8b8e); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2608); -+ mdio_write(tp, 0x06, 0xf626); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x2d8a); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x8ead); -+ mdio_write(tp, 0x06, 0x2705); -+ mdio_write(tp, 0x06, 0xf627); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x8e02); -+ mdio_write(tp, 0x06, 0x0386); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xef69); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x00e1); -+ mdio_write(tp, 0x06, 0xe001); -+ mdio_write(tp, 0x06, 0xad27); -+ mdio_write(tp, 0x06, 0x32e0); -+ mdio_write(tp, 0x06, 0x8b40); -+ mdio_write(tp, 0x06, 0xf720); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x40bf); -+ mdio_write(tp, 0x06, 0x32c1); -+ mdio_write(tp, 0x06, 0x0239); -+ mdio_write(tp, 0x06, 0xf4ad); -+ mdio_write(tp, 0x06, 0x2821); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x20e1); -+ mdio_write(tp, 0x06, 0xe021); -+ mdio_write(tp, 0x06, 0xad20); -+ mdio_write(tp, 0x06, 0x18e0); -+ mdio_write(tp, 0x06, 0x8b40); -+ mdio_write(tp, 0x06, 0xf620); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x40ee); -+ mdio_write(tp, 0x06, 0x8b3b); -+ mdio_write(tp, 0x06, 0xffe0); -+ mdio_write(tp, 0x06, 0x8a8a); -+ mdio_write(tp, 0x06, 0xe18a); -+ mdio_write(tp, 0x06, 0x8be4); -+ mdio_write(tp, 0x06, 0xe000); -+ mdio_write(tp, 0x06, 0xe5e0); -+ mdio_write(tp, 0x06, 0x01ef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8f9); -+ mdio_write(tp, 0x06, 0xface); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x69fa); -+ mdio_write(tp, 0x06, 0xd401); -+ mdio_write(tp, 0x06, 0x55b4); -+ mdio_write(tp, 0x06, 0xfebf); -+ mdio_write(tp, 0x06, 0x1c5e); -+ mdio_write(tp, 0x06, 0x0239); -+ mdio_write(tp, 0x06, 0xf4ac); -+ mdio_write(tp, 0x06, 0x280b); -+ mdio_write(tp, 0x06, 0xbf1c); -+ mdio_write(tp, 0x06, 0x5b02); -+ mdio_write(tp, 0x06, 0x39f4); -+ mdio_write(tp, 0x06, 0xac28); -+ mdio_write(tp, 0x06, 0x49ae); -+ mdio_write(tp, 0x06, 0x64bf); -+ mdio_write(tp, 0x06, 0x1c5b); -+ mdio_write(tp, 0x06, 0x0239); -+ mdio_write(tp, 0x06, 0xf4ac); -+ mdio_write(tp, 0x06, 0x285b); -+ mdio_write(tp, 0x06, 0xd000); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0x62ac); -+ mdio_write(tp, 0x06, 0x2105); -+ mdio_write(tp, 0x06, 0xac22); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x4ebf); -+ mdio_write(tp, 0x06, 0xe0c4); -+ mdio_write(tp, 0x06, 0xbe85); -+ mdio_write(tp, 0x06, 0xecd2); -+ mdio_write(tp, 0x06, 0x04d8); -+ mdio_write(tp, 0x06, 0x19d9); -+ mdio_write(tp, 0x06, 0x1907); -+ mdio_write(tp, 0x06, 0xdc19); -+ mdio_write(tp, 0x06, 0xdd19); -+ mdio_write(tp, 0x06, 0x0789); -+ mdio_write(tp, 0x06, 0x89ef); -+ mdio_write(tp, 0x06, 0x645e); -+ mdio_write(tp, 0x06, 0x07ff); -+ mdio_write(tp, 0x06, 0x0d65); -+ mdio_write(tp, 0x06, 0x5cf8); -+ mdio_write(tp, 0x06, 0x001e); -+ mdio_write(tp, 0x06, 0x46dc); -+ mdio_write(tp, 0x06, 0x19dd); -+ mdio_write(tp, 0x06, 0x19b2); -+ mdio_write(tp, 0x06, 0xe2d4); -+ mdio_write(tp, 0x06, 0x0001); -+ mdio_write(tp, 0x06, 0xbf1c); -+ mdio_write(tp, 0x06, 0x5b02); -+ mdio_write(tp, 0x06, 0x3a21); -+ mdio_write(tp, 0x06, 0xae1d); -+ mdio_write(tp, 0x06, 0xbee0); -+ mdio_write(tp, 0x06, 0xc4bf); -+ mdio_write(tp, 0x06, 0x85ec); -+ mdio_write(tp, 0x06, 0xd204); -+ mdio_write(tp, 0x06, 0xd819); -+ mdio_write(tp, 0x06, 0xd919); -+ mdio_write(tp, 0x06, 0x07dc); -+ mdio_write(tp, 0x06, 0x19dd); -+ mdio_write(tp, 0x06, 0x1907); -+ mdio_write(tp, 0x06, 0xb2f4); -+ mdio_write(tp, 0x06, 0xd400); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x1c5b); -+ mdio_write(tp, 0x06, 0x023a); -+ mdio_write(tp, 0x06, 0x21fe); -+ mdio_write(tp, 0x06, 0xef96); -+ mdio_write(tp, 0x06, 0xfec6); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc05); -+ mdio_write(tp, 0x06, 0xf9e2); -+ mdio_write(tp, 0x06, 0xe0ea); -+ mdio_write(tp, 0x06, 0xe3e0); -+ mdio_write(tp, 0x06, 0xeb5a); -+ mdio_write(tp, 0x06, 0x070c); -+ mdio_write(tp, 0x06, 0x031e); -+ mdio_write(tp, 0x06, 0x20e6); -+ mdio_write(tp, 0x06, 0xe0ea); -+ mdio_write(tp, 0x06, 0xe7e0); -+ mdio_write(tp, 0x06, 0xebe0); -+ mdio_write(tp, 0x06, 0xe0fc); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0xfdfd); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x69e0); -+ mdio_write(tp, 0x06, 0x8b80); -+ mdio_write(tp, 0x06, 0xad27); -+ mdio_write(tp, 0x06, 0x22bf); -+ mdio_write(tp, 0x06, 0x47ba); -+ mdio_write(tp, 0x06, 0x0239); -+ mdio_write(tp, 0x06, 0xf4e0); -+ mdio_write(tp, 0x06, 0x8b44); -+ mdio_write(tp, 0x06, 0x1f01); -+ mdio_write(tp, 0x06, 0x9e15); -+ mdio_write(tp, 0x06, 0xe58b); -+ mdio_write(tp, 0x06, 0x44ad); -+ mdio_write(tp, 0x06, 0x2907); -+ mdio_write(tp, 0x06, 0xac28); -+ mdio_write(tp, 0x06, 0x04d1); -+ mdio_write(tp, 0x06, 0x01ae); -+ mdio_write(tp, 0x06, 0x02d1); -+ mdio_write(tp, 0x06, 0x00bf); -+ mdio_write(tp, 0x06, 0x8342); -+ mdio_write(tp, 0x06, 0x023a); -+ mdio_write(tp, 0x06, 0x21ef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xad26); -+ mdio_write(tp, 0x06, 0x30e0); -+ mdio_write(tp, 0x06, 0xe036); -+ mdio_write(tp, 0x06, 0xe1e0); -+ mdio_write(tp, 0x06, 0x37e1); -+ mdio_write(tp, 0x06, 0x8b3f); -+ mdio_write(tp, 0x06, 0x1f10); -+ mdio_write(tp, 0x06, 0x9e23); -+ mdio_write(tp, 0x06, 0xe48b); -+ mdio_write(tp, 0x06, 0x3fac); -+ mdio_write(tp, 0x06, 0x200b); -+ mdio_write(tp, 0x06, 0xac21); -+ mdio_write(tp, 0x06, 0x0dac); -+ mdio_write(tp, 0x06, 0x250f); -+ mdio_write(tp, 0x06, 0xac27); -+ mdio_write(tp, 0x06, 0x11ae); -+ mdio_write(tp, 0x06, 0x1202); -+ mdio_write(tp, 0x06, 0x2cb5); -+ mdio_write(tp, 0x06, 0xae0d); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0xe7ae); -+ mdio_write(tp, 0x06, 0x0802); -+ mdio_write(tp, 0x06, 0x2cd7); -+ mdio_write(tp, 0x06, 0xae03); -+ mdio_write(tp, 0x06, 0x022c); -+ mdio_write(tp, 0x06, 0xeafc); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x6902); -+ mdio_write(tp, 0x06, 0x8304); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x14e1); -+ mdio_write(tp, 0x06, 0xe015); -+ mdio_write(tp, 0x06, 0xad26); -+ mdio_write(tp, 0x06, 0x08d1); -+ mdio_write(tp, 0x06, 0x1ebf); -+ mdio_write(tp, 0x06, 0x2d47); -+ mdio_write(tp, 0x06, 0x023a); -+ mdio_write(tp, 0x06, 0x21ef); -+ mdio_write(tp, 0x06, 0x96fe); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0x8b85); -+ mdio_write(tp, 0x06, 0xad27); -+ mdio_write(tp, 0x06, 0x2fd0); -+ mdio_write(tp, 0x06, 0x0b02); -+ mdio_write(tp, 0x06, 0x3826); -+ mdio_write(tp, 0x06, 0x5882); -+ mdio_write(tp, 0x06, 0x7882); -+ mdio_write(tp, 0x06, 0x9f24); -+ mdio_write(tp, 0x06, 0xe08b); -+ mdio_write(tp, 0x06, 0x32e1); -+ mdio_write(tp, 0x06, 0x8b33); -+ mdio_write(tp, 0x06, 0x1f10); -+ mdio_write(tp, 0x06, 0x9e1a); -+ mdio_write(tp, 0x06, 0x10e4); -+ mdio_write(tp, 0x06, 0x8b32); -+ mdio_write(tp, 0x06, 0xe0e0); -+ mdio_write(tp, 0x06, 0x28e1); -+ mdio_write(tp, 0x06, 0xe029); -+ mdio_write(tp, 0x06, 0xf72c); -+ mdio_write(tp, 0x06, 0xe4e0); -+ mdio_write(tp, 0x06, 0x28e5); -+ mdio_write(tp, 0x06, 0xe029); -+ mdio_write(tp, 0x06, 0xf62c); -+ mdio_write(tp, 0x06, 0xe4e0); -+ mdio_write(tp, 0x06, 0x28e5); -+ mdio_write(tp, 0x06, 0xe029); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0x00e1); -+ mdio_write(tp, 0x06, 0x4077); -+ mdio_write(tp, 0x06, 0xe140); -+ mdio_write(tp, 0x06, 0xbbe0); -+ mdio_write(tp, 0x06, 0x2a00); -+ mdio_write(tp, 0x05, 0xe142); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp,0x06, gphy_val); -+ mdio_write(tp, 0x05, 0xe140); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp,0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp,0x1f, 0x0005); -+ for (i = 0; i < 200; i++) { -+ udelay(100); -+ gphy_val = mdio_read(tp, 0x00); -+ if (gphy_val & BIT_7) -+ break; -+ } -+ mdio_write(tp,0x1f, 0x0007); -+ mdio_write(tp,0x1e, 0x0023); -+ gphy_val = mdio_read(tp, 0x17); -+ gphy_val |= BIT_1; -+ if (tp->RequiredSecLanDonglePatch) -+ gphy_val &= ~BIT_2; -+ mdio_write(tp,0x17, gphy_val); -+ mdio_write(tp,0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x09, 0xA20F); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x1f, 0x0003); -+ mdio_write(tp, 0x01, 0x328A); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp,0x1f, 0x0000); -+ mdio_write(tp,0x00, 0x9200); -+} -+ -+static void -+rtl8168_set_phy_mcu_8168g_1(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned int gphy_val,i; -+ -+ mdio_write(tp, 0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val |= BIT_4; -+ mdio_write(tp, 0x10, gphy_val); -+ mdio_write(tp, 0x1f, 0x0B80); -+ for (i = 0; i < 10; i++) { -+ if (mdio_read(tp, 0x10) & 0x0040) -+ break; -+ mdelay(10); -+ } -+ mdio_write(tp, 0x1f, 0x0A43); -+ mdio_write(tp, 0x13, 0x8146); -+ mdio_write(tp, 0x14, 0x2300); -+ mdio_write(tp, 0x13, 0xB820); -+ mdio_write(tp, 0x14, 0x0210); -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0xB820); -+ mdio_write(tp, 0x14, 0x0290); -+ mdio_write(tp, 0x13, 0xA012); -+ mdio_write(tp, 0x14, 0x0000); -+ mdio_write(tp, 0x13, 0xA014); -+ mdio_write(tp, 0x14, 0x2c04); -+ mdio_write(tp, 0x14, 0x2c0c); -+ mdio_write(tp, 0x14, 0x2c6c); -+ mdio_write(tp, 0x14, 0x2d0d); -+ mdio_write(tp, 0x14, 0x31ce); -+ mdio_write(tp, 0x14, 0x506d); -+ mdio_write(tp, 0x14, 0xd708); -+ mdio_write(tp, 0x14, 0x3108); -+ mdio_write(tp, 0x14, 0x106d); -+ mdio_write(tp, 0x14, 0x1560); -+ mdio_write(tp, 0x14, 0x15a9); -+ mdio_write(tp, 0x14, 0x206e); -+ mdio_write(tp, 0x14, 0x175b); -+ mdio_write(tp, 0x14, 0x6062); -+ mdio_write(tp, 0x14, 0xd700); -+ mdio_write(tp, 0x14, 0x5fae); -+ mdio_write(tp, 0x14, 0xd708); -+ mdio_write(tp, 0x14, 0x3107); -+ mdio_write(tp, 0x14, 0x4c1e); -+ mdio_write(tp, 0x14, 0x4169); -+ mdio_write(tp, 0x14, 0x316a); -+ mdio_write(tp, 0x14, 0x0c19); -+ mdio_write(tp, 0x14, 0x31aa); -+ mdio_write(tp, 0x14, 0x0c19); -+ mdio_write(tp, 0x14, 0x2c1b); -+ mdio_write(tp, 0x14, 0x5e62); -+ mdio_write(tp, 0x14, 0x26b5); -+ mdio_write(tp, 0x14, 0x31ab); -+ mdio_write(tp, 0x14, 0x5c1e); -+ mdio_write(tp, 0x14, 0x2c0c); -+ mdio_write(tp, 0x14, 0xc040); -+ mdio_write(tp, 0x14, 0x8808); -+ mdio_write(tp, 0x14, 0xc520); -+ mdio_write(tp, 0x14, 0xc421); -+ mdio_write(tp, 0x14, 0xd05a); -+ mdio_write(tp, 0x14, 0xd19a); -+ mdio_write(tp, 0x14, 0xd709); -+ mdio_write(tp, 0x14, 0x608f); -+ mdio_write(tp, 0x14, 0xd06b); -+ mdio_write(tp, 0x14, 0xd18a); -+ mdio_write(tp, 0x14, 0x2c2c); -+ mdio_write(tp, 0x14, 0xd0be); -+ mdio_write(tp, 0x14, 0xd188); -+ mdio_write(tp, 0x14, 0x2c2c); -+ mdio_write(tp, 0x14, 0xd708); -+ mdio_write(tp, 0x14, 0x4072); -+ mdio_write(tp, 0x14, 0xc104); -+ mdio_write(tp, 0x14, 0x2c3e); -+ mdio_write(tp, 0x14, 0x4076); -+ mdio_write(tp, 0x14, 0xc110); -+ mdio_write(tp, 0x14, 0x2c3e); -+ mdio_write(tp, 0x14, 0x4071); -+ mdio_write(tp, 0x14, 0xc102); -+ mdio_write(tp, 0x14, 0x2c3e); -+ mdio_write(tp, 0x14, 0x4070); -+ mdio_write(tp, 0x14, 0xc101); -+ mdio_write(tp, 0x14, 0x2c3e); -+ mdio_write(tp, 0x14, 0x175b); -+ mdio_write(tp, 0x14, 0xd709); -+ mdio_write(tp, 0x14, 0x3390); -+ mdio_write(tp, 0x14, 0x5c39); -+ mdio_write(tp, 0x14, 0x2c4e); -+ mdio_write(tp, 0x14, 0x175b); -+ mdio_write(tp, 0x14, 0xd708); -+ mdio_write(tp, 0x14, 0x6193); -+ mdio_write(tp, 0x14, 0xd709); -+ mdio_write(tp, 0x14, 0x5f9d); -+ mdio_write(tp, 0x14, 0x408b); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x6042); -+ mdio_write(tp, 0x14, 0xb401); -+ mdio_write(tp, 0x14, 0x175b); -+ mdio_write(tp, 0x14, 0xd708); -+ mdio_write(tp, 0x14, 0x6073); -+ mdio_write(tp, 0x14, 0x5fbc); -+ mdio_write(tp, 0x14, 0x2c4d); -+ mdio_write(tp, 0x14, 0x26ed); -+ mdio_write(tp, 0x14, 0xb280); -+ mdio_write(tp, 0x14, 0xa841); -+ mdio_write(tp, 0x14, 0x9420); -+ mdio_write(tp, 0x14, 0x8710); -+ mdio_write(tp, 0x14, 0xd709); -+ mdio_write(tp, 0x14, 0x42ec); -+ mdio_write(tp, 0x14, 0x606d); -+ mdio_write(tp, 0x14, 0xd207); -+ mdio_write(tp, 0x14, 0x2c57); -+ mdio_write(tp, 0x14, 0xd203); -+ mdio_write(tp, 0x14, 0x33ff); -+ mdio_write(tp, 0x14, 0x563b); -+ mdio_write(tp, 0x14, 0x3275); -+ mdio_write(tp, 0x14, 0x7c5e); -+ mdio_write(tp, 0x14, 0xb240); -+ mdio_write(tp, 0x14, 0xb402); -+ mdio_write(tp, 0x14, 0x263b); -+ mdio_write(tp, 0x14, 0x6096); -+ mdio_write(tp, 0x14, 0xb240); -+ mdio_write(tp, 0x14, 0xb406); -+ mdio_write(tp, 0x14, 0x263b); -+ mdio_write(tp, 0x14, 0x31d7); -+ mdio_write(tp, 0x14, 0x7c67); -+ mdio_write(tp, 0x14, 0xb240); -+ mdio_write(tp, 0x14, 0xb40e); -+ mdio_write(tp, 0x14, 0x263b); -+ mdio_write(tp, 0x14, 0xb410); -+ mdio_write(tp, 0x14, 0x8802); -+ mdio_write(tp, 0x14, 0xb240); -+ mdio_write(tp, 0x14, 0x940e); -+ mdio_write(tp, 0x14, 0x263b); -+ mdio_write(tp, 0x14, 0xba04); -+ mdio_write(tp, 0x14, 0x1cd6); -+ mdio_write(tp, 0x14, 0xa902); -+ mdio_write(tp, 0x14, 0xd711); -+ mdio_write(tp, 0x14, 0x4045); -+ mdio_write(tp, 0x14, 0xa980); -+ mdio_write(tp, 0x14, 0x3003); -+ mdio_write(tp, 0x14, 0x59b1); -+ mdio_write(tp, 0x14, 0xa540); -+ mdio_write(tp, 0x14, 0xa601); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x4043); -+ mdio_write(tp, 0x14, 0xa910); -+ mdio_write(tp, 0x14, 0xd711); -+ mdio_write(tp, 0x14, 0x60a0); -+ mdio_write(tp, 0x14, 0xca33); -+ mdio_write(tp, 0x14, 0xcb33); -+ mdio_write(tp, 0x14, 0xa941); -+ mdio_write(tp, 0x14, 0x2c82); -+ mdio_write(tp, 0x14, 0xcaff); -+ mdio_write(tp, 0x14, 0xcbff); -+ mdio_write(tp, 0x14, 0xa921); -+ mdio_write(tp, 0x14, 0xce02); -+ mdio_write(tp, 0x14, 0xe070); -+ mdio_write(tp, 0x14, 0x0f10); -+ mdio_write(tp, 0x14, 0xaf01); -+ mdio_write(tp, 0x14, 0x8f01); -+ mdio_write(tp, 0x14, 0x1766); -+ mdio_write(tp, 0x14, 0x8e02); -+ mdio_write(tp, 0x14, 0x1787); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x609c); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x7fa4); -+ mdio_write(tp, 0x14, 0x2cd4); -+ mdio_write(tp, 0x14, 0x1ce9); -+ mdio_write(tp, 0x14, 0xce04); -+ mdio_write(tp, 0x14, 0xe070); -+ mdio_write(tp, 0x14, 0x0f20); -+ mdio_write(tp, 0x14, 0xaf01); -+ mdio_write(tp, 0x14, 0x8f01); -+ mdio_write(tp, 0x14, 0x1766); -+ mdio_write(tp, 0x14, 0x8e04); -+ mdio_write(tp, 0x14, 0x6044); -+ mdio_write(tp, 0x14, 0x2cd4); -+ mdio_write(tp, 0x14, 0xa520); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x4043); -+ mdio_write(tp, 0x14, 0x2cc1); -+ mdio_write(tp, 0x14, 0xe00f); -+ mdio_write(tp, 0x14, 0x0501); -+ mdio_write(tp, 0x14, 0x1cef); -+ mdio_write(tp, 0x14, 0xb801); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x4060); -+ mdio_write(tp, 0x14, 0x7fc4); -+ mdio_write(tp, 0x14, 0x2cd4); -+ mdio_write(tp, 0x14, 0x1cf5); -+ mdio_write(tp, 0x14, 0xe00f); -+ mdio_write(tp, 0x14, 0x0502); -+ mdio_write(tp, 0x14, 0x1cef); -+ mdio_write(tp, 0x14, 0xb802); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x4061); -+ mdio_write(tp, 0x14, 0x7fc4); -+ mdio_write(tp, 0x14, 0x2cd4); -+ mdio_write(tp, 0x14, 0x1cf5); -+ mdio_write(tp, 0x14, 0xe00f); -+ mdio_write(tp, 0x14, 0x0504); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x6099); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x7fa4); -+ mdio_write(tp, 0x14, 0x2cd4); -+ mdio_write(tp, 0x14, 0xc17f); -+ mdio_write(tp, 0x14, 0xc200); -+ mdio_write(tp, 0x14, 0xc43f); -+ mdio_write(tp, 0x14, 0xcc03); -+ mdio_write(tp, 0x14, 0xa701); -+ mdio_write(tp, 0x14, 0xa510); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x4018); -+ mdio_write(tp, 0x14, 0x9910); -+ mdio_write(tp, 0x14, 0x8510); -+ mdio_write(tp, 0x14, 0x2860); -+ mdio_write(tp, 0x14, 0xe00f); -+ mdio_write(tp, 0x14, 0x0504); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x6099); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x7fa4); -+ mdio_write(tp, 0x14, 0x2cd4); -+ mdio_write(tp, 0x14, 0xa608); -+ mdio_write(tp, 0x14, 0xc17d); -+ mdio_write(tp, 0x14, 0xc200); -+ mdio_write(tp, 0x14, 0xc43f); -+ mdio_write(tp, 0x14, 0xcc03); -+ mdio_write(tp, 0x14, 0xa701); -+ mdio_write(tp, 0x14, 0xa510); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x4018); -+ mdio_write(tp, 0x14, 0x9910); -+ mdio_write(tp, 0x14, 0x8510); -+ mdio_write(tp, 0x14, 0x2926); -+ mdio_write(tp, 0x14, 0x1792); -+ mdio_write(tp, 0x14, 0x27db); -+ mdio_write(tp, 0x14, 0xc000); -+ mdio_write(tp, 0x14, 0xc100); -+ mdio_write(tp, 0x14, 0xc200); -+ mdio_write(tp, 0x14, 0xc300); -+ mdio_write(tp, 0x14, 0xc400); -+ mdio_write(tp, 0x14, 0xc500); -+ mdio_write(tp, 0x14, 0xc600); -+ mdio_write(tp, 0x14, 0xc7c1); -+ mdio_write(tp, 0x14, 0xc800); -+ mdio_write(tp, 0x14, 0xcc00); -+ mdio_write(tp, 0x14, 0x0800); -+ mdio_write(tp, 0x14, 0xca0f); -+ mdio_write(tp, 0x14, 0xcbff); -+ mdio_write(tp, 0x14, 0xa901); -+ mdio_write(tp, 0x14, 0x8902); -+ mdio_write(tp, 0x14, 0xc900); -+ mdio_write(tp, 0x14, 0xca00); -+ mdio_write(tp, 0x14, 0xcb00); -+ mdio_write(tp, 0x14, 0x0800); -+ mdio_write(tp, 0x14, 0xb804); -+ mdio_write(tp, 0x14, 0x0800); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x6044); -+ mdio_write(tp, 0x14, 0x9804); -+ mdio_write(tp, 0x14, 0x0800); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x6099); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x7fa4); -+ mdio_write(tp, 0x14, 0x2cd4); -+ mdio_write(tp, 0x14, 0x0800); -+ mdio_write(tp, 0x14, 0xa510); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x6098); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x7fa4); -+ mdio_write(tp, 0x14, 0x2cd4); -+ mdio_write(tp, 0x14, 0x8510); -+ mdio_write(tp, 0x14, 0x0800); -+ mdio_write(tp, 0x14, 0xd711); -+ mdio_write(tp, 0x14, 0x3003); -+ mdio_write(tp, 0x14, 0x1d01); -+ mdio_write(tp, 0x14, 0x2d0b); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x60be); -+ mdio_write(tp, 0x14, 0xe060); -+ mdio_write(tp, 0x14, 0x0920); -+ mdio_write(tp, 0x14, 0x1cd6); -+ mdio_write(tp, 0x14, 0x2c89); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x3063); -+ mdio_write(tp, 0x14, 0x1948); -+ mdio_write(tp, 0x14, 0x288a); -+ mdio_write(tp, 0x14, 0x1cd6); -+ mdio_write(tp, 0x14, 0x29bd); -+ mdio_write(tp, 0x14, 0xa802); -+ mdio_write(tp, 0x14, 0xa303); -+ mdio_write(tp, 0x14, 0x843f); -+ mdio_write(tp, 0x14, 0x81ff); -+ mdio_write(tp, 0x14, 0x8208); -+ mdio_write(tp, 0x14, 0xa201); -+ mdio_write(tp, 0x14, 0xc001); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x30a0); -+ mdio_write(tp, 0x14, 0x0d1c); -+ mdio_write(tp, 0x14, 0x30a0); -+ mdio_write(tp, 0x14, 0x3d13); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x7f4c); -+ mdio_write(tp, 0x14, 0x2ab6); -+ mdio_write(tp, 0x14, 0xe003); -+ mdio_write(tp, 0x14, 0x0202); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x6090); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x7fac); -+ mdio_write(tp, 0x14, 0x2ab6); -+ mdio_write(tp, 0x14, 0xa20c); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x6091); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x7fac); -+ mdio_write(tp, 0x14, 0x2ab6); -+ mdio_write(tp, 0x14, 0x820e); -+ mdio_write(tp, 0x14, 0xa3e0); -+ mdio_write(tp, 0x14, 0xa520); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x609d); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x7fac); -+ mdio_write(tp, 0x14, 0x2ab6); -+ mdio_write(tp, 0x14, 0x8520); -+ mdio_write(tp, 0x14, 0x6703); -+ mdio_write(tp, 0x14, 0x2d34); -+ mdio_write(tp, 0x14, 0xa13e); -+ mdio_write(tp, 0x14, 0xc001); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x4000); -+ mdio_write(tp, 0x14, 0x6046); -+ mdio_write(tp, 0x14, 0x2d0d); -+ mdio_write(tp, 0x14, 0xa43f); -+ mdio_write(tp, 0x14, 0xa101); -+ mdio_write(tp, 0x14, 0xc020); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x3121); -+ mdio_write(tp, 0x14, 0x0d45); -+ mdio_write(tp, 0x14, 0x30c0); -+ mdio_write(tp, 0x14, 0x3d0d); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x7f4c); -+ mdio_write(tp, 0x14, 0x2ab6); -+ mdio_write(tp, 0x14, 0xa540); -+ mdio_write(tp, 0x14, 0xc001); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x4001); -+ mdio_write(tp, 0x14, 0xe00f); -+ mdio_write(tp, 0x14, 0x0501); -+ mdio_write(tp, 0x14, 0x1dac); -+ mdio_write(tp, 0x14, 0xc1c4); -+ mdio_write(tp, 0x14, 0xa268); -+ mdio_write(tp, 0x14, 0xa303); -+ mdio_write(tp, 0x14, 0x8420); -+ mdio_write(tp, 0x14, 0xe00f); -+ mdio_write(tp, 0x14, 0x0502); -+ mdio_write(tp, 0x14, 0x1dac); -+ mdio_write(tp, 0x14, 0xc002); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x4000); -+ mdio_write(tp, 0x14, 0x8208); -+ mdio_write(tp, 0x14, 0x8410); -+ mdio_write(tp, 0x14, 0xa121); -+ mdio_write(tp, 0x14, 0xc002); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x4000); -+ mdio_write(tp, 0x14, 0x8120); -+ mdio_write(tp, 0x14, 0x8180); -+ mdio_write(tp, 0x14, 0x1d97); -+ mdio_write(tp, 0x14, 0xa180); -+ mdio_write(tp, 0x14, 0xa13a); -+ mdio_write(tp, 0x14, 0x8240); -+ mdio_write(tp, 0x14, 0xa430); -+ mdio_write(tp, 0x14, 0xc010); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x30e1); -+ mdio_write(tp, 0x14, 0x0abc); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x7f8c); -+ mdio_write(tp, 0x14, 0x2ab6); -+ mdio_write(tp, 0x14, 0xa480); -+ mdio_write(tp, 0x14, 0xa230); -+ mdio_write(tp, 0x14, 0xa303); -+ mdio_write(tp, 0x14, 0xc001); -+ mdio_write(tp, 0x14, 0xd70c); -+ mdio_write(tp, 0x14, 0x4124); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x6120); -+ mdio_write(tp, 0x14, 0xd711); -+ mdio_write(tp, 0x14, 0x3128); -+ mdio_write(tp, 0x14, 0x3d76); -+ mdio_write(tp, 0x14, 0x2d70); -+ mdio_write(tp, 0x14, 0xa801); -+ mdio_write(tp, 0x14, 0x2d6c); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x4000); -+ mdio_write(tp, 0x14, 0xe018); -+ mdio_write(tp, 0x14, 0x0208); -+ mdio_write(tp, 0x14, 0xa1f8); -+ mdio_write(tp, 0x14, 0x8480); -+ mdio_write(tp, 0x14, 0xc004); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x4000); -+ mdio_write(tp, 0x14, 0x6046); -+ mdio_write(tp, 0x14, 0x2d0d); -+ mdio_write(tp, 0x14, 0xa43f); -+ mdio_write(tp, 0x14, 0xa105); -+ mdio_write(tp, 0x14, 0x8228); -+ mdio_write(tp, 0x14, 0xc004); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x4000); -+ mdio_write(tp, 0x14, 0x81bc); -+ mdio_write(tp, 0x14, 0xa220); -+ mdio_write(tp, 0x14, 0x1d97); -+ mdio_write(tp, 0x14, 0x8220); -+ mdio_write(tp, 0x14, 0xa1bc); -+ mdio_write(tp, 0x14, 0xc040); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x30e1); -+ mdio_write(tp, 0x14, 0x0abc); -+ mdio_write(tp, 0x14, 0x30e1); -+ mdio_write(tp, 0x14, 0x3d0d); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x7f4c); -+ mdio_write(tp, 0x14, 0x2ab6); -+ mdio_write(tp, 0x14, 0xa802); -+ mdio_write(tp, 0x14, 0xd70c); -+ mdio_write(tp, 0x14, 0x4244); -+ mdio_write(tp, 0x14, 0xa301); -+ mdio_write(tp, 0x14, 0xc004); -+ mdio_write(tp, 0x14, 0xd711); -+ mdio_write(tp, 0x14, 0x3128); -+ mdio_write(tp, 0x14, 0x3da5); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x5f80); -+ mdio_write(tp, 0x14, 0xd711); -+ mdio_write(tp, 0x14, 0x3109); -+ mdio_write(tp, 0x14, 0x3da7); -+ mdio_write(tp, 0x14, 0x2dab); -+ mdio_write(tp, 0x14, 0xa801); -+ mdio_write(tp, 0x14, 0x2d9a); -+ mdio_write(tp, 0x14, 0xa802); -+ mdio_write(tp, 0x14, 0xc004); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x4000); -+ mdio_write(tp, 0x14, 0x0800); -+ mdio_write(tp, 0x14, 0xa510); -+ mdio_write(tp, 0x14, 0xd710); -+ mdio_write(tp, 0x14, 0x609a); -+ mdio_write(tp, 0x14, 0xd71e); -+ mdio_write(tp, 0x14, 0x7fac); -+ mdio_write(tp, 0x14, 0x2ab6); -+ mdio_write(tp, 0x14, 0x8510); -+ mdio_write(tp, 0x14, 0x0800); -+ mdio_write(tp, 0x13, 0xA01A); -+ mdio_write(tp, 0x14, 0x0000); -+ mdio_write(tp, 0x13, 0xA006); -+ mdio_write(tp, 0x14, 0x0ad6); -+ mdio_write(tp, 0x13, 0xA004); -+ mdio_write(tp, 0x14, 0x07f5); -+ mdio_write(tp, 0x13, 0xA002); -+ mdio_write(tp, 0x14, 0x06a9); -+ mdio_write(tp, 0x13, 0xA000); -+ mdio_write(tp, 0x14, 0xf069); -+ mdio_write(tp, 0x13, 0xB820); -+ mdio_write(tp, 0x14, 0x0210); -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x83a0); -+ mdio_write(tp, 0x14, 0xaf83); -+ mdio_write(tp, 0x14, 0xacaf); -+ mdio_write(tp, 0x14, 0x83b8); -+ mdio_write(tp, 0x14, 0xaf83); -+ mdio_write(tp, 0x14, 0xcdaf); -+ mdio_write(tp, 0x14, 0x83d3); -+ mdio_write(tp, 0x14, 0x0204); -+ mdio_write(tp, 0x14, 0x9a02); -+ mdio_write(tp, 0x14, 0x09a9); -+ mdio_write(tp, 0x14, 0x0284); -+ mdio_write(tp, 0x14, 0x61af); -+ mdio_write(tp, 0x14, 0x02fc); -+ mdio_write(tp, 0x14, 0xad20); -+ mdio_write(tp, 0x14, 0x0302); -+ mdio_write(tp, 0x14, 0x867c); -+ mdio_write(tp, 0x14, 0xad21); -+ mdio_write(tp, 0x14, 0x0302); -+ mdio_write(tp, 0x14, 0x85c9); -+ mdio_write(tp, 0x14, 0xad22); -+ mdio_write(tp, 0x14, 0x0302); -+ mdio_write(tp, 0x14, 0x1bc0); -+ mdio_write(tp, 0x14, 0xaf17); -+ mdio_write(tp, 0x14, 0xe302); -+ mdio_write(tp, 0x14, 0x8703); -+ mdio_write(tp, 0x14, 0xaf18); -+ mdio_write(tp, 0x14, 0x6201); -+ mdio_write(tp, 0x14, 0x06e0); -+ mdio_write(tp, 0x14, 0x8148); -+ mdio_write(tp, 0x14, 0xaf3c); -+ mdio_write(tp, 0x14, 0x69f8); -+ mdio_write(tp, 0x14, 0xf9fa); -+ mdio_write(tp, 0x14, 0xef69); -+ mdio_write(tp, 0x14, 0xee80); -+ mdio_write(tp, 0x14, 0x10f7); -+ mdio_write(tp, 0x14, 0xee80); -+ mdio_write(tp, 0x14, 0x131f); -+ mdio_write(tp, 0x14, 0xd104); -+ mdio_write(tp, 0x14, 0xbf87); -+ mdio_write(tp, 0x14, 0xf302); -+ mdio_write(tp, 0x14, 0x4259); -+ mdio_write(tp, 0x14, 0x0287); -+ mdio_write(tp, 0x14, 0x88bf); -+ mdio_write(tp, 0x14, 0x87cf); -+ mdio_write(tp, 0x14, 0xd7b8); -+ mdio_write(tp, 0x14, 0x22d0); -+ mdio_write(tp, 0x14, 0x0c02); -+ mdio_write(tp, 0x14, 0x4252); -+ mdio_write(tp, 0x14, 0xee80); -+ mdio_write(tp, 0x14, 0xcda0); -+ mdio_write(tp, 0x14, 0xee80); -+ mdio_write(tp, 0x14, 0xce8b); -+ mdio_write(tp, 0x14, 0xee80); -+ mdio_write(tp, 0x14, 0xd1f5); -+ mdio_write(tp, 0x14, 0xee80); -+ mdio_write(tp, 0x14, 0xd2a9); -+ mdio_write(tp, 0x14, 0xee80); -+ mdio_write(tp, 0x14, 0xd30a); -+ mdio_write(tp, 0x14, 0xee80); -+ mdio_write(tp, 0x14, 0xf010); -+ mdio_write(tp, 0x14, 0xee80); -+ mdio_write(tp, 0x14, 0xf38f); -+ mdio_write(tp, 0x14, 0xee81); -+ mdio_write(tp, 0x14, 0x011e); -+ mdio_write(tp, 0x14, 0xee81); -+ mdio_write(tp, 0x14, 0x0b4a); -+ mdio_write(tp, 0x14, 0xee81); -+ mdio_write(tp, 0x14, 0x0c7c); -+ mdio_write(tp, 0x14, 0xee81); -+ mdio_write(tp, 0x14, 0x127f); -+ mdio_write(tp, 0x14, 0xd100); -+ mdio_write(tp, 0x14, 0x0210); -+ mdio_write(tp, 0x14, 0xb5ee); -+ mdio_write(tp, 0x14, 0x8088); -+ mdio_write(tp, 0x14, 0xa4ee); -+ mdio_write(tp, 0x14, 0x8089); -+ mdio_write(tp, 0x14, 0x44ee); -+ mdio_write(tp, 0x14, 0x809a); -+ mdio_write(tp, 0x14, 0xa4ee); -+ mdio_write(tp, 0x14, 0x809b); -+ mdio_write(tp, 0x14, 0x44ee); -+ mdio_write(tp, 0x14, 0x809c); -+ mdio_write(tp, 0x14, 0xa7ee); -+ mdio_write(tp, 0x14, 0x80a5); -+ mdio_write(tp, 0x14, 0xa7d2); -+ mdio_write(tp, 0x14, 0x0002); -+ mdio_write(tp, 0x14, 0x0e66); -+ mdio_write(tp, 0x14, 0x0285); -+ mdio_write(tp, 0x14, 0xc0ee); -+ mdio_write(tp, 0x14, 0x87fc); -+ mdio_write(tp, 0x14, 0x00e0); -+ mdio_write(tp, 0x14, 0x8245); -+ mdio_write(tp, 0x14, 0xf622); -+ mdio_write(tp, 0x14, 0xe482); -+ mdio_write(tp, 0x14, 0x45ef); -+ mdio_write(tp, 0x14, 0x96fe); -+ mdio_write(tp, 0x14, 0xfdfc); -+ mdio_write(tp, 0x14, 0x0402); -+ mdio_write(tp, 0x14, 0x847a); -+ mdio_write(tp, 0x14, 0x0284); -+ mdio_write(tp, 0x14, 0xb302); -+ mdio_write(tp, 0x14, 0x0cab); -+ mdio_write(tp, 0x14, 0x020c); -+ mdio_write(tp, 0x14, 0xc402); -+ mdio_write(tp, 0x14, 0x0cef); -+ mdio_write(tp, 0x14, 0x020d); -+ mdio_write(tp, 0x14, 0x0802); -+ mdio_write(tp, 0x14, 0x0d33); -+ mdio_write(tp, 0x14, 0x020c); -+ mdio_write(tp, 0x14, 0x3d04); -+ mdio_write(tp, 0x14, 0xf8fa); -+ mdio_write(tp, 0x14, 0xef69); -+ mdio_write(tp, 0x14, 0xe182); -+ mdio_write(tp, 0x14, 0x2fac); -+ mdio_write(tp, 0x14, 0x291a); -+ mdio_write(tp, 0x14, 0xe082); -+ mdio_write(tp, 0x14, 0x24ac); -+ mdio_write(tp, 0x14, 0x2102); -+ mdio_write(tp, 0x14, 0xae22); -+ mdio_write(tp, 0x14, 0x0210); -+ mdio_write(tp, 0x14, 0x57f6); -+ mdio_write(tp, 0x14, 0x21e4); -+ mdio_write(tp, 0x14, 0x8224); -+ mdio_write(tp, 0x14, 0xd101); -+ mdio_write(tp, 0x14, 0xbf44); -+ mdio_write(tp, 0x14, 0xd202); -+ mdio_write(tp, 0x14, 0x4259); -+ mdio_write(tp, 0x14, 0xae10); -+ mdio_write(tp, 0x14, 0x0212); -+ mdio_write(tp, 0x14, 0x4cf6); -+ mdio_write(tp, 0x14, 0x29e5); -+ mdio_write(tp, 0x14, 0x822f); -+ mdio_write(tp, 0x14, 0xe082); -+ mdio_write(tp, 0x14, 0x24f6); -+ mdio_write(tp, 0x14, 0x21e4); -+ mdio_write(tp, 0x14, 0x8224); -+ mdio_write(tp, 0x14, 0xef96); -+ mdio_write(tp, 0x14, 0xfefc); -+ mdio_write(tp, 0x14, 0x04f8); -+ mdio_write(tp, 0x14, 0xe182); -+ mdio_write(tp, 0x14, 0x2fac); -+ mdio_write(tp, 0x14, 0x2a18); -+ mdio_write(tp, 0x14, 0xe082); -+ mdio_write(tp, 0x14, 0x24ac); -+ mdio_write(tp, 0x14, 0x2202); -+ mdio_write(tp, 0x14, 0xae26); -+ mdio_write(tp, 0x14, 0x0284); -+ mdio_write(tp, 0x14, 0xf802); -+ mdio_write(tp, 0x14, 0x8565); -+ mdio_write(tp, 0x14, 0xd101); -+ mdio_write(tp, 0x14, 0xbf44); -+ mdio_write(tp, 0x14, 0xd502); -+ mdio_write(tp, 0x14, 0x4259); -+ mdio_write(tp, 0x14, 0xae0e); -+ mdio_write(tp, 0x14, 0x0284); -+ mdio_write(tp, 0x14, 0xea02); -+ mdio_write(tp, 0x14, 0x85a9); -+ mdio_write(tp, 0x14, 0xe182); -+ mdio_write(tp, 0x14, 0x2ff6); -+ mdio_write(tp, 0x14, 0x2ae5); -+ mdio_write(tp, 0x14, 0x822f); -+ mdio_write(tp, 0x14, 0xe082); -+ mdio_write(tp, 0x14, 0x24f6); -+ mdio_write(tp, 0x14, 0x22e4); -+ mdio_write(tp, 0x14, 0x8224); -+ mdio_write(tp, 0x14, 0xfc04); -+ mdio_write(tp, 0x14, 0xf9e2); -+ mdio_write(tp, 0x14, 0x8011); -+ mdio_write(tp, 0x14, 0xad31); -+ mdio_write(tp, 0x14, 0x05d2); -+ mdio_write(tp, 0x14, 0x0002); -+ mdio_write(tp, 0x14, 0x0e66); -+ mdio_write(tp, 0x14, 0xfd04); -+ mdio_write(tp, 0x14, 0xf8f9); -+ mdio_write(tp, 0x14, 0xfaef); -+ mdio_write(tp, 0x14, 0x69e0); -+ mdio_write(tp, 0x14, 0x8011); -+ mdio_write(tp, 0x14, 0xad21); -+ mdio_write(tp, 0x14, 0x5cbf); -+ mdio_write(tp, 0x14, 0x43be); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x97ac); -+ mdio_write(tp, 0x14, 0x281b); -+ mdio_write(tp, 0x14, 0xbf43); -+ mdio_write(tp, 0x14, 0xc102); -+ mdio_write(tp, 0x14, 0x4297); -+ mdio_write(tp, 0x14, 0xac28); -+ mdio_write(tp, 0x14, 0x12bf); -+ mdio_write(tp, 0x14, 0x43c7); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x97ac); -+ mdio_write(tp, 0x14, 0x2804); -+ mdio_write(tp, 0x14, 0xd300); -+ mdio_write(tp, 0x14, 0xae07); -+ mdio_write(tp, 0x14, 0xd306); -+ mdio_write(tp, 0x14, 0xaf85); -+ mdio_write(tp, 0x14, 0x56d3); -+ mdio_write(tp, 0x14, 0x03e0); -+ mdio_write(tp, 0x14, 0x8011); -+ mdio_write(tp, 0x14, 0xad26); -+ mdio_write(tp, 0x14, 0x25bf); -+ mdio_write(tp, 0x14, 0x4559); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x97e2); -+ mdio_write(tp, 0x14, 0x8073); -+ mdio_write(tp, 0x14, 0x0d21); -+ mdio_write(tp, 0x14, 0xf637); -+ mdio_write(tp, 0x14, 0x0d11); -+ mdio_write(tp, 0x14, 0xf62f); -+ mdio_write(tp, 0x14, 0x1b21); -+ mdio_write(tp, 0x14, 0xaa02); -+ mdio_write(tp, 0x14, 0xae10); -+ mdio_write(tp, 0x14, 0xe280); -+ mdio_write(tp, 0x14, 0x740d); -+ mdio_write(tp, 0x14, 0x21f6); -+ mdio_write(tp, 0x14, 0x371b); -+ mdio_write(tp, 0x14, 0x21aa); -+ mdio_write(tp, 0x14, 0x0313); -+ mdio_write(tp, 0x14, 0xae02); -+ mdio_write(tp, 0x14, 0x2b02); -+ mdio_write(tp, 0x14, 0x020e); -+ mdio_write(tp, 0x14, 0x5102); -+ mdio_write(tp, 0x14, 0x0e66); -+ mdio_write(tp, 0x14, 0x020f); -+ mdio_write(tp, 0x14, 0xa3ef); -+ mdio_write(tp, 0x14, 0x96fe); -+ mdio_write(tp, 0x14, 0xfdfc); -+ mdio_write(tp, 0x14, 0x04f8); -+ mdio_write(tp, 0x14, 0xf9fa); -+ mdio_write(tp, 0x14, 0xef69); -+ mdio_write(tp, 0x14, 0xe080); -+ mdio_write(tp, 0x14, 0x12ad); -+ mdio_write(tp, 0x14, 0x2733); -+ mdio_write(tp, 0x14, 0xbf43); -+ mdio_write(tp, 0x14, 0xbe02); -+ mdio_write(tp, 0x14, 0x4297); -+ mdio_write(tp, 0x14, 0xac28); -+ mdio_write(tp, 0x14, 0x09bf); -+ mdio_write(tp, 0x14, 0x43c1); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x97ad); -+ mdio_write(tp, 0x14, 0x2821); -+ mdio_write(tp, 0x14, 0xbf45); -+ mdio_write(tp, 0x14, 0x5902); -+ mdio_write(tp, 0x14, 0x4297); -+ mdio_write(tp, 0x14, 0xe387); -+ mdio_write(tp, 0x14, 0xffd2); -+ mdio_write(tp, 0x14, 0x001b); -+ mdio_write(tp, 0x14, 0x45ac); -+ mdio_write(tp, 0x14, 0x2711); -+ mdio_write(tp, 0x14, 0xe187); -+ mdio_write(tp, 0x14, 0xfebf); -+ mdio_write(tp, 0x14, 0x87e4); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x590d); -+ mdio_write(tp, 0x14, 0x11bf); -+ mdio_write(tp, 0x14, 0x87e7); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x59ef); -+ mdio_write(tp, 0x14, 0x96fe); -+ mdio_write(tp, 0x14, 0xfdfc); -+ mdio_write(tp, 0x14, 0x04f8); -+ mdio_write(tp, 0x14, 0xfaef); -+ mdio_write(tp, 0x14, 0x69d1); -+ mdio_write(tp, 0x14, 0x00bf); -+ mdio_write(tp, 0x14, 0x87e4); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x59bf); -+ mdio_write(tp, 0x14, 0x87e7); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x59ef); -+ mdio_write(tp, 0x14, 0x96fe); -+ mdio_write(tp, 0x14, 0xfc04); -+ mdio_write(tp, 0x14, 0xee87); -+ mdio_write(tp, 0x14, 0xff46); -+ mdio_write(tp, 0x14, 0xee87); -+ mdio_write(tp, 0x14, 0xfe01); -+ mdio_write(tp, 0x14, 0x04f8); -+ mdio_write(tp, 0x14, 0xfaef); -+ mdio_write(tp, 0x14, 0x69e0); -+ mdio_write(tp, 0x14, 0x8241); -+ mdio_write(tp, 0x14, 0xa000); -+ mdio_write(tp, 0x14, 0x0502); -+ mdio_write(tp, 0x14, 0x85eb); -+ mdio_write(tp, 0x14, 0xae0e); -+ mdio_write(tp, 0x14, 0xa001); -+ mdio_write(tp, 0x14, 0x0502); -+ mdio_write(tp, 0x14, 0x1a5a); -+ mdio_write(tp, 0x14, 0xae06); -+ mdio_write(tp, 0x14, 0xa002); -+ mdio_write(tp, 0x14, 0x0302); -+ mdio_write(tp, 0x14, 0x1ae6); -+ mdio_write(tp, 0x14, 0xef96); -+ mdio_write(tp, 0x14, 0xfefc); -+ mdio_write(tp, 0x14, 0x04f8); -+ mdio_write(tp, 0x14, 0xf9fa); -+ mdio_write(tp, 0x14, 0xef69); -+ mdio_write(tp, 0x14, 0xe082); -+ mdio_write(tp, 0x14, 0x29f6); -+ mdio_write(tp, 0x14, 0x21e4); -+ mdio_write(tp, 0x14, 0x8229); -+ mdio_write(tp, 0x14, 0xe080); -+ mdio_write(tp, 0x14, 0x10ac); -+ mdio_write(tp, 0x14, 0x2202); -+ mdio_write(tp, 0x14, 0xae76); -+ mdio_write(tp, 0x14, 0xe082); -+ mdio_write(tp, 0x14, 0x27f7); -+ mdio_write(tp, 0x14, 0x21e4); -+ mdio_write(tp, 0x14, 0x8227); -+ mdio_write(tp, 0x14, 0xbf43); -+ mdio_write(tp, 0x14, 0x1302); -+ mdio_write(tp, 0x14, 0x4297); -+ mdio_write(tp, 0x14, 0xef21); -+ mdio_write(tp, 0x14, 0xbf43); -+ mdio_write(tp, 0x14, 0x1602); -+ mdio_write(tp, 0x14, 0x4297); -+ mdio_write(tp, 0x14, 0x0c11); -+ mdio_write(tp, 0x14, 0x1e21); -+ mdio_write(tp, 0x14, 0xbf43); -+ mdio_write(tp, 0x14, 0x1902); -+ mdio_write(tp, 0x14, 0x4297); -+ mdio_write(tp, 0x14, 0x0c12); -+ mdio_write(tp, 0x14, 0x1e21); -+ mdio_write(tp, 0x14, 0xe682); -+ mdio_write(tp, 0x14, 0x43a2); -+ mdio_write(tp, 0x14, 0x000a); -+ mdio_write(tp, 0x14, 0xe182); -+ mdio_write(tp, 0x14, 0x27f6); -+ mdio_write(tp, 0x14, 0x29e5); -+ mdio_write(tp, 0x14, 0x8227); -+ mdio_write(tp, 0x14, 0xae42); -+ mdio_write(tp, 0x14, 0xe082); -+ mdio_write(tp, 0x14, 0x44f7); -+ mdio_write(tp, 0x14, 0x21e4); -+ mdio_write(tp, 0x14, 0x8244); -+ mdio_write(tp, 0x14, 0x0246); -+ mdio_write(tp, 0x14, 0xaebf); -+ mdio_write(tp, 0x14, 0x4325); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x97ef); -+ mdio_write(tp, 0x14, 0x21bf); -+ mdio_write(tp, 0x14, 0x431c); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x970c); -+ mdio_write(tp, 0x14, 0x121e); -+ mdio_write(tp, 0x14, 0x21bf); -+ mdio_write(tp, 0x14, 0x431f); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x970c); -+ mdio_write(tp, 0x14, 0x131e); -+ mdio_write(tp, 0x14, 0x21bf); -+ mdio_write(tp, 0x14, 0x4328); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x970c); -+ mdio_write(tp, 0x14, 0x141e); -+ mdio_write(tp, 0x14, 0x21bf); -+ mdio_write(tp, 0x14, 0x44b1); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x970c); -+ mdio_write(tp, 0x14, 0x161e); -+ mdio_write(tp, 0x14, 0x21e6); -+ mdio_write(tp, 0x14, 0x8242); -+ mdio_write(tp, 0x14, 0xee82); -+ mdio_write(tp, 0x14, 0x4101); -+ mdio_write(tp, 0x14, 0xef96); -+ mdio_write(tp, 0x14, 0xfefd); -+ mdio_write(tp, 0x14, 0xfc04); -+ mdio_write(tp, 0x14, 0xf8fa); -+ mdio_write(tp, 0x14, 0xef69); -+ mdio_write(tp, 0x14, 0xe082); -+ mdio_write(tp, 0x14, 0x46a0); -+ mdio_write(tp, 0x14, 0x0005); -+ mdio_write(tp, 0x14, 0x0286); -+ mdio_write(tp, 0x14, 0x96ae); -+ mdio_write(tp, 0x14, 0x06a0); -+ mdio_write(tp, 0x14, 0x0103); -+ mdio_write(tp, 0x14, 0x0219); -+ mdio_write(tp, 0x14, 0x19ef); -+ mdio_write(tp, 0x14, 0x96fe); -+ mdio_write(tp, 0x14, 0xfc04); -+ mdio_write(tp, 0x14, 0xf8fa); -+ mdio_write(tp, 0x14, 0xef69); -+ mdio_write(tp, 0x14, 0xe082); -+ mdio_write(tp, 0x14, 0x29f6); -+ mdio_write(tp, 0x14, 0x20e4); -+ mdio_write(tp, 0x14, 0x8229); -+ mdio_write(tp, 0x14, 0xe080); -+ mdio_write(tp, 0x14, 0x10ac); -+ mdio_write(tp, 0x14, 0x2102); -+ mdio_write(tp, 0x14, 0xae54); -+ mdio_write(tp, 0x14, 0xe082); -+ mdio_write(tp, 0x14, 0x27f7); -+ mdio_write(tp, 0x14, 0x20e4); -+ mdio_write(tp, 0x14, 0x8227); -+ mdio_write(tp, 0x14, 0xbf42); -+ mdio_write(tp, 0x14, 0xe602); -+ mdio_write(tp, 0x14, 0x4297); -+ mdio_write(tp, 0x14, 0xac28); -+ mdio_write(tp, 0x14, 0x22bf); -+ mdio_write(tp, 0x14, 0x430d); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x97e5); -+ mdio_write(tp, 0x14, 0x8247); -+ mdio_write(tp, 0x14, 0xac28); -+ mdio_write(tp, 0x14, 0x20d1); -+ mdio_write(tp, 0x14, 0x03bf); -+ mdio_write(tp, 0x14, 0x4307); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x59ee); -+ mdio_write(tp, 0x14, 0x8246); -+ mdio_write(tp, 0x14, 0x00e1); -+ mdio_write(tp, 0x14, 0x8227); -+ mdio_write(tp, 0x14, 0xf628); -+ mdio_write(tp, 0x14, 0xe582); -+ mdio_write(tp, 0x14, 0x27ae); -+ mdio_write(tp, 0x14, 0x21d1); -+ mdio_write(tp, 0x14, 0x04bf); -+ mdio_write(tp, 0x14, 0x4307); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x59ae); -+ mdio_write(tp, 0x14, 0x08d1); -+ mdio_write(tp, 0x14, 0x05bf); -+ mdio_write(tp, 0x14, 0x4307); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x59e0); -+ mdio_write(tp, 0x14, 0x8244); -+ mdio_write(tp, 0x14, 0xf720); -+ mdio_write(tp, 0x14, 0xe482); -+ mdio_write(tp, 0x14, 0x4402); -+ mdio_write(tp, 0x14, 0x46ae); -+ mdio_write(tp, 0x14, 0xee82); -+ mdio_write(tp, 0x14, 0x4601); -+ mdio_write(tp, 0x14, 0xef96); -+ mdio_write(tp, 0x14, 0xfefc); -+ mdio_write(tp, 0x14, 0x04f8); -+ mdio_write(tp, 0x14, 0xfaef); -+ mdio_write(tp, 0x14, 0x69e0); -+ mdio_write(tp, 0x14, 0x8013); -+ mdio_write(tp, 0x14, 0xad24); -+ mdio_write(tp, 0x14, 0x1cbf); -+ mdio_write(tp, 0x14, 0x87f0); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x97ad); -+ mdio_write(tp, 0x14, 0x2813); -+ mdio_write(tp, 0x14, 0xe087); -+ mdio_write(tp, 0x14, 0xfca0); -+ mdio_write(tp, 0x14, 0x0005); -+ mdio_write(tp, 0x14, 0x0287); -+ mdio_write(tp, 0x14, 0x36ae); -+ mdio_write(tp, 0x14, 0x10a0); -+ mdio_write(tp, 0x14, 0x0105); -+ mdio_write(tp, 0x14, 0x0287); -+ mdio_write(tp, 0x14, 0x48ae); -+ mdio_write(tp, 0x14, 0x08e0); -+ mdio_write(tp, 0x14, 0x8230); -+ mdio_write(tp, 0x14, 0xf626); -+ mdio_write(tp, 0x14, 0xe482); -+ mdio_write(tp, 0x14, 0x30ef); -+ mdio_write(tp, 0x14, 0x96fe); -+ mdio_write(tp, 0x14, 0xfc04); -+ mdio_write(tp, 0x14, 0xf8e0); -+ mdio_write(tp, 0x14, 0x8245); -+ mdio_write(tp, 0x14, 0xf722); -+ mdio_write(tp, 0x14, 0xe482); -+ mdio_write(tp, 0x14, 0x4502); -+ mdio_write(tp, 0x14, 0x46ae); -+ mdio_write(tp, 0x14, 0xee87); -+ mdio_write(tp, 0x14, 0xfc01); -+ mdio_write(tp, 0x14, 0xfc04); -+ mdio_write(tp, 0x14, 0xf8fa); -+ mdio_write(tp, 0x14, 0xef69); -+ mdio_write(tp, 0x14, 0xfb02); -+ mdio_write(tp, 0x14, 0x46d3); -+ mdio_write(tp, 0x14, 0xad50); -+ mdio_write(tp, 0x14, 0x2fbf); -+ mdio_write(tp, 0x14, 0x87ed); -+ mdio_write(tp, 0x14, 0xd101); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x59bf); -+ mdio_write(tp, 0x14, 0x87ed); -+ mdio_write(tp, 0x14, 0xd100); -+ mdio_write(tp, 0x14, 0x0242); -+ mdio_write(tp, 0x14, 0x59e0); -+ mdio_write(tp, 0x14, 0x8245); -+ mdio_write(tp, 0x14, 0xf622); -+ mdio_write(tp, 0x14, 0xe482); -+ mdio_write(tp, 0x14, 0x4502); -+ mdio_write(tp, 0x14, 0x46ae); -+ mdio_write(tp, 0x14, 0xd100); -+ mdio_write(tp, 0x14, 0xbf87); -+ mdio_write(tp, 0x14, 0xf002); -+ mdio_write(tp, 0x14, 0x4259); -+ mdio_write(tp, 0x14, 0xee87); -+ mdio_write(tp, 0x14, 0xfc00); -+ mdio_write(tp, 0x14, 0xe082); -+ mdio_write(tp, 0x14, 0x30f6); -+ mdio_write(tp, 0x14, 0x26e4); -+ mdio_write(tp, 0x14, 0x8230); -+ mdio_write(tp, 0x14, 0xffef); -+ mdio_write(tp, 0x14, 0x96fe); -+ mdio_write(tp, 0x14, 0xfc04); -+ mdio_write(tp, 0x14, 0xf8f9); -+ mdio_write(tp, 0x14, 0xface); -+ mdio_write(tp, 0x14, 0xfaef); -+ mdio_write(tp, 0x14, 0x69fb); -+ mdio_write(tp, 0x14, 0xbf87); -+ mdio_write(tp, 0x14, 0xb3d7); -+ mdio_write(tp, 0x14, 0x001c); -+ mdio_write(tp, 0x14, 0xd819); -+ mdio_write(tp, 0x14, 0xd919); -+ mdio_write(tp, 0x14, 0xda19); -+ mdio_write(tp, 0x14, 0xdb19); -+ mdio_write(tp, 0x14, 0x07ef); -+ mdio_write(tp, 0x14, 0x9502); -+ mdio_write(tp, 0x14, 0x4259); -+ mdio_write(tp, 0x14, 0x073f); -+ mdio_write(tp, 0x14, 0x0004); -+ mdio_write(tp, 0x14, 0x9fec); -+ mdio_write(tp, 0x14, 0xffef); -+ mdio_write(tp, 0x14, 0x96fe); -+ mdio_write(tp, 0x14, 0xc6fe); -+ mdio_write(tp, 0x14, 0xfdfc); -+ mdio_write(tp, 0x14, 0x0400); -+ mdio_write(tp, 0x14, 0x0145); -+ mdio_write(tp, 0x14, 0x7d00); -+ mdio_write(tp, 0x14, 0x0345); -+ mdio_write(tp, 0x14, 0x5c00); -+ mdio_write(tp, 0x14, 0x0143); -+ mdio_write(tp, 0x14, 0x4f00); -+ mdio_write(tp, 0x14, 0x0387); -+ mdio_write(tp, 0x14, 0xdb00); -+ mdio_write(tp, 0x14, 0x0987); -+ mdio_write(tp, 0x14, 0xde00); -+ mdio_write(tp, 0x14, 0x0987); -+ mdio_write(tp, 0x14, 0xe100); -+ mdio_write(tp, 0x14, 0x0087); -+ mdio_write(tp, 0x14, 0xeaa4); -+ mdio_write(tp, 0x14, 0x00b8); -+ mdio_write(tp, 0x14, 0x20c4); -+ mdio_write(tp, 0x14, 0x1600); -+ mdio_write(tp, 0x14, 0x000f); -+ mdio_write(tp, 0x14, 0xf800); -+ mdio_write(tp, 0x14, 0x7098); -+ mdio_write(tp, 0x14, 0xa58a); -+ mdio_write(tp, 0x14, 0xb6a8); -+ mdio_write(tp, 0x14, 0x3e50); -+ mdio_write(tp, 0x14, 0xa83e); -+ mdio_write(tp, 0x14, 0x33bc); -+ mdio_write(tp, 0x14, 0xc622); -+ mdio_write(tp, 0x14, 0xbcc6); -+ mdio_write(tp, 0x14, 0xaaa4); -+ mdio_write(tp, 0x14, 0x42ff); -+ mdio_write(tp, 0x14, 0xc408); -+ mdio_write(tp, 0x14, 0x00c4); -+ mdio_write(tp, 0x14, 0x16a8); -+ mdio_write(tp, 0x14, 0xbcc0); -+ mdio_write(tp, 0x13, 0xb818); -+ mdio_write(tp, 0x14, 0x02f3); -+ mdio_write(tp, 0x13, 0xb81a); -+ mdio_write(tp, 0x14, 0x17d1); -+ mdio_write(tp, 0x13, 0xb81c); -+ mdio_write(tp, 0x14, 0x185a); -+ mdio_write(tp, 0x13, 0xb81e); -+ mdio_write(tp, 0x14, 0x3c66); -+ mdio_write(tp, 0x13, 0xb820); -+ mdio_write(tp, 0x14, 0x021f); -+ mdio_write(tp, 0x13, 0xc416); -+ mdio_write(tp, 0x14, 0x0500); -+ mdio_write(tp, 0x13, 0xb82e); -+ mdio_write(tp, 0x14, 0xfffc); -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x0000); -+ mdio_write(tp, 0x14, 0x0000); -+ mdio_write(tp, 0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val &= ~(BIT_9); -+ mdio_write(tp, 0x10, gphy_val); -+ mdio_write(tp, 0x1f, 0x0A43); -+ mdio_write(tp, 0x13, 0x8146); -+ mdio_write(tp, 0x14, 0x0000); -+ -+ mdio_write(tp, 0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val &= ~(BIT_4); -+ mdio_write(tp, 0x10, gphy_val); -+} -+ -+static void -+rtl8168_set_phy_mcu_8168gu_2(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned int gphy_val,i; -+ -+ mdio_write(tp, 0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val |= BIT_4; -+ mdio_write(tp, 0x10, gphy_val); -+ mdio_write(tp, 0x1f, 0x0B80); -+ i = 0; -+ do { -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val &= 0x0040; -+ udelay(50); -+ udelay(50); -+ i++; -+ } while(gphy_val != 0x0040 && i <1000); -+ mdio_write(tp, 0x1f, 0x0A43); -+ mdio_write(tp, 0x13, 0x8146); -+ mdio_write(tp, 0x14, 0x0300); -+ mdio_write(tp, 0x13, 0xB82E); -+ mdio_write(tp, 0x14, 0x0001); -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0xb820); -+ mdio_write(tp, 0x14, 0x0290); -+ mdio_write(tp, 0x13, 0xa012); -+ mdio_write(tp, 0x14, 0x0000); -+ mdio_write(tp, 0x13, 0xa014); -+ mdio_write(tp, 0x14, 0x2c04); -+ mdio_write(tp, 0x14, 0x2c07); -+ mdio_write(tp, 0x14, 0x2c07); -+ mdio_write(tp, 0x14, 0x2c07); -+ mdio_write(tp, 0x14, 0xa304); -+ mdio_write(tp, 0x14, 0xa301); -+ mdio_write(tp, 0x14, 0x207e); -+ mdio_write(tp, 0x13, 0xa01a); -+ mdio_write(tp, 0x14, 0x0000); -+ mdio_write(tp, 0x13, 0xa006); -+ mdio_write(tp, 0x14, 0x0fff); -+ mdio_write(tp, 0x13, 0xa004); -+ mdio_write(tp, 0x14, 0x0fff); -+ mdio_write(tp, 0x13, 0xa002); -+ mdio_write(tp, 0x14, 0x0fff); -+ mdio_write(tp, 0x13, 0xa000); -+ mdio_write(tp, 0x14, 0x107c); -+ mdio_write(tp, 0x13, 0xb820); -+ mdio_write(tp, 0x14, 0x0210); -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x0000); -+ mdio_write(tp, 0x14, 0x0000); -+ mdio_write(tp, 0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x17); -+ gphy_val &= ~(BIT_0); -+ mdio_write(tp, 0x17, gphy_val); -+ mdio_write(tp, 0x1f, 0x0A43); -+ mdio_write(tp, 0x13, 0x8146); -+ mdio_write(tp, 0x14, 0x0000); -+ mdio_write(tp, 0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val &= ~(BIT_4); -+ mdio_write(tp, 0x10, gphy_val); -+} -+ -+static void -+rtl8168_set_phy_mcu_8411b_1(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned int gphy_val,i; -+ -+ mdio_write(tp,0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val |= BIT_4; -+ mdio_write(tp,0x10, gphy_val); -+ -+ mdio_write(tp,0x1f, 0x0B80); -+ i = 0; -+ do { -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val &= 0x0040; -+ udelay(50); -+ udelay(50); -+ i++; -+ } while(gphy_val != 0x0040 && i <1000); -+ -+ mdio_write(tp,0x1f, 0x0A43); -+ mdio_write(tp,0x13, 0x8146); -+ mdio_write(tp,0x14, 0x0100); -+ mdio_write(tp,0x13, 0xB82E); -+ mdio_write(tp,0x14, 0x0001); -+ -+ -+ mdio_write(tp,0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0xb820); -+ mdio_write(tp, 0x14, 0x0290); -+ mdio_write(tp, 0x13, 0xa012); -+ mdio_write(tp, 0x14, 0x0000); -+ mdio_write(tp, 0x13, 0xa014); -+ mdio_write(tp, 0x14, 0x2c04); -+ mdio_write(tp, 0x14, 0x2c07); -+ mdio_write(tp, 0x14, 0x2c07); -+ mdio_write(tp, 0x14, 0x2c07); -+ mdio_write(tp, 0x14, 0xa304); -+ mdio_write(tp, 0x14, 0xa301); -+ mdio_write(tp, 0x14, 0x207e); -+ mdio_write(tp, 0x13, 0xa01a); -+ mdio_write(tp, 0x14, 0x0000); -+ mdio_write(tp, 0x13, 0xa006); -+ mdio_write(tp, 0x14, 0x0fff); -+ mdio_write(tp, 0x13, 0xa004); -+ mdio_write(tp, 0x14, 0x0fff); -+ mdio_write(tp, 0x13, 0xa002); -+ mdio_write(tp, 0x14, 0x0fff); -+ mdio_write(tp, 0x13, 0xa000); -+ mdio_write(tp, 0x14, 0x107c); -+ mdio_write(tp, 0x13, 0xb820); -+ mdio_write(tp, 0x14, 0x0210); -+ -+ -+ mdio_write(tp,0x1F, 0x0A43); -+ mdio_write(tp,0x13, 0x0000); -+ mdio_write(tp,0x14, 0x0000); -+ mdio_write(tp,0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x17); -+ gphy_val &= ~(BIT_0); -+ mdio_write(tp,0x17, gphy_val); -+ mdio_write(tp,0x1f, 0x0A43); -+ mdio_write(tp,0x13, 0x8146); -+ mdio_write(tp,0x14, 0x0000); -+ -+ -+ mdio_write(tp,0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val &= ~(BIT_4); -+ mdio_write(tp,0x10, gphy_val); -+} -+ -+static void -+rtl8168_set_phy_mcu_8168h_1(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned int gphy_val,i; -+ -+ mdio_write(tp, 0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val |= BIT_4; -+ mdio_write(tp, 0x10, gphy_val); -+ -+ mdio_write(tp, 0x1f, 0x0B80); -+ i = 0; -+ do { -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val &= 0x0040; -+ udelay(50); -+ udelay(50); -+ i++; -+ } while(gphy_val != 0x0040 && i <1000); -+ -+ mdio_write(tp, 0x1f, 0x0A43); -+ mdio_write(tp, 0x13, 0x8028); -+ mdio_write(tp, 0x14, 0x6200); -+ mdio_write(tp, 0x13, 0xB82E); -+ mdio_write(tp, 0x14, 0x0001); -+ -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0xB820); -+ mdio_write(tp, 0x14, 0x0290); -+ mdio_write(tp, 0x13, 0xA012); -+ mdio_write(tp, 0x14, 0x0000); -+ mdio_write(tp, 0x13, 0xA014); -+ mdio_write(tp, 0x14, 0x2c04); -+ mdio_write(tp, 0x14, 0x2c10); -+ mdio_write(tp, 0x14, 0x2c10); -+ mdio_write(tp, 0x14, 0x2c10); -+ mdio_write(tp, 0x14, 0xa210); -+ mdio_write(tp, 0x14, 0xa101); -+ mdio_write(tp, 0x14, 0xce10); -+ mdio_write(tp, 0x14, 0xe070); -+ mdio_write(tp, 0x14, 0x0f40); -+ mdio_write(tp, 0x14, 0xaf01); -+ mdio_write(tp, 0x14, 0x8f01); -+ mdio_write(tp, 0x14, 0x183e); -+ mdio_write(tp, 0x14, 0x8e10); -+ mdio_write(tp, 0x14, 0x8101); -+ mdio_write(tp, 0x14, 0x8210); -+ mdio_write(tp, 0x14, 0x28da); -+ mdio_write(tp, 0x13, 0xA01A); -+ mdio_write(tp, 0x14, 0x0000); -+ mdio_write(tp, 0x13, 0xA006); -+ mdio_write(tp, 0x14, 0x0017); -+ mdio_write(tp, 0x13, 0xA004); -+ mdio_write(tp, 0x14, 0x0015); -+ mdio_write(tp, 0x13, 0xA002); -+ mdio_write(tp, 0x14, 0x0013); -+ mdio_write(tp, 0x13, 0xA000); -+ mdio_write(tp, 0x14, 0x18d1); -+ mdio_write(tp, 0x13, 0xB820); -+ mdio_write(tp, 0x14, 0x0210); -+ -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x0000); -+ mdio_write(tp, 0x14, 0x0000); -+ mdio_write(tp, 0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x17); -+ gphy_val &= ~(BIT_0); -+ mdio_write(tp, 0x17, gphy_val); -+ mdio_write(tp, 0x1f, 0x0A43); -+ mdio_write(tp, 0x13, 0x8028); -+ mdio_write(tp, 0x14, 0x0000); -+ -+ -+ mdio_write(tp, 0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val &= ~(BIT_4); -+ mdio_write(tp, 0x10, gphy_val); -+} -+ -+static void -+rtl8168_set_phy_mcu_8168h_2(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned int gphy_val,i; -+ -+ mdio_write(tp, 0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val |= BIT_4; -+ mdio_write(tp, 0x10, gphy_val); -+ -+ mdio_write(tp, 0x1f, 0x0B80); -+ i = 0; -+ do { -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val &= 0x0040; -+ udelay(50); -+ udelay(50); -+ i++; -+ } while(gphy_val != 0x0040 && i <1000); -+ -+ mdio_write(tp, 0x1f, 0x0A43); -+ mdio_write(tp, 0x13, 0x8028); -+ mdio_write(tp, 0x14, 0x6201); -+ mdio_write(tp, 0x13, 0xB82E); -+ mdio_write(tp, 0x14, 0x0001); -+ -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0xB820); -+ mdio_write(tp, 0x14, 0x0290); -+ mdio_write(tp, 0x13, 0xA012); -+ mdio_write(tp, 0x14, 0x0000); -+ mdio_write(tp, 0x13, 0xA014); -+ mdio_write(tp, 0x14, 0x2c04); -+ mdio_write(tp, 0x14, 0x2c09); -+ mdio_write(tp, 0x14, 0x2c09); -+ mdio_write(tp, 0x14, 0x2c09); -+ mdio_write(tp, 0x14, 0xad01); -+ mdio_write(tp, 0x14, 0xad01); -+ mdio_write(tp, 0x14, 0xad01); -+ mdio_write(tp, 0x14, 0xad01); -+ mdio_write(tp, 0x14, 0x236c); -+ mdio_write(tp, 0x13, 0xA01A); -+ mdio_write(tp, 0x14, 0x0000); -+ mdio_write(tp, 0x13, 0xA006); -+ mdio_write(tp, 0x14, 0x0fff); -+ mdio_write(tp, 0x13, 0xA004); -+ mdio_write(tp, 0x14, 0x0fff); -+ mdio_write(tp, 0x13, 0xA002); -+ mdio_write(tp, 0x14, 0x0fff); -+ mdio_write(tp, 0x13, 0xA000); -+ mdio_write(tp, 0x14, 0x136b); -+ mdio_write(tp, 0x13, 0xB820); -+ mdio_write(tp, 0x14, 0x0210); -+ -+ -+ mdio_write(tp,0x1F, 0x0A43); -+ mdio_write(tp,0x13, 0x0000); -+ mdio_write(tp,0x14, 0x0000); -+ mdio_write(tp,0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x17); -+ gphy_val &= ~(BIT_0); -+ mdio_write(tp,0x17, gphy_val); -+ mdio_write(tp,0x1f, 0x0A43); -+ mdio_write(tp,0x13, 0x8028); -+ mdio_write(tp,0x14, 0x0000); -+ -+ -+ mdio_write(tp, 0x1f, 0x0B82); -+ gphy_val = mdio_read(tp, 0x10); -+ gphy_val &= ~(BIT_4); -+ mdio_write(tp, 0x10, gphy_val); -+ -+ if (tp->RequiredSecLanDonglePatch) { -+ mdio_write(tp, 0x1F, 0x0A43); -+ gphy_val = mdio_read(tp, 0x11); -+ gphy_val &= ~BIT_6; -+ mdio_write(tp, 0x11, gphy_val); -+ } -+} -+ -+static void -+rtl8168_init_hw_phy_mcu(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ if (tp->NotWrRamCodeToMicroP == TRUE) return; -+ if (rtl8168_check_hw_phy_mcu_code_ver(dev)) return; -+ -+ if (FALSE == rtl8168_phy_ram_code_check(dev)) { -+ rtl8168_set_phy_ram_code_check_fail_flag(dev); -+ return; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ rtl8168_set_phy_mcu_8168e_1(dev); -+ break; -+ case CFG_METHOD_15: -+ rtl8168_set_phy_mcu_8168e_2(dev); -+ break; -+ case CFG_METHOD_16: -+ rtl8168_set_phy_mcu_8168evl_1(dev); -+ break; -+ case CFG_METHOD_17: -+ rtl8168_set_phy_mcu_8168evl_2(dev); -+ break; -+ case CFG_METHOD_18: -+ rtl8168_set_phy_mcu_8168f_1(dev); -+ break; -+ case CFG_METHOD_19: -+ rtl8168_set_phy_mcu_8168f_2(dev); -+ break; -+ case CFG_METHOD_20: -+ rtl8168_set_phy_mcu_8411_1(dev); -+ break; -+ case CFG_METHOD_21: -+ rtl8168_set_phy_mcu_8168g_1(dev); -+ break; -+ case CFG_METHOD_25: -+ rtl8168_set_phy_mcu_8168gu_2(dev); -+ break; -+ case CFG_METHOD_26: -+ rtl8168_set_phy_mcu_8411b_1(dev); -+ break; -+ case CFG_METHOD_29: -+ rtl8168_set_phy_mcu_8168h_1(dev); -+ break; -+ case CFG_METHOD_30: -+ rtl8168_set_phy_mcu_8168h_2(dev); -+ break; -+ } -+ -+ rtl8168_write_hw_phy_mcu_code_ver(dev); -+ -+ mdio_write(tp,0x1F, 0x0000); -+ -+ tp->HwHasWrRamCodeToMicroP = TRUE; -+} -+ -+static void -+rtl8168_hw_phy_config(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ struct pci_dev *pdev = tp->pci_dev; -+ u16 gphy_val; -+ unsigned int i; -+ unsigned long flags; -+ -+ tp->phy_reset_enable(dev); -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ -+ rtl8168_init_hw_phy_mcu(dev); -+ -+ if (tp->mcfg == CFG_METHOD_1) { -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x0B, 0x94B0); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x12, 0x6096); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x0D, 0xF8A0); -+ } else if (tp->mcfg == CFG_METHOD_2) { -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x0B, 0x94B0); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x12, 0x6096); -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ } else if (tp->mcfg == CFG_METHOD_3) { -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x0B, 0x94B0); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x12, 0x6096); -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ } else if (tp->mcfg == CFG_METHOD_4) { -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x12, 0x2300); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x16, 0x000A); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x12, 0xC096); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x00, 0x88DE); -+ mdio_write(tp, 0x01, 0x82B1); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x08, 0x9E30); -+ mdio_write(tp, 0x09, 0x01F0); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x0A, 0x5500); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x03, 0x7002); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x0C, 0x00C8); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) | (1 << 5)); -+ mdio_write(tp, 0x0D, mdio_read(tp, 0x0D) & ~(1 << 5)); -+ } else if (tp->mcfg == CFG_METHOD_5) { -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x12, 0x2300); -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x16, 0x0F0A); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x00, 0x88DE); -+ mdio_write(tp, 0x01, 0x82B1); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x0C, 0x7EB8); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x06, 0x0761); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x03, 0x802F); -+ mdio_write(tp, 0x02, 0x4F02); -+ mdio_write(tp, 0x01, 0x0409); -+ mdio_write(tp, 0x00, 0xF099); -+ mdio_write(tp, 0x04, 0x9800); -+ mdio_write(tp, 0x04, 0x9000); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x16, mdio_read(tp, 0x16) | (1 << 0)); -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) | (1 << 5)); -+ mdio_write(tp, 0x0D, mdio_read(tp, 0x0D) & ~(1 << 5)); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x1D, 0x3D98); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x17, 0x0CC0); -+ mdio_write(tp, 0x1F, 0x0000); -+ } else if (tp->mcfg == CFG_METHOD_6) { -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x12, 0x2300); -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x16, 0x0F0A); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x00, 0x88DE); -+ mdio_write(tp, 0x01, 0x82B1); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x0C, 0x7EB8); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x06, 0x5461); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x06, 0x5461); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x16, mdio_read(tp, 0x16) | (1 << 0)); -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) | (1 << 5)); -+ mdio_write(tp, 0x0D, mdio_read(tp, 0x0D) & ~(1 << 5)); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x1D, 0x3D98); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1f, 0x0001); -+ mdio_write(tp, 0x17, 0x0CC0); -+ mdio_write(tp, 0x1F, 0x0000); -+ } else if (tp->mcfg == CFG_METHOD_7) { -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) | (1 << 5)); -+ mdio_write(tp, 0x0D, mdio_read(tp, 0x0D) & ~(1 << 5)); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x1D, 0x3D98); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x14, 0xCAA3); -+ mdio_write(tp, 0x1C, 0x000A); -+ mdio_write(tp, 0x18, 0x65D0); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x17, 0xB580); -+ mdio_write(tp, 0x18, 0xFF54); -+ mdio_write(tp, 0x19, 0x3954); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x0D, 0x310C); -+ mdio_write(tp, 0x0E, 0x310C); -+ mdio_write(tp, 0x0F, 0x311C); -+ mdio_write(tp, 0x06, 0x0761); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x18, 0xFF55); -+ mdio_write(tp, 0x19, 0x3955); -+ mdio_write(tp, 0x18, 0xFF54); -+ mdio_write(tp, 0x19, 0x3954); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x17, 0x0CC0); -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ } else if (tp->mcfg == CFG_METHOD_8) { -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) | (1 << 5)); -+ mdio_write(tp, 0x0D, mdio_read(tp, 0x0D) & ~(1 << 5)); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x14, 0xCAA3); -+ mdio_write(tp, 0x1C, 0x000A); -+ mdio_write(tp, 0x18, 0x65D0); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x17, 0xB580); -+ mdio_write(tp, 0x18, 0xFF54); -+ mdio_write(tp, 0x19, 0x3954); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x0D, 0x310C); -+ mdio_write(tp, 0x0E, 0x310C); -+ mdio_write(tp, 0x0F, 0x311C); -+ mdio_write(tp, 0x06, 0x0761); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x18, 0xFF55); -+ mdio_write(tp, 0x19, 0x3955); -+ mdio_write(tp, 0x18, 0xFF54); -+ mdio_write(tp, 0x19, 0x3954); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x17, 0x0CC0); -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x16, mdio_read(tp, 0x16) | (1 << 0)); -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ } else if (tp->mcfg == CFG_METHOD_9) { -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x06, 0x4064); -+ mdio_write(tp, 0x07, 0x2863); -+ mdio_write(tp, 0x08, 0x059C); -+ mdio_write(tp, 0x09, 0x26B4); -+ mdio_write(tp, 0x0A, 0x6A19); -+ mdio_write(tp, 0x0B, 0xDCC8); -+ mdio_write(tp, 0x10, 0xF06D); -+ mdio_write(tp, 0x14, 0x7F68); -+ mdio_write(tp, 0x18, 0x7FD9); -+ mdio_write(tp, 0x1C, 0xF0FF); -+ mdio_write(tp, 0x1D, 0x3D9C); -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x12, 0xF49F); -+ mdio_write(tp, 0x13, 0x070B); -+ mdio_write(tp, 0x1A, 0x05AD); -+ mdio_write(tp, 0x14, 0x94C0); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ gphy_val = mdio_read(tp, 0x0B) & 0xFF00; -+ gphy_val |= 0x10; -+ mdio_write(tp, 0x0B, gphy_val); -+ gphy_val = mdio_read(tp, 0x0C) & 0x00FF; -+ gphy_val |= 0xA200; -+ mdio_write(tp, 0x0C, gphy_val); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x06, 0x5561); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8332); -+ mdio_write(tp, 0x06, 0x5561); -+ -+ if (rtl8168_efuse_read(tp, 0x01) == 0xb1) { -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x05, 0x669A); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8330); -+ mdio_write(tp, 0x06, 0x669A); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ gphy_val = mdio_read(tp, 0x0D); -+ if ((gphy_val & 0x00FF) != 0x006C) { -+ gphy_val &= 0xFF00; -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x0D, gphy_val | 0x0065); -+ mdio_write(tp, 0x0D, gphy_val | 0x0066); -+ mdio_write(tp, 0x0D, gphy_val | 0x0067); -+ mdio_write(tp, 0x0D, gphy_val | 0x0068); -+ mdio_write(tp, 0x0D, gphy_val | 0x0069); -+ mdio_write(tp, 0x0D, gphy_val | 0x006A); -+ mdio_write(tp, 0x0D, gphy_val | 0x006B); -+ mdio_write(tp, 0x0D, gphy_val | 0x006C); -+ } -+ } else { -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x05, 0x6662); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8330); -+ mdio_write(tp, 0x06, 0x6662); -+ } -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ gphy_val = mdio_read(tp, 0x0D); -+ gphy_val |= BIT_9; -+ gphy_val |= BIT_8; -+ mdio_write(tp, 0x0D, gphy_val); -+ gphy_val = mdio_read(tp, 0x0F); -+ gphy_val |= BIT_4; -+ mdio_write(tp, 0x0F, gphy_val); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ gphy_val = mdio_read(tp, 0x02); -+ gphy_val &= ~BIT_10; -+ gphy_val &= ~BIT_9; -+ gphy_val |= BIT_8; -+ mdio_write(tp, 0x02, gphy_val); -+ gphy_val = mdio_read(tp, 0x03); -+ gphy_val &= ~BIT_15; -+ gphy_val &= ~BIT_14; -+ gphy_val &= ~BIT_13; -+ mdio_write(tp, 0x03, gphy_val); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x17, 0x0CC0); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x001B); -+ if (mdio_read(tp, 0x06) == 0xBF00) { -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ mdio_write(tp, 0x05, 0x8000); -+ mdio_write(tp, 0x06, 0xf8f9); -+ mdio_write(tp, 0x06, 0xfaef); -+ mdio_write(tp, 0x06, 0x59ee); -+ mdio_write(tp, 0x06, 0xf8ea); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0xf8eb); -+ mdio_write(tp, 0x06, 0x00e0); -+ mdio_write(tp, 0x06, 0xf87c); -+ mdio_write(tp, 0x06, 0xe1f8); -+ mdio_write(tp, 0x06, 0x7d59); -+ mdio_write(tp, 0x06, 0x0fef); -+ mdio_write(tp, 0x06, 0x0139); -+ mdio_write(tp, 0x06, 0x029e); -+ mdio_write(tp, 0x06, 0x06ef); -+ mdio_write(tp, 0x06, 0x1039); -+ mdio_write(tp, 0x06, 0x089f); -+ mdio_write(tp, 0x06, 0x2aee); -+ mdio_write(tp, 0x06, 0xf8ea); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0xf8eb); -+ mdio_write(tp, 0x06, 0x01e0); -+ mdio_write(tp, 0x06, 0xf87c); -+ mdio_write(tp, 0x06, 0xe1f8); -+ mdio_write(tp, 0x06, 0x7d58); -+ mdio_write(tp, 0x06, 0x409e); -+ mdio_write(tp, 0x06, 0x0f39); -+ mdio_write(tp, 0x06, 0x46aa); -+ mdio_write(tp, 0x06, 0x0bbf); -+ mdio_write(tp, 0x06, 0x8290); -+ mdio_write(tp, 0x06, 0xd682); -+ mdio_write(tp, 0x06, 0x9802); -+ mdio_write(tp, 0x06, 0x014f); -+ mdio_write(tp, 0x06, 0xae09); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0x98d6); -+ mdio_write(tp, 0x06, 0x82a0); -+ mdio_write(tp, 0x06, 0x0201); -+ mdio_write(tp, 0x06, 0x4fef); -+ mdio_write(tp, 0x06, 0x95fe); -+ mdio_write(tp, 0x06, 0xfdfc); -+ mdio_write(tp, 0x06, 0x05f8); -+ mdio_write(tp, 0x06, 0xf9fa); -+ mdio_write(tp, 0x06, 0xeef8); -+ mdio_write(tp, 0x06, 0xea00); -+ mdio_write(tp, 0x06, 0xeef8); -+ mdio_write(tp, 0x06, 0xeb00); -+ mdio_write(tp, 0x06, 0xe2f8); -+ mdio_write(tp, 0x06, 0x7ce3); -+ mdio_write(tp, 0x06, 0xf87d); -+ mdio_write(tp, 0x06, 0xa511); -+ mdio_write(tp, 0x06, 0x1112); -+ mdio_write(tp, 0x06, 0xd240); -+ mdio_write(tp, 0x06, 0xd644); -+ mdio_write(tp, 0x06, 0x4402); -+ mdio_write(tp, 0x06, 0x8217); -+ mdio_write(tp, 0x06, 0xd2a0); -+ mdio_write(tp, 0x06, 0xd6aa); -+ mdio_write(tp, 0x06, 0xaa02); -+ mdio_write(tp, 0x06, 0x8217); -+ mdio_write(tp, 0x06, 0xae0f); -+ mdio_write(tp, 0x06, 0xa544); -+ mdio_write(tp, 0x06, 0x4402); -+ mdio_write(tp, 0x06, 0xae4d); -+ mdio_write(tp, 0x06, 0xa5aa); -+ mdio_write(tp, 0x06, 0xaa02); -+ mdio_write(tp, 0x06, 0xae47); -+ mdio_write(tp, 0x06, 0xaf82); -+ mdio_write(tp, 0x06, 0x13ee); -+ mdio_write(tp, 0x06, 0x834e); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x834d); -+ mdio_write(tp, 0x06, 0x0fee); -+ mdio_write(tp, 0x06, 0x834c); -+ mdio_write(tp, 0x06, 0x0fee); -+ mdio_write(tp, 0x06, 0x834f); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8351); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x834a); -+ mdio_write(tp, 0x06, 0xffee); -+ mdio_write(tp, 0x06, 0x834b); -+ mdio_write(tp, 0x06, 0xffe0); -+ mdio_write(tp, 0x06, 0x8330); -+ mdio_write(tp, 0x06, 0xe183); -+ mdio_write(tp, 0x06, 0x3158); -+ mdio_write(tp, 0x06, 0xfee4); -+ mdio_write(tp, 0x06, 0xf88a); -+ mdio_write(tp, 0x06, 0xe5f8); -+ mdio_write(tp, 0x06, 0x8be0); -+ mdio_write(tp, 0x06, 0x8332); -+ mdio_write(tp, 0x06, 0xe183); -+ mdio_write(tp, 0x06, 0x3359); -+ mdio_write(tp, 0x06, 0x0fe2); -+ mdio_write(tp, 0x06, 0x834d); -+ mdio_write(tp, 0x06, 0x0c24); -+ mdio_write(tp, 0x06, 0x5af0); -+ mdio_write(tp, 0x06, 0x1e12); -+ mdio_write(tp, 0x06, 0xe4f8); -+ mdio_write(tp, 0x06, 0x8ce5); -+ mdio_write(tp, 0x06, 0xf88d); -+ mdio_write(tp, 0x06, 0xaf82); -+ mdio_write(tp, 0x06, 0x13e0); -+ mdio_write(tp, 0x06, 0x834f); -+ mdio_write(tp, 0x06, 0x10e4); -+ mdio_write(tp, 0x06, 0x834f); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x4e78); -+ mdio_write(tp, 0x06, 0x009f); -+ mdio_write(tp, 0x06, 0x0ae0); -+ mdio_write(tp, 0x06, 0x834f); -+ mdio_write(tp, 0x06, 0xa010); -+ mdio_write(tp, 0x06, 0xa5ee); -+ mdio_write(tp, 0x06, 0x834e); -+ mdio_write(tp, 0x06, 0x01e0); -+ mdio_write(tp, 0x06, 0x834e); -+ mdio_write(tp, 0x06, 0x7805); -+ mdio_write(tp, 0x06, 0x9e9a); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x4e78); -+ mdio_write(tp, 0x06, 0x049e); -+ mdio_write(tp, 0x06, 0x10e0); -+ mdio_write(tp, 0x06, 0x834e); -+ mdio_write(tp, 0x06, 0x7803); -+ mdio_write(tp, 0x06, 0x9e0f); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x4e78); -+ mdio_write(tp, 0x06, 0x019e); -+ mdio_write(tp, 0x06, 0x05ae); -+ mdio_write(tp, 0x06, 0x0caf); -+ mdio_write(tp, 0x06, 0x81f8); -+ mdio_write(tp, 0x06, 0xaf81); -+ mdio_write(tp, 0x06, 0xa3af); -+ mdio_write(tp, 0x06, 0x81dc); -+ mdio_write(tp, 0x06, 0xaf82); -+ mdio_write(tp, 0x06, 0x13ee); -+ mdio_write(tp, 0x06, 0x8348); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0x8349); -+ mdio_write(tp, 0x06, 0x00e0); -+ mdio_write(tp, 0x06, 0x8351); -+ mdio_write(tp, 0x06, 0x10e4); -+ mdio_write(tp, 0x06, 0x8351); -+ mdio_write(tp, 0x06, 0x5801); -+ mdio_write(tp, 0x06, 0x9fea); -+ mdio_write(tp, 0x06, 0xd000); -+ mdio_write(tp, 0x06, 0xd180); -+ mdio_write(tp, 0x06, 0x1f66); -+ mdio_write(tp, 0x06, 0xe2f8); -+ mdio_write(tp, 0x06, 0xeae3); -+ mdio_write(tp, 0x06, 0xf8eb); -+ mdio_write(tp, 0x06, 0x5af8); -+ mdio_write(tp, 0x06, 0x1e20); -+ mdio_write(tp, 0x06, 0xe6f8); -+ mdio_write(tp, 0x06, 0xeae5); -+ mdio_write(tp, 0x06, 0xf8eb); -+ mdio_write(tp, 0x06, 0xd302); -+ mdio_write(tp, 0x06, 0xb3fe); -+ mdio_write(tp, 0x06, 0xe2f8); -+ mdio_write(tp, 0x06, 0x7cef); -+ mdio_write(tp, 0x06, 0x325b); -+ mdio_write(tp, 0x06, 0x80e3); -+ mdio_write(tp, 0x06, 0xf87d); -+ mdio_write(tp, 0x06, 0x9e03); -+ mdio_write(tp, 0x06, 0x7dff); -+ mdio_write(tp, 0x06, 0xff0d); -+ mdio_write(tp, 0x06, 0x581c); -+ mdio_write(tp, 0x06, 0x551a); -+ mdio_write(tp, 0x06, 0x6511); -+ mdio_write(tp, 0x06, 0xa190); -+ mdio_write(tp, 0x06, 0xd3e2); -+ mdio_write(tp, 0x06, 0x8348); -+ mdio_write(tp, 0x06, 0xe383); -+ mdio_write(tp, 0x06, 0x491b); -+ mdio_write(tp, 0x06, 0x56ab); -+ mdio_write(tp, 0x06, 0x08ef); -+ mdio_write(tp, 0x06, 0x56e6); -+ mdio_write(tp, 0x06, 0x8348); -+ mdio_write(tp, 0x06, 0xe783); -+ mdio_write(tp, 0x06, 0x4910); -+ mdio_write(tp, 0x06, 0xd180); -+ mdio_write(tp, 0x06, 0x1f66); -+ mdio_write(tp, 0x06, 0xa004); -+ mdio_write(tp, 0x06, 0xb9e2); -+ mdio_write(tp, 0x06, 0x8348); -+ mdio_write(tp, 0x06, 0xe383); -+ mdio_write(tp, 0x06, 0x49ef); -+ mdio_write(tp, 0x06, 0x65e2); -+ mdio_write(tp, 0x06, 0x834a); -+ mdio_write(tp, 0x06, 0xe383); -+ mdio_write(tp, 0x06, 0x4b1b); -+ mdio_write(tp, 0x06, 0x56aa); -+ mdio_write(tp, 0x06, 0x0eef); -+ mdio_write(tp, 0x06, 0x56e6); -+ mdio_write(tp, 0x06, 0x834a); -+ mdio_write(tp, 0x06, 0xe783); -+ mdio_write(tp, 0x06, 0x4be2); -+ mdio_write(tp, 0x06, 0x834d); -+ mdio_write(tp, 0x06, 0xe683); -+ mdio_write(tp, 0x06, 0x4ce0); -+ mdio_write(tp, 0x06, 0x834d); -+ mdio_write(tp, 0x06, 0xa000); -+ mdio_write(tp, 0x06, 0x0caf); -+ mdio_write(tp, 0x06, 0x81dc); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x4d10); -+ mdio_write(tp, 0x06, 0xe483); -+ mdio_write(tp, 0x06, 0x4dae); -+ mdio_write(tp, 0x06, 0x0480); -+ mdio_write(tp, 0x06, 0xe483); -+ mdio_write(tp, 0x06, 0x4de0); -+ mdio_write(tp, 0x06, 0x834e); -+ mdio_write(tp, 0x06, 0x7803); -+ mdio_write(tp, 0x06, 0x9e0b); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x4e78); -+ mdio_write(tp, 0x06, 0x049e); -+ mdio_write(tp, 0x06, 0x04ee); -+ mdio_write(tp, 0x06, 0x834e); -+ mdio_write(tp, 0x06, 0x02e0); -+ mdio_write(tp, 0x06, 0x8332); -+ mdio_write(tp, 0x06, 0xe183); -+ mdio_write(tp, 0x06, 0x3359); -+ mdio_write(tp, 0x06, 0x0fe2); -+ mdio_write(tp, 0x06, 0x834d); -+ mdio_write(tp, 0x06, 0x0c24); -+ mdio_write(tp, 0x06, 0x5af0); -+ mdio_write(tp, 0x06, 0x1e12); -+ mdio_write(tp, 0x06, 0xe4f8); -+ mdio_write(tp, 0x06, 0x8ce5); -+ mdio_write(tp, 0x06, 0xf88d); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x30e1); -+ mdio_write(tp, 0x06, 0x8331); -+ mdio_write(tp, 0x06, 0x6801); -+ mdio_write(tp, 0x06, 0xe4f8); -+ mdio_write(tp, 0x06, 0x8ae5); -+ mdio_write(tp, 0x06, 0xf88b); -+ mdio_write(tp, 0x06, 0xae37); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x4e03); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x4ce1); -+ mdio_write(tp, 0x06, 0x834d); -+ mdio_write(tp, 0x06, 0x1b01); -+ mdio_write(tp, 0x06, 0x9e04); -+ mdio_write(tp, 0x06, 0xaaa1); -+ mdio_write(tp, 0x06, 0xaea8); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x4e04); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x4f00); -+ mdio_write(tp, 0x06, 0xaeab); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x4f78); -+ mdio_write(tp, 0x06, 0x039f); -+ mdio_write(tp, 0x06, 0x14ee); -+ mdio_write(tp, 0x06, 0x834e); -+ mdio_write(tp, 0x06, 0x05d2); -+ mdio_write(tp, 0x06, 0x40d6); -+ mdio_write(tp, 0x06, 0x5554); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0x17d2); -+ mdio_write(tp, 0x06, 0xa0d6); -+ mdio_write(tp, 0x06, 0xba00); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0x17fe); -+ mdio_write(tp, 0x06, 0xfdfc); -+ mdio_write(tp, 0x06, 0x05f8); -+ mdio_write(tp, 0x06, 0xe0f8); -+ mdio_write(tp, 0x06, 0x60e1); -+ mdio_write(tp, 0x06, 0xf861); -+ mdio_write(tp, 0x06, 0x6802); -+ mdio_write(tp, 0x06, 0xe4f8); -+ mdio_write(tp, 0x06, 0x60e5); -+ mdio_write(tp, 0x06, 0xf861); -+ mdio_write(tp, 0x06, 0xe0f8); -+ mdio_write(tp, 0x06, 0x48e1); -+ mdio_write(tp, 0x06, 0xf849); -+ mdio_write(tp, 0x06, 0x580f); -+ mdio_write(tp, 0x06, 0x1e02); -+ mdio_write(tp, 0x06, 0xe4f8); -+ mdio_write(tp, 0x06, 0x48e5); -+ mdio_write(tp, 0x06, 0xf849); -+ mdio_write(tp, 0x06, 0xd000); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0x5bbf); -+ mdio_write(tp, 0x06, 0x8350); -+ mdio_write(tp, 0x06, 0xef46); -+ mdio_write(tp, 0x06, 0xdc19); -+ mdio_write(tp, 0x06, 0xddd0); -+ mdio_write(tp, 0x06, 0x0102); -+ mdio_write(tp, 0x06, 0x825b); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0x77e0); -+ mdio_write(tp, 0x06, 0xf860); -+ mdio_write(tp, 0x06, 0xe1f8); -+ mdio_write(tp, 0x06, 0x6158); -+ mdio_write(tp, 0x06, 0xfde4); -+ mdio_write(tp, 0x06, 0xf860); -+ mdio_write(tp, 0x06, 0xe5f8); -+ mdio_write(tp, 0x06, 0x61fc); -+ mdio_write(tp, 0x06, 0x04f9); -+ mdio_write(tp, 0x06, 0xfafb); -+ mdio_write(tp, 0x06, 0xc6bf); -+ mdio_write(tp, 0x06, 0xf840); -+ mdio_write(tp, 0x06, 0xbe83); -+ mdio_write(tp, 0x06, 0x50a0); -+ mdio_write(tp, 0x06, 0x0101); -+ mdio_write(tp, 0x06, 0x071b); -+ mdio_write(tp, 0x06, 0x89cf); -+ mdio_write(tp, 0x06, 0xd208); -+ mdio_write(tp, 0x06, 0xebdb); -+ mdio_write(tp, 0x06, 0x19b2); -+ mdio_write(tp, 0x06, 0xfbff); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0x04f8); -+ mdio_write(tp, 0x06, 0xe0f8); -+ mdio_write(tp, 0x06, 0x48e1); -+ mdio_write(tp, 0x06, 0xf849); -+ mdio_write(tp, 0x06, 0x6808); -+ mdio_write(tp, 0x06, 0xe4f8); -+ mdio_write(tp, 0x06, 0x48e5); -+ mdio_write(tp, 0x06, 0xf849); -+ mdio_write(tp, 0x06, 0x58f7); -+ mdio_write(tp, 0x06, 0xe4f8); -+ mdio_write(tp, 0x06, 0x48e5); -+ mdio_write(tp, 0x06, 0xf849); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0x4d20); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x4e22); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x4ddf); -+ mdio_write(tp, 0x06, 0xff01); -+ mdio_write(tp, 0x06, 0x4edd); -+ mdio_write(tp, 0x06, 0xff01); -+ mdio_write(tp, 0x06, 0xf8fa); -+ mdio_write(tp, 0x06, 0xfbef); -+ mdio_write(tp, 0x06, 0x79bf); -+ mdio_write(tp, 0x06, 0xf822); -+ mdio_write(tp, 0x06, 0xd819); -+ mdio_write(tp, 0x06, 0xd958); -+ mdio_write(tp, 0x06, 0x849f); -+ mdio_write(tp, 0x06, 0x09bf); -+ mdio_write(tp, 0x06, 0x82be); -+ mdio_write(tp, 0x06, 0xd682); -+ mdio_write(tp, 0x06, 0xc602); -+ mdio_write(tp, 0x06, 0x014f); -+ mdio_write(tp, 0x06, 0xef97); -+ mdio_write(tp, 0x06, 0xfffe); -+ mdio_write(tp, 0x06, 0xfc05); -+ mdio_write(tp, 0x06, 0x17ff); -+ mdio_write(tp, 0x06, 0xfe01); -+ mdio_write(tp, 0x06, 0x1700); -+ mdio_write(tp, 0x06, 0x0102); -+ mdio_write(tp, 0x05, 0x83d8); -+ mdio_write(tp, 0x06, 0x8051); -+ mdio_write(tp, 0x05, 0x83d6); -+ mdio_write(tp, 0x06, 0x82a0); -+ mdio_write(tp, 0x05, 0x83d4); -+ mdio_write(tp, 0x06, 0x8000); -+ mdio_write(tp, 0x02, 0x2010); -+ mdio_write(tp, 0x03, 0xdc00); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x0b, 0x0600); -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x00fc); -+ mdio_write(tp, 0x1f, 0x0000); -+ } -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x0D, 0xF880); -+ mdio_write(tp, 0x1F, 0x0000); -+ } else if (tp->mcfg == CFG_METHOD_10) { -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x06, 0x4064); -+ mdio_write(tp, 0x07, 0x2863); -+ mdio_write(tp, 0x08, 0x059C); -+ mdio_write(tp, 0x09, 0x26B4); -+ mdio_write(tp, 0x0A, 0x6A19); -+ mdio_write(tp, 0x0B, 0xDCC8); -+ mdio_write(tp, 0x10, 0xF06D); -+ mdio_write(tp, 0x14, 0x7F68); -+ mdio_write(tp, 0x18, 0x7FD9); -+ mdio_write(tp, 0x1C, 0xF0FF); -+ mdio_write(tp, 0x1D, 0x3D9C); -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x12, 0xF49F); -+ mdio_write(tp, 0x13, 0x070B); -+ mdio_write(tp, 0x1A, 0x05AD); -+ mdio_write(tp, 0x14, 0x94C0); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x06, 0x5561); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8332); -+ mdio_write(tp, 0x06, 0x5561); -+ -+ if (rtl8168_efuse_read(tp, 0x01) == 0xb1) { -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x05, 0x669A); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8330); -+ mdio_write(tp, 0x06, 0x669A); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ gphy_val = mdio_read(tp, 0x0D); -+ if ((gphy_val & 0x00FF) != 0x006C) { -+ gphy_val &= 0xFF00; -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x0D, gphy_val | 0x0065); -+ mdio_write(tp, 0x0D, gphy_val | 0x0066); -+ mdio_write(tp, 0x0D, gphy_val | 0x0067); -+ mdio_write(tp, 0x0D, gphy_val | 0x0068); -+ mdio_write(tp, 0x0D, gphy_val | 0x0069); -+ mdio_write(tp, 0x0D, gphy_val | 0x006A); -+ mdio_write(tp, 0x0D, gphy_val | 0x006B); -+ mdio_write(tp, 0x0D, gphy_val | 0x006C); -+ } -+ } else { -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x05, 0x2642); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8330); -+ mdio_write(tp, 0x06, 0x2642); -+ } -+ -+ if (rtl8168_efuse_read(tp, 0x30) == 0x98) { -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) & ~BIT_1); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x01, mdio_read(tp, 0x01) | BIT_9); -+ } else if (rtl8168_efuse_read(tp, 0x30) == 0x90) { -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x01, mdio_read(tp, 0x01) & ~BIT_9); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x16, 0x5101); -+ } -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ gphy_val = mdio_read(tp, 0x02); -+ gphy_val &= ~BIT_10; -+ gphy_val &= ~BIT_9; -+ gphy_val |= BIT_8; -+ mdio_write(tp, 0x02, gphy_val); -+ gphy_val = mdio_read(tp, 0x03); -+ gphy_val &= ~BIT_15; -+ gphy_val &= ~BIT_14; -+ gphy_val &= ~BIT_13; -+ mdio_write(tp, 0x03, gphy_val); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x17, 0x0CC0); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ gphy_val = mdio_read(tp, 0x0F); -+ gphy_val |= BIT_4; -+ gphy_val |= BIT_2; -+ gphy_val |= BIT_1; -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x0F, gphy_val); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x001B); -+ if (mdio_read(tp, 0x06) == 0xB300) { -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x0080); -+ mdio_write(tp, 0x05, 0x8000); -+ mdio_write(tp, 0x06, 0xf8f9); -+ mdio_write(tp, 0x06, 0xfaee); -+ mdio_write(tp, 0x06, 0xf8ea); -+ mdio_write(tp, 0x06, 0x00ee); -+ mdio_write(tp, 0x06, 0xf8eb); -+ mdio_write(tp, 0x06, 0x00e2); -+ mdio_write(tp, 0x06, 0xf87c); -+ mdio_write(tp, 0x06, 0xe3f8); -+ mdio_write(tp, 0x06, 0x7da5); -+ mdio_write(tp, 0x06, 0x1111); -+ mdio_write(tp, 0x06, 0x12d2); -+ mdio_write(tp, 0x06, 0x40d6); -+ mdio_write(tp, 0x06, 0x4444); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0xc6d2); -+ mdio_write(tp, 0x06, 0xa0d6); -+ mdio_write(tp, 0x06, 0xaaaa); -+ mdio_write(tp, 0x06, 0x0281); -+ mdio_write(tp, 0x06, 0xc6ae); -+ mdio_write(tp, 0x06, 0x0fa5); -+ mdio_write(tp, 0x06, 0x4444); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x4da5); -+ mdio_write(tp, 0x06, 0xaaaa); -+ mdio_write(tp, 0x06, 0x02ae); -+ mdio_write(tp, 0x06, 0x47af); -+ mdio_write(tp, 0x06, 0x81c2); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x4e00); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x4d0f); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x4c0f); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x4f00); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x5100); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x4aff); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x4bff); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x30e1); -+ mdio_write(tp, 0x06, 0x8331); -+ mdio_write(tp, 0x06, 0x58fe); -+ mdio_write(tp, 0x06, 0xe4f8); -+ mdio_write(tp, 0x06, 0x8ae5); -+ mdio_write(tp, 0x06, 0xf88b); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x32e1); -+ mdio_write(tp, 0x06, 0x8333); -+ mdio_write(tp, 0x06, 0x590f); -+ mdio_write(tp, 0x06, 0xe283); -+ mdio_write(tp, 0x06, 0x4d0c); -+ mdio_write(tp, 0x06, 0x245a); -+ mdio_write(tp, 0x06, 0xf01e); -+ mdio_write(tp, 0x06, 0x12e4); -+ mdio_write(tp, 0x06, 0xf88c); -+ mdio_write(tp, 0x06, 0xe5f8); -+ mdio_write(tp, 0x06, 0x8daf); -+ mdio_write(tp, 0x06, 0x81c2); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x4f10); -+ mdio_write(tp, 0x06, 0xe483); -+ mdio_write(tp, 0x06, 0x4fe0); -+ mdio_write(tp, 0x06, 0x834e); -+ mdio_write(tp, 0x06, 0x7800); -+ mdio_write(tp, 0x06, 0x9f0a); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x4fa0); -+ mdio_write(tp, 0x06, 0x10a5); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x4e01); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x4e78); -+ mdio_write(tp, 0x06, 0x059e); -+ mdio_write(tp, 0x06, 0x9ae0); -+ mdio_write(tp, 0x06, 0x834e); -+ mdio_write(tp, 0x06, 0x7804); -+ mdio_write(tp, 0x06, 0x9e10); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x4e78); -+ mdio_write(tp, 0x06, 0x039e); -+ mdio_write(tp, 0x06, 0x0fe0); -+ mdio_write(tp, 0x06, 0x834e); -+ mdio_write(tp, 0x06, 0x7801); -+ mdio_write(tp, 0x06, 0x9e05); -+ mdio_write(tp, 0x06, 0xae0c); -+ mdio_write(tp, 0x06, 0xaf81); -+ mdio_write(tp, 0x06, 0xa7af); -+ mdio_write(tp, 0x06, 0x8152); -+ mdio_write(tp, 0x06, 0xaf81); -+ mdio_write(tp, 0x06, 0x8baf); -+ mdio_write(tp, 0x06, 0x81c2); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x4800); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x4900); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x5110); -+ mdio_write(tp, 0x06, 0xe483); -+ mdio_write(tp, 0x06, 0x5158); -+ mdio_write(tp, 0x06, 0x019f); -+ mdio_write(tp, 0x06, 0xead0); -+ mdio_write(tp, 0x06, 0x00d1); -+ mdio_write(tp, 0x06, 0x801f); -+ mdio_write(tp, 0x06, 0x66e2); -+ mdio_write(tp, 0x06, 0xf8ea); -+ mdio_write(tp, 0x06, 0xe3f8); -+ mdio_write(tp, 0x06, 0xeb5a); -+ mdio_write(tp, 0x06, 0xf81e); -+ mdio_write(tp, 0x06, 0x20e6); -+ mdio_write(tp, 0x06, 0xf8ea); -+ mdio_write(tp, 0x06, 0xe5f8); -+ mdio_write(tp, 0x06, 0xebd3); -+ mdio_write(tp, 0x06, 0x02b3); -+ mdio_write(tp, 0x06, 0xfee2); -+ mdio_write(tp, 0x06, 0xf87c); -+ mdio_write(tp, 0x06, 0xef32); -+ mdio_write(tp, 0x06, 0x5b80); -+ mdio_write(tp, 0x06, 0xe3f8); -+ mdio_write(tp, 0x06, 0x7d9e); -+ mdio_write(tp, 0x06, 0x037d); -+ mdio_write(tp, 0x06, 0xffff); -+ mdio_write(tp, 0x06, 0x0d58); -+ mdio_write(tp, 0x06, 0x1c55); -+ mdio_write(tp, 0x06, 0x1a65); -+ mdio_write(tp, 0x06, 0x11a1); -+ mdio_write(tp, 0x06, 0x90d3); -+ mdio_write(tp, 0x06, 0xe283); -+ mdio_write(tp, 0x06, 0x48e3); -+ mdio_write(tp, 0x06, 0x8349); -+ mdio_write(tp, 0x06, 0x1b56); -+ mdio_write(tp, 0x06, 0xab08); -+ mdio_write(tp, 0x06, 0xef56); -+ mdio_write(tp, 0x06, 0xe683); -+ mdio_write(tp, 0x06, 0x48e7); -+ mdio_write(tp, 0x06, 0x8349); -+ mdio_write(tp, 0x06, 0x10d1); -+ mdio_write(tp, 0x06, 0x801f); -+ mdio_write(tp, 0x06, 0x66a0); -+ mdio_write(tp, 0x06, 0x04b9); -+ mdio_write(tp, 0x06, 0xe283); -+ mdio_write(tp, 0x06, 0x48e3); -+ mdio_write(tp, 0x06, 0x8349); -+ mdio_write(tp, 0x06, 0xef65); -+ mdio_write(tp, 0x06, 0xe283); -+ mdio_write(tp, 0x06, 0x4ae3); -+ mdio_write(tp, 0x06, 0x834b); -+ mdio_write(tp, 0x06, 0x1b56); -+ mdio_write(tp, 0x06, 0xaa0e); -+ mdio_write(tp, 0x06, 0xef56); -+ mdio_write(tp, 0x06, 0xe683); -+ mdio_write(tp, 0x06, 0x4ae7); -+ mdio_write(tp, 0x06, 0x834b); -+ mdio_write(tp, 0x06, 0xe283); -+ mdio_write(tp, 0x06, 0x4de6); -+ mdio_write(tp, 0x06, 0x834c); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x4da0); -+ mdio_write(tp, 0x06, 0x000c); -+ mdio_write(tp, 0x06, 0xaf81); -+ mdio_write(tp, 0x06, 0x8be0); -+ mdio_write(tp, 0x06, 0x834d); -+ mdio_write(tp, 0x06, 0x10e4); -+ mdio_write(tp, 0x06, 0x834d); -+ mdio_write(tp, 0x06, 0xae04); -+ mdio_write(tp, 0x06, 0x80e4); -+ mdio_write(tp, 0x06, 0x834d); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x4e78); -+ mdio_write(tp, 0x06, 0x039e); -+ mdio_write(tp, 0x06, 0x0be0); -+ mdio_write(tp, 0x06, 0x834e); -+ mdio_write(tp, 0x06, 0x7804); -+ mdio_write(tp, 0x06, 0x9e04); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x4e02); -+ mdio_write(tp, 0x06, 0xe083); -+ mdio_write(tp, 0x06, 0x32e1); -+ mdio_write(tp, 0x06, 0x8333); -+ mdio_write(tp, 0x06, 0x590f); -+ mdio_write(tp, 0x06, 0xe283); -+ mdio_write(tp, 0x06, 0x4d0c); -+ mdio_write(tp, 0x06, 0x245a); -+ mdio_write(tp, 0x06, 0xf01e); -+ mdio_write(tp, 0x06, 0x12e4); -+ mdio_write(tp, 0x06, 0xf88c); -+ mdio_write(tp, 0x06, 0xe5f8); -+ mdio_write(tp, 0x06, 0x8de0); -+ mdio_write(tp, 0x06, 0x8330); -+ mdio_write(tp, 0x06, 0xe183); -+ mdio_write(tp, 0x06, 0x3168); -+ mdio_write(tp, 0x06, 0x01e4); -+ mdio_write(tp, 0x06, 0xf88a); -+ mdio_write(tp, 0x06, 0xe5f8); -+ mdio_write(tp, 0x06, 0x8bae); -+ mdio_write(tp, 0x06, 0x37ee); -+ mdio_write(tp, 0x06, 0x834e); -+ mdio_write(tp, 0x06, 0x03e0); -+ mdio_write(tp, 0x06, 0x834c); -+ mdio_write(tp, 0x06, 0xe183); -+ mdio_write(tp, 0x06, 0x4d1b); -+ mdio_write(tp, 0x06, 0x019e); -+ mdio_write(tp, 0x06, 0x04aa); -+ mdio_write(tp, 0x06, 0xa1ae); -+ mdio_write(tp, 0x06, 0xa8ee); -+ mdio_write(tp, 0x06, 0x834e); -+ mdio_write(tp, 0x06, 0x04ee); -+ mdio_write(tp, 0x06, 0x834f); -+ mdio_write(tp, 0x06, 0x00ae); -+ mdio_write(tp, 0x06, 0xabe0); -+ mdio_write(tp, 0x06, 0x834f); -+ mdio_write(tp, 0x06, 0x7803); -+ mdio_write(tp, 0x06, 0x9f14); -+ mdio_write(tp, 0x06, 0xee83); -+ mdio_write(tp, 0x06, 0x4e05); -+ mdio_write(tp, 0x06, 0xd240); -+ mdio_write(tp, 0x06, 0xd655); -+ mdio_write(tp, 0x06, 0x5402); -+ mdio_write(tp, 0x06, 0x81c6); -+ mdio_write(tp, 0x06, 0xd2a0); -+ mdio_write(tp, 0x06, 0xd6ba); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x81c6); -+ mdio_write(tp, 0x06, 0xfefd); -+ mdio_write(tp, 0x06, 0xfc05); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0xf860); -+ mdio_write(tp, 0x06, 0xe1f8); -+ mdio_write(tp, 0x06, 0x6168); -+ mdio_write(tp, 0x06, 0x02e4); -+ mdio_write(tp, 0x06, 0xf860); -+ mdio_write(tp, 0x06, 0xe5f8); -+ mdio_write(tp, 0x06, 0x61e0); -+ mdio_write(tp, 0x06, 0xf848); -+ mdio_write(tp, 0x06, 0xe1f8); -+ mdio_write(tp, 0x06, 0x4958); -+ mdio_write(tp, 0x06, 0x0f1e); -+ mdio_write(tp, 0x06, 0x02e4); -+ mdio_write(tp, 0x06, 0xf848); -+ mdio_write(tp, 0x06, 0xe5f8); -+ mdio_write(tp, 0x06, 0x49d0); -+ mdio_write(tp, 0x06, 0x0002); -+ mdio_write(tp, 0x06, 0x820a); -+ mdio_write(tp, 0x06, 0xbf83); -+ mdio_write(tp, 0x06, 0x50ef); -+ mdio_write(tp, 0x06, 0x46dc); -+ mdio_write(tp, 0x06, 0x19dd); -+ mdio_write(tp, 0x06, 0xd001); -+ mdio_write(tp, 0x06, 0x0282); -+ mdio_write(tp, 0x06, 0x0a02); -+ mdio_write(tp, 0x06, 0x8226); -+ mdio_write(tp, 0x06, 0xe0f8); -+ mdio_write(tp, 0x06, 0x60e1); -+ mdio_write(tp, 0x06, 0xf861); -+ mdio_write(tp, 0x06, 0x58fd); -+ mdio_write(tp, 0x06, 0xe4f8); -+ mdio_write(tp, 0x06, 0x60e5); -+ mdio_write(tp, 0x06, 0xf861); -+ mdio_write(tp, 0x06, 0xfc04); -+ mdio_write(tp, 0x06, 0xf9fa); -+ mdio_write(tp, 0x06, 0xfbc6); -+ mdio_write(tp, 0x06, 0xbff8); -+ mdio_write(tp, 0x06, 0x40be); -+ mdio_write(tp, 0x06, 0x8350); -+ mdio_write(tp, 0x06, 0xa001); -+ mdio_write(tp, 0x06, 0x0107); -+ mdio_write(tp, 0x06, 0x1b89); -+ mdio_write(tp, 0x06, 0xcfd2); -+ mdio_write(tp, 0x06, 0x08eb); -+ mdio_write(tp, 0x06, 0xdb19); -+ mdio_write(tp, 0x06, 0xb2fb); -+ mdio_write(tp, 0x06, 0xfffe); -+ mdio_write(tp, 0x06, 0xfd04); -+ mdio_write(tp, 0x06, 0xf8e0); -+ mdio_write(tp, 0x06, 0xf848); -+ mdio_write(tp, 0x06, 0xe1f8); -+ mdio_write(tp, 0x06, 0x4968); -+ mdio_write(tp, 0x06, 0x08e4); -+ mdio_write(tp, 0x06, 0xf848); -+ mdio_write(tp, 0x06, 0xe5f8); -+ mdio_write(tp, 0x06, 0x4958); -+ mdio_write(tp, 0x06, 0xf7e4); -+ mdio_write(tp, 0x06, 0xf848); -+ mdio_write(tp, 0x06, 0xe5f8); -+ mdio_write(tp, 0x06, 0x49fc); -+ mdio_write(tp, 0x06, 0x044d); -+ mdio_write(tp, 0x06, 0x2000); -+ mdio_write(tp, 0x06, 0x024e); -+ mdio_write(tp, 0x06, 0x2200); -+ mdio_write(tp, 0x06, 0x024d); -+ mdio_write(tp, 0x06, 0xdfff); -+ mdio_write(tp, 0x06, 0x014e); -+ mdio_write(tp, 0x06, 0xddff); -+ mdio_write(tp, 0x06, 0x01f8); -+ mdio_write(tp, 0x06, 0xfafb); -+ mdio_write(tp, 0x06, 0xef79); -+ mdio_write(tp, 0x06, 0xbff8); -+ mdio_write(tp, 0x06, 0x22d8); -+ mdio_write(tp, 0x06, 0x19d9); -+ mdio_write(tp, 0x06, 0x5884); -+ mdio_write(tp, 0x06, 0x9f09); -+ mdio_write(tp, 0x06, 0xbf82); -+ mdio_write(tp, 0x06, 0x6dd6); -+ mdio_write(tp, 0x06, 0x8275); -+ mdio_write(tp, 0x06, 0x0201); -+ mdio_write(tp, 0x06, 0x4fef); -+ mdio_write(tp, 0x06, 0x97ff); -+ mdio_write(tp, 0x06, 0xfefc); -+ mdio_write(tp, 0x06, 0x0517); -+ mdio_write(tp, 0x06, 0xfffe); -+ mdio_write(tp, 0x06, 0x0117); -+ mdio_write(tp, 0x06, 0x0001); -+ mdio_write(tp, 0x06, 0x0200); -+ mdio_write(tp, 0x05, 0x83d8); -+ mdio_write(tp, 0x06, 0x8000); -+ mdio_write(tp, 0x05, 0x83d6); -+ mdio_write(tp, 0x06, 0x824f); -+ mdio_write(tp, 0x02, 0x2010); -+ mdio_write(tp, 0x03, 0xdc00); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x0b, 0x0600); -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0xfff6); -+ mdio_write(tp, 0x06, 0x00fc); -+ mdio_write(tp, 0x1f, 0x0000); -+ } -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x0D, 0xF880); -+ mdio_write(tp, 0x1F, 0x0000); -+ } else if (tp->mcfg == CFG_METHOD_11) { -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x10, 0x0008); -+ mdio_write(tp, 0x0D, 0x006C); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x17, 0x0CC0); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x0B, 0xA4D8); -+ mdio_write(tp, 0x09, 0x281C); -+ mdio_write(tp, 0x07, 0x2883); -+ mdio_write(tp, 0x0A, 0x6B35); -+ mdio_write(tp, 0x1D, 0x3DA4); -+ mdio_write(tp, 0x1C, 0xEFFD); -+ mdio_write(tp, 0x14, 0x7F52); -+ mdio_write(tp, 0x18, 0x7FC6); -+ mdio_write(tp, 0x08, 0x0601); -+ mdio_write(tp, 0x06, 0x4063); -+ mdio_write(tp, 0x10, 0xF074); -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x13, 0x0789); -+ mdio_write(tp, 0x12, 0xF4BD); -+ mdio_write(tp, 0x1A, 0x04FD); -+ mdio_write(tp, 0x14, 0x84B0); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x00, 0x9200); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x01, 0x0340); -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x04, 0x4000); -+ mdio_write(tp, 0x03, 0x1D21); -+ mdio_write(tp, 0x02, 0x0C32); -+ mdio_write(tp, 0x01, 0x0200); -+ mdio_write(tp, 0x00, 0x5554); -+ mdio_write(tp, 0x04, 0x4800); -+ mdio_write(tp, 0x04, 0x4000); -+ mdio_write(tp, 0x04, 0xF000); -+ mdio_write(tp, 0x03, 0xDF01); -+ mdio_write(tp, 0x02, 0xDF20); -+ mdio_write(tp, 0x01, 0x101A); -+ mdio_write(tp, 0x00, 0xA0FF); -+ mdio_write(tp, 0x04, 0xF800); -+ mdio_write(tp, 0x04, 0xF000); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x0023); -+ mdio_write(tp, 0x16, 0x0000); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ gphy_val = mdio_read(tp, 0x0D); -+ gphy_val |= BIT_5; -+ mdio_write(tp, 0x0D, gphy_val); -+ } else if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13) { -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x17, 0x0CC0); -+ -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x002D); -+ mdio_write(tp, 0x18, 0x0040); -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ gphy_val = mdio_read(tp, 0x0D); -+ gphy_val |= BIT_5; -+ mdio_write(tp, 0x0D, gphy_val); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ gphy_val = mdio_read(tp, 0x0C); -+ gphy_val |= BIT_10; -+ mdio_write(tp, 0x0C, gphy_val); -+ } else if (tp->mcfg == CFG_METHOD_14 || tp->mcfg == CFG_METHOD_15) { -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x0023); -+ gphy_val = mdio_read(tp, 0x17) | BIT_1; -+ if (tp->RequiredSecLanDonglePatch) -+ gphy_val &= ~(BIT_2); -+ else -+ gphy_val |= (BIT_2); -+ mdio_write(tp, 0x17, gphy_val); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0x8b80); -+ mdio_write(tp, 0x06, 0xc896); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x0B, 0x6C20); -+ mdio_write(tp, 0x07, 0x2872); -+ mdio_write(tp, 0x1C, 0xEFFF); -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x14, 0x6420); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ gphy_val = mdio_read(tp, 0x08) & 0x00FF; -+ mdio_write(tp, 0x08, gphy_val | 0x8000); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x002D); -+ gphy_val = mdio_read(tp, 0x18); -+ mdio_write(tp, 0x18, gphy_val | 0x0010); -+ mdio_write(tp, 0x1F, 0x0000); -+ gphy_val = mdio_read(tp, 0x14); -+ mdio_write(tp, 0x14, gphy_val | 0x8000); -+ -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x00, 0x080B); -+ mdio_write(tp, 0x0B, 0x09D7); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ if (aspm) { -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x15, 0x1006); -+ } -+ } -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x19, 0x7F46); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8AD2); -+ mdio_write(tp, 0x06, 0x6810); -+ mdio_write(tp, 0x05, 0x8AD4); -+ mdio_write(tp, 0x06, 0x8002); -+ mdio_write(tp, 0x05, 0x8ADE); -+ mdio_write(tp, 0x06, 0x8025); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x002F); -+ mdio_write(tp, 0x15, 0x1919); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x002D); -+ gphy_val = mdio_read(tp, 0x18); -+ mdio_write(tp, 0x18, gphy_val | 0x0040); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B86); -+ gphy_val = mdio_read(tp, 0x06); -+ mdio_write(tp, 0x06, gphy_val | 0x0001); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x00AC); -+ mdio_write(tp, 0x18, 0x0006); -+ mdio_write(tp, 0x1F, 0x0000); -+ } else if (tp->mcfg == CFG_METHOD_16) { -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B80); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_2 | BIT_1; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1f, 0x0004); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x002D); -+ gphy_val = mdio_read(tp, 0x18); -+ gphy_val |= BIT_4; -+ mdio_write(tp, 0x18, gphy_val); -+ mdio_write(tp, 0x1f, 0x0002); -+ mdio_write(tp, 0x1f, 0x0000); -+ gphy_val = mdio_read(tp, 0x14); -+ gphy_val |= BIT_15; -+ mdio_write(tp, 0x14, gphy_val); -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x15, 0x1006); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B86); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x0B, 0x6C14); -+ mdio_write(tp, 0x14, 0x7F3D); -+ mdio_write(tp, 0x1C, 0xFAFE); -+ mdio_write(tp, 0x08, 0x07C5); -+ mdio_write(tp, 0x10, 0xF090); -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x14, 0x641A); -+ mdio_write(tp, 0x1A, 0x0606); -+ mdio_write(tp, 0x12, 0xF480); -+ mdio_write(tp, 0x13, 0x0747); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0004); -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x0078); -+ mdio_write(tp, 0x15, 0xA408); -+ mdio_write(tp, 0x17, 0x5100); -+ mdio_write(tp, 0x19, 0x0008); -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x0D, 0x0207); -+ mdio_write(tp, 0x02, 0x5FD0); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0004); -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x00A1); -+ gphy_val = mdio_read(tp, 0x1A); -+ gphy_val &= ~BIT_2; -+ mdio_write(tp, 0x1A, gphy_val); -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0004); -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x002D); -+ gphy_val = mdio_read(tp, 0x16); -+ gphy_val |= BIT_5; -+ mdio_write(tp, 0x16, gphy_val); -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0004); -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x00AC); -+ mdio_write(tp, 0x18, 0x0006); -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x09, 0xA20F); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B5B); -+ mdio_write(tp, 0x06, 0x9222); -+ mdio_write(tp, 0x05, 0x8B6D); -+ mdio_write(tp, 0x06, 0x8000); -+ mdio_write(tp, 0x05, 0x8B76); -+ mdio_write(tp, 0x06, 0x8000); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ if (pdev->subsystem_vendor == 0x1043 && -+ pdev->subsystem_device == 0x13F7) { -+ -+ static const u16 evl_phy_value[] = { -+ 0x8B56, 0x8B5F, 0x8B68, 0x8B71, -+ 0x8B7A, 0x8A7B, 0x8A7E, 0x8A81, -+ 0x8A84, 0x8A87 -+ }; -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ for (i = 0; i < ARRAY_SIZE(evl_phy_value); i++) { -+ mdio_write(tp, 0x05, evl_phy_value[i]); -+ gphy_val = (0xAA << 8) | (mdio_read(tp, 0x06) & 0xFF); -+ mdio_write(tp, 0x06, gphy_val); -+ } -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x0078); -+ mdio_write(tp, 0x17, 0x51AA); -+ mdio_write(tp, 0x1F, 0x0000); -+ } -+ -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0x8B54); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_11); -+ mdio_write(tp, 0x05, 0x8B5D); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_11); -+ mdio_write(tp, 0x05, 0x8A7C); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A7F); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) | BIT_8); -+ mdio_write(tp, 0x05, 0x8A82); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A85); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A88); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B85); -+ gphy_val = mdio_read(tp, 0x06) | BIT_14 | BIT_15; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ } else if (tp->mcfg == CFG_METHOD_17) { -+ if (pdev->subsystem_vendor == 0x144d && -+ pdev->subsystem_device == 0xc0a6) { -+ mdio_write(tp, 0x1F, 0x0001); -+ mdio_write(tp, 0x0e, 0x6b7f); -+ mdio_write(tp, 0x1f, 0x0000); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B86); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_4; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ } else { -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B80); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_2 | BIT_1; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B86); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val &= ~BIT_4; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ } -+ -+ mdio_write(tp, 0x1f, 0x0004); -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x002D); -+ gphy_val = mdio_read(tp, 0x18); -+ gphy_val |= BIT_4; -+ mdio_write(tp, 0x18, gphy_val); -+ mdio_write(tp, 0x1f, 0x0002); -+ mdio_write(tp, 0x1f, 0x0000); -+ gphy_val = mdio_read(tp, 0x14); -+ gphy_val |= BIT_15; -+ mdio_write(tp, 0x14, gphy_val); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B86); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0004); -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x00AC); -+ mdio_write(tp, 0x18, 0x0006); -+ mdio_write(tp, 0x1F, 0x0002); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x09, 0xA20F); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B85); -+ gphy_val = mdio_read(tp, 0x06) | BIT_14 | BIT_15; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B5B); -+ mdio_write(tp, 0x06, 0x9222); -+ mdio_write(tp, 0x05, 0x8B6D); -+ mdio_write(tp, 0x06, 0x8000); -+ mdio_write(tp, 0x05, 0x8B76); -+ mdio_write(tp, 0x06, 0x8000); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ if (pdev->subsystem_vendor == 0x1043 && -+ pdev->subsystem_device == 0x13F7) { -+ -+ static const u16 evl_phy_value[] = { -+ 0x8B56, 0x8B5F, 0x8B68, 0x8B71, -+ 0x8B7A, 0x8A7B, 0x8A7E, 0x8A81, -+ 0x8A84, 0x8A87 -+ }; -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ for (i = 0; i < ARRAY_SIZE(evl_phy_value); i++) { -+ mdio_write(tp, 0x05, evl_phy_value[i]); -+ gphy_val = (0xAA << 8) | (mdio_read(tp, 0x06) & 0xFF); -+ mdio_write(tp, 0x06, gphy_val); -+ } -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x0078); -+ mdio_write(tp, 0x17, 0x51AA); -+ mdio_write(tp, 0x1F, 0x0000); -+ } -+ -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0x8B54); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_11); -+ mdio_write(tp, 0x05, 0x8B5D); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_11); -+ mdio_write(tp, 0x05, 0x8A7C); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A7F); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) | BIT_8); -+ mdio_write(tp, 0x05, 0x8A82); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A85); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A88); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ if (aspm) { -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1f, 0x0000); -+ gphy_val = mdio_read(tp, 0x15); -+ gphy_val |= BIT_12; -+ mdio_write(tp, 0x15, gphy_val); -+ } -+ } -+ } else if (tp->mcfg == CFG_METHOD_18) { -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8b80); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_2 | BIT_1; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1F, 0x0000); -+ } -+ -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x002D); -+ gphy_val = mdio_read(tp, 0x18); -+ gphy_val |= BIT_4; -+ mdio_write(tp, 0x18, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ gphy_val = mdio_read(tp, 0x14); -+ gphy_val |= BIT_15; -+ mdio_write(tp, 0x14, gphy_val); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B86); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B85); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_14; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x09, 0xA20F); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B55); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x05, 0x8B5E); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x05, 0x8B67); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x05, 0x8B70); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x0078); -+ mdio_write(tp, 0x17, 0x0000); -+ mdio_write(tp, 0x19, 0x00FB); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B79); -+ mdio_write(tp, 0x06, 0xAA00); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1f, 0x0003); -+ mdio_write(tp, 0x01, 0x328A); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0x8B54); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_11); -+ mdio_write(tp, 0x05, 0x8B5D); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_11); -+ mdio_write(tp, 0x05, 0x8A7C); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A7F); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) | BIT_8); -+ mdio_write(tp, 0x05, 0x8A82); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A85); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A88); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0x8b85); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) | BIT_15); -+ mdio_write(tp, 0x1f, 0x0000); -+ } -+ -+ if (aspm) { -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1f, 0x0000); -+ gphy_val = mdio_read(tp, 0x15); -+ gphy_val |= BIT_12; -+ mdio_write(tp, 0x15, gphy_val); -+ } -+ } -+ } else if (tp->mcfg == CFG_METHOD_19) { -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8b80); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_2 | BIT_1; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1F, 0x0000); -+ } -+ -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x002D); -+ gphy_val = mdio_read(tp, 0x18); -+ gphy_val |= BIT_4; -+ mdio_write(tp, 0x18, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ gphy_val = mdio_read(tp, 0x14); -+ gphy_val |= BIT_15; -+ mdio_write(tp, 0x14, gphy_val); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B86); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0x8B54); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_11); -+ mdio_write(tp, 0x05, 0x8B5D); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_11); -+ mdio_write(tp, 0x05, 0x8A7C); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A7F); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) | BIT_8); -+ mdio_write(tp, 0x05, 0x8A82); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A85); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A88); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0x8b85); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) | BIT_15); -+ mdio_write(tp, 0x1f, 0x0000); -+ } -+ -+ if (aspm) { -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1f, 0x0000); -+ gphy_val = mdio_read(tp, 0x15); -+ gphy_val |= BIT_12; -+ mdio_write(tp, 0x15, gphy_val); -+ } -+ } -+ } else if (tp->mcfg == CFG_METHOD_20) { -+ -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8b80); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_2 | BIT_1; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1F, 0x0000); -+ } -+ -+ mdio_write(tp, 0x1f, 0x0007); -+ mdio_write(tp, 0x1e, 0x002D); -+ gphy_val = mdio_read(tp, 0x18); -+ gphy_val |= BIT_4; -+ mdio_write(tp, 0x18, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ gphy_val = mdio_read(tp, 0x14); -+ gphy_val |= BIT_15; -+ mdio_write(tp, 0x14, gphy_val); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B86); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_0; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B85); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_14; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0003); -+ mdio_write(tp, 0x09, 0xA20F); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B55); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x05, 0x8B5E); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x05, 0x8B67); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x05, 0x8B70); -+ mdio_write(tp, 0x06, 0x0000); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x0078); -+ mdio_write(tp, 0x17, 0x0000); -+ mdio_write(tp, 0x19, 0x00FB); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B79); -+ mdio_write(tp, 0x06, 0xAA00); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0x8B54); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_11); -+ mdio_write(tp, 0x05, 0x8B5D); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_11); -+ mdio_write(tp, 0x05, 0x8A7C); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A7F); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) | BIT_8); -+ mdio_write(tp, 0x05, 0x8A82); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A85); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x05, 0x8A88); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) & ~BIT_8); -+ mdio_write(tp, 0x1f, 0x0000); -+ -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1f, 0x0005); -+ mdio_write(tp, 0x05, 0x8b85); -+ mdio_write(tp, 0x06, mdio_read(tp, 0x06) | BIT_15); -+ mdio_write(tp, 0x1f, 0x0000); -+ } -+ -+ if (aspm) { -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1f, 0x0000); -+ gphy_val = mdio_read(tp, 0x15); -+ gphy_val |= BIT_12; -+ mdio_write(tp, 0x15, gphy_val); -+ } -+ } -+ } else if (tp->mcfg == CFG_METHOD_21) { -+ mdio_write(tp, 0x1F, 0x0A46); -+ gphy_val = mdio_read(tp, 0x10); -+ mdio_write(tp, 0x1F, 0x0BCC); -+ if (gphy_val & BIT_8) -+ ClearEthPhyBit(tp, 0x12, BIT_15); -+ else -+ SetEthPhyBit(tp, 0x12, BIT_15); -+ mdio_write(tp, 0x1F, 0x0A46); -+ gphy_val = mdio_read(tp, 0x13); -+ mdio_write(tp, 0x1F, 0x0C41); -+ if (gphy_val & BIT_8) -+ SetEthPhyBit(tp, 0x15, BIT_1); -+ else -+ ClearEthPhyBit(tp, 0x15, BIT_1); -+ -+ mdio_write(tp, 0x1F, 0x0A44); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) | BIT_2 | BIT_3); -+ -+ mdio_write(tp, 0x1F, 0x0BCC); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) & ~BIT_8); -+ mdio_write(tp, 0x1F, 0x0A44); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) | BIT_7); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) | BIT_6); -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8084); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) & ~(BIT_14 | BIT_13)); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_12); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_1); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_0); -+ -+ mdio_write(tp, 0x1F, 0x0A4B); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) | BIT_2); -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8012); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) | BIT_15); -+ -+ mdio_write(tp, 0x1F, 0x0C42); -+ gphy_val = mdio_read(tp, 0x11); -+ gphy_val |= BIT_14; -+ gphy_val &= ~BIT_13; -+ mdio_write(tp, 0x11, gphy_val); -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x809A); -+ mdio_write(tp, 0x14, 0x8022); -+ mdio_write(tp, 0x13, 0x80A0); -+ gphy_val = mdio_read(tp, 0x14) & 0x00FF; -+ gphy_val |= 0x1000; -+ mdio_write(tp, 0x14, gphy_val); -+ mdio_write(tp, 0x13, 0x8088); -+ mdio_write(tp, 0x14, 0x9222); -+ -+ if (aspm) { -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_2); -+ } -+ } -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ } else if (tp->mcfg == CFG_METHOD_22) { -+ //do nothing -+ } else if (tp->mcfg == CFG_METHOD_23) { -+ mdio_write(tp, 0x1F, 0x0A44); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) | (BIT_3 | BIT_2)); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0BCC); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) & ~BIT_8); -+ mdio_write(tp, 0x1F, 0x0A44); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) | BIT_7); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) | BIT_6); -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8084); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) & ~(BIT_14 | BIT_13)); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_12); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_1); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_0); -+ -+ mdio_write(tp, 0x1F, 0x0A4B); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) | BIT_2); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8012); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) | BIT_15); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0C42); -+ ClearAndSetEthPhyBit(tp, -+ 0x11, -+ BIT_13, -+ BIT_14 -+ ); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ if (aspm) { -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_2); -+ } -+ } -+ } else if (tp->mcfg == CFG_METHOD_24) { -+ mdio_write(tp, 0x1F, 0x0BCC); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) & ~BIT_8); -+ mdio_write(tp, 0x1F, 0x0A44); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) | BIT_7); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) | BIT_6); -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8084); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) & ~(BIT_14 | BIT_13)); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_12); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_1); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_0); -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8012); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) | BIT_15); -+ -+ mdio_write(tp, 0x1F, 0x0C42); -+ gphy_val = mdio_read(tp, 0x11); -+ gphy_val |= BIT_14; -+ gphy_val &= ~BIT_13; -+ mdio_write(tp, 0x11, gphy_val); -+ -+ if (aspm) { -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_2); -+ } -+ } -+ } else if (tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26) { -+ mdio_write(tp, 0x1F, 0x0BCC); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) & ~BIT_8); -+ mdio_write(tp, 0x1F, 0x0A44); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) | BIT_7); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) | BIT_6); -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8084); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) & ~(BIT_14 | BIT_13)); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_12); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_1); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_0); -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8012); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) | BIT_15); -+ -+ mdio_write(tp, 0x1F, 0x0BCE); -+ mdio_write(tp, 0x12, 0x8860); -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x80F3); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x8B00); -+ mdio_write(tp, 0x13, 0x80F0); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x3A00); -+ mdio_write(tp, 0x13, 0x80EF); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x0500); -+ mdio_write(tp, 0x13, 0x80F6); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x6E00); -+ mdio_write(tp, 0x13, 0x80EC); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x6800); -+ mdio_write(tp, 0x13, 0x80ED); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x7C00); -+ mdio_write(tp, 0x13, 0x80F2); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0xF400); -+ mdio_write(tp, 0x13, 0x80F4); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x8500); -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8110); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0xA800); -+ mdio_write(tp, 0x13, 0x810F); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x1D00); -+ mdio_write(tp, 0x13, 0x8111); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0xF500); -+ mdio_write(tp, 0x13, 0x8113); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x6100); -+ mdio_write(tp, 0x13, 0x8115); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x9200); -+ mdio_write(tp, 0x13, 0x810E); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x0400); -+ mdio_write(tp, 0x13, 0x810C); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x7C00); -+ mdio_write(tp, 0x13, 0x810B); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x5A00); -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x80D1); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0xFF00); -+ mdio_write(tp, 0x13, 0x80CD); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x9E00); -+ mdio_write(tp, 0x13, 0x80D3); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x0E00); -+ mdio_write(tp, 0x13, 0x80D5); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0xCA00); -+ mdio_write(tp, 0x13, 0x80D7); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x8400); -+ -+ if (aspm) { -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_2); -+ } -+ } -+ } else if (tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28) { -+ mdio_write(tp, 0x1F, 0x0BCC); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) & ~BIT_8); -+ mdio_write(tp, 0x1F, 0x0A44); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) | BIT_7); -+ mdio_write(tp, 0x11, mdio_read(tp, 0x11) | BIT_6); -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8084); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) & ~(BIT_14 | BIT_13)); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_12); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_1); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_0); -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8012); -+ mdio_write(tp, 0x14, mdio_read(tp, 0x14) | BIT_15); -+ -+ mdio_write(tp, 0x1F, 0x0C42); -+ mdio_write(tp, 0x11, (mdio_read(tp, 0x11) & ~BIT_13) | BIT_14); -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x80F3); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x8B00); -+ mdio_write(tp, 0x13, 0x80F0); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x3A00); -+ mdio_write(tp, 0x13, 0x80EF); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x0500); -+ mdio_write(tp, 0x13, 0x80F6); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x6E00); -+ mdio_write(tp, 0x13, 0x80EC); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x6800); -+ mdio_write(tp, 0x13, 0x80ED); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x7C00); -+ mdio_write(tp, 0x13, 0x80F2); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0xF400); -+ mdio_write(tp, 0x13, 0x80F4); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x8500); -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8110); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0xA800); -+ mdio_write(tp, 0x13, 0x810F); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x1D00); -+ mdio_write(tp, 0x13, 0x8111); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0xF500); -+ mdio_write(tp, 0x13, 0x8113); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x6100); -+ mdio_write(tp, 0x13, 0x8115); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x9200); -+ mdio_write(tp, 0x13, 0x810E); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x0400); -+ mdio_write(tp, 0x13, 0x810C); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x7C00); -+ mdio_write(tp, 0x13, 0x810B); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x5A00); -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x80D1); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0xFF00); -+ mdio_write(tp, 0x13, 0x80CD); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x9E00); -+ mdio_write(tp, 0x13, 0x80D3); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x0E00); -+ mdio_write(tp, 0x13, 0x80D5); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0xCA00); -+ mdio_write(tp, 0x13, 0x80D7); -+ mdio_write(tp, 0x14, (mdio_read(tp, 0x14) & ~0xFF00) | 0x8400); -+ -+ if (aspm) { -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x10, mdio_read(tp, 0x10) | BIT_2); -+ } -+ } -+ } else if (tp->mcfg == CFG_METHOD_29) { -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x809b); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ 0xF800 , -+ 0x8000 -+ ); -+ mdio_write(tp, 0x13, 0x80A2); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ 0xFF00 , -+ 0x8000 -+ ); -+ mdio_write(tp, 0x13, 0x80A4); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ 0xFF00 , -+ 0x8500 -+ ); -+ mdio_write(tp, 0x13, 0x809C); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ 0xFF00 , -+ 0xbd00 -+ ); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x80AD); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ 0xF800 , -+ 0x7000 -+ ); -+ mdio_write(tp, 0x13, 0x80B4); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ 0xFF00 , -+ 0x5000 -+ ); -+ mdio_write(tp, 0x13, 0x80AC); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ 0xFF00 , -+ 0x4000 -+ ); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x808E); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ 0xFF00 , -+ 0x1200 -+ ); -+ mdio_write(tp, 0x13, 0x8090); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ 0xFF00 , -+ 0xE500 -+ ); -+ mdio_write(tp, 0x13, 0x8092); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ 0xFF00 , -+ 0x9F00 -+ ); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ if (tp->HwHasWrRamCodeToMicroP) { -+ u16 dout_tapbin; -+ -+ dout_tapbin = 0x0000; -+ mdio_write( tp, 0x1F, 0x0A46 ); -+ gphy_val = mdio_read( tp, 0x13 ); -+ gphy_val &= (BIT_1|BIT_0); -+ gphy_val <<= 2; -+ dout_tapbin |= gphy_val; -+ -+ gphy_val = mdio_read( tp, 0x12 ); -+ gphy_val &= (BIT_15|BIT_14); -+ gphy_val >>= 14; -+ dout_tapbin |= gphy_val; -+ -+ dout_tapbin = ~( dout_tapbin^BIT_3 ); -+ dout_tapbin <<= 12; -+ dout_tapbin &= 0xF000; -+ -+ mdio_write( tp, 0x1F, 0x0A43 ); -+ -+ mdio_write( tp, 0x13, 0x827A ); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ BIT_15|BIT_14|BIT_13|BIT_12, -+ dout_tapbin -+ ); -+ -+ -+ mdio_write( tp, 0x13, 0x827B ); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ BIT_15|BIT_14|BIT_13|BIT_12, -+ dout_tapbin -+ ); -+ -+ -+ mdio_write( tp, 0x13, 0x827C ); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ BIT_15|BIT_14|BIT_13|BIT_12, -+ dout_tapbin -+ ); -+ -+ -+ mdio_write( tp, 0x13, 0x827D ); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ BIT_15|BIT_14|BIT_13|BIT_12, -+ dout_tapbin -+ ); -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8011); -+ SetEthPhyBit(tp, 0x14, BIT_11); -+ mdio_write(tp, 0x1F, 0x0A42); -+ SetEthPhyBit(tp, 0x16, BIT_1); -+ } -+ -+ mdio_write(tp, 0x1F, 0x0A44); -+ SetEthPhyBit( tp, 0x11, BIT_11 ); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ -+ mdio_write(tp, 0x1F, 0x0BCA); -+ ClearAndSetEthPhyBit( tp, -+ 0x17, -+ (BIT_13 | BIT_12) , -+ BIT_14 -+ ); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x803F); -+ ClearEthPhyBit( tp, 0x14, (BIT_13 | BIT_12)); -+ mdio_write(tp, 0x13, 0x8047); -+ ClearEthPhyBit( tp, 0x14, (BIT_13 | BIT_12)); -+ mdio_write(tp, 0x13, 0x804F); -+ ClearEthPhyBit( tp, 0x14, (BIT_13 | BIT_12)); -+ mdio_write(tp, 0x13, 0x8057); -+ ClearEthPhyBit( tp, 0x14, (BIT_13 | BIT_12)); -+ mdio_write(tp, 0x13, 0x805F); -+ ClearEthPhyBit( tp, 0x14, (BIT_13 | BIT_12)); -+ mdio_write(tp, 0x13, 0x8067 ); -+ ClearEthPhyBit( tp, 0x14, (BIT_13 | BIT_12)); -+ mdio_write(tp, 0x13, 0x806F ); -+ ClearEthPhyBit( tp, 0x14, (BIT_13 | BIT_12)); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ if (aspm) { -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1F, 0x0A43); -+ SetEthPhyBit( tp, 0x10, BIT_2 ); -+ mdio_write(tp, 0x1F, 0x0000); -+ } -+ } -+ } else if (tp->mcfg == CFG_METHOD_30) { -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x808A); -+ ClearAndSetEthPhyBit( tp, -+ 0x14, -+ BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0, -+ 0x0A ); -+ -+ if (tp->HwHasWrRamCodeToMicroP) { -+ mdio_write(tp, 0x1F, 0x0A43); -+ mdio_write(tp, 0x13, 0x8011); -+ SetEthPhyBit(tp, 0x14, BIT_11); -+ mdio_write(tp, 0x1F, 0x0A42); -+ SetEthPhyBit(tp, 0x16, BIT_1); -+ } -+ -+ mdio_write(tp, 0x1F, 0x0A44); -+ SetEthPhyBit( tp, 0x11, BIT_11 ); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ if(tp->RequireAdcBiasPatch) { -+ mdio_write(tp, 0x1F, 0x0BCF); -+ mdio_write(tp, 0x16, tp->AdcBiasPatchIoffset); -+ mdio_write(tp, 0x1F, 0x0000); -+ } -+ -+ { -+ u16 rlen; -+ -+ mdio_write(tp, 0x1F, 0x0BCD); -+ gphy_val = mdio_read( tp, 0x16 ); -+ gphy_val &= 0x000F; -+ -+ if( gphy_val > 3 ) { -+ rlen = gphy_val - 3; -+ } else { -+ rlen = 0; -+ } -+ -+ gphy_val = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12); -+ -+ mdio_write(tp, 0x1F, 0x0BCD); -+ mdio_write(tp, 0x17, gphy_val); -+ mdio_write(tp, 0x1F, 0x0000); -+ } -+ -+ if (aspm) { -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ mdio_write(tp, 0x1F, 0x0A43); -+ SetEthPhyBit( tp, 0x10, BIT_2 ); -+ mdio_write(tp, 0x1F, 0x0000); -+ } -+ } -+ } -+ -+ //EthPhyPPSW -+ if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 || -+ tp->mcfg == CFG_METHOD_24 || tp->mcfg == CFG_METHOD_25 || -+ tp->mcfg == CFG_METHOD_26) { -+ //disable EthPhyPPSW -+ mdio_write(tp, 0x1F, 0x0BCD); -+ mdio_write(tp, 0x14, 0x5065); -+ mdio_write(tp, 0x14, 0xD065); -+ mdio_write(tp, 0x1F, 0x0BC8); -+ mdio_write(tp, 0x11, 0x5655); -+ mdio_write(tp, 0x1F, 0x0BCD); -+ mdio_write(tp, 0x14, 0x1065); -+ mdio_write(tp, 0x14, 0x9065); -+ mdio_write(tp, 0x14, 0x1065); -+ mdio_write(tp, 0x1F, 0x0000); -+ } else if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ //enable EthPhyPPSW -+ mdio_write(tp, 0x1F, 0x0A44); -+ SetEthPhyBit( tp, 0x11, BIT_7 ); -+ mdio_write(tp, 0x1F, 0x0000); -+ } -+ -+ /*ocp phy power saving*/ -+ if (tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 || -+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 || -+ tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ if (aspm) { -+ mdio_write_phy_ocp(tp, 0x0C41, 0x13, 0x0000); -+ mdio_write_phy_ocp(tp, 0x0C41, 0x13, 0x0050); -+ } -+ } -+ -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ -+ if (tp->HwHasWrRamCodeToMicroP == TRUE) { -+ if (eee_enable == 1) -+ rtl8168_enable_EEE(tp); -+ else -+ rtl8168_disable_EEE(tp); -+ } -+} -+ -+static inline void rtl8168_delete_esd_timer(struct net_device *dev, struct timer_list *timer) -+{ -+ del_timer_sync(timer); -+} -+ -+static inline void rtl8168_request_esd_timer(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ struct timer_list *timer = &tp->esd_timer; -+ -+ init_timer(timer); -+ timer->expires = jiffies + RTL8168_ESD_TIMEOUT; -+ timer->data = (unsigned long)(dev); -+ timer->function = rtl8168_esd_timer; -+ add_timer(timer); -+} -+ -+static inline void rtl8168_delete_link_timer(struct net_device *dev, struct timer_list *timer) -+{ -+ del_timer_sync(timer); -+} -+ -+static inline void rtl8168_request_link_timer(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ struct timer_list *timer = &tp->link_timer; -+ -+ init_timer(timer); -+ timer->expires = jiffies + RTL8168_LINK_TIMEOUT; -+ timer->data = (unsigned long)(dev); -+ timer->function = rtl8168_link_timer; -+ add_timer(timer); -+} -+ -+#ifdef CONFIG_NET_POLL_CONTROLLER -+/* -+ * Polling 'interrupt' - used by things like netconsole to send skbs -+ * without having to re-enable interrupts. It's not called while -+ * the interrupt routine is executing. -+ */ -+static void -+rtl8168_netpoll(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ struct pci_dev *pdev = tp->pci_dev; -+ -+ disable_irq(pdev->irq); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+ rtl8168_interrupt(pdev->irq, dev, NULL); -+#else -+ rtl8168_interrupt(pdev->irq, dev); -+#endif -+ enable_irq(pdev->irq); -+} -+#endif -+ -+static void -+rtl8168_get_bios_setting(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_9: -+ case CFG_METHOD_10: -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ tp->bios_setting = RTL_R32(0x8c); -+ break; -+ } -+} -+ -+static void -+rtl8168_set_bios_setting(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_9: -+ case CFG_METHOD_10: -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ RTL_W32(0x8C, tp->bios_setting); -+ break; -+ } -+} -+ -+static void -+rtl8168_init_software_variable(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ struct pci_dev *pdev = tp->pci_dev; -+ -+ rtl8168_get_bios_setting(dev); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ tp->HwSuppDashVer = 1; -+ break; -+ case CFG_METHOD_23: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ tp->HwSuppDashVer = 2; -+ break; -+ default: -+ tp->HwSuppDashVer = 0; -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ tp->HwSuppNowIsOobVer = 1; -+ break; -+ } -+ -+#ifdef ENABLE_REALWOW_SUPPORT -+ get_realwow_hw_version(dev); -+#endif //ENABLE_REALWOW_SUPPORT -+ -+ if (HW_DASH_SUPPORT_DASH(tp) && rtl8168_check_dash(tp)) -+ tp->DASH = 1; -+ else -+ tp->DASH = 0; -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_1: -+ tp->intr_mask = RxDescUnavail | RxFIFOOver | TxDescUnavail | TxOK | RxOK | SWInt; -+ tp->timer_intr_mask = PCSTimeout | RxFIFOOver; -+ break; -+ case CFG_METHOD_2: -+ case CFG_METHOD_3: -+ case CFG_METHOD_4: -+ tp->intr_mask = RxDescUnavail | TxDescUnavail | TxOK | RxOK | SWInt; -+ tp->timer_intr_mask = PCSTimeout; -+ break; -+ default: -+ tp->intr_mask = RxDescUnavail | TxOK | RxOK | SWInt; -+ tp->timer_intr_mask = PCSTimeout; -+ break; -+ } -+ -+#ifdef ENABLE_DASH_SUPPORT -+ if(tp->DASH) { -+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) { -+ tp->timer_intr_mask |= ( ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET); -+ tp->intr_mask |= ( ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET); -+ } else { -+ tp->timer_intr_mask |= ( ISRIMR_DP_DASH_OK | ISRIMR_DP_HOST_OK | ISRIMR_DP_REQSYS_OK ); -+ tp->intr_mask |= ( ISRIMR_DP_DASH_OK | ISRIMR_DP_HOST_OK | ISRIMR_DP_REQSYS_OK ); -+ } -+ } -+#endif -+ -+ tp->max_jumbo_frame_size = rtl_chip_info[tp->chipset].jumbo_frame_sz; -+ -+ if (aspm) { -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ tp->org_pci_offset_99 = rtl8168_csi_fun0_read_byte(tp, 0x99); -+ tp->org_pci_offset_99 &= ~(BIT_5|BIT_6); -+ break; -+ } -+ switch (tp->mcfg) { -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ tp->org_pci_offset_180 = rtl8168_csi_fun0_read_byte(tp, 0x180); -+ break; -+ } -+ } -+ -+ pci_read_config_byte(pdev, 0x80, &tp->org_pci_offset_80); -+ pci_read_config_byte(pdev, 0x81, &tp->org_pci_offset_81); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ if ((tp->features & RTL_FEATURE_MSI) && (tp->org_pci_offset_80 & BIT_1)) -+ tp->use_timer_interrrupt = FALSE; -+ else -+ tp->use_timer_interrrupt = TRUE; -+ break; -+ default: -+ tp->use_timer_interrrupt = TRUE; -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_1: -+ case CFG_METHOD_2: -+ case CFG_METHOD_3: -+ tp->ShortPacketSwChecksum = TRUE; -+ break; -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ tp->ShortPacketSwChecksum = TRUE; -+ tp->UseSwPaddingShortPkt = TRUE; -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_30: { -+ u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0; -+ u16 TmpUshort; -+ -+ mac_ocp_write( tp, 0xDD02, 0x807D); -+ TmpUshort = mac_ocp_read( tp, 0xDD02 ); -+ ioffset_p3 = ( (TmpUshort & BIT_7) >>7 ); -+ ioffset_p3 <<= 3; -+ TmpUshort = mac_ocp_read( tp, 0xDD00 ); -+ -+ ioffset_p3 |= ((TmpUshort & (BIT_15 | BIT_14 | BIT_13))>>13); -+ -+ ioffset_p2 = ((TmpUshort & (BIT_12|BIT_11|BIT_10|BIT_9))>>9); -+ ioffset_p1 = ((TmpUshort & (BIT_8|BIT_7|BIT_6|BIT_5))>>5); -+ -+ ioffset_p0 = ( (TmpUshort & BIT_4) >>4 ); -+ ioffset_p0 <<= 3; -+ ioffset_p0 |= (TmpUshort & (BIT_2| BIT_1 | BIT_0)); -+ -+ if((ioffset_p3 == 0x0F) && (ioffset_p2 == 0x0F) && (ioffset_p1 == 0x0F) && (ioffset_p0 == 0x0F)) { -+ tp->RequireAdcBiasPatch = FALSE; -+ } else { -+ tp->RequireAdcBiasPatch = TRUE; -+ tp->AdcBiasPatchIoffset = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0); -+ } -+ } -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: { -+ u16 rg_saw_cnt; -+ -+ mdio_write(tp, 0x1F, 0x0C42); -+ rg_saw_cnt = mdio_read(tp, 0x13); -+ rg_saw_cnt &= ~(BIT_15|BIT_14); -+ mdio_write(tp, 0x1F, 0x0000); -+ -+ if ( rg_saw_cnt > 0) { -+ tp->SwrCnt1msIni = 16000000/rg_saw_cnt; -+ tp->SwrCnt1msIni &= 0x0FFF; -+ -+ tp->RequireAdjustUpsTxLinkPulseTiming = TRUE; -+ } -+ } -+ break; -+ } -+ -+ if (pdev->subsystem_vendor == 0x144d) { -+ if (pdev->subsystem_device == 0xc098 || -+ pdev->subsystem_device == 0xc0b1 || -+ pdev->subsystem_device == 0xc0b8) -+ hwoptimize |= HW_PATCH_SAMSUNG_LAN_DONGLE; -+ } -+ -+ if (hwoptimize & HW_PATCH_SAMSUNG_LAN_DONGLE) { -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ case CFG_METHOD_30: -+ tp->RequiredSecLanDonglePatch = TRUE; -+ break; -+ } -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_14; -+ break; -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_16; -+ break; -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_18; -+ break; -+ case CFG_METHOD_20: -+ tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_20; -+ break; -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_21; -+ break; -+ case CFG_METHOD_23: -+ case CFG_METHOD_27: -+ tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_23; -+ break; -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_24; -+ break; -+ case CFG_METHOD_26: -+ tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_26; -+ break; -+ case CFG_METHOD_28: -+ tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_28; -+ break; -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_29; -+ break; -+ } -+ -+ if (tp->HwIcVerUnknown) { -+ tp->NotWrRamCodeToMicroP = TRUE; -+ tp->NotWrMcuPatchCode = TRUE; -+ } -+ -+ rtl8168_get_hw_wol(dev); -+ -+ rtl8168_link_option((u8*)&autoneg, (u16*)&speed, (u8*)&duplex); -+ -+ tp->autoneg = autoneg; -+ tp->speed = speed; -+ tp->duplex = duplex; -+} -+ -+static void -+rtl8168_release_board(struct pci_dev *pdev, -+ struct net_device *dev, -+ void __iomem *ioaddr) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ rtl8168_set_bios_setting(dev); -+ rtl8168_rar_set(tp, tp->org_mac_addr); -+ tp->wol_enabled = WOL_DISABLED; -+ -+ if(!tp->DASH) -+ rtl8168_phy_power_down(dev); -+ -+#ifdef ENABLE_DASH_SUPPORT -+ if(tp->DASH) -+ FreeAllocatedDashShareMemory(dev); -+#endif -+ -+ iounmap(ioaddr); -+ pci_release_regions(pdev); -+ pci_disable_device(pdev); -+ free_netdev(dev); -+} -+ -+static int -+rtl8168_get_mac_address(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ int i; -+ -+ -+ if (tp->mcfg == CFG_METHOD_18 || -+ tp->mcfg == CFG_METHOD_19 || -+ tp->mcfg == CFG_METHOD_20 || -+ tp->mcfg == CFG_METHOD_21 || -+ tp->mcfg == CFG_METHOD_22 || -+ tp->mcfg == CFG_METHOD_23 || -+ tp->mcfg == CFG_METHOD_24 || -+ tp->mcfg == CFG_METHOD_25 || -+ tp->mcfg == CFG_METHOD_26 || -+ tp->mcfg == CFG_METHOD_27 || -+ tp->mcfg == CFG_METHOD_28 || -+ tp->mcfg == CFG_METHOD_29 || -+ tp->mcfg == CFG_METHOD_30) { -+ u16 mac_addr[3]; -+ -+ *(u32*)&mac_addr[0] = rtl8168_eri_read(ioaddr, 0xE0, 4, ERIAR_ExGMAC); -+ *(u16*)&mac_addr[2] = rtl8168_eri_read(ioaddr, 0xE4, 2, ERIAR_ExGMAC); -+ -+ if (is_valid_ether_addr((u8*)mac_addr)) -+ rtl8168_rar_set(tp, (uint8_t*)mac_addr); -+ } else { -+ if (tp->eeprom_type != EEPROM_TYPE_NONE) { -+ u16 mac_addr[3]; -+ -+ /* Get MAC address from EEPROM */ -+ if (tp->mcfg == CFG_METHOD_16 || -+ tp->mcfg == CFG_METHOD_17 || -+ tp->mcfg == CFG_METHOD_18 || -+ tp->mcfg == CFG_METHOD_19 || -+ tp->mcfg == CFG_METHOD_20 || -+ tp->mcfg == CFG_METHOD_21 || -+ tp->mcfg == CFG_METHOD_22 || -+ tp->mcfg == CFG_METHOD_23 || -+ tp->mcfg == CFG_METHOD_24 || -+ tp->mcfg == CFG_METHOD_25 || -+ tp->mcfg == CFG_METHOD_26 || -+ tp->mcfg == CFG_METHOD_27 || -+ tp->mcfg == CFG_METHOD_28 || -+ tp->mcfg == CFG_METHOD_29 || -+ tp->mcfg == CFG_METHOD_30) { -+ mac_addr[0] = rtl_eeprom_read_sc(tp, 1); -+ mac_addr[1] = rtl_eeprom_read_sc(tp, 2); -+ mac_addr[2] = rtl_eeprom_read_sc(tp, 3); -+ } else { -+ mac_addr[0] = rtl_eeprom_read_sc(tp, 7); -+ mac_addr[1] = rtl_eeprom_read_sc(tp, 8); -+ mac_addr[2] = rtl_eeprom_read_sc(tp, 9); -+ } -+ -+ if (is_valid_ether_addr((u8*)mac_addr)) -+ rtl8168_rar_set(tp, (uint8_t*)mac_addr); -+ } -+ } -+ -+ for (i = 0; i < MAC_ADDR_LEN; i++) { -+ dev->dev_addr[i] = RTL_R8(MAC0 + i); -+ tp->org_mac_addr[i] = dev->dev_addr[i]; /* keep the original MAC address */ -+ } -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) -+ memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); -+#endif -+// memcpy(dev->dev_addr, dev->dev_addr, dev->addr_len); -+ -+ return 0; -+} -+ -+/** -+ * rtl8168_set_mac_address - Change the Ethernet Address of the NIC -+ * @dev: network interface device structure -+ * @p: pointer to an address structure -+ * -+ * Return 0 on success, negative on failure -+ **/ -+static int -+rtl8168_set_mac_address(struct net_device *dev, -+ void *p) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ struct sockaddr *addr = p; -+ unsigned long flags; -+ -+ if (!is_valid_ether_addr(addr->sa_data)) -+ return -EADDRNOTAVAIL; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); -+ -+ rtl8168_rar_set(tp, dev->dev_addr); -+ -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ return 0; -+} -+ -+/****************************************************************************** -+ * rtl8168_rar_set - Puts an ethernet address into a receive address register. -+ * -+ * tp - The private data structure for driver -+ * addr - Address to put into receive address register -+ *****************************************************************************/ -+void -+rtl8168_rar_set(struct rtl8168_private *tp, -+ uint8_t *addr) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ uint32_t rar_low = 0; -+ uint32_t rar_high = 0; -+ -+ rar_low = ((uint32_t) addr[0] | -+ ((uint32_t) addr[1] << 8) | -+ ((uint32_t) addr[2] << 16) | -+ ((uint32_t) addr[3] << 24)); -+ -+ rar_high = ((uint32_t) addr[4] | -+ ((uint32_t) addr[5] << 8)); -+ -+ RTL_W8(Cfg9346, Cfg9346_Unlock); -+ RTL_W32(MAC0, rar_low); -+ RTL_W32(MAC4, rar_high); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ RTL_W32(SecMAC0, rar_low); -+ RTL_W16(SecMAC4, (uint16_t)rar_high); -+ break; -+ } -+ -+ if (tp->mcfg == CFG_METHOD_17) { -+ rtl8168_eri_write(ioaddr, 0xf0, 4, rar_low << 16, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xf4, 4, rar_low >> 16 | rar_high << 16, ERIAR_ExGMAC); -+ } -+ -+ RTL_W8(Cfg9346, Cfg9346_Lock); -+} -+ -+#ifdef ETHTOOL_OPS_COMPAT -+static int ethtool_get_settings(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_cmd cmd = { ETHTOOL_GSET }; -+ int err; -+ -+ if (!ethtool_ops->get_settings) -+ return -EOPNOTSUPP; -+ -+ err = ethtool_ops->get_settings(dev, &cmd); -+ if (err < 0) -+ return err; -+ -+ if (copy_to_user(useraddr, &cmd, sizeof(cmd))) -+ return -EFAULT; -+ return 0; -+} -+ -+static int ethtool_set_settings(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_cmd cmd; -+ -+ if (!ethtool_ops->set_settings) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&cmd, useraddr, sizeof(cmd))) -+ return -EFAULT; -+ -+ return ethtool_ops->set_settings(dev, &cmd); -+} -+ -+static int ethtool_get_drvinfo(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_drvinfo info; -+ struct ethtool_ops *ops = ethtool_ops; -+ -+ if (!ops->get_drvinfo) -+ return -EOPNOTSUPP; -+ -+ memset(&info, 0, sizeof(info)); -+ info.cmd = ETHTOOL_GDRVINFO; -+ ops->get_drvinfo(dev, &info); -+ -+ if (ops->self_test_count) -+ info.testinfo_len = ops->self_test_count(dev); -+ if (ops->get_stats_count) -+ info.n_stats = ops->get_stats_count(dev); -+ if (ops->get_regs_len) -+ info.regdump_len = ops->get_regs_len(dev); -+ if (ops->get_eeprom_len) -+ info.eedump_len = ops->get_eeprom_len(dev); -+ -+ if (copy_to_user(useraddr, &info, sizeof(info))) -+ return -EFAULT; -+ return 0; -+} -+ -+static int ethtool_get_regs(struct net_device *dev, char *useraddr) -+{ -+ struct ethtool_regs regs; -+ struct ethtool_ops *ops = ethtool_ops; -+ void *regbuf; -+ int reglen, ret; -+ -+ if (!ops->get_regs || !ops->get_regs_len) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(®s, useraddr, sizeof(regs))) -+ return -EFAULT; -+ -+ reglen = ops->get_regs_len(dev); -+ if (regs.len > reglen) -+ regs.len = reglen; -+ -+ regbuf = kmalloc(reglen, GFP_USER); -+ if (!regbuf) -+ return -ENOMEM; -+ -+ ops->get_regs(dev, ®s, regbuf); -+ -+ ret = -EFAULT; -+ if (copy_to_user(useraddr, ®s, sizeof(regs))) -+ goto out; -+ useraddr += offsetof(struct ethtool_regs, data); -+ if (copy_to_user(useraddr, regbuf, reglen)) -+ goto out; -+ ret = 0; -+ -+out: -+ kfree(regbuf); -+ return ret; -+} -+ -+static int ethtool_get_wol(struct net_device *dev, char *useraddr) -+{ -+ struct ethtool_wolinfo wol = { ETHTOOL_GWOL }; -+ -+ if (!ethtool_ops->get_wol) -+ return -EOPNOTSUPP; -+ -+ ethtool_ops->get_wol(dev, &wol); -+ -+ if (copy_to_user(useraddr, &wol, sizeof(wol))) -+ return -EFAULT; -+ return 0; -+} -+ -+static int ethtool_set_wol(struct net_device *dev, char *useraddr) -+{ -+ struct ethtool_wolinfo wol; -+ -+ if (!ethtool_ops->set_wol) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&wol, useraddr, sizeof(wol))) -+ return -EFAULT; -+ -+ return ethtool_ops->set_wol(dev, &wol); -+} -+ -+static int ethtool_get_msglevel(struct net_device *dev, char *useraddr) -+{ -+ struct ethtool_value edata = { ETHTOOL_GMSGLVL }; -+ -+ if (!ethtool_ops->get_msglevel) -+ return -EOPNOTSUPP; -+ -+ edata.data = ethtool_ops->get_msglevel(dev); -+ -+ if (copy_to_user(useraddr, &edata, sizeof(edata))) -+ return -EFAULT; -+ return 0; -+} -+ -+static int ethtool_set_msglevel(struct net_device *dev, char *useraddr) -+{ -+ struct ethtool_value edata; -+ -+ if (!ethtool_ops->set_msglevel) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&edata, useraddr, sizeof(edata))) -+ return -EFAULT; -+ -+ ethtool_ops->set_msglevel(dev, edata.data); -+ return 0; -+} -+ -+static int ethtool_nway_reset(struct net_device *dev) -+{ -+ if (!ethtool_ops->nway_reset) -+ return -EOPNOTSUPP; -+ -+ return ethtool_ops->nway_reset(dev); -+} -+ -+static int ethtool_get_link(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_value edata = { ETHTOOL_GLINK }; -+ -+ if (!ethtool_ops->get_link) -+ return -EOPNOTSUPP; -+ -+ edata.data = ethtool_ops->get_link(dev); -+ -+ if (copy_to_user(useraddr, &edata, sizeof(edata))) -+ return -EFAULT; -+ return 0; -+} -+ -+static int ethtool_get_eeprom(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_eeprom eeprom; -+ struct ethtool_ops *ops = ethtool_ops; -+ u8 *data; -+ int ret; -+ -+ if (!ops->get_eeprom || !ops->get_eeprom_len) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&eeprom, useraddr, sizeof(eeprom))) -+ return -EFAULT; -+ -+ /* Check for wrap and zero */ -+ if (eeprom.offset + eeprom.len <= eeprom.offset) -+ return -EINVAL; -+ -+ /* Check for exceeding total eeprom len */ -+ if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev)) -+ return -EINVAL; -+ -+ data = kmalloc(eeprom.len, GFP_USER); -+ if (!data) -+ return -ENOMEM; -+ -+ ret = -EFAULT; -+ if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len)) -+ goto out; -+ -+ ret = ops->get_eeprom(dev, &eeprom, data); -+ if (ret) -+ goto out; -+ -+ ret = -EFAULT; -+ if (copy_to_user(useraddr, &eeprom, sizeof(eeprom))) -+ goto out; -+ if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len)) -+ goto out; -+ ret = 0; -+ -+out: -+ kfree(data); -+ return ret; -+} -+ -+static int ethtool_set_eeprom(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_eeprom eeprom; -+ struct ethtool_ops *ops = ethtool_ops; -+ u8 *data; -+ int ret; -+ -+ if (!ops->set_eeprom || !ops->get_eeprom_len) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&eeprom, useraddr, sizeof(eeprom))) -+ return -EFAULT; -+ -+ /* Check for wrap and zero */ -+ if (eeprom.offset + eeprom.len <= eeprom.offset) -+ return -EINVAL; -+ -+ /* Check for exceeding total eeprom len */ -+ if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev)) -+ return -EINVAL; -+ -+ data = kmalloc(eeprom.len, GFP_USER); -+ if (!data) -+ return -ENOMEM; -+ -+ ret = -EFAULT; -+ if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len)) -+ goto out; -+ -+ ret = ops->set_eeprom(dev, &eeprom, data); -+ if (ret) -+ goto out; -+ -+ if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len)) -+ ret = -EFAULT; -+ -+out: -+ kfree(data); -+ return ret; -+} -+ -+static int ethtool_get_coalesce(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_coalesce coalesce = { ETHTOOL_GCOALESCE }; -+ -+ if (!ethtool_ops->get_coalesce) -+ return -EOPNOTSUPP; -+ -+ ethtool_ops->get_coalesce(dev, &coalesce); -+ -+ if (copy_to_user(useraddr, &coalesce, sizeof(coalesce))) -+ return -EFAULT; -+ return 0; -+} -+ -+static int ethtool_set_coalesce(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_coalesce coalesce; -+ -+ if (!ethtool_ops->get_coalesce) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&coalesce, useraddr, sizeof(coalesce))) -+ return -EFAULT; -+ -+ return ethtool_ops->set_coalesce(dev, &coalesce); -+} -+ -+static int ethtool_get_ringparam(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_ringparam ringparam = { ETHTOOL_GRINGPARAM }; -+ -+ if (!ethtool_ops->get_ringparam) -+ return -EOPNOTSUPP; -+ -+ ethtool_ops->get_ringparam(dev, &ringparam); -+ -+ if (copy_to_user(useraddr, &ringparam, sizeof(ringparam))) -+ return -EFAULT; -+ return 0; -+} -+ -+static int ethtool_set_ringparam(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_ringparam ringparam; -+ -+ if (!ethtool_ops->get_ringparam) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&ringparam, useraddr, sizeof(ringparam))) -+ return -EFAULT; -+ -+ return ethtool_ops->set_ringparam(dev, &ringparam); -+} -+ -+static int ethtool_get_pauseparam(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_pauseparam pauseparam = { ETHTOOL_GPAUSEPARAM }; -+ -+ if (!ethtool_ops->get_pauseparam) -+ return -EOPNOTSUPP; -+ -+ ethtool_ops->get_pauseparam(dev, &pauseparam); -+ -+ if (copy_to_user(useraddr, &pauseparam, sizeof(pauseparam))) -+ return -EFAULT; -+ return 0; -+} -+ -+static int ethtool_set_pauseparam(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_pauseparam pauseparam; -+ -+ if (!ethtool_ops->get_pauseparam) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&pauseparam, useraddr, sizeof(pauseparam))) -+ return -EFAULT; -+ -+ return ethtool_ops->set_pauseparam(dev, &pauseparam); -+} -+ -+static int ethtool_get_rx_csum(struct net_device *dev, char *useraddr) -+{ -+ struct ethtool_value edata = { ETHTOOL_GRXCSUM }; -+ -+ if (!ethtool_ops->get_rx_csum) -+ return -EOPNOTSUPP; -+ -+ edata.data = ethtool_ops->get_rx_csum(dev); -+ -+ if (copy_to_user(useraddr, &edata, sizeof(edata))) -+ return -EFAULT; -+ return 0; -+} -+ -+static int ethtool_set_rx_csum(struct net_device *dev, char *useraddr) -+{ -+ struct ethtool_value edata; -+ -+ if (!ethtool_ops->set_rx_csum) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&edata, useraddr, sizeof(edata))) -+ return -EFAULT; -+ -+ ethtool_ops->set_rx_csum(dev, edata.data); -+ return 0; -+} -+ -+static int ethtool_get_tx_csum(struct net_device *dev, char *useraddr) -+{ -+ struct ethtool_value edata = { ETHTOOL_GTXCSUM }; -+ -+ if (!ethtool_ops->get_tx_csum) -+ return -EOPNOTSUPP; -+ -+ edata.data = ethtool_ops->get_tx_csum(dev); -+ -+ if (copy_to_user(useraddr, &edata, sizeof(edata))) -+ return -EFAULT; -+ return 0; -+} -+ -+static int ethtool_set_tx_csum(struct net_device *dev, char *useraddr) -+{ -+ struct ethtool_value edata; -+ -+ if (!ethtool_ops->set_tx_csum) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&edata, useraddr, sizeof(edata))) -+ return -EFAULT; -+ -+ return ethtool_ops->set_tx_csum(dev, edata.data); -+} -+ -+static int ethtool_get_sg(struct net_device *dev, char *useraddr) -+{ -+ struct ethtool_value edata = { ETHTOOL_GSG }; -+ -+ if (!ethtool_ops->get_sg) -+ return -EOPNOTSUPP; -+ -+ edata.data = ethtool_ops->get_sg(dev); -+ -+ if (copy_to_user(useraddr, &edata, sizeof(edata))) -+ return -EFAULT; -+ return 0; -+} -+ -+static int ethtool_set_sg(struct net_device *dev, char *useraddr) -+{ -+ struct ethtool_value edata; -+ -+ if (!ethtool_ops->set_sg) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&edata, useraddr, sizeof(edata))) -+ return -EFAULT; -+ -+ return ethtool_ops->set_sg(dev, edata.data); -+} -+ -+static int ethtool_get_tso(struct net_device *dev, char *useraddr) -+{ -+ struct ethtool_value edata = { ETHTOOL_GTSO }; -+ -+ if (!ethtool_ops->get_tso) -+ return -EOPNOTSUPP; -+ -+ edata.data = ethtool_ops->get_tso(dev); -+ -+ if (copy_to_user(useraddr, &edata, sizeof(edata))) -+ return -EFAULT; -+ return 0; -+} -+ -+static int ethtool_set_tso(struct net_device *dev, char *useraddr) -+{ -+ struct ethtool_value edata; -+ -+ if (!ethtool_ops->set_tso) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&edata, useraddr, sizeof(edata))) -+ return -EFAULT; -+ -+ return ethtool_ops->set_tso(dev, edata.data); -+} -+ -+static int ethtool_self_test(struct net_device *dev, char *useraddr) -+{ -+ struct ethtool_test test; -+ struct ethtool_ops *ops = ethtool_ops; -+ u64 *data; -+ int ret; -+ -+ if (!ops->self_test || !ops->self_test_count) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&test, useraddr, sizeof(test))) -+ return -EFAULT; -+ -+ test.len = ops->self_test_count(dev); -+ data = kmalloc(test.len * sizeof(u64), GFP_USER); -+ if (!data) -+ return -ENOMEM; -+ -+ ops->self_test(dev, &test, data); -+ -+ ret = -EFAULT; -+ if (copy_to_user(useraddr, &test, sizeof(test))) -+ goto out; -+ useraddr += sizeof(test); -+ if (copy_to_user(useraddr, data, test.len * sizeof(u64))) -+ goto out; -+ ret = 0; -+ -+out: -+ kfree(data); -+ return ret; -+} -+ -+static int ethtool_get_strings(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_gstrings gstrings; -+ struct ethtool_ops *ops = ethtool_ops; -+ u8 *data; -+ int ret; -+ -+ if (!ops->get_strings) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&gstrings, useraddr, sizeof(gstrings))) -+ return -EFAULT; -+ -+ switch (gstrings.string_set) { -+ case ETH_SS_TEST: -+ if (!ops->self_test_count) -+ return -EOPNOTSUPP; -+ gstrings.len = ops->self_test_count(dev); -+ break; -+ case ETH_SS_STATS: -+ if (!ops->get_stats_count) -+ return -EOPNOTSUPP; -+ gstrings.len = ops->get_stats_count(dev); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ data = kmalloc(gstrings.len * ETH_GSTRING_LEN, GFP_USER); -+ if (!data) -+ return -ENOMEM; -+ -+ ops->get_strings(dev, gstrings.string_set, data); -+ -+ ret = -EFAULT; -+ if (copy_to_user(useraddr, &gstrings, sizeof(gstrings))) -+ goto out; -+ useraddr += sizeof(gstrings); -+ if (copy_to_user(useraddr, data, gstrings.len * ETH_GSTRING_LEN)) -+ goto out; -+ ret = 0; -+ -+out: -+ kfree(data); -+ return ret; -+} -+ -+static int ethtool_phys_id(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_value id; -+ -+ if (!ethtool_ops->phys_id) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&id, useraddr, sizeof(id))) -+ return -EFAULT; -+ -+ return ethtool_ops->phys_id(dev, id.data); -+} -+ -+static int ethtool_get_stats(struct net_device *dev, void *useraddr) -+{ -+ struct ethtool_stats stats; -+ struct ethtool_ops *ops = ethtool_ops; -+ u64 *data; -+ int ret; -+ -+ if (!ops->get_ethtool_stats || !ops->get_stats_count) -+ return -EOPNOTSUPP; -+ -+ if (copy_from_user(&stats, useraddr, sizeof(stats))) -+ return -EFAULT; -+ -+ stats.n_stats = ops->get_stats_count(dev); -+ data = kmalloc(stats.n_stats * sizeof(u64), GFP_USER); -+ if (!data) -+ return -ENOMEM; -+ -+ ops->get_ethtool_stats(dev, &stats, data); -+ -+ ret = -EFAULT; -+ if (copy_to_user(useraddr, &stats, sizeof(stats))) -+ goto out; -+ useraddr += sizeof(stats); -+ if (copy_to_user(useraddr, data, stats.n_stats * sizeof(u64))) -+ goto out; -+ ret = 0; -+ -+out: -+ kfree(data); -+ return ret; -+} -+ -+static int ethtool_ioctl(struct ifreq *ifr) -+{ -+ struct net_device *dev = __dev_get_by_name(ifr->ifr_name); -+ void *useraddr = (void *) ifr->ifr_data; -+ u32 ethcmd; -+ -+ /* -+ * XXX: This can be pushed down into the ethtool_* handlers that -+ * need it. Keep existing behaviour for the moment. -+ */ -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ if (!dev || !netif_device_present(dev)) -+ return -ENODEV; -+ -+ if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd))) -+ return -EFAULT; -+ -+ switch (ethcmd) { -+ case ETHTOOL_GSET: -+ return ethtool_get_settings(dev, useraddr); -+ case ETHTOOL_SSET: -+ return ethtool_set_settings(dev, useraddr); -+ case ETHTOOL_GDRVINFO: -+ return ethtool_get_drvinfo(dev, useraddr); -+ case ETHTOOL_GREGS: -+ return ethtool_get_regs(dev, useraddr); -+ case ETHTOOL_GWOL: -+ return ethtool_get_wol(dev, useraddr); -+ case ETHTOOL_SWOL: -+ return ethtool_set_wol(dev, useraddr); -+ case ETHTOOL_GMSGLVL: -+ return ethtool_get_msglevel(dev, useraddr); -+ case ETHTOOL_SMSGLVL: -+ return ethtool_set_msglevel(dev, useraddr); -+ case ETHTOOL_NWAY_RST: -+ return ethtool_nway_reset(dev); -+ case ETHTOOL_GLINK: -+ return ethtool_get_link(dev, useraddr); -+ case ETHTOOL_GEEPROM: -+ return ethtool_get_eeprom(dev, useraddr); -+ case ETHTOOL_SEEPROM: -+ return ethtool_set_eeprom(dev, useraddr); -+ case ETHTOOL_GCOALESCE: -+ return ethtool_get_coalesce(dev, useraddr); -+ case ETHTOOL_SCOALESCE: -+ return ethtool_set_coalesce(dev, useraddr); -+ case ETHTOOL_GRINGPARAM: -+ return ethtool_get_ringparam(dev, useraddr); -+ case ETHTOOL_SRINGPARAM: -+ return ethtool_set_ringparam(dev, useraddr); -+ case ETHTOOL_GPAUSEPARAM: -+ return ethtool_get_pauseparam(dev, useraddr); -+ case ETHTOOL_SPAUSEPARAM: -+ return ethtool_set_pauseparam(dev, useraddr); -+ case ETHTOOL_GRXCSUM: -+ return ethtool_get_rx_csum(dev, useraddr); -+ case ETHTOOL_SRXCSUM: -+ return ethtool_set_rx_csum(dev, useraddr); -+ case ETHTOOL_GTXCSUM: -+ return ethtool_get_tx_csum(dev, useraddr); -+ case ETHTOOL_STXCSUM: -+ return ethtool_set_tx_csum(dev, useraddr); -+ case ETHTOOL_GSG: -+ return ethtool_get_sg(dev, useraddr); -+ case ETHTOOL_SSG: -+ return ethtool_set_sg(dev, useraddr); -+ case ETHTOOL_GTSO: -+ return ethtool_get_tso(dev, useraddr); -+ case ETHTOOL_STSO: -+ return ethtool_set_tso(dev, useraddr); -+ case ETHTOOL_TEST: -+ return ethtool_self_test(dev, useraddr); -+ case ETHTOOL_GSTRINGS: -+ return ethtool_get_strings(dev, useraddr); -+ case ETHTOOL_PHYS_ID: -+ return ethtool_phys_id(dev, useraddr); -+ case ETHTOOL_GSTATS: -+ return ethtool_get_stats(dev, useraddr); -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ return -EOPNOTSUPP; -+} -+#endif //ETHTOOL_OPS_COMPAT -+ -+static int -+rtl8168_do_ioctl(struct net_device *dev, -+ struct ifreq *ifr, -+ int cmd) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ struct mii_ioctl_data *data = if_mii(ifr); -+ int ret; -+ unsigned long flags; -+ -+ ret = 0; -+ switch (cmd) { -+ case SIOCGMIIPHY: -+ data->phy_id = 32; /* Internal PHY */ -+ break; -+ -+ case SIOCGMIIREG: -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0000); -+ data->val_out = mdio_read(tp, data->reg_num); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ case SIOCSMIIREG: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0000); -+ mdio_write(tp, data->reg_num, data->val_in); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+#ifdef ETHTOOL_OPS_COMPAT -+ case SIOCETHTOOL: -+ ret = ethtool_ioctl(ifr); -+ break; -+#endif -+ case SIOCDEVPRIVATE_RTLASF: -+ if (!netif_running(dev)) { -+ ret = -ENODEV; -+ break; -+ } -+ -+ ret = rtl8168_asf_ioctl(dev, ifr); -+ break; -+ -+#ifdef ENABLE_DASH_SUPPORT -+ case SIOCDEVPRIVATE_RTLDASH: -+ if (!netif_running(dev)) { -+ ret = -ENODEV; -+ break; -+ } -+ -+ ret = rtl8168_dash_ioctl(dev, ifr); -+ break; -+#endif -+ -+#ifdef ENABLE_REALWOW_SUPPORT -+ case SIOCDEVPRIVATE_RTLREALWOW: -+ if (!netif_running(dev)) { -+ ret = -ENODEV; -+ break; -+ } -+ -+ ret = rtl8168_realwow_ioctl(dev, ifr); -+ break; -+#endif -+ -+ case SIOCRTLTOOL: -+ ret = rtltool_ioctl(tp, ifr); -+ break; -+ -+ default: -+ ret = -EOPNOTSUPP; -+ break; -+ } -+ -+ return ret; -+} -+ -+static void -+rtl8168_phy_power_up(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 csi_tmp; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0000); -+ switch (tp->mcfg) { -+ case CFG_METHOD_1: -+ case CFG_METHOD_2: -+ case CFG_METHOD_3: -+ case CFG_METHOD_4: -+ case CFG_METHOD_5: -+ case CFG_METHOD_6: -+ case CFG_METHOD_7: -+ case CFG_METHOD_8: -+ case CFG_METHOD_9: -+ case CFG_METHOD_10: -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ mdio_write(tp, 0x0E, 0x0000); -+ break; -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1AB, 1, ERIAR_ExGMAC); -+ csi_tmp |= ( BIT_2 | BIT_3 | BIT_4 | BIT_5 | BIT_6 | BIT_7 ); -+ rtl8168_eri_write(ioaddr, 0x1AB, 1, csi_tmp, ERIAR_ExGMAC); -+ break; -+ default: -+ break; -+ } -+ mdio_write(tp, MII_BMCR, BMCR_ANENABLE); -+ -+ //wait mdc/mdio ready -+ switch (tp->mcfg) { -+ case CFG_METHOD_23: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ mdelay(10); -+ break; -+ } -+ -+ //wait ups resume (phy state 3) -+ switch (tp->mcfg) { -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ rtl8168_wait_phy_ups_resume(dev, 3); -+ break; -+ }; -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+} -+ -+static void -+rtl8168_phy_power_down(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 csi_tmp; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0000); -+ switch (tp->mcfg) { -+ case CFG_METHOD_1: -+ case CFG_METHOD_2: -+ case CFG_METHOD_3: -+ case CFG_METHOD_4: -+ case CFG_METHOD_5: -+ case CFG_METHOD_6: -+ case CFG_METHOD_7: -+ case CFG_METHOD_8: -+ case CFG_METHOD_9: -+ case CFG_METHOD_10: -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ mdio_write(tp, 0x0E, 0x0200); -+ mdio_write(tp, MII_BMCR, BMCR_PDOWN); -+ break; -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ mdio_write(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); -+ break; -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ mdio_write(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1AB, 1, ERIAR_ExGMAC); -+ csi_tmp &= ~( BIT_2 | BIT_3 | BIT_4 | BIT_5 | BIT_6 | BIT_7 ); -+ rtl8168_eri_write(ioaddr, 0x1AB, 1, csi_tmp, ERIAR_ExGMAC); -+ -+ RTL_W8(0xD0, RTL_R8(0xD0) & ~BIT_6); -+ break; -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ mdio_write(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1AB, 1, ERIAR_ExGMAC); -+ csi_tmp &= ~( BIT_2 | BIT_3 | BIT_4 | BIT_5 | BIT_6 | BIT_7 ); -+ rtl8168_eri_write(ioaddr, 0x1AB, 1, csi_tmp, ERIAR_ExGMAC); -+ break; -+ default: -+ mdio_write(tp, MII_BMCR, BMCR_PDOWN); -+ break; -+ } -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+} -+ -+static int __devinit -+rtl8168_init_board(struct pci_dev *pdev, -+ struct net_device **dev_out, -+ void __iomem **ioaddr_out) -+{ -+ void __iomem *ioaddr; -+ struct net_device *dev; -+ struct rtl8168_private *tp; -+ int rc = -ENOMEM, i, pm_cap; -+ -+ assert(ioaddr_out != NULL); -+ -+ /* dev zeroed in alloc_etherdev */ -+ dev = alloc_etherdev(sizeof (*tp)); -+ if (dev == NULL) { -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ if (netif_msg_drv(&debug)) -+ dev_err(&pdev->dev, "unable to alloc new ethernet\n"); -+#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ goto err_out; -+ } -+ -+ SET_MODULE_OWNER(dev); -+ SET_NETDEV_DEV(dev, &pdev->dev); -+ tp = netdev_priv(dev); -+ tp->dev = dev; -+ tp->msg_enable = netif_msg_init(debug.msg_enable, R8168_MSG_DEFAULT); -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) -+ if (!aspm) -+ pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | -+ PCIE_LINK_STATE_CLKPM); -+#endif -+ -+ /* enable device (incl. PCI PM wakeup and hotplug setup) */ -+ rc = pci_enable_device(pdev); -+ if (rc < 0) { -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ if (netif_msg_probe(tp)) -+ dev_err(&pdev->dev, "enable failure\n"); -+#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ goto err_out_free_dev; -+ } -+ -+ rc = pci_set_mwi(pdev); -+ if (rc < 0) -+ goto err_out_disable; -+ -+ /* save power state before pci_enable_device overwrites it */ -+ pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); -+ if (pm_cap) { -+ u16 pwr_command; -+ -+ pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command); -+ } else { -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ if (netif_msg_probe(tp)) { -+ dev_err(&pdev->dev, "PowerManagement capability not found.\n"); -+ } -+#else -+ printk("PowerManagement capability not found.\n"); -+#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ -+ } -+ -+ /* make sure PCI base addr 1 is MMIO */ -+ if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ if (netif_msg_probe(tp)) -+ dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n"); -+#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ rc = -ENODEV; -+ goto err_out_mwi; -+ } -+ /* check for weird/broken PCI region reporting */ -+ if (pci_resource_len(pdev, 2) < R8168_REGS_SIZE) { -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ if (netif_msg_probe(tp)) -+ dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); -+#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ rc = -ENODEV; -+ goto err_out_mwi; -+ } -+ -+ rc = pci_request_regions(pdev, MODULENAME); -+ if (rc < 0) { -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ if (netif_msg_probe(tp)) -+ dev_err(&pdev->dev, "could not request regions.\n"); -+#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ goto err_out_mwi; -+ } -+ -+ if ((sizeof(dma_addr_t) > 4) && -+ !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { -+ dev->features |= NETIF_F_HIGHDMA; -+ } else { -+ rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); -+ if (rc < 0) { -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ if (netif_msg_probe(tp)) -+ dev_err(&pdev->dev, "DMA configuration failed.\n"); -+#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ goto err_out_free_res; -+ } -+ } -+ -+ pci_set_master(pdev); -+ -+ /* ioremap MMIO region */ -+ ioaddr = ioremap(pci_resource_start(pdev, 2), R8168_REGS_SIZE); -+ if (ioaddr == NULL) { -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ if (netif_msg_probe(tp)) -+ dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); -+#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ rc = -EIO; -+ goto err_out_free_res; -+ } -+ -+ /* Identify chip attached to board */ -+ rtl8168_get_mac_version(tp, ioaddr); -+ -+ rtl8168_print_mac_version(tp); -+ -+ for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) { -+ if (tp->mcfg == rtl_chip_info[i].mcfg) -+ break; -+ } -+ -+ if (i < 0) { -+ /* Unknown chip: assume array element #0, original RTL-8168 */ -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ if (netif_msg_probe(tp)) -+ dev_printk(KERN_DEBUG, &pdev->dev, "unknown chip version, assuming %s\n", rtl_chip_info[0].name); -+#else -+ printk("Realtek unknown chip version, assuming %s\n", rtl_chip_info[0].name); -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ i++; -+ } -+ -+ tp->chipset = i; -+ -+ *ioaddr_out = ioaddr; -+ *dev_out = dev; -+out: -+ return rc; -+ -+err_out_free_res: -+ pci_release_regions(pdev); -+ -+err_out_mwi: -+ pci_clear_mwi(pdev); -+ -+err_out_disable: -+ pci_disable_device(pdev); -+ -+err_out_free_dev: -+ free_netdev(dev); -+err_out: -+ *ioaddr_out = NULL; -+ *dev_out = NULL; -+ goto out; -+} -+ -+#define PCI_DEVICE_SERIAL_NUMBER (0x0164) -+ -+static void -+rtl8168_esd_timer(unsigned long __opaque) -+{ -+ struct net_device *dev = (struct net_device *)__opaque; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ struct pci_dev *pdev = tp->pci_dev; -+ struct timer_list *timer = &tp->esd_timer; -+ unsigned long timeout = RTL8168_ESD_TIMEOUT; -+ unsigned long flags; -+ u8 cmd; -+ u16 io_base_l; -+ u16 mem_base_l; -+ u16 mem_base_h; -+ u8 ilr; -+ u16 resv_0x1c_h; -+ u16 resv_0x1c_l; -+ u16 resv_0x20_l; -+ u16 resv_0x20_h; -+ u16 resv_0x24_l; -+ u16 resv_0x24_h; -+ u16 resv_0x2c_h; -+ u16 resv_0x2c_l; -+ u32 pci_sn_l; -+ u32 pci_sn_h; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ tp->esd_flag = 0; -+ -+ pci_read_config_byte(pdev, PCI_COMMAND, &cmd); -+ if (cmd != tp->pci_cfg_space.cmd) { -+ pci_write_config_byte(pdev, PCI_COMMAND, tp->pci_cfg_space.cmd); -+ tp->esd_flag |= BIT_0; -+ } -+ -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_0, &io_base_l); -+ if (io_base_l != tp->pci_cfg_space.io_base_l) { -+ pci_write_config_word(pdev, PCI_BASE_ADDRESS_0, tp->pci_cfg_space.io_base_l); -+ tp->esd_flag |= BIT_1; -+ } -+ -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_2, &mem_base_l); -+ if (mem_base_l != tp->pci_cfg_space.mem_base_l) { -+ pci_write_config_word(pdev, PCI_BASE_ADDRESS_2, tp->pci_cfg_space.mem_base_l); -+ tp->esd_flag |= BIT_2; -+ } -+ -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_2 + 2, &mem_base_h); -+ if (mem_base_h!= tp->pci_cfg_space.mem_base_h) { -+ pci_write_config_word(pdev, PCI_BASE_ADDRESS_2 + 2, tp->pci_cfg_space.mem_base_h); -+ tp->esd_flag |= BIT_3; -+ } -+ -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_3, &resv_0x1c_l); -+ if (resv_0x1c_l != tp->pci_cfg_space.resv_0x1c_l) { -+ pci_write_config_word(pdev, PCI_BASE_ADDRESS_3, tp->pci_cfg_space.resv_0x1c_l); -+ tp->esd_flag |= BIT_4; -+ } -+ -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_3 + 2, &resv_0x1c_h); -+ if (resv_0x1c_h != tp->pci_cfg_space.resv_0x1c_h) { -+ pci_write_config_word(pdev, PCI_BASE_ADDRESS_3 + 2, tp->pci_cfg_space.resv_0x1c_h); -+ tp->esd_flag |= BIT_5; -+ } -+ -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_4, &resv_0x20_l); -+ if (resv_0x20_l != tp->pci_cfg_space.resv_0x20_l) { -+ pci_write_config_word(pdev, PCI_BASE_ADDRESS_4, tp->pci_cfg_space.resv_0x20_l); -+ tp->esd_flag |= BIT_6; -+ } -+ -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_4 + 2, &resv_0x20_h); -+ if (resv_0x20_h != tp->pci_cfg_space.resv_0x20_h) { -+ pci_write_config_word(pdev, PCI_BASE_ADDRESS_4 + 2, tp->pci_cfg_space.resv_0x20_h); -+ tp->esd_flag |= BIT_7; -+ } -+ -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_5, &resv_0x24_l); -+ if (resv_0x24_l != tp->pci_cfg_space.resv_0x24_l) { -+ pci_write_config_word(pdev, PCI_BASE_ADDRESS_5, tp->pci_cfg_space.resv_0x24_l); -+ tp->esd_flag |= BIT_8; -+ } -+ -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_5 + 2, &resv_0x24_h); -+ if (resv_0x24_h != tp->pci_cfg_space.resv_0x24_h) { -+ pci_write_config_word(pdev, PCI_BASE_ADDRESS_5 + 2, tp->pci_cfg_space.resv_0x24_h); -+ tp->esd_flag |= BIT_9; -+ } -+ -+ pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &ilr); -+ if (ilr != tp->pci_cfg_space.ilr) { -+ pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, tp->pci_cfg_space.ilr); -+ tp->esd_flag |= BIT_10; -+ } -+ -+ pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &resv_0x2c_l); -+ if (resv_0x2c_l != tp->pci_cfg_space.resv_0x2c_l) { -+ pci_write_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, tp->pci_cfg_space.resv_0x2c_l); -+ tp->esd_flag |= BIT_11; -+ } -+ -+ pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID + 2, &resv_0x2c_h); -+ if (resv_0x2c_h != tp->pci_cfg_space.resv_0x2c_h) { -+ pci_write_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID + 2, tp->pci_cfg_space.resv_0x2c_h); -+ tp->esd_flag |= BIT_12; -+ } -+ -+ pci_sn_l = rtl8168_csi_read(tp, PCI_DEVICE_SERIAL_NUMBER); -+ if (pci_sn_l != tp->pci_cfg_space.pci_sn_l) { -+ rtl8168_csi_write(tp, PCI_DEVICE_SERIAL_NUMBER, tp->pci_cfg_space.pci_sn_l); -+ tp->esd_flag |= BIT_13; -+ } -+ -+ pci_sn_h = rtl8168_csi_read(tp, PCI_DEVICE_SERIAL_NUMBER + 4); -+ if (pci_sn_h != tp->pci_cfg_space.pci_sn_h) { -+ rtl8168_csi_write(tp, PCI_DEVICE_SERIAL_NUMBER + 4, tp->pci_cfg_space.pci_sn_h); -+ tp->esd_flag |= BIT_14; -+ } -+ -+ if (tp->esd_flag != 0) { -+ netif_stop_queue(dev); -+ netif_carrier_off(dev); -+ rtl8168_hw_reset(dev); -+ rtl8168_tx_clear(tp); -+ rtl8168_rx_clear(tp); -+ rtl8168_init_ring(dev); -+ rtl8168_hw_init(dev); -+ rtl8168_powerup_pll(dev); -+ rtl8168_hw_ephy_config(dev); -+ rtl8168_hw_phy_config(dev); -+ rtl8168_hw_config(dev); -+ rtl8168_set_speed(dev, tp->autoneg, tp->speed, tp->duplex); -+ tp->esd_flag = 0; -+ } -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ mod_timer(timer, jiffies + timeout); -+} -+ -+static void -+rtl8168_link_timer(unsigned long __opaque) -+{ -+ struct net_device *dev = (struct net_device *)__opaque; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ struct timer_list *timer = &tp->link_timer; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ rtl8168_check_link_status(dev); -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ mod_timer(timer, jiffies + RTL8168_LINK_TIMEOUT); -+} -+ -+/* Cfg9346_Unlock assumed. */ -+static unsigned rtl8168_try_msi(struct pci_dev *pdev, struct rtl8168_private *tp) -+{ -+ unsigned msi = 0; -+ -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) -+ if (pci_enable_msi(pdev)) -+ dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); -+ else -+ msi |= RTL_FEATURE_MSI; -+#endif -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_1: -+ case CFG_METHOD_2: -+ case CFG_METHOD_3: -+ case CFG_METHOD_4: -+ case CFG_METHOD_5: -+ case CFG_METHOD_6: -+ case CFG_METHOD_7: -+ case CFG_METHOD_8: -+ msi &= ~RTL_FEATURE_MSI; -+ break; -+ } -+ -+ return msi; -+} -+ -+static void rtl8168_disable_msi(struct pci_dev *pdev, struct rtl8168_private *tp) -+{ -+ if (tp->features & RTL_FEATURE_MSI) { -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) -+ pci_disable_msi(pdev); -+#endif -+ tp->features &= ~RTL_FEATURE_MSI; -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) -+static const struct net_device_ops rtl8168_netdev_ops = { -+ .ndo_open = rtl8168_open, -+ .ndo_stop = rtl8168_close, -+ .ndo_get_stats = rtl8168_get_stats, -+ .ndo_start_xmit = rtl8168_start_xmit, -+ .ndo_tx_timeout = rtl8168_tx_timeout, -+ .ndo_change_mtu = rtl8168_change_mtu, -+ .ndo_set_mac_address = rtl8168_set_mac_address, -+ .ndo_do_ioctl = rtl8168_do_ioctl, -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) -+ .ndo_set_multicast_list = rtl8168_set_rx_mode, -+#else -+ .ndo_set_rx_mode = rtl8168_set_rx_mode, -+#endif -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) -+#ifdef CONFIG_R8168_VLAN -+ .ndo_vlan_rx_register = rtl8168_vlan_rx_register, -+#endif -+#else -+ .ndo_fix_features = rtl8168_fix_features, -+ .ndo_set_features = rtl8168_set_features, -+#endif -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ .ndo_poll_controller = rtl8168_netpoll, -+#endif -+}; -+#endif -+ -+static int __devinit -+rtl8168_init_one(struct pci_dev *pdev, -+ const struct pci_device_id *ent) -+{ -+ struct net_device *dev = NULL; -+ struct rtl8168_private *tp; -+ void __iomem *ioaddr = NULL; -+ static int board_idx = -1; -+ -+ int rc; -+ -+ assert(pdev != NULL); -+ assert(ent != NULL); -+ -+ board_idx++; -+ -+ if (netif_msg_drv(&debug)) -+ printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", -+ MODULENAME, RTL8168_VERSION); -+ -+ rc = rtl8168_init_board(pdev, &dev, &ioaddr); -+ if (rc) -+ return rc; -+ -+ tp = netdev_priv(dev); -+ assert(ioaddr != NULL); -+ -+ tp->mmio_addr = ioaddr; -+ tp->set_speed = rtl8168_set_speed_xmii; -+ tp->get_settings = rtl8168_gset_xmii; -+ tp->phy_reset_enable = rtl8168_xmii_reset_enable; -+ tp->phy_reset_pending = rtl8168_xmii_reset_pending; -+ tp->link_ok = rtl8168_xmii_link_ok; -+ -+ tp->features |= rtl8168_try_msi(pdev, tp); -+ -+ RTL_NET_DEVICE_OPS(rtl8168_netdev_ops); -+ -+ SET_ETHTOOL_OPS(dev, &rtl8168_ethtool_ops); -+ -+ dev->watchdog_timeo = RTL8168_TX_TIMEOUT; -+ dev->irq = pdev->irq; -+ dev->base_addr = (unsigned long) ioaddr; -+ -+#ifdef CONFIG_R8168_NAPI -+ RTL_NAPI_CONFIG(dev, tp, rtl8168_poll, R8168_NAPI_WEIGHT); -+#endif -+ -+#ifdef CONFIG_R8168_VLAN -+ if (tp->mcfg != CFG_METHOD_DEFAULT) { -+ dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -+ dev->vlan_rx_kill_vid = rtl8168_vlan_rx_kill_vid; -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -+ } -+#endif -+ -+ tp->cp_cmd |= RTL_R16(CPlusCmd); -+ if (tp->mcfg != CFG_METHOD_DEFAULT) { -+ dev->features |= NETIF_F_IP_CSUM; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) -+ tp->cp_cmd |= RxChkSum; -+#else -+ dev->features |= NETIF_F_RXCSUM | NETIF_F_SG; -+ dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | -+ NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; -+ dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | -+ NETIF_F_HIGHDMA; -+#endif -+ } -+ -+ tp->pci_dev = pdev; -+ -+ spin_lock_init(&tp->lock); -+ -+ spin_lock_init(&tp->phy_lock); -+ -+ rtl8168_init_software_variable(dev); -+ -+#ifdef ENABLE_DASH_SUPPORT -+ if(tp->DASH) -+ AllocateDashShareMemory(dev); -+#endif -+ -+ rtl8168_exit_oob(dev); -+ -+ rtl8168_hw_init(dev); -+ -+ rtl8168_hw_reset(dev); -+ -+ /* Get production from EEPROM */ -+ if (((tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 || -+ tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_29 || -+ tp->mcfg == CFG_METHOD_30) && (mac_ocp_read(tp, 0xDC00) & BIT_3)) || -+ ((tp->mcfg == CFG_METHOD_26) && (mac_ocp_read(tp, 0xDC00) & BIT_4))) -+ tp->eeprom_type = EEPROM_TYPE_NONE; -+ else -+ rtl_eeprom_type(tp); -+ -+ if (tp->eeprom_type == EEPROM_TYPE_93C46 || tp->eeprom_type == EEPROM_TYPE_93C56) -+ rtl_set_eeprom_sel_low(ioaddr); -+ -+ rtl8168_get_mac_address(dev); -+ -+ pci_set_drvdata(pdev, dev); -+ -+ rc = register_netdev(dev); -+ if (rc) { -+#ifdef CONFIG_R8168_NAPI -+ RTL_NAPI_DEL(tp); -+#endif -+ rtl8168_release_board(pdev, dev, ioaddr); -+ return rc; -+ } -+ -+ printk(KERN_INFO "%s: This product is covered by one or more of the following patents: US6,570,884, US6,115,776, and US6,327,625.\n", MODULENAME); -+ -+ netif_carrier_off(dev); -+ -+ printk("%s", GPL_CLAIM); -+ -+ return 0; -+} -+ -+static void __devexit -+rtl8168_remove_one(struct pci_dev *pdev) -+{ -+ struct net_device *dev = pci_get_drvdata(pdev); -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ assert(dev != NULL); -+ assert(tp != NULL); -+ -+#ifdef CONFIG_R8168_NAPI -+ RTL_NAPI_DEL(tp); -+#endif -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ case CFG_METHOD_23: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ if (tp->DASH) -+ rtl8168_driver_stop(tp); -+ break; -+ } -+ -+ unregister_netdev(dev); -+ rtl8168_disable_msi(pdev, tp); -+#ifdef ENABLE_R8168_PROCFS -+ rtl8168_proc_remove(dev); -+#endif -+ rtl8168_release_board(pdev, dev, tp->mmio_addr); -+ pci_set_drvdata(pdev, NULL); -+} -+ -+static void -+rtl8168_set_rxbufsize(struct rtl8168_private *tp, -+ struct net_device *dev) -+{ -+ unsigned int mtu = dev->mtu; -+ -+ tp->rx_buf_sz = (mtu > ETH_DATA_LEN) ? mtu + ETH_HLEN + 8 + 1 : RX_BUF_SIZE; -+} -+ -+static int rtl8168_open(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ struct pci_dev *pdev = tp->pci_dev; -+ int retval; -+ -+ retval = -ENOMEM; -+ -+#ifdef ENABLE_R8168_PROCFS -+ rtl8168_proc_init(dev); -+#endif -+ rtl8168_set_rxbufsize(tp, dev); -+ /* -+ * Rx and Tx descriptors needs 256 bytes alignment. -+ * pci_alloc_consistent provides more. -+ */ -+ tp->TxDescArray = pci_alloc_consistent(pdev, R8168_TX_RING_BYTES, -+ &tp->TxPhyAddr); -+ if (!tp->TxDescArray) -+ goto err_free_all_allocated_mem; -+ -+ tp->RxDescArray = pci_alloc_consistent(pdev, R8168_RX_RING_BYTES, -+ &tp->RxPhyAddr); -+ if (!tp->RxDescArray) -+ goto err_free_all_allocated_mem; -+ -+ tp->tally_vaddr = pci_alloc_consistent(pdev, sizeof(*tp->tally_vaddr), &tp->tally_paddr); -+ if (!tp->tally_vaddr) -+ goto err_free_all_allocated_mem; -+ -+ if (tp->UseSwPaddingShortPkt) { -+ tp->ShortPacketEmptyBuffer = pci_alloc_consistent(pdev, SHORT_PACKET_PADDING_BUF_SIZE, -+ &tp->ShortPacketEmptyBufferPhy); -+ if (!tp->ShortPacketEmptyBuffer) -+ goto err_free_all_allocated_mem; -+ -+ memset(tp->ShortPacketEmptyBuffer, 0x0, SHORT_PACKET_PADDING_BUF_SIZE); -+ } -+ -+ retval = rtl8168_init_ring(dev); -+ if (retval < 0) -+ goto err_free_all_allocated_mem; -+ -+ if (netif_msg_probe(tp)) { -+ printk(KERN_INFO "%s: 0x%lx, " -+ "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " -+ "IRQ %d\n", -+ dev->name, -+ dev->base_addr, -+ dev->dev_addr[0], dev->dev_addr[1], -+ dev->dev_addr[2], dev->dev_addr[3], -+ dev->dev_addr[4], dev->dev_addr[5], dev->irq); -+ } -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ INIT_WORK(&tp->task, NULL, dev); -+#else -+ INIT_DELAYED_WORK(&tp->task, NULL); -+#endif -+ -+#ifdef CONFIG_R8168_NAPI -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ RTL_NAPI_ENABLE(dev, &tp->napi); -+#endif -+#endif -+ -+ rtl8168_exit_oob(dev); -+ -+ rtl8168_tally_counter_clear(tp); -+ -+ rtl8168_hw_init(dev); -+ -+ rtl8168_hw_reset(dev); -+ -+ rtl8168_powerup_pll(dev); -+ -+ rtl8168_hw_ephy_config(dev); -+ -+ rtl8168_hw_phy_config(dev); -+ -+ rtl8168_hw_config(dev); -+ -+ rtl8168_dsm(dev, DSM_IF_UP); -+ -+ rtl8168_set_speed(dev, tp->autoneg, tp->speed, tp->duplex); -+ -+ retval = request_irq(dev->irq, rtl8168_interrupt, (tp->features & RTL_FEATURE_MSI) ? 0 : SA_SHIRQ, dev->name, dev); -+ if (retval<0) -+ goto err_free_all_allocated_mem; -+ -+ if (tp->esd_flag == 0) -+ rtl8168_request_esd_timer(dev); -+ -+ rtl8168_request_link_timer(dev); -+ -+out: -+ -+ return retval; -+ -+err_free_all_allocated_mem: -+ if (tp->tally_vaddr != NULL) { -+ pci_free_consistent(pdev, sizeof(*tp->tally_vaddr), tp->tally_vaddr, -+ tp->tally_paddr); -+ -+ tp->tally_vaddr = NULL; -+ } -+ -+ if (tp->RxDescArray != NULL) { -+ pci_free_consistent(pdev, R8168_RX_RING_BYTES, tp->RxDescArray, -+ tp->RxPhyAddr); -+ tp->RxDescArray = NULL; -+ } -+ -+ if (tp->TxDescArray != NULL) { -+ pci_free_consistent(pdev, R8168_TX_RING_BYTES, tp->TxDescArray, -+ tp->TxPhyAddr); -+ tp->TxDescArray = NULL; -+ } -+ -+ if (tp->ShortPacketEmptyBuffer != NULL) { -+ pci_free_consistent(pdev, ETH_ZLEN, tp->ShortPacketEmptyBuffer, -+ tp->ShortPacketEmptyBufferPhy); -+ tp->ShortPacketEmptyBuffer = NULL; -+ } -+ -+ goto out; -+} -+ -+static void -+rtl8168_dsm(struct net_device *dev, int dev_state) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ switch (dev_state) { -+ case DSM_MAC_INIT: -+ if ((tp->mcfg == CFG_METHOD_5) || (tp->mcfg == CFG_METHOD_6)) { -+ if (RTL_R8(MACDBG) & 0x80) -+ RTL_W8(GPIO, RTL_R8(GPIO) | GPIO_en); -+ else -+ RTL_W8(GPIO, RTL_R8(GPIO) & ~GPIO_en); -+ } -+ -+ break; -+ case DSM_NIC_GOTO_D3: -+ case DSM_IF_DOWN: -+ if ((tp->mcfg == CFG_METHOD_5) || (tp->mcfg == CFG_METHOD_6)) { -+ if (RTL_R8(MACDBG) & 0x80) -+ RTL_W8(GPIO, RTL_R8(GPIO) & ~GPIO_en); -+ } -+ break; -+ -+ case DSM_NIC_RESUME_D3: -+ case DSM_IF_UP: -+ if ((tp->mcfg == CFG_METHOD_5) || (tp->mcfg == CFG_METHOD_6)) { -+ if (RTL_R8(MACDBG) & 0x80) -+ RTL_W8(GPIO, RTL_R8(GPIO) | GPIO_en); -+ } -+ -+ break; -+ } -+ -+} -+static void -+set_offset70F(struct rtl8168_private *tp, u8 setting) -+{ -+ -+ u32 csi_tmp; -+ u32 temp = (u32)setting; -+ temp = temp << 24; -+ /*set PCI configuration space offset 0x70F to setting*/ -+ /*When the register offset of PCI configuration space larger than 0xff, use CSI to access it.*/ -+ -+ csi_tmp = rtl8168_csi_read(tp, 0x70c) & 0x00ffffff; -+ rtl8168_csi_write(tp, 0x70c, csi_tmp | temp); -+} -+ -+static void -+set_offset79(struct rtl8168_private *tp, u8 setting) -+{ -+ //Set PCI configuration space offset 0x79 to setting -+ -+ struct pci_dev *pdev = tp->pci_dev; -+ u8 device_control; -+ -+ pci_read_config_byte(pdev, 0x79, &device_control); -+ device_control &= ~0x70; -+ device_control |= setting; -+ pci_write_config_byte(pdev, 0x79, device_control); -+ -+} -+ -+static void -+rtl8168_hw_set_rx_packet_filter(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ u32 mc_filter[2]; /* Multicast hash filter */ -+ int rx_mode; -+ u32 tmp = 0; -+ -+ if (dev->flags & IFF_PROMISC) { -+ /* Unconditionally log net taps. */ -+ if (netif_msg_link(tp)) -+ printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", -+ dev->name); -+ -+ rx_mode = -+ AcceptBroadcast | AcceptMulticast | AcceptMyPhys | -+ AcceptAllPhys; -+ mc_filter[1] = mc_filter[0] = 0xffffffff; -+ } else if ((netdev_mc_count(dev) > multicast_filter_limit) -+ || (dev->flags & IFF_ALLMULTI)) { -+ /* Too many to filter perfectly -- accept all multicasts. */ -+ rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; -+ mc_filter[1] = mc_filter[0] = 0xffffffff; -+ } else { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) -+ struct dev_mc_list *mclist; -+ unsigned int i; -+ -+ rx_mode = AcceptBroadcast | AcceptMyPhys; -+ mc_filter[1] = mc_filter[0] = 0; -+ for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; -+ i++, mclist = mclist->next) { -+ int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; -+ mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); -+ rx_mode |= AcceptMulticast; -+ } -+#else -+ struct netdev_hw_addr *ha; -+ -+ rx_mode = AcceptBroadcast | AcceptMyPhys; -+ mc_filter[1] = mc_filter[0] = 0; -+ netdev_for_each_mc_addr(ha, dev) { -+ int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; -+ mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); -+ rx_mode |= AcceptMulticast; -+ } -+#endif -+ } -+ -+ tmp = mc_filter[0]; -+ mc_filter[0] = swab32(mc_filter[1]); -+ mc_filter[1] = swab32(tmp); -+ -+ tp->rtl8168_rx_config = rtl_chip_info[tp->chipset].RCR_Cfg; -+ tmp = tp->rtl8168_rx_config | rx_mode | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); -+ -+ RTL_W32(RxConfig, tmp); -+ RTL_W32(MAR0 + 0, mc_filter[0]); -+ RTL_W32(MAR0 + 4, mc_filter[1]); -+} -+ -+static void -+rtl8168_set_rx_mode(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ rtl8168_hw_set_rx_packet_filter(dev); -+ -+ spin_unlock_irqrestore(&tp->lock, flags); -+} -+ -+static void -+rtl8168_hw_config(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ struct pci_dev *pdev = tp->pci_dev; -+ u8 device_control; -+ u16 mac_ocp_data; -+ u32 csi_tmp; -+ unsigned long flags; -+ -+ RTL_W32(RxConfig, (RX_DMA_BURST << RxCfgDMAShift)); -+ -+ rtl8168_hw_reset(dev); -+ -+ RTL_W8(Cfg9346, Cfg9346_Unlock); -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ RTL_W8(0xF1, RTL_R8(0xF1) & ~BIT_7); -+ RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7); -+ RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0); -+ break; -+ } -+ -+ //clear io_rdy_l23 -+ switch (tp->mcfg) { -+ case CFG_METHOD_20: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ RTL_W8(Config3, RTL_R8(Config3) & ~BIT_1); -+ break; -+ } -+ -+ RTL_W8(MTPS, Reserved1_data); -+ -+ tp->cp_cmd |= INTT_1; -+ if (tp->use_timer_interrrupt) -+ tp->cp_cmd |= PktCntrDisable; -+ else -+ tp->cp_cmd &= ~PktCntrDisable; -+ -+ RTL_W16(IntrMitigate, 0x5f51); -+ -+ rtl8168_tally_counter_addr_fill(tp); -+ -+ rtl8168_desc_addr_fill(tp); -+ -+ /* Set DMA burst size and Interframe Gap Time */ -+ if (tp->mcfg == CFG_METHOD_1) -+ RTL_W32(TxConfig, (TX_DMA_BURST_512 << TxDMAShift) | -+ (InterFrameGap << TxInterFrameGapShift)); -+ else -+ RTL_W32(TxConfig, (TX_DMA_BURST_unlimited << TxDMAShift) | -+ (InterFrameGap << TxInterFrameGapShift)); -+ -+ if (tp->mcfg == CFG_METHOD_4) { -+ set_offset70F(tp, 0x27); -+ -+ RTL_W8(DBG_reg, (0x0E << 4) | Fix_Nak_1 | Fix_Nak_2); -+ -+ RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); -+ -+ //disable clock request. -+ pci_write_config_byte(pdev, 0x81, 0x00); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); -+ -+ set_offset79(tp, 0x20); -+ -+ //tx checksum offload disable -+ dev->features &= ~NETIF_F_IP_CSUM; -+ -+ //rx checksum offload disable -+ } else { -+ RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); -+ -+ set_offset79(tp, 0x50); -+ -+ //tx checksum offload enable -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ -+ //rx checksum offload enable -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) -+ tp->cp_cmd |= RxChkSum; -+#else -+ dev->features |= NETIF_F_RXCSUM; -+#endif -+ -+ tp->cp_cmd &= ~(EnableBist | Macdbgo_oe | Force_halfdup | -+ Force_rxflow_en | Force_txflow_en | Cxpl_dbg_sel | -+ ASF | PktCntrDisable | Macdbgo_sel); -+ } else if (tp->mcfg == CFG_METHOD_5) { -+ -+ set_offset70F(tp, 0x27); -+ -+ RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); -+ -+ //disable clock request. -+ pci_write_config_byte(pdev, 0x81, 0x00); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); -+ -+ set_offset79(tp, 0x20); -+ -+ //tx checksum offload disable -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } else { -+ RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); -+ -+ set_offset79(tp, 0x50); -+ -+ //tx checksum offload enable -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ -+ //rx checksum offload enable -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) -+ tp->cp_cmd |= RxChkSum; -+#else -+ dev->features |= NETIF_F_RXCSUM; -+#endif -+ } else if (tp->mcfg == CFG_METHOD_6) { -+ set_offset70F(tp, 0x27); -+ -+ RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); -+ -+ //disable clock request. -+ pci_write_config_byte(pdev, 0x81, 0x00); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); -+ -+ set_offset79(tp, 0x20); -+ -+ //tx checksum offload disable -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } else { -+ RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); -+ -+ set_offset79(tp, 0x50); -+ -+ //tx checksum offload enable -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ -+ //rx checksum offload enable -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) -+ tp->cp_cmd |= RxChkSum; -+#else -+ dev->features |= NETIF_F_RXCSUM; -+#endif -+ } else if (tp->mcfg == CFG_METHOD_7) { -+ set_offset70F(tp, 0x27); -+ -+ rtl8168_eri_write(ioaddr, 0x1EC, 1, 0x07, ERIAR_ASF); -+ -+ //disable clock request. -+ pci_write_config_byte(pdev, 0x81, 0x00); -+ -+ RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); -+ -+ set_offset79(tp, 0x20); -+ -+ //tx checksum offload disable -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } else { -+ RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); -+ -+ -+ set_offset79(tp, 0x50); -+ -+ //tx checksum offload enable -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ } else if (tp->mcfg == CFG_METHOD_8) { -+ -+ set_offset70F(tp, 0x27); -+ -+ rtl8168_eri_write(ioaddr, 0x1EC, 1, 0x07, ERIAR_ASF); -+ -+ //disable clock request. -+ pci_write_config_byte(pdev, 0x81, 0x00); -+ -+ RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); -+ -+ RTL_W8(0xD1, 0x20); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); -+ -+ set_offset79(tp, 0x20); -+ -+ //tx checksum offload disable -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } else { -+ RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); -+ -+ -+ set_offset79(tp, 0x50); -+ -+ //tx checksum offload enable -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ } else if (tp->mcfg == CFG_METHOD_9) { -+ set_offset70F(tp, 0x27); -+ -+ /* disable clock request. */ -+ pci_write_config_byte(pdev, 0x81, 0x00); -+ -+ RTL_W8(Config3, RTL_R8(Config3) & ~BIT_4); -+ RTL_W8(DBG_reg, RTL_R8(DBG_reg) | BIT_7 | BIT_1); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); -+ -+ set_offset79(tp, 0x20); -+ -+ /* tx checksum offload disable */ -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } else { -+ RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); -+ -+ -+ set_offset79(tp, 0x50); -+ -+ /* tx checksum offload enable */ -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ -+ RTL_W8(TDFNR, 0x8); -+ -+ } else if (tp->mcfg == CFG_METHOD_10) { -+ set_offset70F(tp, 0x27); -+ -+ RTL_W8(DBG_reg, RTL_R8(DBG_reg) | BIT_7 | BIT_1); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); -+ -+ set_offset79(tp, 0x20); -+ -+ /* tx checksum offload disable */ -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } else { -+ RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); -+ -+ set_offset79(tp, 0x50); -+ -+ /* tx checksum offload enable */ -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ -+ RTL_W8(TDFNR, 0x8); -+ -+ RTL_W8(Config1, RTL_R8(Config1) | 0x10); -+ -+ /* disable clock request. */ -+ pci_write_config_byte(pdev, 0x81, 0x00); -+ } else if (tp->mcfg == CFG_METHOD_11 || tp->mcfg == CFG_METHOD_13) { -+ set_offset70F(tp, 0x17); -+ set_offset79(tp, 0x50); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); -+ -+ /* tx checksum offload disable */ -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } else { -+ RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); -+ -+ /* tx checksum offload enable */ -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ -+ pci_write_config_byte(pdev, 0x81, 0x00); -+ -+ RTL_W8(Config1, RTL_R8(Config1) | 0x10); -+ -+ } else if (tp->mcfg == CFG_METHOD_12) { -+ set_offset70F(tp, 0x17); -+ set_offset79(tp, 0x50); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); -+ -+ /* tx checksum offload disable */ -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } else { -+ RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); -+ -+ /* tx checksum offload enable */ -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ -+ pci_write_config_byte(pdev, 0x81, 0x01); -+ -+ RTL_W8(Config1, RTL_R8(Config1) | 0x10); -+ -+ } else if (tp->mcfg == CFG_METHOD_14 || tp->mcfg == CFG_METHOD_15) { -+ -+ set_offset70F(tp, 0x27); -+ set_offset79(tp, 0x50); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(MTPS, 0x24); -+ RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) | 0x01); -+ -+ /* tx checksum offload disable */ -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } else { -+ RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); -+ RTL_W8(Config4, RTL_R8(Config4) & ~0x01); -+ -+ /* tx checksum offload enable */ -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ -+ RTL_W8(0xF3, RTL_R8(0xF3) | BIT_5); -+ RTL_W8(0xF3, RTL_R8(0xF3) & ~BIT_5); -+ -+ RTL_W8(0xD0, RTL_R8(0xD0) | BIT_7 | BIT_6); -+ -+ RTL_W8(0xD1, RTL_R8(0xD1) | BIT_2 | BIT_3); -+ -+ RTL_W8(0xF1, RTL_R8(0xF1) | BIT_6 | BIT_5 | BIT_4 | BIT_2 | BIT_1); -+ -+ RTL_W8(TDFNR, 0x8); -+ -+ if (aspm) -+ RTL_W8(0xF1, RTL_R8(0xF1) | BIT_7); -+ -+ RTL_W8(Config5, RTL_R8(Config5) & ~BIT_3); -+ -+ RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); -+ -+ RTL_W8(Config1, RTL_R8(Config1) & ~0x10); -+ } else if (tp->mcfg == CFG_METHOD_16 || tp->mcfg == CFG_METHOD_17) { -+ set_offset70F(tp, 0x17); -+ set_offset79(tp, 0x50); -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0xD5, 1, ERIAR_ExGMAC) | BIT_3 | BIT_2; -+ rtl8168_eri_write(ioaddr, 0xD5, 1, csi_tmp, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xC0, 2, 0x0000, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xB8, 4, 0x00000000, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xC8, 4, 0x00100002, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xE8, 4, 0x00100006, ERIAR_ExGMAC); -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1D0, 4, ERIAR_ExGMAC); -+ csi_tmp |= BIT_1; -+ rtl8168_eri_write(ioaddr, 0x1D0, 1, csi_tmp, ERIAR_ExGMAC); -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0xDC, 1, ERIAR_ExGMAC); -+ csi_tmp &= ~BIT_0; -+ rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC); -+ csi_tmp |= BIT_0; -+ rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC); -+ -+ RTL_W32(TxConfig, RTL_R32(TxConfig) | BIT_7); -+ RTL_W8(0xD3, RTL_R8(0xD3) & ~BIT_7); -+ RTL_W8(0x1B, RTL_R8(0x1B) & ~0x07); -+ -+ if (tp->mcfg == CFG_METHOD_16) { -+ RTL_W32(0xB0, 0xEE480010); -+ RTL_W8(0x1A, RTL_R8(0x1A) & ~(BIT_2|BIT_3)); -+ rtl8168_eri_write(ioaddr, 0x1DC, 1, 0x64, ERIAR_ExGMAC); -+ } else { -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC); -+ csi_tmp |= BIT_4; -+ rtl8168_eri_write(ioaddr, 0x1B0, 1, csi_tmp, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xCC, 4, 0x00000050, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xD0, 4, 0x07ff0060, ERIAR_ExGMAC); -+ } -+ -+ RTL_W8(TDFNR, 0x8); -+ -+ RTL_W8(Config2, RTL_R8(Config2) & ~PMSTS_En); -+ -+ RTL_W8(0xD0, RTL_R8(0xD0) | BIT_6); -+ RTL_W8(0xF2, RTL_R8(0xF2) | BIT_6); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(MTPS, 0x27); -+ -+ /* tx checksum offload disable */ -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } else { -+ /* tx checksum offload enable */ -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ -+ /* disable clock request. */ -+ pci_write_config_byte(pdev, 0x81, 0x00); -+ -+ } else if (tp->mcfg == CFG_METHOD_18 || tp->mcfg == CFG_METHOD_19) { -+ set_offset70F(tp, 0x17); -+ set_offset79(tp, 0x50); -+ -+ rtl8168_eri_write(ioaddr, 0xC8, 4, 0x00100002, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xE8, 4, 0x00100006, ERIAR_ExGMAC); -+ RTL_W32(TxConfig, RTL_R32(TxConfig) | BIT_7); -+ RTL_W8(0xD3, RTL_R8(0xD3) & ~BIT_7); -+ csi_tmp = rtl8168_eri_read(ioaddr, 0xDC, 1, ERIAR_ExGMAC); -+ csi_tmp &= ~BIT_0; -+ rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC); -+ csi_tmp |= BIT_0; -+ rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC); -+ -+ if (aspm) -+ RTL_W8(0xF1, RTL_R8(0xF1) | BIT_7); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(MTPS, 0x27); -+ -+ /* tx checksum offload disable */ -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } else { -+ /* tx checksum offload enable */ -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ -+ RTL_W8(TDFNR, 0x8); -+ -+ RTL_W8(0xD0, RTL_R8(0xD0) | BIT_6); -+ RTL_W8(0xF2, RTL_R8(0xF2) | BIT_6); -+ -+ rtl8168_eri_write(ioaddr, 0xC0, 2, 0x0000, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xB8, 4, 0x00000000, ERIAR_ExGMAC); -+ csi_tmp = rtl8168_eri_read(ioaddr, 0xD5, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_3 | BIT_2; -+ rtl8168_eri_write(ioaddr, 0xD5, 1, csi_tmp, ERIAR_ExGMAC); -+ RTL_W8(0x1B,RTL_R8(0x1B) & ~0x07); -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_4; -+ rtl8168_eri_write(ioaddr, 0x1B0, 1, csi_tmp, ERIAR_ExGMAC); -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1d0, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_4 | BIT_1; -+ rtl8168_eri_write(ioaddr, 0x1d0, 1, csi_tmp, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xCC, 4, 0x00000050, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xd0, 4, 0x00000060, ERIAR_ExGMAC); -+ } else if (tp->mcfg == CFG_METHOD_20) { -+ set_offset70F(tp, 0x17); -+ set_offset79(tp, 0x50); -+ -+ rtl8168_eri_write(ioaddr, 0xC8, 4, 0x00100002, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xE8, 4, 0x00100006, ERIAR_ExGMAC); -+ RTL_W32(TxConfig, RTL_R32(TxConfig) | BIT_7); -+ RTL_W8(0xD3, RTL_R8(0xD3) & ~BIT_7); -+ csi_tmp = rtl8168_eri_read(ioaddr, 0xDC, 1, ERIAR_ExGMAC); -+ csi_tmp &= ~BIT_0; -+ rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC); -+ csi_tmp |= BIT_0; -+ rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC); -+ -+ if (aspm) -+ RTL_W8(0xF1, RTL_R8(0xF1) | BIT_7); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(MTPS, 0x27); -+ -+ /* tx checksum offload disable */ -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } else { -+ /* tx checksum offload enable */ -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ -+ RTL_W8(TDFNR, 0x8); -+ -+ RTL_W8(0xD0, RTL_R8(0xD0) | BIT_6); -+ RTL_W8(0xF2, RTL_R8(0xF2) | BIT_6); -+ rtl8168_eri_write(ioaddr, 0xC0, 2, 0x0000, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xB8, 4, 0x00000000, ERIAR_ExGMAC); -+ csi_tmp = rtl8168_eri_read(ioaddr, 0xD5, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_3 | BIT_2; -+ rtl8168_eri_write(ioaddr, 0xD5, 1, csi_tmp, ERIAR_ExGMAC); -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_4; -+ rtl8168_eri_write(ioaddr, 0x1B0, 1, csi_tmp, ERIAR_ExGMAC); -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1d0, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_4 | BIT_1; -+ rtl8168_eri_write(ioaddr, 0x1d0, 1, csi_tmp, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xCC, 4, 0x00000050, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xd0, 4, 0x00000060, ERIAR_ExGMAC); -+ } else if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 || -+ tp->mcfg == CFG_METHOD_24 || tp->mcfg == CFG_METHOD_25 || -+ tp->mcfg == CFG_METHOD_26 || tp->mcfg == CFG_METHOD_29 || -+ tp->mcfg == CFG_METHOD_30) { -+ set_offset70F(tp, 0x17); -+ set_offset79(tp, 0x50); -+ -+ rtl8168_eri_write(ioaddr, 0xC8, 4, 0x00080002, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xCC, 1, 0x38, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xD0, 1, 0x48, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xE8, 4, 0x00100006, ERIAR_ExGMAC); -+ -+ RTL_W32(TxConfig, RTL_R32(TxConfig) | BIT_7); -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0xDC, 1, ERIAR_ExGMAC); -+ csi_tmp &= ~BIT_0; -+ rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC); -+ csi_tmp |= BIT_0; -+ rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC); -+ -+ if (tp->mcfg == CFG_METHOD_26) { -+ mac_ocp_data = mac_ocp_read(tp, 0xD3C0); -+ mac_ocp_data &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0); -+ mac_ocp_data |= 0x03A9; -+ mac_ocp_write(tp, 0xD3C0, mac_ocp_data); -+ mac_ocp_data = mac_ocp_read(tp, 0xD3C2); -+ mac_ocp_data &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0); -+ mac_ocp_write(tp, 0xD3C2, mac_ocp_data); -+ mac_ocp_data = mac_ocp_read(tp, 0xD3C4); -+ mac_ocp_data |= BIT_0; -+ mac_ocp_write(tp, 0xD3C4, mac_ocp_data); -+ } else if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ -+ if(tp->RequireAdjustUpsTxLinkPulseTiming) { -+ mac_ocp_data = mac_ocp_read(tp, 0xD412); -+ mac_ocp_data &= ~(0x0FFF); -+ mac_ocp_data |= tp->SwrCnt1msIni ; -+ mac_ocp_write(tp, 0xD412, mac_ocp_data); -+ } -+ -+ mac_ocp_data = mac_ocp_read(tp, 0xE056); -+ mac_ocp_data &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4); -+ mac_ocp_data |= (BIT_6 | BIT_5 | BIT_4); -+ mac_ocp_write(tp, 0xE056, mac_ocp_data); -+ -+ mac_ocp_data = mac_ocp_read(tp, 0xE052); -+ mac_ocp_data &= ~( BIT_14 | BIT_13); -+ mac_ocp_data |= BIT_15; -+ mac_ocp_data |= BIT_3; -+ mac_ocp_write(tp, 0xE052, mac_ocp_data); -+ -+ mac_ocp_data = mac_ocp_read(tp, 0xD420); -+ mac_ocp_data &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0); -+ mac_ocp_data |= 0x47F; -+ mac_ocp_write(tp, 0xD420, mac_ocp_data); -+ -+ mac_ocp_data = mac_ocp_read(tp, 0xE0D6); -+ mac_ocp_data &= ~(BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0); -+ mac_ocp_data |= 0x17F; -+ mac_ocp_write(tp, 0xE0D6, mac_ocp_data); -+ } -+ -+ RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); -+ -+ RTL_W8(0x1B, RTL_R8(0x1B) & ~0x07); -+ -+ RTL_W8(TDFNR, 0x4); -+ -+ RTL_W8(Config2, RTL_R8(Config2) & ~PMSTS_En); -+ -+ if (aspm) -+ RTL_W8(0xF1, RTL_R8(0xF1) | BIT_7); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(MTPS, 0x27); -+ -+ /* tx checksum offload disable */ -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } else { -+ /* tx checksum offload enable */ -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ -+ RTL_W8(0xD0, RTL_R8(0xD0) | BIT_6); -+ RTL_W8(0xF2, RTL_R8(0xF2) | BIT_6); -+ -+ RTL_W8(0xD0, RTL_R8(0xD0) | BIT_7); -+ -+ rtl8168_eri_write(ioaddr, 0xC0, 2, 0x0000, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xB8, 4, 0x00000000, ERIAR_ExGMAC); -+ -+ rtl8168_eri_write(ioaddr, 0x5F0, 2, 0x4F87, ERIAR_ExGMAC); -+ -+ if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ csi_tmp = rtl8168_eri_read(ioaddr, 0xD4, 4, ERIAR_ExGMAC); -+ csi_tmp |= (BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12); -+ rtl8168_eri_write(ioaddr, 0xD4, 4, csi_tmp, ERIAR_ExGMAC); -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0xDC, 4, ERIAR_ExGMAC); -+ csi_tmp |= (BIT_2 | BIT_3 | BIT_4); -+ rtl8168_eri_write(ioaddr, 0xDC, 4, csi_tmp, ERIAR_ExGMAC); -+ } else { -+ csi_tmp = rtl8168_eri_read(ioaddr, 0xD4, 4, ERIAR_ExGMAC); -+ csi_tmp |= (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12); -+ rtl8168_eri_write(ioaddr, 0xD4, 4, csi_tmp, ERIAR_ExGMAC); -+ } -+ -+ if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 || -+ tp->mcfg == CFG_METHOD_24 || tp->mcfg == CFG_METHOD_25) { -+ mac_ocp_write(tp, 0xC140, 0xFFFF); -+ } else if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ mac_ocp_write(tp, 0xC140, 0xFFFF); -+ mac_ocp_write(tp, 0xC142, 0xFFFF); -+ } -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC); -+ csi_tmp &= ~BIT_12; -+ rtl8168_eri_write(ioaddr, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC); -+ -+ if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) { -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x2FC, 1, ERIAR_ExGMAC); -+ csi_tmp &= ~(BIT_2); -+ rtl8168_eri_write(ioaddr, 0x2FC, 1, csi_tmp, ERIAR_ExGMAC); -+ } else { -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x2FC, 1, ERIAR_ExGMAC); -+ csi_tmp &= ~(BIT_0 | BIT_1 | BIT_2); -+ csi_tmp |= BIT_0; -+ rtl8168_eri_write(ioaddr, 0x2FC, 1, csi_tmp, ERIAR_ExGMAC); -+ } -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1D0, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_1; -+ rtl8168_eri_write(ioaddr, 0x1D0, 1, csi_tmp, ERIAR_ExGMAC); -+ } else if (tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_27 || -+ tp->mcfg == CFG_METHOD_28) { -+ set_offset70F(tp, 0x17); -+ set_offset79(tp, 0x50); -+ -+ rtl8168_eri_write(ioaddr, 0xC8, 4, 0x00080002, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xCC, 1, 0x2F, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xD0, 1, 0x5F, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xE8, 4, 0x00100006, ERIAR_ExGMAC); -+ -+ RTL_W32(TxConfig, RTL_R32(TxConfig) | BIT_7); -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0xDC, 1, ERIAR_ExGMAC); -+ csi_tmp &= ~BIT_0; -+ rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC); -+ csi_tmp |= BIT_0; -+ rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC); -+ -+ RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); -+ -+ RTL_W8(0xD0, RTL_R8(0xD0) | BIT_6); -+ RTL_W8(0xF2, RTL_R8(0xF2) | BIT_6); -+ -+ RTL_W8(0xD0, RTL_R8(0xD0) | BIT_7); -+ -+ rtl8168_eri_write(ioaddr, 0xC0, 2, 0x0000, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0xB8, 4, 0x00000000, ERIAR_ExGMAC); -+ RTL_W8(0x1B, RTL_R8(0x1B) & ~0x07); -+ -+ RTL_W8(TDFNR, 0x4); -+ -+ if (aspm) -+ RTL_W8(0xF1, RTL_R8(0xF1) | BIT_7); -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC); -+ csi_tmp &= ~BIT_12; -+ rtl8168_eri_write(ioaddr, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC); -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x2FC, 1, ERIAR_ExGMAC); -+ csi_tmp &= ~(BIT_0 | BIT_1 | BIT_2); -+ csi_tmp |= BIT_0; -+ rtl8168_eri_write(ioaddr, 0x2FC, 1, csi_tmp, ERIAR_ExGMAC); -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1D0, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_1; -+ rtl8168_eri_write(ioaddr, 0x1D0, 1, csi_tmp, ERIAR_ExGMAC); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ RTL_W8(MTPS, 0x27); -+ -+ /* tx checksum offload disable */ -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } else { -+ /* tx checksum offload enable */ -+ dev->features |= NETIF_F_IP_CSUM; -+ } -+ -+ if (tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28) { -+ OOB_mutex_lock(tp); -+ rtl8168_eri_write(ioaddr, 0x5F0, 2, 0x4F87, ERIAR_ExGMAC); -+ OOB_mutex_unlock(tp); -+ } -+ -+ csi_tmp = rtl8168_eri_read(ioaddr, 0xD4, 4, ERIAR_ExGMAC); -+ csi_tmp |= ( BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12 ); -+ rtl8168_eri_write(ioaddr, 0xD4, 4, csi_tmp, ERIAR_ExGMAC); -+ -+ mac_ocp_write(tp, 0xC140, 0xFFFF); -+ mac_ocp_write(tp, 0xC142, 0xFFFF); -+ -+ if (tp->mcfg == CFG_METHOD_28) { -+ mac_ocp_data = mac_ocp_read(tp, 0xD3E2); -+ mac_ocp_data &= 0xF000; -+ mac_ocp_data |= 0x3A9; -+ mac_ocp_write(tp, 0xD3E2, mac_ocp_data); -+ -+ mac_ocp_data = mac_ocp_read(tp, 0xD3E4); -+ mac_ocp_data &= 0xFF00; -+ mac_ocp_write(tp, 0xD3E4, mac_ocp_data); -+ -+ mac_ocp_data = mac_ocp_read(tp, 0xE860); -+ mac_ocp_data |= BIT_7; -+ mac_ocp_write(tp, 0xE860, mac_ocp_data); -+ } -+ } else if (tp->mcfg == CFG_METHOD_1) { -+ RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ pci_read_config_byte(pdev, 0x69, &device_control); -+ device_control &= ~0x70; -+ device_control |= 0x28; -+ pci_write_config_byte(pdev, 0x69, device_control); -+ } else { -+ pci_read_config_byte(pdev, 0x69, &device_control); -+ device_control &= ~0x70; -+ device_control |= 0x58; -+ pci_write_config_byte(pdev, 0x69, device_control); -+ } -+ } else if (tp->mcfg == CFG_METHOD_2) { -+ RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ pci_read_config_byte(pdev, 0x69, &device_control); -+ device_control &= ~0x70; -+ device_control |= 0x28; -+ pci_write_config_byte(pdev, 0x69, device_control); -+ -+ RTL_W8(Config4, RTL_R8(Config4) | (1 << 0)); -+ } else { -+ pci_read_config_byte(pdev, 0x69, &device_control); -+ device_control &= ~0x70; -+ device_control |= 0x58; -+ pci_write_config_byte(pdev, 0x69, device_control); -+ -+ RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); -+ } -+ } else if (tp->mcfg == CFG_METHOD_3) { -+ RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); -+ -+ if (dev->mtu > ETH_DATA_LEN) { -+ pci_read_config_byte(pdev, 0x69, &device_control); -+ device_control &= ~0x70; -+ device_control |= 0x28; -+ pci_write_config_byte(pdev, 0x69, device_control); -+ -+ RTL_W8(Config4, RTL_R8(Config4) | (1 << 0)); -+ } else { -+ pci_read_config_byte(pdev, 0x69, &device_control); -+ device_control &= ~0x70; -+ device_control |= 0x58; -+ pci_write_config_byte(pdev, 0x69, device_control); -+ -+ RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); -+ } -+ } else if (tp->mcfg == CFG_METHOD_DEFAULT) { -+ dev->features &= ~NETIF_F_IP_CSUM; -+ } -+ -+ if ((tp->mcfg == CFG_METHOD_1) || (tp->mcfg == CFG_METHOD_2) || (tp->mcfg == CFG_METHOD_3)) { -+ /* csum offload command for RTL8168B/8111B */ -+ tp->tx_tcp_csum_cmd = TxIPCS | TxTCPCS; -+ tp->tx_udp_csum_cmd = TxIPCS | TxUDPCS; -+ tp->tx_ip_csum_cmd = TxIPCS; -+ } else { -+ /* csum offload command for RTL8168C/8111C and RTL8168CP/8111CP */ -+ tp->tx_tcp_csum_cmd = TxIPCS_C | TxTCPCS_C; -+ tp->tx_udp_csum_cmd = TxIPCS_C | TxUDPCS_C; -+ tp->tx_ip_csum_cmd = TxIPCS_C; -+ } -+ -+ -+ //other hw parameters -+ if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 || -+ tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 || -+ tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 || -+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28) -+ rtl8168_eri_write(ioaddr, 0x2F8, 2, 0x1D8F, ERIAR_ExGMAC); -+ -+ if (tp->bios_setting & BIT_28) { -+ if (tp->mcfg == CFG_METHOD_18 || tp->mcfg == CFG_METHOD_19 || -+ tp->mcfg == CFG_METHOD_20) { -+ u32 gphy_val; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_write(tp, 0x1F, 0x0007); -+ mdio_write(tp, 0x1E, 0x002C); -+ gphy_val = mdio_read(tp, 0x16); -+ gphy_val |= BIT_10; -+ mdio_write(tp, 0x16, gphy_val); -+ mdio_write(tp, 0x1F, 0x0005); -+ mdio_write(tp, 0x05, 0x8B80); -+ gphy_val = mdio_read(tp, 0x06); -+ gphy_val |= BIT_7; -+ mdio_write(tp, 0x06, gphy_val); -+ mdio_write(tp, 0x1F, 0x0000); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ } -+ } -+ -+ rtl8168_hw_clear_timer_int(dev); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ if (aspm) { -+ rtl8168_init_pci_offset_99(tp); -+ } -+ break; -+ } -+ switch (tp->mcfg) { -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ if (aspm) { -+ rtl8168_init_pci_offset_180(tp); -+ } -+ break; -+ } -+ -+ tp->cp_cmd &= ~(EnableBist | Macdbgo_oe | Force_halfdup | -+ Force_rxflow_en | Force_txflow_en | Cxpl_dbg_sel | -+ ASF | Macdbgo_sel); -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) -+ RTL_W16(CPlusCmd, tp->cp_cmd); -+#else -+ rtl8168_hw_set_features(dev, dev->features); -+#endif -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: { -+ int timeout; -+ for (timeout = 0; timeout < 10; timeout++) { -+ if ((rtl8168_eri_read(ioaddr, 0x1AE, 2, ERIAR_ExGMAC) & BIT_13)==0) -+ break; -+ mdelay(1); -+ } -+ } -+ break; -+ } -+ -+ RTL_W16(RxMaxSize, tp->rx_buf_sz); -+ -+ rtl8168_disable_rxdvgate(dev); -+ -+ if (tp->mcfg == CFG_METHOD_11 || tp->mcfg == CFG_METHOD_12) -+ rtl8168_mac_loopback_test(tp); -+ -+ if (!tp->pci_cfg_is_read) { -+ pci_read_config_byte(pdev, PCI_COMMAND, &tp->pci_cfg_space.cmd); -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_0, &tp->pci_cfg_space.io_base_l); -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_0 + 2, &tp->pci_cfg_space.io_base_h); -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_2, &tp->pci_cfg_space.mem_base_l); -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_2 + 2, &tp->pci_cfg_space.mem_base_h); -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_3, &tp->pci_cfg_space.resv_0x1c_l); -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_3 + 2, &tp->pci_cfg_space.resv_0x1c_h); -+ pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tp->pci_cfg_space.ilr); -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_4, &tp->pci_cfg_space.resv_0x20_l); -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_4 + 2, &tp->pci_cfg_space.resv_0x20_h); -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_5, &tp->pci_cfg_space.resv_0x24_l); -+ pci_read_config_word(pdev, PCI_BASE_ADDRESS_5 + 2, &tp->pci_cfg_space.resv_0x24_h); -+ pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->pci_cfg_space.resv_0x2c_l); -+ pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID + 2, &tp->pci_cfg_space.resv_0x2c_h); -+ tp->pci_cfg_space.pci_sn_l = rtl8168_csi_read(tp, PCI_DEVICE_SERIAL_NUMBER); -+ tp->pci_cfg_space.pci_sn_h = rtl8168_csi_read(tp, PCI_DEVICE_SERIAL_NUMBER + 4); -+ -+ tp->pci_cfg_is_read = 1; -+ } -+ -+ rtl8168_dsm(dev, DSM_MAC_INIT); -+ -+ /* Set Rx packet filter */ -+ rtl8168_hw_set_rx_packet_filter(dev); -+ -+#ifdef ENABLE_DASH_SUPPORT -+ if (tp->DASH) -+ NICChkTypeEnableDashInterrupt(tp); -+#endif -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ if (aspm) { -+ RTL_W8(Config5, RTL_R8(Config5) | BIT_0); -+ RTL_W8(Config2, RTL_R8(Config2) | BIT_7); -+ } else { -+ RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7); -+ RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0); -+ } -+ break; -+ } -+ -+ RTL_W8(Cfg9346, Cfg9346_Lock); -+ -+ udelay(10); -+} -+ -+static void -+rtl8168_hw_start(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ rtl8168_hw_config(dev); -+ -+ RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); -+ -+ rtl8168_enable_hw_interrupt(tp, ioaddr); -+} -+ -+ -+static int -+rtl8168_change_mtu(struct net_device *dev, -+ int new_mtu) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ int max_mtu; -+ int ret = 0; -+ unsigned long flags; -+ -+ if (tp->mcfg == CFG_METHOD_DEFAULT) -+ max_mtu = ETH_DATA_LEN; -+ else -+ max_mtu = tp->max_jumbo_frame_size - ETH_HLEN - 8; -+ -+ if (new_mtu < ETH_ZLEN) -+ return -EINVAL; -+ else if (new_mtu > max_mtu) -+ new_mtu = max_mtu; -+ -+ if (!netif_running(dev)) -+ goto out; -+ -+ rtl8168_down(dev); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ dev->mtu = new_mtu; -+ -+ rtl8168_set_rxbufsize(tp, dev); -+ -+ ret = rtl8168_init_ring(dev); -+ -+ if (ret < 0) { -+ spin_unlock_irqrestore(&tp->lock, flags); -+ goto out; -+ } -+ -+#ifdef CONFIG_R8168_NAPI -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ RTL_NAPI_ENABLE(dev, &tp->napi); -+#endif -+#endif//CONFIG_R8168_NAPI -+ -+ netif_stop_queue(dev); -+ netif_carrier_off(dev); -+ rtl8168_hw_config(dev); -+ spin_unlock_irqrestore(&tp->lock, flags); -+ rtl8168_set_speed(dev, tp->autoneg, tp->speed, tp->duplex); -+ -+ mod_timer(&tp->esd_timer, jiffies + RTL8168_ESD_TIMEOUT); -+ mod_timer(&tp->link_timer, jiffies + RTL8168_LINK_TIMEOUT); -+ -+out: -+ return ret; -+} -+ -+static inline void -+rtl8168_make_unusable_by_asic(struct RxDesc *desc) -+{ -+ desc->addr = 0x0badbadbadbadbadull; -+ desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); -+} -+ -+static void -+rtl8168_free_rx_skb(struct rtl8168_private *tp, -+ struct sk_buff **sk_buff, -+ struct RxDesc *desc) -+{ -+ struct pci_dev *pdev = tp->pci_dev; -+ -+ pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz, -+ PCI_DMA_FROMDEVICE); -+ dev_kfree_skb(*sk_buff); -+ *sk_buff = NULL; -+ rtl8168_make_unusable_by_asic(desc); -+} -+ -+static inline void -+rtl8168_mark_to_asic(struct RxDesc *desc, -+ u32 rx_buf_sz) -+{ -+ u32 eor = le32_to_cpu(desc->opts1) & RingEnd; -+ -+ desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); -+} -+ -+static inline void -+rtl8168_map_to_asic(struct RxDesc *desc, -+ dma_addr_t mapping, -+ u32 rx_buf_sz) -+{ -+ desc->addr = cpu_to_le64(mapping); -+ wmb(); -+ rtl8168_mark_to_asic(desc, rx_buf_sz); -+} -+ -+static int -+rtl8168_alloc_rx_skb(struct pci_dev *pdev, -+ struct sk_buff **sk_buff, -+ struct RxDesc *desc, -+ int rx_buf_sz) -+{ -+ struct sk_buff *skb; -+ dma_addr_t mapping; -+ int ret = 0; -+ -+ skb = dev_alloc_skb(rx_buf_sz + RTK_RX_ALIGN); -+ if (!skb) -+ goto err_out; -+ -+ skb_reserve(skb, RTK_RX_ALIGN); -+ *sk_buff = skb; -+ -+ mapping = pci_map_single(pdev, skb->data, rx_buf_sz, -+ PCI_DMA_FROMDEVICE); -+ -+ rtl8168_map_to_asic(desc, mapping, rx_buf_sz); -+ -+out: -+ return ret; -+ -+err_out: -+ ret = -ENOMEM; -+ rtl8168_make_unusable_by_asic(desc); -+ goto out; -+} -+ -+static void -+rtl8168_rx_clear(struct rtl8168_private *tp) -+{ -+ int i; -+ -+ for (i = 0; i < NUM_RX_DESC; i++) { -+ if (tp->Rx_skbuff[i]) -+ rtl8168_free_rx_skb(tp, tp->Rx_skbuff + i, -+ tp->RxDescArray + i); -+ } -+} -+ -+static u32 -+rtl8168_rx_fill(struct rtl8168_private *tp, -+ struct net_device *dev, -+ u32 start, -+ u32 end) -+{ -+ u32 cur; -+ -+ for (cur = start; end - cur > 0; cur++) { -+ int ret, i = cur % NUM_RX_DESC; -+ -+ if (tp->Rx_skbuff[i]) -+ continue; -+ -+ ret = rtl8168_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i, -+ tp->RxDescArray + i, tp->rx_buf_sz); -+ if (ret < 0) -+ break; -+ } -+ return cur - start; -+} -+ -+static inline void -+rtl8168_mark_as_last_descriptor(struct RxDesc *desc) -+{ -+ desc->opts1 |= cpu_to_le32(RingEnd); -+} -+ -+static void -+rtl8168_desc_addr_fill(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if (!tp->TxPhyAddr || !tp->RxPhyAddr) -+ return; -+ -+ RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_BIT_MASK(32))); -+ RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32)); -+ RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_BIT_MASK(32))); -+ RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32)); -+} -+ -+static void -+rtl8168_tx_desc_init(struct rtl8168_private *tp) -+{ -+ int i = 0; -+ -+ memset(tp->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); -+ -+ for (i = 0; i < NUM_TX_DESC; i++) { -+ if (i == (NUM_TX_DESC - 1)) -+ tp->TxDescArray[i].opts1 = cpu_to_le32(RingEnd); -+ } -+} -+ -+static void -+rtl8168_rx_desc_offset0_init(struct rtl8168_private *tp, int own) -+{ -+ int i = 0; -+ int ownbit = 0; -+ -+ if (own) -+ ownbit = DescOwn; -+ -+ for (i = 0; i < NUM_RX_DESC; i++) { -+ if (i == (NUM_RX_DESC - 1)) -+ tp->RxDescArray[i].opts1 = cpu_to_le32((ownbit | RingEnd) | (unsigned long)tp->rx_buf_sz); -+ else -+ tp->RxDescArray[i].opts1 = cpu_to_le32(ownbit | (unsigned long)tp->rx_buf_sz); -+ } -+} -+ -+static void -+rtl8168_rx_desc_init(struct rtl8168_private *tp) -+{ -+ memset(tp->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); -+} -+ -+static int -+rtl8168_init_ring(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ rtl8168_init_ring_indexes(tp); -+ -+ memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); -+ memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *)); -+ -+ rtl8168_tx_desc_init(tp); -+ rtl8168_rx_desc_init(tp); -+ -+ if (rtl8168_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC) -+ goto err_out; -+ -+ rtl8168_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); -+ -+ return 0; -+ -+err_out: -+ rtl8168_rx_clear(tp); -+ return -ENOMEM; -+} -+ -+static void -+rtl8168_unmap_tx_skb(struct pci_dev *pdev, -+ struct ring_info *tx_skb, -+ struct TxDesc *desc) -+{ -+ unsigned int len = tx_skb->len; -+ -+ pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE); -+ desc->opts1 = 0x00; -+ desc->opts2 = 0x00; -+ desc->addr = 0x00; -+ tx_skb->len = 0; -+} -+ -+static void -+rtl8168_tx_clear(struct rtl8168_private *tp) -+{ -+ unsigned int i; -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) -+ struct net_device *dev = tp->dev; -+#endif -+ -+ for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) { -+ unsigned int entry = i % NUM_TX_DESC; -+ struct ring_info *tx_skb = tp->tx_skb + entry; -+ unsigned int len = tx_skb->len; -+ -+ if (len) { -+ struct sk_buff *skb = tx_skb->skb; -+ -+ rtl8168_unmap_tx_skb(tp->pci_dev, tx_skb, -+ tp->TxDescArray + entry); -+ if (skb) { -+ dev_kfree_skb(skb); -+ tx_skb->skb = NULL; -+ } -+ RTLDEV->stats.tx_dropped++; -+ } -+ } -+ tp->cur_tx = tp->dirty_tx = 0; -+} -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static void rtl8168_schedule_work(struct net_device *dev, void (*task)(void *)) -+{ -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ INIT_WORK(&tp->task, task, dev); -+ schedule_delayed_work(&tp->task, 4); -+#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+} -+ -+static void rtl8168_cancel_schedule_work(struct net_device *dev) -+{ -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ cancel_work_sync(&tp->task); -+#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+} -+ -+#else -+static void rtl8168_schedule_work(struct net_device *dev, work_func_t task) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ INIT_DELAYED_WORK(&tp->task, task); -+ schedule_delayed_work(&tp->task, 4); -+} -+ -+static void rtl8168_cancel_schedule_work(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ cancel_delayed_work_sync(&tp->task); -+} -+#endif -+ -+static void -+rtl8168_wait_for_quiescence(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ synchronize_irq(dev->irq); -+ -+ /* Wait for any pending NAPI task to complete */ -+#ifdef CONFIG_R8168_NAPI -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ RTL_NAPI_DISABLE(dev, &tp->napi); -+#endif -+#endif//CONFIG_R8168_NAPI -+ -+ rtl8168_irq_mask_and_ack(tp, ioaddr); -+ -+#ifdef CONFIG_R8168_NAPI -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ RTL_NAPI_ENABLE(dev, &tp->napi); -+#endif -+#endif//CONFIG_R8168_NAPI -+} -+ -+#if 0 -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static void rtl8168_reinit_task(void *_data) -+#else -+static void rtl8168_reinit_task(struct work_struct *work) -+#endif -+{ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ struct net_device *dev = _data; -+#else -+ struct rtl8168_private *tp = -+ container_of(work, struct rtl8168_private, task.work); -+ struct net_device *dev = tp->dev; -+#endif -+ int ret; -+ -+ if (netif_running(dev)) { -+ rtl8168_wait_for_quiescence(dev); -+ rtl8168_close(dev); -+ } -+ -+ ret = rtl8168_open(dev); -+ if (unlikely(ret < 0)) { -+ if (net_ratelimit()) { -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ if (netif_msg_drv(tp)) { -+ printk(PFX KERN_ERR -+ "%s: reinit failure (status = %d)." -+ " Rescheduling.\n", dev->name, ret); -+ } -+ } -+ rtl8168_schedule_work(dev, rtl8168_reinit_task); -+ } -+} -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static void rtl8168_reset_task(void *_data) -+{ -+ struct net_device *dev = _data; -+ struct rtl8168_private *tp = netdev_priv(dev); -+#else -+static void rtl8168_reset_task(struct work_struct *work) -+{ -+ struct rtl8168_private *tp = -+ container_of(work, struct rtl8168_private, task.work); -+ struct net_device *dev = tp->dev; -+#endif -+ unsigned long flags; -+ -+ if (!netif_running(dev)) -+ return; -+ -+ rtl8168_wait_for_quiescence(dev); -+ -+ rtl8168_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ rtl8168_tx_clear(tp); -+ -+ if (tp->dirty_rx == tp->cur_rx) { -+ rtl8168_rx_clear(tp); -+ rtl8168_init_ring(dev); -+ rtl8168_set_speed(dev, tp->autoneg, tp->speed, tp->duplex); -+ spin_unlock_irqrestore(&tp->lock, flags); -+ } else { -+ spin_unlock_irqrestore(&tp->lock, flags); -+ if (net_ratelimit()) { -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ if (netif_msg_intr(tp)) { -+ printk(PFX KERN_EMERG -+ "%s: Rx buffers shortage\n", dev->name); -+ } -+ } -+ rtl8168_schedule_work(dev, rtl8168_reset_task); -+ } -+} -+ -+static void -+rtl8168_tx_timeout(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ netif_stop_queue(dev); -+ netif_carrier_off(dev); -+ rtl8168_hw_reset(dev); -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ /* Let's wait a bit while any (async) irq lands on */ -+ rtl8168_schedule_work(dev, rtl8168_reset_task); -+} -+ -+static int -+rtl8168_xmit_frags(struct rtl8168_private *tp, -+ struct sk_buff *skb, -+ u32 opts1, -+ u32 opts2) -+{ -+ struct skb_shared_info *info = skb_shinfo(skb); -+ unsigned int cur_frag, entry; -+ struct TxDesc *txd = NULL; -+ -+ entry = tp->cur_tx; -+ for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { -+ skb_frag_t *frag = info->frags + cur_frag; -+ dma_addr_t mapping; -+ u32 status, len; -+ void *addr; -+ -+ entry = (entry + 1) % NUM_TX_DESC; -+ -+ txd = tp->TxDescArray + entry; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) -+ len = frag->size; -+ addr = ((void *) page_address(frag->page)) + frag->page_offset; -+#else -+ len = skb_frag_size(frag); -+ addr = skb_frag_address(frag); -+#endif -+ mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); -+ -+ /* anti gcc 2.95.3 bugware (sic) */ -+ status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); -+ -+ txd->addr = cpu_to_le64(mapping); -+ -+ tp->tx_skb[entry].len = len; -+ -+ txd->opts1 = cpu_to_le32(status); -+ txd->opts2 = cpu_to_le32(opts2); -+ } -+ -+ if (cur_frag) { -+ tp->tx_skb[entry].skb = skb; -+ wmb(); -+ txd->opts1 |= cpu_to_le32(LastFrag); -+ } -+ -+ return cur_frag; -+} -+ -+static inline u32 -+rtl8168_tx_csum(struct sk_buff *skb, -+ struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -+ const struct iphdr *ip = skb->nh.iph; -+#else -+ const struct iphdr *ip = ip_hdr(skb); -+#endif -+ u32 csum_cmd = 0; -+ -+ if (skb->ip_summed == CHECKSUM_PARTIAL) { -+ if (ip->protocol == IPPROTO_TCP) -+ csum_cmd = tp->tx_tcp_csum_cmd; -+ else if (ip->protocol == IPPROTO_UDP) -+ csum_cmd = tp->tx_udp_csum_cmd; -+ else if (ip->protocol == IPPROTO_IP) -+ csum_cmd = tp->tx_ip_csum_cmd; -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ else -+ WARN_ON(1); /* we need a WARN() */ -+#endif -+ } -+ -+ if (tp->ShortPacketSwChecksum && skb->len < 60) { -+ if (csum_cmd != 0) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,7) -+ skb_checksum_help(&skb, 0); -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) -+ skb_checksum_help(skb, 0); -+#else -+ skb_checksum_help(skb); -+#endif -+ csum_cmd = 0; -+ } -+ } -+ -+ return csum_cmd; -+} -+ -+static void -+rtl8168_sw_padding_short_pkt(struct rtl8168_private *tp, -+ struct sk_buff *skb, -+ u32 opts1, -+ u32 opts2) -+{ -+ unsigned int entry; -+ dma_addr_t mapping; -+ u32 status, len; -+ void *addr; -+ struct TxDesc *txd = NULL; -+ -+ if (skb->len >= ETH_ZLEN) return; -+ -+ entry = tp->cur_tx; -+ do { -+ entry = (entry + 1) % NUM_TX_DESC; -+ -+ txd = tp->TxDescArray + entry; -+ len = ETH_ZLEN - skb->len; -+ addr = tp->ShortPacketEmptyBuffer; -+ mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); -+ -+ status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); -+ -+ txd->addr = cpu_to_le64(mapping); -+ -+ txd->opts1 = cpu_to_le32(status); -+ txd->opts2 = cpu_to_le32(opts2); -+ -+ wmb(); -+ txd->opts1 |= cpu_to_le32(LastFrag); -+ } while(FALSE); -+} -+ -+ -+static int -+rtl8168_start_xmit(struct sk_buff *skb, -+ struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned int frags, entry; -+ struct TxDesc *txd; -+ void __iomem *ioaddr = tp->mmio_addr; -+ dma_addr_t mapping; -+ u32 len; -+ u32 opts1; -+ u32 opts2; -+ int ret = NETDEV_TX_OK; -+ unsigned long flags, large_send; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { -+ if (netif_msg_drv(tp)) { -+ printk(KERN_ERR -+ "%s: BUG! Tx Ring full when queue awake!\n", -+ dev->name); -+ } -+ goto err_stop; -+ } -+ -+ entry = tp->cur_tx % NUM_TX_DESC; -+ txd = tp->TxDescArray + entry; -+ -+ if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) -+ goto err_stop; -+ -+ opts1 = DescOwn; -+ opts2 = rtl8168_tx_vlan_tag(tp, skb); -+ -+ large_send = 0; -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ if (dev->features & NETIF_F_TSO) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) -+ u32 mss = skb_shinfo(skb)->tso_size; -+#else -+ u32 mss = skb_shinfo(skb)->gso_size; -+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) -+ -+ /* TCP Segmentation Offload (or TCP Large Send) */ -+ if (mss) { -+ if ((tp->mcfg == CFG_METHOD_1) || -+ (tp->mcfg == CFG_METHOD_2) || -+ (tp->mcfg == CFG_METHOD_3)) { -+ opts1 |= LargeSend | ((mss & MSSMask) << 16); -+ } else if ((tp->mcfg == CFG_METHOD_11) || -+ (tp->mcfg == CFG_METHOD_12) || -+ (tp->mcfg == CFG_METHOD_13)) { -+ opts2 |= LargeSend_DP | ((mss & MSSMask) << 18); -+ } else { -+ opts1 |= LargeSend; -+ opts2 |= (mss & MSSMask) << 18; -+ } -+ large_send = 1; -+ } -+ } -+#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ -+ if (large_send == 0) { -+ if (dev->features & NETIF_F_IP_CSUM) { -+ if ((tp->mcfg == CFG_METHOD_1) || (tp->mcfg == CFG_METHOD_2) || (tp->mcfg == CFG_METHOD_3)) -+ opts1 |= rtl8168_tx_csum(skb, dev); -+ else -+ opts2 |= rtl8168_tx_csum(skb, dev); -+ } -+ } -+ -+ frags = rtl8168_xmit_frags(tp, skb, opts1, opts2); -+ if (frags) { -+ len = skb_headlen(skb); -+ opts1 |= FirstFrag; -+ } else { -+ len = skb->len; -+ -+ tp->tx_skb[entry].skb = skb; -+ -+ if (tp->UseSwPaddingShortPkt && len < 60) { -+ rtl8168_sw_padding_short_pkt(tp, skb, opts1, opts2); -+ opts1 |= FirstFrag; -+ frags++; -+ } else { -+ opts1 |= FirstFrag | LastFrag; -+ } -+ } -+ -+ opts1 |= len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); -+ mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE); -+ tp->tx_skb[entry].len = len; -+ txd->addr = cpu_to_le64(mapping); -+ txd->opts2 = cpu_to_le32(opts2); -+ txd->opts1 = cpu_to_le32(opts1&~DescOwn); -+ wmb(); -+ txd->opts1 = cpu_to_le32(opts1); -+ -+ dev->trans_start = jiffies; -+ -+ tp->cur_tx += frags + 1; -+ -+ wmb(); -+ -+ RTL_W8(TxPoll, NPQ); /* set polling bit */ -+ -+ if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { -+ netif_stop_queue(dev); -+ smp_rmb(); -+ if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) -+ netif_wake_queue(dev); -+ } -+ -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+out: -+ return ret; -+err_stop: -+ netif_stop_queue(dev); -+ ret = NETDEV_TX_BUSY; -+ RTLDEV->stats.tx_dropped++; -+ -+ spin_unlock_irqrestore(&tp->lock, flags); -+ goto out; -+} -+ -+static void -+rtl8168_tx_interrupt(struct net_device *dev, -+ struct rtl8168_private *tp, -+ void __iomem *ioaddr) -+{ -+ unsigned int dirty_tx, tx_left; -+ -+ assert(dev != NULL); -+ assert(tp != NULL); -+ assert(ioaddr != NULL); -+ -+ dirty_tx = tp->dirty_tx; -+ smp_rmb(); -+ tx_left = tp->cur_tx - dirty_tx; -+ -+ while (tx_left > 0) { -+ unsigned int entry = dirty_tx % NUM_TX_DESC; -+ struct ring_info *tx_skb = tp->tx_skb + entry; -+ u32 len = tx_skb->len; -+ u32 status; -+ -+ rmb(); -+ status = le32_to_cpu(tp->TxDescArray[entry].opts1); -+ if (status & DescOwn) -+ break; -+ -+ RTLDEV->stats.tx_bytes += len; -+ RTLDEV->stats.tx_packets++; -+ -+ rtl8168_unmap_tx_skb(tp->pci_dev, -+ tx_skb, -+ tp->TxDescArray + entry); -+ -+ if (tx_skb->skb!=NULL) { -+ dev_kfree_skb_irq(tx_skb->skb); -+ tx_skb->skb = NULL; -+ } -+ dirty_tx++; -+ tx_left--; -+ } -+ -+ if (tp->dirty_tx != dirty_tx) { -+ tp->dirty_tx = dirty_tx; -+ smp_wmb(); -+ if (netif_queue_stopped(dev) && -+ (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { -+ netif_wake_queue(dev); -+ } -+ smp_rmb(); -+ if (tp->cur_tx != dirty_tx) -+ RTL_W8(TxPoll, NPQ); -+ } -+} -+ -+static inline int -+rtl8168_fragmented_frame(u32 status) -+{ -+ return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); -+} -+ -+static inline void -+rtl8168_rx_csum(struct rtl8168_private *tp, -+ struct sk_buff *skb, -+ struct RxDesc *desc) -+{ -+ u32 opts1 = le32_to_cpu(desc->opts1); -+ u32 opts2 = le32_to_cpu(desc->opts2); -+ u32 status = opts1 & RxProtoMask; -+ -+ if ((tp->mcfg == CFG_METHOD_1) || -+ (tp->mcfg == CFG_METHOD_2) || -+ (tp->mcfg == CFG_METHOD_3)) { -+ /* rx csum offload for RTL8168B/8111B */ -+ if (((status == RxProtoTCP) && !(opts1 & RxTCPF)) || -+ ((status == RxProtoUDP) && !(opts1 & RxUDPF)) || -+ ((status == RxProtoIP) && !(opts1 & RxIPF))) -+ skb->ip_summed = CHECKSUM_UNNECESSARY; -+ else -+ skb->ip_summed = CHECKSUM_NONE; -+ } else { -+ /* rx csum offload for RTL8168C/8111C and RTL8168CP/8111CP */ -+ if (((status == RxTCPT) && !(opts1 & RxTCPF)) || -+ ((status == RxUDPT) && !(opts1 & RxUDPF)) || -+ ((status == 0) && (opts2 & RxV4F) && !(opts1 & RxIPF))) -+ skb->ip_summed = CHECKSUM_UNNECESSARY; -+ else -+ skb->ip_summed = CHECKSUM_NONE; -+ } -+} -+ -+static inline int -+rtl8168_try_rx_copy(struct sk_buff **sk_buff, -+ int pkt_size, -+ struct RxDesc *desc, -+ int rx_buf_sz) -+{ -+ int ret = -1; -+ -+ if (pkt_size < rx_copybreak) { -+ struct sk_buff *skb; -+ -+ skb = dev_alloc_skb(pkt_size + RTK_RX_ALIGN); -+ if (skb) { -+ u8 *data; -+ -+ data = sk_buff[0]->data; -+ skb_reserve(skb, RTK_RX_ALIGN); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37) -+ prefetch(data - RTK_RX_ALIGN); -+#endif -+ eth_copy_and_sum(skb, data, pkt_size, 0); -+ *sk_buff = skb; -+ rtl8168_mark_to_asic(desc, rx_buf_sz); -+ ret = 0; -+ } -+ } -+ return ret; -+} -+ -+static inline void -+rtl8168_rx_skb(struct rtl8168_private *tp, -+ struct sk_buff *skb) -+{ -+#ifdef CONFIG_R8168_NAPI -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) -+ netif_receive_skb(skb); -+#else -+ napi_gro_receive(&tp->napi, skb); -+#endif -+#else -+ netif_rx(skb); -+#endif -+} -+ -+static int -+rtl8168_rx_interrupt(struct net_device *dev, -+ struct rtl8168_private *tp, -+ void __iomem *ioaddr, u32 budget) -+{ -+ unsigned int cur_rx, rx_left; -+ unsigned int delta, count = 0; -+ unsigned int entry; -+ struct RxDesc *desc; -+ u32 status; -+ u32 rx_quota = RTL_RX_QUOTA(dev, budget); -+ -+ assert(dev != NULL); -+ assert(tp != NULL); -+ assert(ioaddr != NULL); -+ -+ if ((tp->RxDescArray == NULL) || (tp->Rx_skbuff == NULL)) -+ goto rx_out; -+ -+ cur_rx = tp->cur_rx; -+ entry = cur_rx % NUM_RX_DESC; -+ desc = tp->RxDescArray + entry; -+ rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; -+ rx_left = rtl8168_rx_quota(rx_left, (u32)rx_quota); -+ -+ for (; rx_left > 0; rx_left--) { -+ rmb(); -+ status = le32_to_cpu(desc->opts1); -+ if (status & DescOwn) -+ break; -+ if (unlikely(status & RxRES)) { -+ if (netif_msg_rx_err(tp)) { -+ printk(KERN_INFO -+ "%s: Rx ERROR. status = %08x\n", -+ dev->name, status); -+ } -+ -+ RTLDEV->stats.rx_errors++; -+ -+ if (status & (RxRWT | RxRUNT)) -+ RTLDEV->stats.rx_length_errors++; -+ if (status & RxCRC) -+ RTLDEV->stats.rx_crc_errors++; -+ rtl8168_mark_to_asic(desc, tp->rx_buf_sz); -+ } else { -+ struct sk_buff *skb = tp->Rx_skbuff[entry]; -+ int pkt_size = (status & 0x00003FFF) - 4; -+ void (*pci_action)(struct pci_dev *, dma_addr_t, -+ size_t, int) = pci_dma_sync_single_for_device; -+ -+ /* -+ * The driver does not support incoming fragmented -+ * frames. They are seen as a symptom of over-mtu -+ * sized frames. -+ */ -+ if (unlikely(rtl8168_fragmented_frame(status))) { -+ RTLDEV->stats.rx_dropped++; -+ RTLDEV->stats.rx_length_errors++; -+ rtl8168_mark_to_asic(desc, tp->rx_buf_sz); -+ continue; -+ } -+ -+ if (tp->cp_cmd & RxChkSum) -+ rtl8168_rx_csum(tp, skb, desc); -+ -+ pci_dma_sync_single_for_cpu(tp->pci_dev, -+ le64_to_cpu(desc->addr), tp->rx_buf_sz, -+ PCI_DMA_FROMDEVICE); -+ -+ if (rtl8168_try_rx_copy(&skb, pkt_size, desc, -+ tp->rx_buf_sz)) { -+ pci_action = pci_unmap_single; -+ tp->Rx_skbuff[entry] = NULL; -+ } -+ -+ pci_action(tp->pci_dev, le64_to_cpu(desc->addr), -+ tp->rx_buf_sz, PCI_DMA_FROMDEVICE); -+ -+ skb->dev = dev; -+ skb_put(skb, pkt_size); -+ skb->protocol = eth_type_trans(skb, dev); -+ -+ if (rtl8168_rx_vlan_skb(tp, desc, skb) < 0) -+ rtl8168_rx_skb(tp, skb); -+ -+ dev->last_rx = jiffies; -+ RTLDEV->stats.rx_bytes += pkt_size; -+ RTLDEV->stats.rx_packets++; -+ } -+ -+ cur_rx++; -+ entry = cur_rx % NUM_RX_DESC; -+ desc = tp->RxDescArray + entry; -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37) -+ prefetch(desc); -+#endif -+ } -+ -+ count = cur_rx - tp->cur_rx; -+ tp->cur_rx = cur_rx; -+ -+ delta = rtl8168_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx); -+ if (!delta && count && netif_msg_intr(tp)) -+ printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name); -+ tp->dirty_rx += delta; -+ -+ /* -+ * FIXME: until there is periodic timer to try and refill the ring, -+ * a temporary shortage may definitely kill the Rx process. -+ * - disable the asic to try and avoid an overflow and kick it again -+ * after refill ? -+ * - how do others driver handle this condition (Uh oh...). -+ */ -+ if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp)) -+ printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name); -+ -+rx_out: -+ return count; -+} -+ -+/* -+ *The interrupt handler does all of the Rx thread work and cleans up after -+ *the Tx thread. -+ */ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+static irqreturn_t rtl8168_interrupt(int irq, void *dev_instance, struct pt_regs *regs) -+#else -+static irqreturn_t rtl8168_interrupt(int irq, void *dev_instance) -+#endif -+{ -+ struct net_device *dev = (struct net_device *) dev_instance; -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ int status; -+ int handled = 0; -+ -+ do { -+ status = RTL_R16(IntrStatus); -+ -+ if(!(tp->features & RTL_FEATURE_MSI)) { -+ /* hotplug/major error/no more work/shared irq */ -+ if ((status == 0xFFFF) || !status) -+ break; -+ -+ if (!(status & (tp->intr_mask | tp->timer_intr_mask))) -+ break; -+ -+ if (unlikely(!netif_running(dev))) { -+ break; -+ } -+ } -+ -+ handled = 1; -+ -+ rtl8168_disable_hw_interrupt(tp, ioaddr); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_9: -+ case CFG_METHOD_10: -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ case CFG_METHOD_14: -+ case CFG_METHOD_15: -+ case CFG_METHOD_16: -+ case CFG_METHOD_17: -+ case CFG_METHOD_18: -+ case CFG_METHOD_19: -+ case CFG_METHOD_20: -+ case CFG_METHOD_21: -+ case CFG_METHOD_22: -+ case CFG_METHOD_23: -+ case CFG_METHOD_24: -+ case CFG_METHOD_25: -+ case CFG_METHOD_26: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ /* RX_OVERFLOW RE-START mechanism now HW handles it automatically*/ -+ RTL_W16(IntrStatus, status&~RxFIFOOver); -+ break; -+ default: -+ RTL_W16(IntrStatus, status); -+ break; -+ } -+ -+ //Work around for rx fifo overflow -+ if (unlikely(status & RxFIFOOver)) { -+ if (tp->mcfg == CFG_METHOD_1) { -+ netif_stop_queue(dev); -+ udelay(300); -+ rtl8168_hw_reset(dev); -+ rtl8168_tx_clear(tp); -+ rtl8168_rx_clear(tp); -+ rtl8168_init_ring(dev); -+ rtl8168_hw_start(dev); -+ netif_wake_queue(dev); -+ } -+ } -+ -+#ifdef ENABLE_DASH_SUPPORT -+ if ( tp->DASH ) { -+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) { -+ u8 DashIntType2Status; -+ -+ DashIntType2Status = RTL_R8(IBISR0); -+ if (DashIntType2Status & ISRIMR_DASH_TYPE2_ROK) { -+ tp->RcvFwDashOkEvt = TRUE; -+ } -+ if (DashIntType2Status & ISRIMR_DASH_TYPE2_TOK) { -+ tp->SendFwHostOkEvt = TRUE; -+ } -+ if(DashIntType2Status & ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE) { -+ tp->DashFwDisableRx = TRUE; -+ } -+ -+ RTL_W8(IBISR0, DashIntType2Status); -+ -+ //hau_dbg -+ //printk("status = %X DashIntType2Status = %X.\n", status, DashIntType2Status); -+ } else { -+ if (IntrStatus & ISRIMR_DP_REQSYS_OK) { -+ tp->RcvFwReqSysOkEvt = TRUE; -+ } -+ if (IntrStatus & ISRIMR_DP_DASH_OK) { -+ tp->RcvFwDashOkEvt = TRUE; -+ } -+ if (IntrStatus & ISRIMR_DP_HOST_OK) { -+ tp->SendFwHostOkEvt = TRUE; -+ } -+ } -+ } -+#endif -+ -+#ifdef CONFIG_R8168_NAPI -+ if (status & tp->intr_mask || tp->keep_intr_cnt > 0) { -+ if (tp->keep_intr_cnt > 0) tp->keep_intr_cnt--; -+ -+ if (likely(RTL_NETIF_RX_SCHEDULE_PREP(dev, &tp->napi))) -+ __RTL_NETIF_RX_SCHEDULE(dev, &tp->napi); -+ else if (netif_msg_intr(tp)) -+ printk(KERN_INFO "%s: interrupt %04x in poll\n", -+ dev->name, status); -+ } else { -+ tp->keep_intr_cnt = RTK_KEEP_INTERRUPT_COUNT; -+ rtl8168_switch_to_hw_interrupt(tp, ioaddr); -+ } -+#else -+ if (status & tp->intr_mask || tp->keep_intr_cnt > 0) { -+ if (tp->keep_intr_cnt > 0) tp->keep_intr_cnt--; -+ -+ rtl8168_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); -+ rtl8168_tx_interrupt(dev, tp, ioaddr); -+ -+#ifdef ENABLE_DASH_SUPPORT -+ if ( tp->DASH ) { -+ struct net_device *dev = tp->dev; -+ -+ HandleDashInterrupt(dev); -+ } -+#endif -+ -+ rtl8168_switch_to_timer_interrupt(tp, ioaddr); -+ } else { -+ tp->keep_intr_cnt = RTK_KEEP_INTERRUPT_COUNT; -+ rtl8168_switch_to_hw_interrupt(tp, ioaddr); -+ } -+#endif -+ -+ } while (false); -+ -+ return IRQ_RETVAL(handled); -+} -+ -+#ifdef CONFIG_R8168_NAPI -+static int rtl8168_poll(napi_ptr napi, napi_budget budget) -+{ -+ struct rtl8168_private *tp = RTL_GET_PRIV(napi, struct rtl8168_private); -+ void __iomem *ioaddr = tp->mmio_addr; -+ RTL_GET_NETDEV(tp) -+ unsigned int work_to_do = RTL_NAPI_QUOTA(budget, dev); -+ unsigned int work_done; -+ unsigned long flags; -+ -+ work_done = rtl8168_rx_interrupt(dev, tp, ioaddr, (u32) budget); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ rtl8168_tx_interrupt(dev, tp, ioaddr); -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ RTL_NAPI_QUOTA_UPDATE(dev, work_done, budget); -+ -+ if (work_done < work_to_do) { -+#ifdef ENABLE_DASH_SUPPORT -+ if ( tp->DASH ) { -+ struct net_device *dev = tp->dev; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ HandleDashInterrupt(dev); -+ spin_unlock_irqrestore(&tp->lock, flags); -+ } -+#endif -+ -+ RTL_NETIF_RX_COMPLETE(dev, napi); -+ /* -+ * 20040426: the barrier is not strictly required but the -+ * behavior of the irq handler could be less predictable -+ * without it. Btw, the lack of flush for the posted pci -+ * write is safe - FR -+ */ -+ smp_wmb(); -+ -+ rtl8168_switch_to_timer_interrupt(tp, ioaddr); -+ } -+ -+ return RTL_NAPI_RETURN_VALUE; -+} -+#endif//CONFIG_R8168_NAPI -+ -+static void rtl8168_sleep_rx_enable(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ void __iomem *ioaddr = tp->mmio_addr; -+ -+ if ((tp->mcfg == CFG_METHOD_1) || (tp->mcfg == CFG_METHOD_2)) { -+ RTL_W8(ChipCmd, CmdReset); -+ rtl8168_rx_desc_offset0_init(tp, 0); -+ RTL_W8(ChipCmd, CmdRxEnb); -+ } else if (tp->mcfg == CFG_METHOD_14 || tp->mcfg == CFG_METHOD_15) { -+ rtl8168_ephy_write(ioaddr, 0x19, 0xFF64); -+ RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); -+ } -+} -+ -+static void rtl8168_down(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ unsigned long flags; -+ -+ rtl8168_delete_esd_timer(dev, &tp->esd_timer); -+ -+ rtl8168_delete_link_timer(dev, &tp->link_timer); -+ -+#ifdef CONFIG_R8168_NAPI -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23) -+ napi_disable(&tp->napi); -+#endif -+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)) && (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)) -+ netif_poll_disable(dev); -+#endif -+#endif -+ -+ netif_stop_queue(dev); -+ -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,11) -+ /* Give a racing hard_start_xmit a few cycles to complete. */ -+ synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ -+#endif -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ netif_carrier_off(dev); -+ -+ rtl8168_dsm(dev, DSM_IF_DOWN); -+ -+ rtl8168_hw_reset(dev); -+ -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ synchronize_irq(dev->irq); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ rtl8168_tx_clear(tp); -+ -+ rtl8168_rx_clear(tp); -+ -+ rtl8168_sleep_rx_enable(dev); -+ -+ spin_unlock_irqrestore(&tp->lock, flags); -+} -+ -+static int rtl8168_close(struct net_device *dev) -+{ -+ struct rtl8168_private *tp = netdev_priv(dev); -+ struct pci_dev *pdev = tp->pci_dev; -+ -+ if (tp->TxDescArray!=NULL && tp->RxDescArray!=NULL) { -+ rtl8168_cancel_schedule_work(dev); -+ -+ rtl8168_down(dev); -+ -+ rtl8168_hw_d3_para(dev); -+ -+ rtl8168_powerdown_pll(dev); -+ -+ free_irq(dev->irq, dev); -+ -+ pci_free_consistent(pdev, R8168_RX_RING_BYTES, tp->RxDescArray, -+ tp->RxPhyAddr); -+ pci_free_consistent(pdev, R8168_TX_RING_BYTES, tp->TxDescArray, -+ tp->TxPhyAddr); -+ tp->TxDescArray = NULL; -+ tp->RxDescArray = NULL; -+ -+ if (tp->tally_vaddr != NULL) { -+ pci_free_consistent(pdev, sizeof(*tp->tally_vaddr), tp->tally_vaddr, tp->tally_paddr); -+ tp->tally_vaddr = NULL; -+ } -+ -+ if (tp->ShortPacketEmptyBuffer != NULL) { -+ pci_free_consistent(pdev, SHORT_PACKET_PADDING_BUF_SIZE, tp->ShortPacketEmptyBuffer, -+ tp->ShortPacketEmptyBufferPhy); -+ tp->ShortPacketEmptyBuffer = NULL; -+ } -+ } -+ -+ return 0; -+} -+ -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,11) -+static void rtl8168_shutdown(struct pci_dev *pdev) -+{ -+ struct net_device *dev = pci_get_drvdata(pdev); -+ struct rtl8168_private *tp = netdev_priv(dev); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ case CFG_METHOD_23: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ if (tp->DASH) -+ rtl8168_driver_stop(tp); -+ break; -+ } -+ -+ rtl8168_set_bios_setting(dev); -+ rtl8168_rar_set(tp, tp->org_mac_addr); -+ -+#ifdef ENABLE_REALWOW_SUPPORT -+ set_realwow_d3_para(dev); -+#endif -+ -+ if (s5wol == 0) -+ tp->wol_enabled = WOL_DISABLED; -+ -+ rtl8168_close(dev); -+ rtl8168_disable_msi(pdev, tp); -+} -+#endif -+ -+/** -+ * rtl8168_get_stats - Get rtl8168 read/write statistics -+ * @dev: The Ethernet Device to get statistics for -+ * -+ * Get TX/RX statistics for rtl8168 -+ */ -+static struct -+net_device_stats *rtl8168_get_stats(struct net_device *dev) -+{ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -+ struct rtl8168_private *tp = netdev_priv(dev); -+#endif -+ if (netif_running(dev)) { -+// spin_lock_irqsave(&tp->lock, flags); -+// spin_unlock_irqrestore(&tp->lock, flags); -+ } -+ -+ return &RTLDEV->stats; -+} -+ -+#ifdef CONFIG_PM -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) -+static int -+rtl8168_suspend(struct pci_dev *pdev, u32 state) -+#else -+static int -+rtl8168_suspend(struct pci_dev *pdev, pm_message_t state) -+#endif -+{ -+ struct net_device *dev = pci_get_drvdata(pdev); -+ struct rtl8168_private *tp = netdev_priv(dev); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+ u32 pci_pm_state = pci_choose_state(pdev, state); -+#endif -+ unsigned long flags; -+ -+ if (!netif_running(dev)) -+ goto out; -+ -+ rtl8168_cancel_schedule_work(dev); -+ -+ rtl8168_delete_esd_timer(dev, &tp->esd_timer); -+ -+ rtl8168_delete_link_timer(dev, &tp->link_timer); -+ -+ netif_stop_queue(dev); -+ -+ netif_carrier_off(dev); -+ -+ rtl8168_dsm(dev, DSM_NIC_GOTO_D3); -+ -+ netif_device_detach(dev); -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ -+ rtl8168_hw_reset(dev); -+ -+ rtl8168_sleep_rx_enable(dev); -+ -+ rtl8168_hw_d3_para(dev); -+ -+#ifdef ENABLE_REALWOW_SUPPORT -+ set_realwow_d3_para(dev); -+#endif -+ -+ rtl8168_powerdown_pll(dev); -+ -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_11: -+ case CFG_METHOD_12: -+ case CFG_METHOD_13: -+ case CFG_METHOD_23: -+ case CFG_METHOD_27: -+ case CFG_METHOD_28: -+ if (tp->DASH) -+ rtl8168_driver_stop(tp); -+ break; -+ } -+ -+out: -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+ pci_save_state(pdev, &pci_pm_state); -+#else -+ pci_save_state(pdev); -+#endif -+ pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled); -+// pci_set_power_state(pdev, pci_choose_state(pdev, state)); -+ -+ return 0; -+} -+ -+static int -+rtl8168_resume(struct pci_dev *pdev) -+{ -+ struct net_device *dev = pci_get_drvdata(pdev); -+ struct rtl8168_private *tp = netdev_priv(dev); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+ u32 pci_pm_state = PCI_D0; -+#endif -+ -+ pci_set_power_state(pdev, PCI_D0); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+ pci_restore_state(pdev, &pci_pm_state); -+#else -+ pci_restore_state(pdev); -+#endif -+ pci_enable_wake(pdev, PCI_D0, 0); -+ -+ /* restore last modified mac address */ -+ rtl8168_rar_set(tp, dev->dev_addr); -+ -+ if (!netif_running(dev)) -+ goto out; -+ -+ rtl8168_exit_oob(dev); -+ -+ rtl8168_dsm(dev, DSM_NIC_RESUME_D3); -+ -+ rtl8168_hw_init(dev); -+ -+ rtl8168_powerup_pll(dev); -+ -+ rtl8168_hw_ephy_config(dev); -+ -+ rtl8168_hw_phy_config(dev); -+ -+ rtl8168_schedule_work(dev, rtl8168_reset_task); -+ -+ netif_device_attach(dev); -+ -+ mod_timer(&tp->esd_timer, jiffies + RTL8168_ESD_TIMEOUT); -+ mod_timer(&tp->link_timer, jiffies + RTL8168_LINK_TIMEOUT); -+out: -+ return 0; -+} -+ -+#endif /* CONFIG_PM */ -+ -+static struct pci_driver rtl8168_pci_driver = { -+ .name = MODULENAME, -+ .id_table = rtl8168_pci_tbl, -+ .probe = rtl8168_init_one, -+ .remove = __devexit_p(rtl8168_remove_one), -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,11) -+ .shutdown = rtl8168_shutdown, -+#endif -+#ifdef CONFIG_PM -+ .suspend = rtl8168_suspend, -+ .resume = rtl8168_resume, -+#endif -+}; -+ -+static int __init -+rtl8168_init_module(void) -+{ -+#ifdef ENABLE_R8168_PROCFS -+ rtl8168_proc_module_init(); -+#endif -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) -+ return pci_register_driver(&rtl8168_pci_driver); -+#else -+ return pci_module_init(&rtl8168_pci_driver); -+#endif -+} -+ -+static void __exit -+rtl8168_cleanup_module(void) -+{ -+ pci_unregister_driver(&rtl8168_pci_driver); -+#ifdef ENABLE_R8168_PROCFS -+ if (rtl8168_proc) { -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) -+ remove_proc_subtree(MODULENAME, init_net.proc_net); -+#else -+ remove_proc_entry(MODULENAME, init_net.proc_net); -+#endif -+ rtl8168_proc = NULL; -+ } -+#endif -+} -+ -+module_init(rtl8168_init_module); -+module_exit(rtl8168_cleanup_module); -diff --git a/drivers/net/ethernet/realtek/r8168_realwow.h b/drivers/net/ethernet/realtek/r8168_realwow.h -new file mode 100755 -index 0000000..9f050fe ---- /dev/null -+++ b/drivers/net/ethernet/realtek/r8168_realwow.h -@@ -0,0 +1,117 @@ -+/* -+################################################################################ -+# -+# r8168 is the Linux device driver released for Realtek Gigabit Ethernet -+# controllers with PCI-Express interface. -+# -+# Copyright(c) 2015 Realtek Semiconductor Corp. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the Free -+# Software Foundation; either version 2 of the License, or (at your option) -+# any later version. -+# -+# This program is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+# more details. -+# -+# You should have received a copy of the GNU General Public License along with -+# this program; if not, see <http://www.gnu.org/licenses/>. -+# -+# Author: -+# Realtek NIC software team <nicfae@realtek.com> -+# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan -+# -+################################################################################ -+*/ -+ -+/************************************************************************************ -+ * This product is covered by one or more of the following patents: -+ * US6,570,884, US6,115,776, and US6,327,625. -+ ***********************************************************************************/ -+ -+#ifndef _LINUX_R8168_REALWOW_H -+#define _LINUX_R8168_REALWOW_H -+ -+#define SIOCDEVPRIVATE_RTLREALWOW SIOCDEVPRIVATE+3 -+ -+#define MAX_RealWoW_KCP_SIZE (100) -+#define MAX_RealWoW_Payload (64) -+ -+#define KA_TX_PACKET_SIZE (100) -+#define KA_WAKEUP_PATTERN_SIZE (120) -+ -+//HwSuppKeepAliveOffloadVer -+#define HW_SUPPORT_KCP_OFFLOAD(_M) ((_M)->HwSuppKCPOffloadVer > 0) -+ -+enum rtl_realwow_cmd { -+ -+ RTL_REALWOW_SET_KCP_DISABLE=0, -+ RTL_REALWOW_SET_KCP_INFO, -+ RTL_REALWOW_SET_KCP_CONTENT, -+ -+ RTL_REALWOW_SET_KCP_ACKPKTINFO, -+ RTL_REALWOW_SET_KCP_WPINFO, -+ RTL_REALWOW_SET_KCPDHCP_TIMEOUT, -+ -+ RTLT_REALWOW_COMMAND_INVALID -+}; -+ -+struct rtl_realwow_ioctl_struct { -+ __u32 cmd; -+ __u32 offset; -+ __u32 len; -+ union { -+ __u32 data; -+ void *data_buffer; -+ }; -+}; -+ -+typedef struct _MP_KCPInfo { -+ u8 DIPv4[4]; -+ u8 MacID[6]; -+ u16 UdpPort[2]; -+ u8 PKTLEN[2]; -+ -+ u16 ackLostCnt; -+ u8 KCP_WakePattern[MAX_RealWoW_Payload]; -+ u8 KCP_AckPacket[MAX_RealWoW_Payload]; -+ u32 KCP_interval; -+ u8 KCP_WakePattern_Len; -+ u8 KCP_AckPacket_Len; -+ u8 KCP_TxPacket[2][KA_TX_PACKET_SIZE]; -+} MP_KCP_INFO, *PMP_KCP_INFO; -+ -+typedef struct _KCPInfo { -+ u32 nId; // = id -+ u8 DIPv4[4]; -+ u8 MacID[6]; -+ u16 UdpPort; -+ u16 PKTLEN; -+} KCPInfo, *PKCPInfo; -+ -+typedef struct _KCPContent { -+ u32 id; // = id -+ u32 mSec; // = msec -+ u32 size; // =size -+ u8 bPacket[MAX_RealWoW_KCP_SIZE]; // put packet here -+} KCPContent, *PKCPContent; -+ -+typedef struct _RealWoWAckPktInfo { -+ u16 ackLostCnt; -+ u16 patterntSize; -+ u8 pattern[MAX_RealWoW_Payload]; -+} RealWoWAckPktInfo,*PRealWoWAckPktInfo; -+ -+typedef struct _RealWoWWPInfo { -+ u16 patterntSize; -+ u8 pattern[MAX_RealWoW_Payload]; -+} RealWoWWPInfo,*PRealWoWWPInfo; -+ -+int rtl8168_realwow_ioctl(struct net_device *dev, struct ifreq *ifr); -+void realwow_hw_init(struct net_device *dev); -+void get_realwow_hw_version(struct net_device *dev); -+void set_realwow_d3_para(struct net_device *dev); -+ -+#endif /* _LINUX_R8168_REALWOW_H */ -\ No newline at end of file -diff --git a/drivers/net/ethernet/realtek/rtl_eeprom.c b/drivers/net/ethernet/realtek/rtl_eeprom.c -new file mode 100755 -index 0000000..de0e008 ---- /dev/null -+++ b/drivers/net/ethernet/realtek/rtl_eeprom.c -@@ -0,0 +1,291 @@ -+/* -+################################################################################ -+# -+# r8168 is the Linux device driver released for Realtek Gigabit Ethernet -+# controllers with PCI-Express interface. -+# -+# Copyright(c) 2015 Realtek Semiconductor Corp. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the Free -+# Software Foundation; either version 2 of the License, or (at your option) -+# any later version. -+# -+# This program is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+# more details. -+# -+# You should have received a copy of the GNU General Public License along with -+# this program; if not, see <http://www.gnu.org/licenses/>. -+# -+# Author: -+# Realtek NIC software team <nicfae@realtek.com> -+# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan -+# -+################################################################################ -+*/ -+ -+/************************************************************************************ -+ * This product is covered by one or more of the following patents: -+ * US6,570,884, US6,115,776, and US6,327,625. -+ ***********************************************************************************/ -+ -+#include <linux/init.h> -+#include <linux/module.h> -+#include <linux/version.h> -+#include <linux/ethtool.h> -+#include <linux/netdevice.h> -+#include <linux/delay.h> -+ -+#include <asm/io.h> -+ -+#include "r8168.h" -+#include "rtl_eeprom.h" -+ -+//------------------------------------------------------------------- -+//rtl_eeprom_type(): -+// tell the eeprom type -+//return value: -+// 0: the eeprom type is 93C46 -+// 1: the eeprom type is 93C56 or 93C66 -+//------------------------------------------------------------------- -+void rtl_eeprom_type(struct rtl8168_private *tp) -+{ -+ void __iomem *ioaddr=tp->mmio_addr; -+ u16 magic = 0; -+ -+ if (tp->mcfg == CFG_METHOD_DEFAULT) -+ goto out_no_eeprom; -+ -+ if(RTL_R8(0xD2)&0x04) { -+ //not support -+ //tp->eeprom_type = EEPROM_TWSI; -+ //tp->eeprom_len = 256; -+ goto out_no_eeprom; -+ } else if(RTL_R32(RxConfig) & RxCfg_9356SEL) { -+ tp->eeprom_type = EEPROM_TYPE_93C56; -+ tp->eeprom_len = 256; -+ } else { -+ tp->eeprom_type = EEPROM_TYPE_93C46; -+ tp->eeprom_len = 128; -+ } -+ -+ magic = rtl_eeprom_read_sc(tp, 0); -+ -+out_no_eeprom: -+ if ((magic != 0x8129) && (magic != 0x8128)) { -+ tp->eeprom_type = EEPROM_TYPE_NONE; -+ tp->eeprom_len = 0; -+ } -+} -+ -+void rtl_eeprom_cleanup(void __iomem *ioaddr) -+{ -+ u8 x; -+ -+ x = RTL_R8(Cfg9346); -+ x &= ~(Cfg9346_EEDI | Cfg9346_EECS); -+ -+ RTL_W8(Cfg9346, x); -+ -+ rtl_raise_clock(&x, ioaddr); -+ rtl_lower_clock(&x, ioaddr); -+} -+ -+int rtl_eeprom_cmd_done(void __iomem *ioaddr) -+{ -+ u8 x; -+ int i; -+ -+ rtl_stand_by(ioaddr); -+ -+ for (i = 0; i < 50000; i++) { -+ x = RTL_R8(Cfg9346); -+ -+ if (x & Cfg9346_EEDO) { -+ udelay(RTL_CLOCK_RATE * 2 * 3); -+ return 0; -+ } -+ udelay(1); -+ } -+ -+ return -1; -+} -+ -+//------------------------------------------------------------------- -+//rtl_eeprom_read_sc(): -+// read one word from eeprom -+//------------------------------------------------------------------- -+u16 rtl_eeprom_read_sc(struct rtl8168_private *tp, u16 reg) -+{ -+ void __iomem *ioaddr=tp->mmio_addr; -+ int addr_sz = 6; -+ u8 x; -+ u16 data; -+ -+ if(tp->eeprom_type == EEPROM_TYPE_NONE) { -+ return -1; -+ } -+ -+ if (tp->eeprom_type==EEPROM_TYPE_93C46) -+ addr_sz = 6; -+ else if (tp->eeprom_type==EEPROM_TYPE_93C56) -+ addr_sz = 8; -+ -+ x = Cfg9346_EEM1 | Cfg9346_EECS; -+ RTL_W8(Cfg9346, x); -+ -+ rtl_shift_out_bits(RTL_EEPROM_READ_OPCODE, 3, ioaddr); -+ rtl_shift_out_bits(reg, addr_sz, ioaddr); -+ -+ data = rtl_shift_in_bits(ioaddr); -+ -+ rtl_eeprom_cleanup(ioaddr); -+ -+ RTL_W8(Cfg9346, 0); -+ -+ return data; -+} -+ -+//------------------------------------------------------------------- -+//rtl_eeprom_write_sc(): -+// write one word to a specific address in the eeprom -+//------------------------------------------------------------------- -+void rtl_eeprom_write_sc(struct rtl8168_private *tp, u16 reg, u16 data) -+{ -+ void __iomem *ioaddr=tp->mmio_addr; -+ u8 x; -+ int addr_sz = 6; -+ int w_dummy_addr = 4; -+ -+ if(tp->eeprom_type == EEPROM_TYPE_NONE) { -+ return ; -+ } -+ -+ if (tp->eeprom_type==EEPROM_TYPE_93C46) { -+ addr_sz = 6; -+ w_dummy_addr = 4; -+ } else if (tp->eeprom_type==EEPROM_TYPE_93C56) { -+ addr_sz = 8; -+ w_dummy_addr = 6; -+ } -+ -+ x = Cfg9346_EEM1 | Cfg9346_EECS; -+ RTL_W8(Cfg9346, x); -+ -+ rtl_shift_out_bits(RTL_EEPROM_EWEN_OPCODE, 5, ioaddr); -+ rtl_shift_out_bits(reg, w_dummy_addr, ioaddr); -+ rtl_stand_by(ioaddr); -+ -+ rtl_shift_out_bits(RTL_EEPROM_ERASE_OPCODE, 3, ioaddr); -+ rtl_shift_out_bits(reg, addr_sz, ioaddr); -+ if (rtl_eeprom_cmd_done(ioaddr) < 0) { -+ return; -+ } -+ rtl_stand_by(ioaddr); -+ -+ rtl_shift_out_bits(RTL_EEPROM_WRITE_OPCODE, 3, ioaddr); -+ rtl_shift_out_bits(reg, addr_sz, ioaddr); -+ rtl_shift_out_bits(data, 16, ioaddr); -+ if (rtl_eeprom_cmd_done(ioaddr) < 0) { -+ return; -+ } -+ rtl_stand_by(ioaddr); -+ -+ rtl_shift_out_bits(RTL_EEPROM_EWDS_OPCODE, 5, ioaddr); -+ rtl_shift_out_bits(reg, w_dummy_addr, ioaddr); -+ -+ rtl_eeprom_cleanup(ioaddr); -+ RTL_W8(Cfg9346, 0); -+} -+ -+void rtl_raise_clock(u8 *x, void __iomem *ioaddr) -+{ -+ *x = *x | Cfg9346_EESK; -+ RTL_W8(Cfg9346, *x); -+ udelay(RTL_CLOCK_RATE); -+} -+ -+void rtl_lower_clock(u8 *x, void __iomem *ioaddr) -+{ -+ -+ *x = *x & ~Cfg9346_EESK; -+ RTL_W8(Cfg9346, *x); -+ udelay(RTL_CLOCK_RATE); -+} -+ -+void rtl_shift_out_bits(int data, int count, void __iomem *ioaddr) -+{ -+ u8 x; -+ int mask; -+ -+ mask = 0x01 << (count - 1); -+ x = RTL_R8(Cfg9346); -+ x &= ~(Cfg9346_EEDI | Cfg9346_EEDO); -+ -+ do { -+ if (data & mask) -+ x |= Cfg9346_EEDI; -+ else -+ x &= ~Cfg9346_EEDI; -+ -+ RTL_W8(Cfg9346, x); -+ udelay(RTL_CLOCK_RATE); -+ rtl_raise_clock(&x, ioaddr); -+ rtl_lower_clock(&x, ioaddr); -+ mask = mask >> 1; -+ } while(mask); -+ -+ x &= ~Cfg9346_EEDI; -+ RTL_W8(Cfg9346, x); -+} -+ -+u16 rtl_shift_in_bits(void __iomem *ioaddr) -+{ -+ u8 x; -+ u16 d, i; -+ -+ x = RTL_R8(Cfg9346); -+ x &= ~(Cfg9346_EEDI | Cfg9346_EEDO); -+ -+ d = 0; -+ -+ for (i = 0; i < 16; i++) { -+ d = d << 1; -+ rtl_raise_clock(&x, ioaddr); -+ -+ x = RTL_R8(Cfg9346); -+ x &= ~Cfg9346_EEDI; -+ -+ if (x & Cfg9346_EEDO) -+ d |= 1; -+ -+ rtl_lower_clock(&x, ioaddr); -+ } -+ -+ return d; -+} -+ -+void rtl_stand_by(void __iomem *ioaddr) -+{ -+ u8 x; -+ -+ x = RTL_R8(Cfg9346); -+ x &= ~(Cfg9346_EECS | Cfg9346_EESK); -+ RTL_W8(Cfg9346, x); -+ udelay(RTL_CLOCK_RATE); -+ -+ x |= Cfg9346_EECS; -+ RTL_W8(Cfg9346, x); -+} -+ -+void rtl_set_eeprom_sel_low(void __iomem *ioaddr) -+{ -+ RTL_W8(Cfg9346, Cfg9346_EEM1); -+ RTL_W8(Cfg9346, Cfg9346_EEM1 | Cfg9346_EESK); -+ -+ udelay(20); -+ -+ RTL_W8(Cfg9346, Cfg9346_EEM1); -+} -diff --git a/drivers/net/ethernet/realtek/rtl_eeprom.h b/drivers/net/ethernet/realtek/rtl_eeprom.h -new file mode 100755 -index 0000000..fd6ffbd ---- /dev/null -+++ b/drivers/net/ethernet/realtek/rtl_eeprom.h -@@ -0,0 +1,55 @@ -+/* -+################################################################################ -+# -+# r8168 is the Linux device driver released for Realtek Gigabit Ethernet -+# controllers with PCI-Express interface. -+# -+# Copyright(c) 2015 Realtek Semiconductor Corp. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the Free -+# Software Foundation; either version 2 of the License, or (at your option) -+# any later version. -+# -+# This program is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+# more details. -+# -+# You should have received a copy of the GNU General Public License along with -+# this program; if not, see <http://www.gnu.org/licenses/>. -+# -+# Author: -+# Realtek NIC software team <nicfae@realtek.com> -+# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan -+# -+################################################################################ -+*/ -+ -+/************************************************************************************ -+ * This product is covered by one or more of the following patents: -+ * US6,570,884, US6,115,776, and US6,327,625. -+ ***********************************************************************************/ -+ -+//EEPROM opcodes -+#define RTL_EEPROM_READ_OPCODE 06 -+#define RTL_EEPROM_WRITE_OPCODE 05 -+#define RTL_EEPROM_ERASE_OPCODE 07 -+#define RTL_EEPROM_EWEN_OPCODE 19 -+#define RTL_EEPROM_EWDS_OPCODE 16 -+ -+#define RTL_CLOCK_RATE 3 -+ -+void rtl_eeprom_type(struct rtl8168_private *tp); -+void rtl_eeprom_cleanup(void __iomem *ioaddr); -+u16 rtl_eeprom_read_sc(struct rtl8168_private *tp, u16 reg); -+void rtl_eeprom_write_sc(struct rtl8168_private *tp, u16 reg, u16 data); -+void rtl_shift_out_bits(int data, int count, void __iomem *ioaddr); -+u16 rtl_shift_in_bits(void __iomem *ioaddr); -+void rtl_raise_clock(u8 *x, void __iomem *ioaddr); -+void rtl_lower_clock(u8 *x, void __iomem *ioaddr); -+void rtl_stand_by(void __iomem *ioaddr); -+void rtl_set_eeprom_sel_low(void __iomem *ioaddr); -+ -+ -+ -diff --git a/drivers/net/ethernet/realtek/rtltool.c b/drivers/net/ethernet/realtek/rtltool.c -new file mode 100755 -index 0000000..d84fc4a ---- /dev/null -+++ b/drivers/net/ethernet/realtek/rtltool.c -@@ -0,0 +1,304 @@ -+#include <linux/module.h> -+#include <linux/version.h> -+#include <linux/pci.h> -+#include <linux/netdevice.h> -+#include <linux/delay.h> -+#include <linux/in.h> -+#include <linux/ethtool.h> -+#include "r8168.h" -+#include "rtl_eeprom.h" -+#include "rtltool.h" -+ -+int rtltool_ioctl(struct rtl8168_private *tp, struct ifreq *ifr) -+{ -+ struct rtltool_cmd my_cmd; -+ unsigned long flags, flags2; -+ int ret; -+ -+ if (copy_from_user(&my_cmd, ifr->ifr_data, sizeof(my_cmd))) -+ return -EFAULT; -+ -+ ret = 0; -+ switch (my_cmd.cmd) { -+ case RTLTOOL_READ_MAC: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ if (my_cmd.len==1) -+ my_cmd.data = readb(tp->mmio_addr+my_cmd.offset); -+ else if (my_cmd.len==2) -+ my_cmd.data = readw(tp->mmio_addr+(my_cmd.offset&~1)); -+ else if (my_cmd.len==4) -+ my_cmd.data = readl(tp->mmio_addr+(my_cmd.offset&~3)); -+ else { -+ ret = -EOPNOTSUPP; -+ break; -+ } -+ -+ if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { -+ ret = -EFAULT; -+ break; -+ } -+ break; -+ -+ case RTLTOOL_WRITE_MAC: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ if (my_cmd.len==1) -+ writeb(my_cmd.data, tp->mmio_addr+my_cmd.offset); -+ else if (my_cmd.len==2) -+ writew(my_cmd.data, tp->mmio_addr+(my_cmd.offset&~1)); -+ else if (my_cmd.len==4) -+ writel(my_cmd.data, tp->mmio_addr+(my_cmd.offset&~3)); -+ else { -+ ret = -EOPNOTSUPP; -+ break; -+ } -+ -+ break; -+ -+ case RTLTOOL_READ_PHY: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ my_cmd.data = mdio_read(tp, my_cmd.offset); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ -+ if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { -+ ret = -EFAULT; -+ break; -+ } -+ -+ break; -+ -+ case RTLTOOL_WRITE_PHY: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mdio_prot_write(tp, my_cmd.offset, my_cmd.data); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ case RTLTOOL_READ_EPHY: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ my_cmd.data = rtl8168_ephy_read(tp->mmio_addr, my_cmd.offset); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ -+ if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { -+ ret = -EFAULT; -+ break; -+ } -+ -+ break; -+ -+ case RTLTOOL_WRITE_EPHY: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ rtl8168_ephy_write(tp->mmio_addr, my_cmd.offset, my_cmd.data); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ case RTLTOOL_READ_ERI: -+ my_cmd.data = 0; -+ if (my_cmd.len==1 || my_cmd.len==2 || my_cmd.len==4) { -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ my_cmd.data = rtl8168_eri_read(tp->mmio_addr, my_cmd.offset, my_cmd.len, ERIAR_ExGMAC); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ } else { -+ ret = -EOPNOTSUPP; -+ break; -+ } -+ -+ if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { -+ ret = -EFAULT; -+ break; -+ } -+ -+ break; -+ -+ case RTLTOOL_WRITE_ERI: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ if (my_cmd.len==1 || my_cmd.len==2 || my_cmd.len==4) { -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ rtl8168_eri_write(tp->mmio_addr, my_cmd.offset, my_cmd.len, my_cmd.data, ERIAR_ExGMAC); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ } else { -+ ret = -EOPNOTSUPP; -+ break; -+ } -+ break; -+ -+ case RTLTOOL_READ_PCI: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ my_cmd.data = 0; -+ if (my_cmd.len==1) -+ pci_read_config_byte(tp->pci_dev, my_cmd.offset, -+ (u8 *)&my_cmd.data); -+ else if (my_cmd.len==2) -+ pci_read_config_word(tp->pci_dev, my_cmd.offset, -+ (u16 *)&my_cmd.data); -+ else if (my_cmd.len==4) -+ pci_read_config_dword(tp->pci_dev, my_cmd.offset, -+ &my_cmd.data); -+ else { -+ ret = -EOPNOTSUPP; -+ break; -+ } -+ -+ if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { -+ ret = -EFAULT; -+ break; -+ } -+ break; -+ -+ case RTLTOOL_WRITE_PCI: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ if (my_cmd.len==1) -+ pci_write_config_byte(tp->pci_dev, my_cmd.offset, -+ my_cmd.data); -+ else if (my_cmd.len==2) -+ pci_write_config_word(tp->pci_dev, my_cmd.offset, -+ my_cmd.data); -+ else if (my_cmd.len==4) -+ pci_write_config_dword(tp->pci_dev, my_cmd.offset, -+ my_cmd.data); -+ else { -+ ret = -EOPNOTSUPP; -+ break; -+ } -+ -+ break; -+ -+ case RTLTOOL_READ_EEPROM: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ my_cmd.data = rtl_eeprom_read_sc(tp, my_cmd.offset); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ -+ if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { -+ ret = -EFAULT; -+ break; -+ } -+ -+ break; -+ -+ case RTLTOOL_WRITE_EEPROM: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ rtl_eeprom_write_sc(tp, my_cmd.offset, my_cmd.data); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ case RTL_READ_OOB_MAC: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ OOB_mutex_lock(tp); -+ my_cmd.data = OCP_read(tp, my_cmd.offset, 4); -+ OOB_mutex_unlock(tp); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ -+ if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { -+ ret = -EFAULT; -+ break; -+ } -+ break; -+ -+ case RTL_WRITE_OOB_MAC: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ if (my_cmd.len == 0 || my_cmd.len > 4) -+ return -EOPNOTSUPP; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ OOB_mutex_lock(tp); -+ OCP_write(tp, my_cmd.offset, my_cmd.len, my_cmd.data); -+ OOB_mutex_unlock(tp); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ case RTL_ENABLE_PCI_DIAG: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ spin_lock_irqsave(&tp->phy_lock, flags2); -+ tp->rtk_enable_diag = 1; -+ spin_unlock_irqrestore(&tp->phy_lock, flags2); -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ dprintk("enable rtk diag\n"); -+ break; -+ -+ case RTL_DISABLE_PCI_DIAG: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ spin_lock_irqsave(&tp->lock, flags); -+ spin_lock_irqsave(&tp->phy_lock, flags2); -+ tp->rtk_enable_diag = 0; -+ spin_unlock_irqrestore(&tp->phy_lock, flags2); -+ spin_unlock_irqrestore(&tp->lock, flags); -+ -+ dprintk("disable rtk diag\n"); -+ break; -+ -+ case RTL_READ_MAC_OCP: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ if (my_cmd.offset % 2) -+ return -EOPNOTSUPP; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ my_cmd.data = mac_ocp_read(tp, my_cmd.offset); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ -+ if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { -+ ret = -EFAULT; -+ break; -+ } -+ break; -+ -+ case RTL_WRITE_MAC_OCP: -+ if (!capable(CAP_NET_ADMIN)) -+ return -EPERM; -+ -+ if ((my_cmd.offset % 2) || (my_cmd.len != 2)) -+ return -EOPNOTSUPP; -+ -+ spin_lock_irqsave(&tp->phy_lock, flags); -+ mac_ocp_write(tp, my_cmd.offset, (u16)my_cmd.data); -+ spin_unlock_irqrestore(&tp->phy_lock, flags); -+ break; -+ -+ default: -+ ret = -EOPNOTSUPP; -+ break; -+ } -+ -+ return ret; -+} -diff --git a/drivers/net/ethernet/realtek/rtltool.h b/drivers/net/ethernet/realtek/rtltool.h -new file mode 100755 -index 0000000..4cbe128 ---- /dev/null -+++ b/drivers/net/ethernet/realtek/rtltool.h -@@ -0,0 +1,49 @@ -+#ifndef _LINUX_RTLTOOL_H -+#define _LINUX_RTLTOOL_H -+ -+#define SIOCRTLTOOL SIOCDEVPRIVATE+1 -+ -+enum rtl_cmd { -+ RTLTOOL_READ_MAC=0, -+ RTLTOOL_WRITE_MAC, -+ RTLTOOL_READ_PHY, -+ RTLTOOL_WRITE_PHY, -+ RTLTOOL_READ_EPHY, -+ RTLTOOL_WRITE_EPHY, -+ RTLTOOL_READ_ERI, -+ RTLTOOL_WRITE_ERI, -+ RTLTOOL_READ_PCI, -+ RTLTOOL_WRITE_PCI, -+ RTLTOOL_READ_EEPROM, -+ RTLTOOL_WRITE_EEPROM, -+ -+ RTL_READ_OOB_MAC, -+ RTL_WRITE_OOB_MAC, -+ -+ RTL_ENABLE_PCI_DIAG, -+ RTL_DISABLE_PCI_DIAG, -+ -+ RTL_READ_MAC_OCP, -+ RTL_WRITE_MAC_OCP, -+ -+ RTLTOOL_INVALID -+}; -+ -+struct rtltool_cmd { -+ __u32 cmd; -+ __u32 offset; -+ __u32 len; -+ __u32 data; -+}; -+ -+enum mode_access { -+ MODE_NONE=0, -+ MODE_READ, -+ MODE_WRITE -+}; -+ -+#ifdef __KERNEL__ -+int rtltool_ioctl(struct rtl8168_private *tp, struct ifreq *ifr); -+#endif -+ -+#endif /* _LINUX_RTLTOOL_H */ --- -1.9.1 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0001-fix-hang-issue-when-enable-CONFIG_DRM_AMD_ACP.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0001-fix-hang-issue-when-enable-CONFIG_DRM_AMD_ACP.patch deleted file mode 100644 index 5d66128d..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/0001-fix-hang-issue-when-enable-CONFIG_DRM_AMD_ACP.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 0425f76fdb78fcede5819426814748912804eaa0 Mon Sep 17 00:00:00 2001 -From: Xiaogang <xiaogang.chen@amd.com> -Date: Wed, 20 Jul 2016 11:48:13 -0500 -Subject: [PATCH] fix hang issue when enable CONFIG_DRM_AMD_ACP - ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - mode change 100644 => 100755 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -old mode 100644 -new mode 100755 -index d6b0bff..34491f8 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -@@ -84,7 +84,6 @@ static int acp_sw_init(void *handle) - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - adev->acp.parent = adev->dev; -- - adev->acp.cgs_device = - amdgpu_cgs_create_device(adev); - if (!adev->acp.cgs_device) -@@ -356,20 +355,27 @@ static int acp_hw_init(void *handle) - adev->acp.acp_cell[0].num_resources = 4; - adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; - -+ adev->acp.acp_cell[0].ignore_resource_conflicts = 1; -+ - adev->acp.acp_cell[1].name = "designware-i2s"; - adev->acp.acp_cell[1].num_resources = 1; - adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; - adev->acp.acp_cell[1].platform_data = &i2s_pdata[0]; - adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data); - -+ adev->acp.acp_cell[1].ignore_resource_conflicts = 1; -+ - adev->acp.acp_cell[2].name = "designware-i2s"; - adev->acp.acp_cell[2].num_resources = 1; - adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2]; - adev->acp.acp_cell[2].platform_data = &i2s_pdata[1]; - adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data); - -+ adev->acp.acp_cell[2].ignore_resource_conflicts = 1; -+ - r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell, - ACP_DEVS); -+ - if (r) - return r; - --- -2.1.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0002-r8168-incorporate-changes-from-the-8.041.01-version.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0002-r8168-incorporate-changes-from-the-8.041.01-version.patch deleted file mode 100644 index 38a8e0cc..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/0002-r8168-incorporate-changes-from-the-8.041.01-version.patch +++ /dev/null @@ -1,243 +0,0 @@ -From e7dfa17dca57163b4a37f83ce5319367b370fa7d Mon Sep 17 00:00:00 2001 -From: Awais Belal <awais_belal@mentor.com> -Date: Thu, 18 Feb 2016 17:27:09 +0500 -Subject: [PATCH] r8168: incorporate changes from the 8.041.01 version - -Updates incorporated from the official REALTEK release -of the r8168 driver version 8.041.01. - -Signed-off-by: Awais Belal <awais_belal@mentor.com> ---- - drivers/net/ethernet/realtek/r8168.h | 2 +- - drivers/net/ethernet/realtek/r8168_n.c | 87 ++++++++++++++++++++++++---------- - 2 files changed, 63 insertions(+), 26 deletions(-) - -diff --git a/drivers/net/ethernet/realtek/r8168.h b/drivers/net/ethernet/realtek/r8168.h -index 95dec0e..eaa181f 100755 ---- a/drivers/net/ethernet/realtek/r8168.h -+++ b/drivers/net/ethernet/realtek/r8168.h -@@ -141,7 +141,7 @@ - #define NAPI_SUFFIX "" - #endif - --#define RTL8168_VERSION "8.040.00" NAPI_SUFFIX -+#define RTL8168_VERSION "8.041.01" NAPI_SUFFIX - #define MODULENAME "r8168" - #define PFX MODULENAME ": " - -diff --git a/drivers/net/ethernet/realtek/r8168_n.c b/drivers/net/ethernet/realtek/r8168_n.c -index 8b08e63..d197630 100755 ---- a/drivers/net/ethernet/realtek/r8168_n.c -+++ b/drivers/net/ethernet/realtek/r8168_n.c -@@ -297,7 +297,7 @@ static struct pci_device_id rtl8168_pci_tbl[] = { - - MODULE_DEVICE_TABLE(pci, rtl8168_pci_tbl); - --static int rx_copybreak = 200; -+static int rx_copybreak = 0; - static int timer_count = 0x2600; - - static struct { -@@ -3241,9 +3241,11 @@ rtl8168_init_pci_offset_99(struct rtl8168_private *tp) - - switch (tp->mcfg) { - case CFG_METHOD_26: -- csi_tmp = rtl8168_eri_read(ioaddr, 0x5C2, 1, ERIAR_ExGMAC); -- csi_tmp &= ~BIT_1; -- rtl8168_eri_write(ioaddr, 0x5C2, 1, csi_tmp, ERIAR_ExGMAC); -+ if (tp->org_pci_offset_99 & BIT_2) { -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x5C2, 1, ERIAR_ExGMAC); -+ csi_tmp &= ~BIT_1; -+ rtl8168_eri_write(ioaddr, 0x5C2, 1, csi_tmp, ERIAR_ExGMAC); -+ } - break; - } - -@@ -3272,9 +3274,19 @@ rtl8168_init_pci_offset_99(struct rtl8168_private *tp) - - switch (tp->mcfg) { - case CFG_METHOD_26: -- csi_tmp = rtl8168_eri_read(ioaddr, 0x5C8, 1, ERIAR_ExGMAC); -- csi_tmp |= BIT_0; -- rtl8168_eri_write(ioaddr, 0x5C8, 1, csi_tmp, ERIAR_ExGMAC); -+ rtl8168_eri_write(ioaddr, 0x5C0, 1, 0xFA, ERIAR_ExGMAC); -+ break; -+ } -+ -+ switch (tp->mcfg) { -+ case CFG_METHOD_26: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ if (tp->org_pci_offset_99 & BIT_2) { -+ csi_tmp = rtl8168_eri_read(ioaddr, 0x5C8, 1, ERIAR_ExGMAC); -+ csi_tmp |= BIT_0; -+ rtl8168_eri_write(ioaddr, 0x5C8, 1, csi_tmp, ERIAR_ExGMAC); -+ } - break; - } - -@@ -3306,18 +3318,6 @@ rtl8168_init_pci_offset_99(struct rtl8168_private *tp) - } - - switch (tp->mcfg) { -- case CFG_METHOD_26: -- case CFG_METHOD_29: -- case CFG_METHOD_30: -- RTL_W8(0xB6, RTL_R8(0xB6) | BIT_0); -- -- csi_tmp = rtl8168_eri_read(ioaddr, 0x5C8, 1, ERIAR_ExGMAC); -- csi_tmp |= BIT_0; -- rtl8168_eri_write(ioaddr, 0x5C8, 1, csi_tmp, ERIAR_ExGMAC); -- break; -- } -- -- switch (tp->mcfg) { - case CFG_METHOD_21: - case CFG_METHOD_22: - case CFG_METHOD_24: -@@ -3331,6 +3331,15 @@ rtl8168_init_pci_offset_99(struct rtl8168_private *tp) - break; - } - -+ switch (tp->mcfg) { -+ case CFG_METHOD_26: -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ if (tp->org_pci_offset_99 & BIT_2) -+ RTL_W8(0xB6, RTL_R8(0xB6) | BIT_0); -+ break; -+ } -+ - rtl8168_enable_pci_offset_99(tp); - } - -@@ -4841,7 +4850,7 @@ static int rtl8168_enable_EEE(struct rtl8168_private *tp) - case CFG_METHOD_28: - OOB_mutex_lock(tp); - data = mac_ocp_read(tp, 0xE052); -- data |= BIT_0; -+ data &= ~BIT_0; - mac_ocp_write(tp, 0xE052, data); - OOB_mutex_unlock(tp); - data = mac_ocp_read(tp, 0xE056); -@@ -4861,7 +4870,8 @@ static int rtl8168_enable_EEE(struct rtl8168_private *tp) - mdio_write(tp, 0x10, data); - - mdio_write(tp, 0x1F, 0x0A44); -- data = mdio_read( tp, 0x11 ) | BIT_12 | BIT_13| BIT_14; -+ data = mdio_read(tp, 0x11) | BIT_13 | BIT_14; -+ data &= ~(BIT_12); - mdio_write(tp, 0x11, data); - spin_unlock_irqrestore(&tp->phy_lock, flags); - break; -@@ -5091,7 +5101,7 @@ static int rtl8168_disable_EEE(struct rtl8168_private *tp) - mdio_write(tp, 0x10, data); - - mdio_write(tp, 0x1F, 0x0A44); -- data = mdio_read( tp, 0x11 ) & ~(BIT_12 | BIT_13 | BIT_14); -+ data = mdio_read(tp, 0x11) & ~(BIT_12 | BIT_13 | BIT_14); - mdio_write(tp, 0x11, data); - spin_unlock_irqrestore(&tp->phy_lock, flags); - break; -@@ -5684,6 +5694,8 @@ rtl8168_exit_oob(struct net_device *dev) - void __iomem *ioaddr = tp->mmio_addr; - u16 data16; - -+ RTL_W32(RxConfig, RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | AcceptAllPhys)); -+ - switch (tp->mcfg) { - case CFG_METHOD_23: - case CFG_METHOD_27: -@@ -6767,6 +6779,8 @@ rtl8168_hw_mac_mcu_config(struct net_device *dev) - mac_ocp_write(tp, 0xFC2A, 0x0210); - mac_ocp_write(tp, 0xFC2C, 0x1A04); - mac_ocp_write(tp, 0xFC2E, 0x0B26); -+ mac_ocp_write(tp, 0xFC30, 0x0F02); -+ mac_ocp_write(tp, 0xFC32, 0x0CA0); - - mac_ocp_write(tp, 0xFC38, 0x003F); - } -@@ -7122,7 +7136,7 @@ rtl8168_hw_ephy_config(struct net_device *dev) - (BIT_13 | BIT_12 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_4), - (BIT_5 | BIT_11) - ); -- ClearPCIePhyBit(tp, 0x1E, BIT_0); -+ SetPCIePhyBit(tp, 0x1E, BIT_0); - ClearPCIePhyBit(tp, 0x19, BIT_15); - - ClearPCIePhyBit(tp, 0x19, (BIT_5 | BIT_0)); -@@ -22105,7 +22119,7 @@ rtl8168_init_board(struct pci_dev *pdev, - tp->msg_enable = netif_msg_init(debug.msg_enable, R8168_MSG_DEFAULT); - - #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) -- if (!aspm) -+ if (!aspm || tp->mcfg == CFG_METHOD_9) - pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | - PCIE_LINK_STATE_CLKPM); - #endif -@@ -22575,6 +22589,7 @@ rtl8168_init_one(struct pci_dev *pdev, - #ifdef CONFIG_R8168_NAPI - RTL_NAPI_DEL(tp); - #endif -+ rtl8168_disable_msi(pdev, tp); - rtl8168_release_board(pdev, dev, ioaddr); - return rc; - } -@@ -22794,10 +22809,10 @@ rtl8168_dsm(struct net_device *dev, int dev_state) - } - - } -+ - static void - set_offset70F(struct rtl8168_private *tp, u8 setting) - { -- - u32 csi_tmp; - u32 temp = (u32)setting; - temp = temp << 24; -@@ -22824,6 +22839,19 @@ set_offset79(struct rtl8168_private *tp, u8 setting) - } - - static void -+set_offset711(struct rtl8168_private *tp, u8 setting) -+{ -+ u32 csi_tmp; -+ u32 temp = (u32)setting; -+ temp &= 0x0f; -+ temp = temp << 12; -+ /*set PCI configuration space offset 0x711 to setting*/ -+ -+ csi_tmp = rtl8168_csi_read(tp, 0x710) & 0xffff0fff; -+ rtl8168_csi_write(tp, 0x710, csi_tmp | temp); -+} -+ -+static void - rtl8168_hw_set_rx_packet_filter(struct net_device *dev) - { - struct rtl8168_private *tp = netdev_priv(dev); -@@ -23433,6 +23461,8 @@ rtl8168_hw_config(struct net_device *dev) - tp->mcfg == CFG_METHOD_30) { - set_offset70F(tp, 0x17); - set_offset79(tp, 0x50); -+ if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22) -+ set_offset711(tp, 0x04); - - rtl8168_eri_write(ioaddr, 0xC8, 4, 0x00080002, ERIAR_ExGMAC); - rtl8168_eri_write(ioaddr, 0xCC, 1, 0x38, ERIAR_ExGMAC); -@@ -23742,6 +23772,13 @@ rtl8168_hw_config(struct net_device *dev) - rtl8168_hw_clear_timer_int(dev); - - switch (tp->mcfg) { -+ case CFG_METHOD_29: -+ case CFG_METHOD_30: -+ mac_ocp_write(tp, 0xE098, 0x0AA2); -+ break; -+ } -+ -+ switch (tp->mcfg) { - case CFG_METHOD_21: - case CFG_METHOD_22: - case CFG_METHOD_23: --- -1.9.1 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1113-enable-UVD-context-buffer-for-older-HW-MIME-Version-.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1113-enable-UVD-context-buffer-for-older-HW-MIME-Version-.patch deleted file mode 100644 index 17691311..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1113-enable-UVD-context-buffer-for-older-HW-MIME-Version-.patch +++ /dev/null @@ -1,137 +0,0 @@ -From d4fc4a943bb3f18c6a1d89c367a04c5ea82c7575 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Sat, 17 Sep 2016 14:39:50 +0530 -Subject: [PATCH 03/12] enable UVD context buffer for older HW MIME-Version: - 1.0 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Supported starting on certain FW versions. - -Signed-off-by: Christian König <christian.koenig@amd.com> -Reviewed-by: Leo Liu <leo.liu@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + - drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 63 +++++++++++++++++++++++++++++++-- - 2 files changed, 61 insertions(+), 3 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -index 551f763..28f8481 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -@@ -1670,6 +1670,7 @@ struct amdgpu_uvd { - struct amdgpu_ring ring; - struct amdgpu_irq_src irq; - bool address_64_bit; -+ bool use_ctx_buf; - struct amd_sched_entity entity; - }; - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -index 74f0019..9050af2 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -@@ -42,6 +42,15 @@ - /* 1 second timeout */ - #define UVD_IDLE_TIMEOUT_MS 1000 - -+/* Firmware versions for VI */ -+#define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) -+#define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) -+#define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) -+#define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) -+ -+/* Polaris10/11 firmware version */ -+#define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) -+ - /* Firmware Names */ - #ifdef CONFIG_DRM_AMDGPU_CIK - #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" -@@ -415,7 +424,8 @@ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) - * - * Peek into the decode message and calculate the necessary buffer sizes. - */ --static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) -+static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, -+ unsigned buf_sizes[]) - { - unsigned stream_type = msg[4]; - unsigned width = msg[6]; -@@ -437,7 +447,6 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) - - switch (stream_type) { - case 0: /* H264 */ -- case 7: /* H264 Perf */ - switch(level) { - case 30: - num_dpb_buffer = 8100 / fs_in_mb; -@@ -515,6 +524,54 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) - min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); - break; - -+ case 7: /* H264 Perf */ -+ switch(level) { -+ case 30: -+ num_dpb_buffer = 8100 / fs_in_mb; -+ break; -+ case 31: -+ num_dpb_buffer = 18000 / fs_in_mb; -+ break; -+ case 32: -+ num_dpb_buffer = 20480 / fs_in_mb; -+ break; -+ case 41: -+ num_dpb_buffer = 32768 / fs_in_mb; -+ break; -+ case 42: -+ num_dpb_buffer = 34816 / fs_in_mb; -+ break; -+ case 50: -+ num_dpb_buffer = 110400 / fs_in_mb; -+ break; -+ case 51: -+ num_dpb_buffer = 184320 / fs_in_mb; -+ break; -+ default: -+ num_dpb_buffer = 184320 / fs_in_mb; -+ break; -+ } -+ num_dpb_buffer++; -+ if (num_dpb_buffer > 17) -+ num_dpb_buffer = 17; -+ -+ /* reference picture buffer */ -+ min_dpb_size = image_size * num_dpb_buffer; -+ -+ if (!adev->uvd.use_ctx_buf){ -+ /* macroblock context buffer */ -+ min_dpb_size += -+ width_in_mb * height_in_mb * num_dpb_buffer * 192; -+ -+ /* IT surface buffer */ -+ min_dpb_size += width_in_mb * height_in_mb * 32; -+ } else { -+ /* macroblock context buffer */ -+ min_ctx_size = -+ width_in_mb * height_in_mb * num_dpb_buffer * 192; -+ } -+ break; -+ - case 16: /* H265 */ - image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; - image_size = ALIGN(image_size, 256); -@@ -610,7 +667,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, - - case 1: - /* it's a decode msg, calc buffer sizes */ -- r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes); -+ r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); - amdgpu_bo_kunmap(bo); - if (r) - return r; --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1114-fix-default-UVD-context-size.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1114-fix-default-UVD-context-size.patch deleted file mode 100644 index 9bfac892..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1114-fix-default-UVD-context-size.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 769574cc4720acfd1eca9bc5467e1a5a4a7956f3 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Sat, 17 Sep 2016 14:41:30 +0530 -Subject: [PATCH 04/12] fix default UVD context size -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Context buffers should be denied by default, not allowed. - -Signed-off-by: Christian König <christian.koenig@amd.com> -Reviewed-by: Leo Liu <leo.liu@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -index 9050af2..ddc487d 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -@@ -439,7 +439,7 @@ static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, - unsigned fs_in_mb = width_in_mb * height_in_mb; - - unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; -- unsigned min_ctx_size = 0; -+ unsigned min_ctx_size = ~0; - - image_size = width * height; - image_size += image_size / 2; --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1115-fix-IB-alignment-for-UVD.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1115-fix-IB-alignment-for-UVD.patch deleted file mode 100644 index 0f64355f..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1115-fix-IB-alignment-for-UVD.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 953b9fd99e928cb79128d9339cbb71259ae8f0de Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Sat, 17 Sep 2016 14:53:56 +0530 -Subject: [PATCH 05/12] fix IB alignment for UVD - -According to the hw team, it should be 16, not 8. - -Cc: Peter Fang <peter.fang@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Cc: stable@vger.kernel.org -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -index 78bd8b1..459d8b7 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -@@ -227,7 +227,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file - type = AMD_IP_BLOCK_TYPE_UVD; - ring_mask = adev->uvd.ring.ready ? 1 : 0; - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; -- ib_size_alignment = 8; -+ ib_size_alignment = 16; - break; - case AMDGPU_HW_IP_VCE: - type = AMD_IP_BLOCK_TYPE_VCE; --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1116-fix-VCE-ib-alignment-value.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1116-fix-VCE-ib-alignment-value.patch deleted file mode 100644 index 39bdd3aa..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1116-fix-VCE-ib-alignment-value.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 1edb59b7025457bfe3efff045e7120b70b65d1f6 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Sat, 17 Sep 2016 14:56:40 +0530 -Subject: [PATCH 06/12] fix VCE ib alignment value - -The VCE rings only require single dword alignment. - -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -index 459d8b7..b6de8d5 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -@@ -234,7 +234,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file - for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++) - ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; -- ib_size_alignment = 8; -+ ib_size_alignment = 1; - break; - default: - return -EINVAL; --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1117-add-support-for-UVD_NO_OP-register.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1117-add-support-for-UVD_NO_OP-register.patch deleted file mode 100644 index 6d1b4da9..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1117-add-support-for-UVD_NO_OP-register.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 56c8ca5434ce175d98e33cffcfe554cc7e3cb70a Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Sat, 17 Sep 2016 15:10:08 +0530 -Subject: [PATCH 07/12] add support for UVD_NO_OP register -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Writes to this register are the preferred way to do NOPs. - -Reviewed-by: Christian König <christian.koenig@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 1 + - drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h | 1 + - 2 files changed, 2 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -index ddc487d..2ca93a4 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -@@ -823,6 +823,7 @@ static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, - return r; - break; - case mmUVD_ENGINE_CNTL: -+ case mmUVD_NO_OP: - break; - default: - DRM_ERROR("Invalid reg 0x%X!\n", reg); -diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h -index f3e53b1..19802e9 100644 ---- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h -+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h -@@ -34,6 +34,7 @@ - #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 - #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 - #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 -+#define mmUVD_NO_OP 0x3bff - #define mmUVD_SEMA_CNTL 0x3d00 - #define mmUVD_LMI_EXT40_ADDR 0x3d26 - #define mmUVD_CTX_INDEX 0x3d28 --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1118-switch-UVD-code-to-use-UVD_NO_OP-for-padding.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1118-switch-UVD-code-to-use-UVD_NO_OP-for-padding.patch deleted file mode 100644 index 36737218..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1118-switch-UVD-code-to-use-UVD_NO_OP-for-padding.patch +++ /dev/null @@ -1,106 +0,0 @@ -From f60f754ee9efe8d43beadccb7bf0b169f77a6247 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Sat, 17 Sep 2016 15:13:33 +0530 -Subject: [PATCH 08/12] switch UVD code to use UVD_NO_OP for padding -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Replace packet2's with packet0 writes to UVD_NO_OP. The -value written to UVD_NO_OP does not matter. - -Reviewed-by: Christian König <christian.koenig@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 6 ++++-- - drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 2 +- - drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 2 +- - drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 +- - drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h | 1 + - drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h | 1 + - 6 files changed, 9 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -index 2ca93a4..f14e4aa 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -@@ -964,8 +964,10 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, - ib->ptr[3] = addr >> 32; - ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); - ib->ptr[5] = 0; -- for (i = 6; i < 16; ++i) -- ib->ptr[i] = PACKET2(0); -+ for (i = 6; i < 16; i += 2) { -+ ib->ptr[i] = PACKET0(mmUVD_NO_OP, 0); -+ ib->ptr[i+1] = 0; -+ } - ib->length_dw = 16; - - if (direct) { -diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c -index a75ffb5b..ab4857d 100644 ---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c -+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c -@@ -114,7 +114,7 @@ static int uvd_v4_2_sw_init(void *handle) - - ring = &adev->uvd.ring; - sprintf(ring->name, "uvd"); -- r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, -+ r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, - &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); - - return r; -diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c -index ecb8101..2b115bd 100644 ---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c -@@ -111,7 +111,7 @@ static int uvd_v5_0_sw_init(void *handle) - - ring = &adev->uvd.ring; - sprintf(ring->name, "uvd"); -- r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, -+ r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, - &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); - - return r; -diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c -index 0887ea9..e33e3f4 100644 ---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c -@@ -115,7 +115,7 @@ static int uvd_v6_0_sw_init(void *handle) - - ring = &adev->uvd.ring; - sprintf(ring->name, "uvd"); -- r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, -+ r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, - &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); - - return r; -diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h -index eb4cf53..cc972d2 100644 ---- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h -+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h -@@ -34,6 +34,7 @@ - #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 - #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 - #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 -+#define mmUVD_NO_OP 0x3bff - #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69 - #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68 - #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67 -diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h -index 6f6fb34..d24d086 100644 ---- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h -+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h -@@ -35,6 +35,7 @@ - #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 - #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 - #define mmUVD_POWER_STATUS_U 0x3bfd -+#define mmUVD_NO_OP 0x3bff - #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69 - #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68 - #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67 --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1119-move-amdgpu_drm.h-to-driver-include-dir.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1119-move-amdgpu_drm.h-to-driver-include-dir.patch deleted file mode 100644 index 34295779..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1119-move-amdgpu_drm.h-to-driver-include-dir.patch +++ /dev/null @@ -1,1366 +0,0 @@ -From b85cb50d1c4416a804a6c9040675f74df48760ef Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Mon, 19 Sep 2016 12:16:57 +0530 -Subject: [PATCH 09/12] move amdgpu_drm.h to driver include dir - -Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 683 ++++++++++++++++++++++ - include/uapi/drm/amdgpu_drm.h | 653 --------------------- - 2 files changed, 683 insertions(+), 653 deletions(-) - create mode 100644 drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h - delete mode 100644 include/uapi/drm/amdgpu_drm.h - -diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -new file mode 100644 -index 0000000..c84f977 ---- /dev/null -+++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -@@ -0,0 +1,683 @@ -+/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- -+ * -+ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. -+ * Copyright 2000 VA Linux Systems, Inc., Fremont, California. -+ * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. -+ * Copyright 2014 Advanced Micro Devices, Inc. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included in -+ * all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ * -+ * Authors: -+ * Kevin E. Martin <martin@valinux.com> -+ * Gareth Hughes <gareth@valinux.com> -+ * Keith Whitwell <keith@tungstengraphics.com> -+ */ -+ -+#ifndef __AMDGPU_DRM_H__ -+#define __AMDGPU_DRM_H__ -+ -+#include "drm.h" -+ -+#define DRM_AMDGPU_GEM_CREATE 0x00 -+#define DRM_AMDGPU_GEM_MMAP 0x01 -+#define DRM_AMDGPU_CTX 0x02 -+#define DRM_AMDGPU_BO_LIST 0x03 -+#define DRM_AMDGPU_CS 0x04 -+#define DRM_AMDGPU_INFO 0x05 -+#define DRM_AMDGPU_GEM_METADATA 0x06 -+#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 -+#define DRM_AMDGPU_GEM_VA 0x08 -+#define DRM_AMDGPU_WAIT_CS 0x09 -+#define DRM_AMDGPU_GEM_OP 0x10 -+#define DRM_AMDGPU_GEM_USERPTR 0x11 -+#define DRM_AMDGPU_FREESYNC 0x14 -+ -+#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) -+#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) -+#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) -+#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) -+#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) -+#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) -+#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) -+#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) -+#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) -+#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) -+#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) -+#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) -+#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) -+ -+#define AMDGPU_GEM_DOMAIN_CPU 0x1 -+#define AMDGPU_GEM_DOMAIN_GTT 0x2 -+#define AMDGPU_GEM_DOMAIN_VRAM 0x4 -+#define AMDGPU_GEM_DOMAIN_GDS 0x8 -+#define AMDGPU_GEM_DOMAIN_GWS 0x10 -+#define AMDGPU_GEM_DOMAIN_OA 0x20 -+ -+/* Flag that CPU access will be required for the case of VRAM domain */ -+#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) -+/* Flag that CPU access will not work, this VRAM domain is invisible */ -+#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) -+/* Flag that USWC attributes should be used for GTT */ -+#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) -+/* Flag that the memory allocation should be pinned */ -+#define AMDGPU_GEM_CREATE_NO_EVICT (1 << 3) -+ -+struct drm_amdgpu_gem_create_in { -+ /** the requested memory size */ -+ __u64 bo_size; -+ /** physical start_addr alignment in bytes for some HW requirements */ -+ __u64 alignment; -+ /** the requested memory domains */ -+ __u64 domains; -+ /** allocation flags */ -+ __u64 domain_flags; -+}; -+ -+struct drm_amdgpu_gem_create_out { -+ /** returned GEM object handle */ -+ __u32 handle; -+ __u32 _pad; -+}; -+ -+union drm_amdgpu_gem_create { -+ struct drm_amdgpu_gem_create_in in; -+ struct drm_amdgpu_gem_create_out out; -+}; -+ -+/** Opcode to create new residency list. */ -+#define AMDGPU_BO_LIST_OP_CREATE 0 -+/** Opcode to destroy previously created residency list */ -+#define AMDGPU_BO_LIST_OP_DESTROY 1 -+/** Opcode to update resource information in the list */ -+#define AMDGPU_BO_LIST_OP_UPDATE 2 -+ -+struct drm_amdgpu_bo_list_in { -+ /** Type of operation */ -+ __u32 operation; -+ /** Handle of list or 0 if we want to create one */ -+ __u32 list_handle; -+ /** Number of BOs in list */ -+ __u32 bo_number; -+ /** Size of each element describing BO */ -+ __u32 bo_info_size; -+ /** Pointer to array describing BOs */ -+ __u64 bo_info_ptr; -+}; -+ -+struct drm_amdgpu_bo_list_entry { -+ /** Handle of BO */ -+ __u32 bo_handle; -+ /** New (if specified) BO priority to be used during migration */ -+ __u32 bo_priority; -+}; -+ -+struct drm_amdgpu_bo_list_out { -+ /** Handle of resource list */ -+ __u32 list_handle; -+ __u32 _pad; -+}; -+ -+union drm_amdgpu_bo_list { -+ struct drm_amdgpu_bo_list_in in; -+ struct drm_amdgpu_bo_list_out out; -+}; -+ -+/* context related */ -+#define AMDGPU_CTX_OP_ALLOC_CTX 1 -+#define AMDGPU_CTX_OP_FREE_CTX 2 -+#define AMDGPU_CTX_OP_QUERY_STATE 3 -+ -+/* GPU reset status */ -+#define AMDGPU_CTX_NO_RESET 0 -+/* this the context caused it */ -+#define AMDGPU_CTX_GUILTY_RESET 1 -+/* some other context caused it */ -+#define AMDGPU_CTX_INNOCENT_RESET 2 -+/* unknown cause */ -+#define AMDGPU_CTX_UNKNOWN_RESET 3 -+ -+struct drm_amdgpu_ctx_in { -+ /** AMDGPU_CTX_OP_* */ -+ __u32 op; -+ /** For future use, no flags defined so far */ -+ __u32 flags; -+ __u32 ctx_id; -+ __u32 _pad; -+}; -+ -+union drm_amdgpu_ctx_out { -+ struct { -+ __u32 ctx_id; -+ __u32 _pad; -+ } alloc; -+ -+ struct { -+ /** For future use, no flags defined so far */ -+ __u64 flags; -+ /** Number of resets caused by this context so far. */ -+ __u32 hangs; -+ /** Reset status since the last call of the ioctl. */ -+ __u32 reset_status; -+ } state; -+}; -+ -+union drm_amdgpu_ctx { -+ struct drm_amdgpu_ctx_in in; -+ union drm_amdgpu_ctx_out out; -+}; -+ -+/* -+ * This is not a reliable API and you should expect it to fail for any -+ * number of reasons and have fallback path that do not use userptr to -+ * perform any operation. -+ */ -+#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) -+#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) -+#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) -+#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) -+ -+struct drm_amdgpu_gem_userptr { -+ __u64 addr; -+ __u64 size; -+ /* AMDGPU_GEM_USERPTR_* */ -+ __u32 flags; -+ /* Resulting GEM handle */ -+ __u32 handle; -+}; -+ -+/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ -+#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 -+#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf -+#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 -+#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f -+#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 -+#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 -+#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 -+#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 -+#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 -+#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 -+#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 -+#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 -+#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 -+#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 -+#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 -+#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 -+ -+#define AMDGPU_TILING_SET(field, value) \ -+ (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) -+#define AMDGPU_TILING_GET(value, field) \ -+ (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) -+ -+#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 -+#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 -+ -+/** The same structure is shared for input/output */ -+struct drm_amdgpu_gem_metadata { -+ /** GEM Object handle */ -+ __u32 handle; -+ /** Do we want get or set metadata */ -+ __u32 op; -+ struct { -+ /** For future use, no flags defined so far */ -+ __u64 flags; -+ /** family specific tiling info */ -+ __u64 tiling_info; -+ __u32 data_size_bytes; -+ __u32 data[64]; -+ } data; -+}; -+ -+struct drm_amdgpu_gem_mmap_in { -+ /** the GEM object handle */ -+ __u32 handle; -+ __u32 _pad; -+}; -+ -+struct drm_amdgpu_gem_mmap_out { -+ /** mmap offset from the vma offset manager */ -+ __u64 addr_ptr; -+}; -+ -+union drm_amdgpu_gem_mmap { -+ struct drm_amdgpu_gem_mmap_in in; -+ struct drm_amdgpu_gem_mmap_out out; -+}; -+ -+struct drm_amdgpu_gem_wait_idle_in { -+ /** GEM object handle */ -+ __u32 handle; -+ /** For future use, no flags defined so far */ -+ __u32 flags; -+ /** Absolute timeout to wait */ -+ __u64 timeout; -+}; -+ -+struct drm_amdgpu_gem_wait_idle_out { -+ /** BO status: 0 - BO is idle, 1 - BO is busy */ -+ __u32 status; -+ /** Returned current memory domain */ -+ __u32 domain; -+}; -+ -+union drm_amdgpu_gem_wait_idle { -+ struct drm_amdgpu_gem_wait_idle_in in; -+ struct drm_amdgpu_gem_wait_idle_out out; -+}; -+ -+struct drm_amdgpu_wait_cs_in { -+ /** Command submission handle */ -+ __u64 handle; -+ /** Absolute timeout to wait */ -+ __u64 timeout; -+ __u32 ip_type; -+ __u32 ip_instance; -+ __u32 ring; -+ __u32 ctx_id; -+}; -+ -+struct drm_amdgpu_wait_cs_out { -+ /** CS status: 0 - CS completed, 1 - CS still busy */ -+ __u64 status; -+}; -+ -+union drm_amdgpu_wait_cs { -+ struct drm_amdgpu_wait_cs_in in; -+ struct drm_amdgpu_wait_cs_out out; -+}; -+ -+#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 -+#define AMDGPU_GEM_OP_SET_PLACEMENT 1 -+ -+/* Sets or returns a value associated with a buffer. */ -+struct drm_amdgpu_gem_op { -+ /** GEM object handle */ -+ __u32 handle; -+ /** AMDGPU_GEM_OP_* */ -+ __u32 op; -+ /** Input or return value */ -+ __u64 value; -+}; -+ -+#define AMDGPU_VA_OP_MAP 1 -+#define AMDGPU_VA_OP_UNMAP 2 -+ -+/* Delay the page table update till the next CS */ -+#define AMDGPU_VM_DELAY_UPDATE (1 << 0) -+ -+/* Mapping flags */ -+/* readable mapping */ -+#define AMDGPU_VM_PAGE_READABLE (1 << 1) -+/* writable mapping */ -+#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) -+/* executable mapping, new for VI */ -+#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) -+ -+struct drm_amdgpu_gem_va { -+ /** GEM object handle */ -+ __u32 handle; -+ __u32 _pad; -+ /** AMDGPU_VA_OP_* */ -+ __u32 operation; -+ /** AMDGPU_VM_PAGE_* */ -+ __u32 flags; -+ /** va address to assign . Must be correctly aligned.*/ -+ __u64 va_address; -+ /** Specify offset inside of BO to assign. Must be correctly aligned.*/ -+ __u64 offset_in_bo; -+ /** Specify mapping size. Must be correctly aligned. */ -+ __u64 map_size; -+}; -+ -+#define AMDGPU_HW_IP_GFX 0 -+#define AMDGPU_HW_IP_COMPUTE 1 -+#define AMDGPU_HW_IP_DMA 2 -+#define AMDGPU_HW_IP_UVD 3 -+#define AMDGPU_HW_IP_VCE 4 -+#define AMDGPU_HW_IP_NUM 5 -+ -+#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 -+ -+#define AMDGPU_CHUNK_ID_IB 0x01 -+#define AMDGPU_CHUNK_ID_FENCE 0x02 -+#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 -+ -+struct drm_amdgpu_cs_chunk { -+ __u32 chunk_id; -+ __u32 length_dw; -+ __u64 chunk_data; -+}; -+ -+struct drm_amdgpu_cs_in { -+ /** Rendering context id */ -+ __u32 ctx_id; -+ /** Handle of resource list associated with CS */ -+ __u32 bo_list_handle; -+ __u32 num_chunks; -+ __u32 _pad; -+ /** this points to __u64 * which point to cs chunks */ -+ __u64 chunks; -+}; -+ -+struct drm_amdgpu_cs_out { -+ __u64 handle; -+}; -+ -+union drm_amdgpu_cs { -+ struct drm_amdgpu_cs_in in; -+ struct drm_amdgpu_cs_out out; -+}; -+ -+/* Specify flags to be used for IB */ -+ -+/* This IB should be submitted to CE */ -+#define AMDGPU_IB_FLAG_CE (1<<0) -+ -+/* CE Preamble */ -+#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) -+ -+struct drm_amdgpu_cs_chunk_ib { -+ __u32 _pad; -+ /** AMDGPU_IB_FLAG_* */ -+ __u32 flags; -+ /** Virtual address to begin IB execution */ -+ __u64 va_start; -+ /** Size of submission */ -+ __u32 ib_bytes; -+ /** HW IP to submit to */ -+ __u32 ip_type; -+ /** HW IP index of the same type to submit to */ -+ __u32 ip_instance; -+ /** Ring index to submit to */ -+ __u32 ring; -+}; -+ -+struct drm_amdgpu_cs_chunk_dep { -+ __u32 ip_type; -+ __u32 ip_instance; -+ __u32 ring; -+ __u32 ctx_id; -+ __u64 handle; -+}; -+ -+struct drm_amdgpu_cs_chunk_fence { -+ __u32 handle; -+ __u32 offset; -+}; -+ -+struct drm_amdgpu_cs_chunk_data { -+ union { -+ struct drm_amdgpu_cs_chunk_ib ib_data; -+ struct drm_amdgpu_cs_chunk_fence fence_data; -+ }; -+}; -+ -+/** -+ * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU -+ * -+ */ -+#define AMDGPU_IDS_FLAGS_FUSION 0x1 -+ -+/* indicate if acceleration can be working */ -+#define AMDGPU_INFO_ACCEL_WORKING 0x00 -+/* get the crtc_id from the mode object id? */ -+#define AMDGPU_INFO_CRTC_FROM_ID 0x01 -+/* query hw IP info */ -+#define AMDGPU_INFO_HW_IP_INFO 0x02 -+/* query hw IP instance count for the specified type */ -+#define AMDGPU_INFO_HW_IP_COUNT 0x03 -+/* timestamp for GL_ARB_timer_query */ -+#define AMDGPU_INFO_TIMESTAMP 0x05 -+/* Query the firmware version */ -+#define AMDGPU_INFO_FW_VERSION 0x0e -+ /* Subquery id: Query VCE firmware version */ -+ #define AMDGPU_INFO_FW_VCE 0x1 -+ /* Subquery id: Query UVD firmware version */ -+ #define AMDGPU_INFO_FW_UVD 0x2 -+ /* Subquery id: Query GMC firmware version */ -+ #define AMDGPU_INFO_FW_GMC 0x03 -+ /* Subquery id: Query GFX ME firmware version */ -+ #define AMDGPU_INFO_FW_GFX_ME 0x04 -+ /* Subquery id: Query GFX PFP firmware version */ -+ #define AMDGPU_INFO_FW_GFX_PFP 0x05 -+ /* Subquery id: Query GFX CE firmware version */ -+ #define AMDGPU_INFO_FW_GFX_CE 0x06 -+ /* Subquery id: Query GFX RLC firmware version */ -+ #define AMDGPU_INFO_FW_GFX_RLC 0x07 -+ /* Subquery id: Query GFX MEC firmware version */ -+ #define AMDGPU_INFO_FW_GFX_MEC 0x08 -+ /* Subquery id: Query SMC firmware version */ -+ #define AMDGPU_INFO_FW_SMC 0x0a -+ /* Subquery id: Query SDMA firmware version */ -+ #define AMDGPU_INFO_FW_SDMA 0x0b -+/* number of bytes moved for TTM migration */ -+#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f -+/* the used VRAM size */ -+#define AMDGPU_INFO_VRAM_USAGE 0x10 -+/* the used GTT size */ -+#define AMDGPU_INFO_GTT_USAGE 0x11 -+/* Information about GDS, etc. resource configuration */ -+#define AMDGPU_INFO_GDS_CONFIG 0x13 -+/* Query information about VRAM and GTT domains */ -+#define AMDGPU_INFO_VRAM_GTT 0x14 -+/* Query information about register in MMR address space*/ -+#define AMDGPU_INFO_READ_MMR_REG 0x15 -+/* Query information about device: rev id, family, etc. */ -+#define AMDGPU_INFO_DEV_INFO 0x16 -+/* visible vram usage */ -+#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 -+/* virtual range */ -+#define AMDGPU_INFO_VIRTUAL_RANGE 0x18 -+/* gpu capability */ -+#define AMDGPU_INFO_CAPABILITY 0x50 -+/* query pin memory capability */ -+#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) -+ -+#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 -+#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff -+#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 -+#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff -+ -+/* Input structure for the INFO ioctl */ -+struct drm_amdgpu_info { -+ /* Where the return value will be stored */ -+ __u64 return_pointer; -+ /* The size of the return value. Just like "size" in "snprintf", -+ * it limits how many bytes the kernel can write. */ -+ __u32 return_size; -+ /* The query request id. */ -+ __u32 query; -+ -+ union { -+ struct { -+ __u32 id; -+ __u32 _pad; -+ } mode_crtc; -+ -+ struct { -+ /** AMDGPU_HW_IP_* */ -+ __u32 type; -+ /** -+ * Index of the IP if there are more IPs of the same -+ * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. -+ */ -+ __u32 ip_instance; -+ } query_hw_ip; -+ -+ struct { -+ __u32 dword_offset; -+ /** number of registers to read */ -+ __u32 count; -+ __u32 instance; -+ /** For future use, no flags defined so far */ -+ __u32 flags; -+ } read_mmr_reg; -+ -+ struct { -+ /** AMDGPU_INFO_FW_* */ -+ __u32 fw_type; -+ /** -+ * Index of the IP if there are more IPs of -+ * the same type. -+ */ -+ __u32 ip_instance; -+ /** -+ * Index of the engine. Whether this is used depends -+ * on the firmware type. (e.g. MEC, SDMA) -+ */ -+ __u32 index; -+ __u32 _pad; -+ } query_fw; -+ -+ struct { -+ uint32_t aperture; -+ uint32_t _pad; -+ } virtual_range; -+ }; -+}; -+ -+struct drm_amdgpu_info_gds { -+ /** GDS GFX partition size */ -+ __u32 gds_gfx_partition_size; -+ /** GDS compute partition size */ -+ __u32 compute_partition_size; -+ /** total GDS memory size */ -+ __u32 gds_total_size; -+ /** GWS size per GFX partition */ -+ __u32 gws_per_gfx_partition; -+ /** GSW size per compute partition */ -+ __u32 gws_per_compute_partition; -+ /** OA size per GFX partition */ -+ __u32 oa_per_gfx_partition; -+ /** OA size per compute partition */ -+ __u32 oa_per_compute_partition; -+ __u32 _pad; -+}; -+ -+struct drm_amdgpu_info_vram_gtt { -+ __u64 vram_size; -+ __u64 vram_cpu_accessible_size; -+ __u64 gtt_size; -+}; -+ -+struct drm_amdgpu_info_firmware { -+ __u32 ver; -+ __u32 feature; -+}; -+ -+#define AMDGPU_VRAM_TYPE_UNKNOWN 0 -+#define AMDGPU_VRAM_TYPE_GDDR1 1 -+#define AMDGPU_VRAM_TYPE_DDR2 2 -+#define AMDGPU_VRAM_TYPE_GDDR3 3 -+#define AMDGPU_VRAM_TYPE_GDDR4 4 -+#define AMDGPU_VRAM_TYPE_GDDR5 5 -+#define AMDGPU_VRAM_TYPE_HBM 6 -+#define AMDGPU_VRAM_TYPE_DDR3 7 -+ -+struct drm_amdgpu_info_device { -+ /** PCI Device ID */ -+ __u32 device_id; -+ /** Internal chip revision: A0, A1, etc.) */ -+ __u32 chip_rev; -+ __u32 external_rev; -+ /** Revision id in PCI Config space */ -+ __u32 pci_rev; -+ __u32 family; -+ __u32 num_shader_engines; -+ __u32 num_shader_arrays_per_engine; -+ /* in KHz */ -+ __u32 gpu_counter_freq; -+ __u64 max_engine_clock; -+ __u64 max_memory_clock; -+ /* cu information */ -+ __u32 cu_active_number; -+ __u32 cu_ao_mask; -+ __u32 cu_bitmap[4][4]; -+ /** Render backend pipe mask. One render backend is CB+DB. */ -+ __u32 enabled_rb_pipes_mask; -+ __u32 num_rb_pipes; -+ __u32 num_hw_gfx_contexts; -+ __u32 _pad; -+ __u64 ids_flags; -+ /** Starting virtual address for UMDs. */ -+ __u64 virtual_address_offset; -+ /** The maximum virtual address */ -+ __u64 virtual_address_max; -+ /** Required alignment of virtual addresses. */ -+ __u32 virtual_address_alignment; -+ /** Page table entry - fragment size */ -+ __u32 pte_fragment_size; -+ __u32 gart_page_size; -+ /** constant engine ram size*/ -+ __u32 ce_ram_size; -+ /** video memory type info*/ -+ __u32 vram_type; -+ /** video memory bit width*/ -+ __u32 vram_bit_width; -+ /* vce harvesting instance */ -+ __u32 vce_harvest_config; -+}; -+ -+struct drm_amdgpu_info_hw_ip { -+ /** Version of h/w IP */ -+ __u32 hw_ip_version_major; -+ __u32 hw_ip_version_minor; -+ /** Capabilities */ -+ __u64 capabilities_flags; -+ /** command buffer address start alignment*/ -+ __u32 ib_start_alignment; -+ /** command buffer size alignment*/ -+ __u32 ib_size_alignment; -+ /** Bitmask of available rings. Bit 0 means ring 0, etc. */ -+ __u32 available_rings; -+ __u32 _pad; -+}; -+ -+/* -+ * Supported GPU families -+ */ -+#define AMDGPU_FAMILY_UNKNOWN 0 -+#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ -+#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ -+#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ -+#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ -+ -+/** -+ * Definition of System Unified Address (SUA) apertures -+ */ -+#define AMDGPU_SUA_APERTURE_PRIVATE 1 -+#define AMDGPU_SUA_APERTURE_SHARED 2 -+struct drm_amdgpu_virtual_range { -+ uint64_t start; -+ uint64_t end; -+}; -+ -+/* -+ * Definition of free sync enter and exit signals -+ * We may have more options in the future -+ */ -+#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1 -+#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2 -+ -+struct drm_amdgpu_freesync { -+ __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ -+ /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ -+ __u32 spare[7]; -+}; -+ -+#endif -diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h -deleted file mode 100644 -index 7039d22..0000000 ---- a/include/uapi/drm/amdgpu_drm.h -+++ /dev/null -@@ -1,653 +0,0 @@ --/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- -- * -- * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. -- * Copyright 2000 VA Linux Systems, Inc., Fremont, California. -- * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. -- * Copyright 2014 Advanced Micro Devices, Inc. -- * -- * Permission is hereby granted, free of charge, to any person obtaining a -- * copy of this software and associated documentation files (the "Software"), -- * to deal in the Software without restriction, including without limitation -- * the rights to use, copy, modify, merge, publish, distribute, sublicense, -- * and/or sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following conditions: -- * -- * The above copyright notice and this permission notice shall be included in -- * all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. -- * -- * Authors: -- * Kevin E. Martin <martin@valinux.com> -- * Gareth Hughes <gareth@valinux.com> -- * Keith Whitwell <keith@tungstengraphics.com> -- */ -- --#ifndef __AMDGPU_DRM_H__ --#define __AMDGPU_DRM_H__ -- --#include "drm.h" -- --#define DRM_AMDGPU_GEM_CREATE 0x00 --#define DRM_AMDGPU_GEM_MMAP 0x01 --#define DRM_AMDGPU_CTX 0x02 --#define DRM_AMDGPU_BO_LIST 0x03 --#define DRM_AMDGPU_CS 0x04 --#define DRM_AMDGPU_INFO 0x05 --#define DRM_AMDGPU_GEM_METADATA 0x06 --#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 --#define DRM_AMDGPU_GEM_VA 0x08 --#define DRM_AMDGPU_WAIT_CS 0x09 --#define DRM_AMDGPU_GEM_OP 0x10 --#define DRM_AMDGPU_GEM_USERPTR 0x11 --#define DRM_AMDGPU_FREESYNC 0x14 -- --#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) --#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) --#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) --#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) --#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) --#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) --#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) --#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) --#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) --#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) --#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) --#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) --#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) -- --#define AMDGPU_GEM_DOMAIN_CPU 0x1 --#define AMDGPU_GEM_DOMAIN_GTT 0x2 --#define AMDGPU_GEM_DOMAIN_VRAM 0x4 --#define AMDGPU_GEM_DOMAIN_GDS 0x8 --#define AMDGPU_GEM_DOMAIN_GWS 0x10 --#define AMDGPU_GEM_DOMAIN_OA 0x20 -- --/* Flag that CPU access will be required for the case of VRAM domain */ --#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) --/* Flag that CPU access will not work, this VRAM domain is invisible */ --#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) --/* Flag that USWC attributes should be used for GTT */ --#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) -- --struct drm_amdgpu_gem_create_in { -- /** the requested memory size */ -- uint64_t bo_size; -- /** physical start_addr alignment in bytes for some HW requirements */ -- uint64_t alignment; -- /** the requested memory domains */ -- uint64_t domains; -- /** allocation flags */ -- uint64_t domain_flags; --}; -- --struct drm_amdgpu_gem_create_out { -- /** returned GEM object handle */ -- uint32_t handle; -- uint32_t _pad; --}; -- --union drm_amdgpu_gem_create { -- struct drm_amdgpu_gem_create_in in; -- struct drm_amdgpu_gem_create_out out; --}; -- --/** Opcode to create new residency list. */ --#define AMDGPU_BO_LIST_OP_CREATE 0 --/** Opcode to destroy previously created residency list */ --#define AMDGPU_BO_LIST_OP_DESTROY 1 --/** Opcode to update resource information in the list */ --#define AMDGPU_BO_LIST_OP_UPDATE 2 -- --struct drm_amdgpu_bo_list_in { -- /** Type of operation */ -- uint32_t operation; -- /** Handle of list or 0 if we want to create one */ -- uint32_t list_handle; -- /** Number of BOs in list */ -- uint32_t bo_number; -- /** Size of each element describing BO */ -- uint32_t bo_info_size; -- /** Pointer to array describing BOs */ -- uint64_t bo_info_ptr; --}; -- --struct drm_amdgpu_bo_list_entry { -- /** Handle of BO */ -- uint32_t bo_handle; -- /** New (if specified) BO priority to be used during migration */ -- uint32_t bo_priority; --}; -- --struct drm_amdgpu_bo_list_out { -- /** Handle of resource list */ -- uint32_t list_handle; -- uint32_t _pad; --}; -- --union drm_amdgpu_bo_list { -- struct drm_amdgpu_bo_list_in in; -- struct drm_amdgpu_bo_list_out out; --}; -- --/* context related */ --#define AMDGPU_CTX_OP_ALLOC_CTX 1 --#define AMDGPU_CTX_OP_FREE_CTX 2 --#define AMDGPU_CTX_OP_QUERY_STATE 3 -- --/* GPU reset status */ --#define AMDGPU_CTX_NO_RESET 0 --/* this the context caused it */ --#define AMDGPU_CTX_GUILTY_RESET 1 --/* some other context caused it */ --#define AMDGPU_CTX_INNOCENT_RESET 2 --/* unknown cause */ --#define AMDGPU_CTX_UNKNOWN_RESET 3 -- --struct drm_amdgpu_ctx_in { -- /** AMDGPU_CTX_OP_* */ -- uint32_t op; -- /** For future use, no flags defined so far */ -- uint32_t flags; -- uint32_t ctx_id; -- uint32_t _pad; --}; -- --union drm_amdgpu_ctx_out { -- struct { -- uint32_t ctx_id; -- uint32_t _pad; -- } alloc; -- -- struct { -- /** For future use, no flags defined so far */ -- uint64_t flags; -- /** Number of resets caused by this context so far. */ -- uint32_t hangs; -- /** Reset status since the last call of the ioctl. */ -- uint32_t reset_status; -- } state; --}; -- --union drm_amdgpu_ctx { -- struct drm_amdgpu_ctx_in in; -- union drm_amdgpu_ctx_out out; --}; -- --/* -- * This is not a reliable API and you should expect it to fail for any -- * number of reasons and have fallback path that do not use userptr to -- * perform any operation. -- */ --#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) --#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) --#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) --#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) -- --struct drm_amdgpu_gem_userptr { -- uint64_t addr; -- uint64_t size; -- /* AMDGPU_GEM_USERPTR_* */ -- uint32_t flags; -- /* Resulting GEM handle */ -- uint32_t handle; --}; -- --/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ --#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 --#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf --#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 --#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f --#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 --#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 --#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 --#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 --#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 --#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 --#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 --#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 --#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 --#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 --#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 --#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 -- --#define AMDGPU_TILING_SET(field, value) \ -- (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) --#define AMDGPU_TILING_GET(value, field) \ -- (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) -- --#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 --#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 -- --/** The same structure is shared for input/output */ --struct drm_amdgpu_gem_metadata { -- /** GEM Object handle */ -- uint32_t handle; -- /** Do we want get or set metadata */ -- uint32_t op; -- struct { -- /** For future use, no flags defined so far */ -- uint64_t flags; -- /** family specific tiling info */ -- uint64_t tiling_info; -- uint32_t data_size_bytes; -- uint32_t data[64]; -- } data; --}; -- --struct drm_amdgpu_gem_mmap_in { -- /** the GEM object handle */ -- uint32_t handle; -- uint32_t _pad; --}; -- --struct drm_amdgpu_gem_mmap_out { -- /** mmap offset from the vma offset manager */ -- uint64_t addr_ptr; --}; -- --union drm_amdgpu_gem_mmap { -- struct drm_amdgpu_gem_mmap_in in; -- struct drm_amdgpu_gem_mmap_out out; --}; -- --struct drm_amdgpu_gem_wait_idle_in { -- /** GEM object handle */ -- uint32_t handle; -- /** For future use, no flags defined so far */ -- uint32_t flags; -- /** Absolute timeout to wait */ -- uint64_t timeout; --}; -- --struct drm_amdgpu_gem_wait_idle_out { -- /** BO status: 0 - BO is idle, 1 - BO is busy */ -- uint32_t status; -- /** Returned current memory domain */ -- uint32_t domain; --}; -- --union drm_amdgpu_gem_wait_idle { -- struct drm_amdgpu_gem_wait_idle_in in; -- struct drm_amdgpu_gem_wait_idle_out out; --}; -- --struct drm_amdgpu_wait_cs_in { -- /** Command submission handle */ -- uint64_t handle; -- /** Absolute timeout to wait */ -- uint64_t timeout; -- uint32_t ip_type; -- uint32_t ip_instance; -- uint32_t ring; -- uint32_t ctx_id; --}; -- --struct drm_amdgpu_wait_cs_out { -- /** CS status: 0 - CS completed, 1 - CS still busy */ -- uint64_t status; --}; -- --union drm_amdgpu_wait_cs { -- struct drm_amdgpu_wait_cs_in in; -- struct drm_amdgpu_wait_cs_out out; --}; -- --#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 --#define AMDGPU_GEM_OP_SET_PLACEMENT 1 -- --/* Sets or returns a value associated with a buffer. */ --struct drm_amdgpu_gem_op { -- /** GEM object handle */ -- uint32_t handle; -- /** AMDGPU_GEM_OP_* */ -- uint32_t op; -- /** Input or return value */ -- uint64_t value; --}; -- --#define AMDGPU_VA_OP_MAP 1 --#define AMDGPU_VA_OP_UNMAP 2 -- --/* Delay the page table update till the next CS */ --#define AMDGPU_VM_DELAY_UPDATE (1 << 0) -- --/* Mapping flags */ --/* readable mapping */ --#define AMDGPU_VM_PAGE_READABLE (1 << 1) --/* writable mapping */ --#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) --/* executable mapping, new for VI */ --#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) -- --struct drm_amdgpu_gem_va { -- /** GEM object handle */ -- uint32_t handle; -- uint32_t _pad; -- /** AMDGPU_VA_OP_* */ -- uint32_t operation; -- /** AMDGPU_VM_PAGE_* */ -- uint32_t flags; -- /** va address to assign . Must be correctly aligned.*/ -- uint64_t va_address; -- /** Specify offset inside of BO to assign. Must be correctly aligned.*/ -- uint64_t offset_in_bo; -- /** Specify mapping size. Must be correctly aligned. */ -- uint64_t map_size; --}; -- --#define AMDGPU_HW_IP_GFX 0 --#define AMDGPU_HW_IP_COMPUTE 1 --#define AMDGPU_HW_IP_DMA 2 --#define AMDGPU_HW_IP_UVD 3 --#define AMDGPU_HW_IP_VCE 4 --#define AMDGPU_HW_IP_NUM 5 -- --#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 -- --#define AMDGPU_CHUNK_ID_IB 0x01 --#define AMDGPU_CHUNK_ID_FENCE 0x02 --#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 -- --struct drm_amdgpu_cs_chunk { -- uint32_t chunk_id; -- uint32_t length_dw; -- uint64_t chunk_data; --}; -- --struct drm_amdgpu_cs_in { -- /** Rendering context id */ -- uint32_t ctx_id; -- /** Handle of resource list associated with CS */ -- uint32_t bo_list_handle; -- uint32_t num_chunks; -- uint32_t _pad; -- /** this points to uint64_t * which point to cs chunks */ -- uint64_t chunks; --}; -- --struct drm_amdgpu_cs_out { -- uint64_t handle; --}; -- --union drm_amdgpu_cs { -- struct drm_amdgpu_cs_in in; -- struct drm_amdgpu_cs_out out; --}; -- --/* Specify flags to be used for IB */ -- --/* This IB should be submitted to CE */ --#define AMDGPU_IB_FLAG_CE (1<<0) -- --/* CE Preamble */ --#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) -- --struct drm_amdgpu_cs_chunk_ib { -- uint32_t _pad; -- /** AMDGPU_IB_FLAG_* */ -- uint32_t flags; -- /** Virtual address to begin IB execution */ -- uint64_t va_start; -- /** Size of submission */ -- uint32_t ib_bytes; -- /** HW IP to submit to */ -- uint32_t ip_type; -- /** HW IP index of the same type to submit to */ -- uint32_t ip_instance; -- /** Ring index to submit to */ -- uint32_t ring; --}; -- --struct drm_amdgpu_cs_chunk_dep { -- uint32_t ip_type; -- uint32_t ip_instance; -- uint32_t ring; -- uint32_t ctx_id; -- uint64_t handle; --}; -- --struct drm_amdgpu_cs_chunk_fence { -- uint32_t handle; -- uint32_t offset; --}; -- --struct drm_amdgpu_cs_chunk_data { -- union { -- struct drm_amdgpu_cs_chunk_ib ib_data; -- struct drm_amdgpu_cs_chunk_fence fence_data; -- }; --}; -- --/** -- * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU -- * -- */ --#define AMDGPU_IDS_FLAGS_FUSION 0x1 -- --/* indicate if acceleration can be working */ --#define AMDGPU_INFO_ACCEL_WORKING 0x00 --/* get the crtc_id from the mode object id? */ --#define AMDGPU_INFO_CRTC_FROM_ID 0x01 --/* query hw IP info */ --#define AMDGPU_INFO_HW_IP_INFO 0x02 --/* query hw IP instance count for the specified type */ --#define AMDGPU_INFO_HW_IP_COUNT 0x03 --/* timestamp for GL_ARB_timer_query */ --#define AMDGPU_INFO_TIMESTAMP 0x05 --/* Query the firmware version */ --#define AMDGPU_INFO_FW_VERSION 0x0e -- /* Subquery id: Query VCE firmware version */ -- #define AMDGPU_INFO_FW_VCE 0x1 -- /* Subquery id: Query UVD firmware version */ -- #define AMDGPU_INFO_FW_UVD 0x2 -- /* Subquery id: Query GMC firmware version */ -- #define AMDGPU_INFO_FW_GMC 0x03 -- /* Subquery id: Query GFX ME firmware version */ -- #define AMDGPU_INFO_FW_GFX_ME 0x04 -- /* Subquery id: Query GFX PFP firmware version */ -- #define AMDGPU_INFO_FW_GFX_PFP 0x05 -- /* Subquery id: Query GFX CE firmware version */ -- #define AMDGPU_INFO_FW_GFX_CE 0x06 -- /* Subquery id: Query GFX RLC firmware version */ -- #define AMDGPU_INFO_FW_GFX_RLC 0x07 -- /* Subquery id: Query GFX MEC firmware version */ -- #define AMDGPU_INFO_FW_GFX_MEC 0x08 -- /* Subquery id: Query SMC firmware version */ -- #define AMDGPU_INFO_FW_SMC 0x0a -- /* Subquery id: Query SDMA firmware version */ -- #define AMDGPU_INFO_FW_SDMA 0x0b --/* number of bytes moved for TTM migration */ --#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f --/* the used VRAM size */ --#define AMDGPU_INFO_VRAM_USAGE 0x10 --/* the used GTT size */ --#define AMDGPU_INFO_GTT_USAGE 0x11 --/* Information about GDS, etc. resource configuration */ --#define AMDGPU_INFO_GDS_CONFIG 0x13 --/* Query information about VRAM and GTT domains */ --#define AMDGPU_INFO_VRAM_GTT 0x14 --/* Query information about register in MMR address space*/ --#define AMDGPU_INFO_READ_MMR_REG 0x15 --/* Query information about device: rev id, family, etc. */ --#define AMDGPU_INFO_DEV_INFO 0x16 --/* visible vram usage */ --#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 -- --#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 --#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff --#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 --#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff -- --/* Input structure for the INFO ioctl */ --struct drm_amdgpu_info { -- /* Where the return value will be stored */ -- uint64_t return_pointer; -- /* The size of the return value. Just like "size" in "snprintf", -- * it limits how many bytes the kernel can write. */ -- uint32_t return_size; -- /* The query request id. */ -- uint32_t query; -- -- union { -- struct { -- uint32_t id; -- uint32_t _pad; -- } mode_crtc; -- -- struct { -- /** AMDGPU_HW_IP_* */ -- uint32_t type; -- /** -- * Index of the IP if there are more IPs of the same -- * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. -- */ -- uint32_t ip_instance; -- } query_hw_ip; -- -- struct { -- uint32_t dword_offset; -- /** number of registers to read */ -- uint32_t count; -- uint32_t instance; -- /** For future use, no flags defined so far */ -- uint32_t flags; -- } read_mmr_reg; -- -- struct { -- /** AMDGPU_INFO_FW_* */ -- uint32_t fw_type; -- /** -- * Index of the IP if there are more IPs of -- * the same type. -- */ -- uint32_t ip_instance; -- /** -- * Index of the engine. Whether this is used depends -- * on the firmware type. (e.g. MEC, SDMA) -- */ -- uint32_t index; -- uint32_t _pad; -- } query_fw; -- }; --}; -- --struct drm_amdgpu_info_gds { -- /** GDS GFX partition size */ -- uint32_t gds_gfx_partition_size; -- /** GDS compute partition size */ -- uint32_t compute_partition_size; -- /** total GDS memory size */ -- uint32_t gds_total_size; -- /** GWS size per GFX partition */ -- uint32_t gws_per_gfx_partition; -- /** GSW size per compute partition */ -- uint32_t gws_per_compute_partition; -- /** OA size per GFX partition */ -- uint32_t oa_per_gfx_partition; -- /** OA size per compute partition */ -- uint32_t oa_per_compute_partition; -- uint32_t _pad; --}; -- --struct drm_amdgpu_info_vram_gtt { -- uint64_t vram_size; -- uint64_t vram_cpu_accessible_size; -- uint64_t gtt_size; --}; -- --struct drm_amdgpu_info_firmware { -- uint32_t ver; -- uint32_t feature; --}; -- --#define AMDGPU_VRAM_TYPE_UNKNOWN 0 --#define AMDGPU_VRAM_TYPE_GDDR1 1 --#define AMDGPU_VRAM_TYPE_DDR2 2 --#define AMDGPU_VRAM_TYPE_GDDR3 3 --#define AMDGPU_VRAM_TYPE_GDDR4 4 --#define AMDGPU_VRAM_TYPE_GDDR5 5 --#define AMDGPU_VRAM_TYPE_HBM 6 --#define AMDGPU_VRAM_TYPE_DDR3 7 -- --struct drm_amdgpu_info_device { -- /** PCI Device ID */ -- uint32_t device_id; -- /** Internal chip revision: A0, A1, etc.) */ -- uint32_t chip_rev; -- uint32_t external_rev; -- /** Revision id in PCI Config space */ -- uint32_t pci_rev; -- uint32_t family; -- uint32_t num_shader_engines; -- uint32_t num_shader_arrays_per_engine; -- /* in KHz */ -- uint32_t gpu_counter_freq; -- uint64_t max_engine_clock; -- uint64_t max_memory_clock; -- /* cu information */ -- uint32_t cu_active_number; -- uint32_t cu_ao_mask; -- uint32_t cu_bitmap[4][4]; -- /** Render backend pipe mask. One render backend is CB+DB. */ -- uint32_t enabled_rb_pipes_mask; -- uint32_t num_rb_pipes; -- uint32_t num_hw_gfx_contexts; -- uint32_t _pad; -- uint64_t ids_flags; -- /** Starting virtual address for UMDs. */ -- uint64_t virtual_address_offset; -- /** The maximum virtual address */ -- uint64_t virtual_address_max; -- /** Required alignment of virtual addresses. */ -- uint32_t virtual_address_alignment; -- /** Page table entry - fragment size */ -- uint32_t pte_fragment_size; -- uint32_t gart_page_size; -- /** constant engine ram size*/ -- uint32_t ce_ram_size; -- /** video memory type info*/ -- uint32_t vram_type; -- /** video memory bit width*/ -- uint32_t vram_bit_width; -- /* vce harvesting instance */ -- uint32_t vce_harvest_config; --}; -- --struct drm_amdgpu_info_hw_ip { -- /** Version of h/w IP */ -- uint32_t hw_ip_version_major; -- uint32_t hw_ip_version_minor; -- /** Capabilities */ -- uint64_t capabilities_flags; -- /** command buffer address start alignment*/ -- uint32_t ib_start_alignment; -- /** command buffer size alignment*/ -- uint32_t ib_size_alignment; -- /** Bitmask of available rings. Bit 0 means ring 0, etc. */ -- uint32_t available_rings; -- uint32_t _pad; --}; -- --/* -- * Supported GPU families -- */ --#define AMDGPU_FAMILY_UNKNOWN 0 --#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ --#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ --#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ --#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ -- --struct drm_amdgpu_freesync { -- __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ -- /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ -- __u32 spare[7]; --}; -- --#endif --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1120-fix-amdgpu_drm.h-include-problem.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1120-fix-amdgpu_drm.h-include-problem.patch deleted file mode 100644 index 820c021e..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1120-fix-amdgpu_drm.h-include-problem.patch +++ /dev/null @@ -1,51 +0,0 @@ -From e194f8487e72796b41916e5df38658ee891d0007 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Wed, 28 Sep 2016 14:57:00 +0530 -Subject: [PATCH] fix amdgpu_drm.h include problem. - -Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/Makefile | 2 ++ - drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 2 +- - include/uapi/drm/amdgpu_drm.h | 1 + - 3 files changed, 4 insertions(+), 1 deletion(-) - create mode 100644 include/uapi/drm/amdgpu_drm.h - -diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile -index 215f8fc..28e8e4c 100644 ---- a/drivers/gpu/drm/amd/amdgpu/Makefile -+++ b/drivers/gpu/drm/amd/amdgpu/Makefile -@@ -17,6 +17,8 @@ ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \ - -I$(FULL_AMD_DAL_PATH)/dc \ - -I$(FULL_AMD_DAL_PATH)/amdgpu_dm - -+LINUXINCLUDE := -I$(FULL_AMD_PATH)/include/uapi $(LINUXINCLUDE) -+ - amdgpu-y := amdgpu_drv.o - - # add KMS driver -diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -index c84f977..17c7d3f 100644 ---- a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -+++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -@@ -32,7 +32,7 @@ - #ifndef __AMDGPU_DRM_H__ - #define __AMDGPU_DRM_H__ - --#include "drm.h" -+#include <drm/drm.h> - - #define DRM_AMDGPU_GEM_CREATE 0x00 - #define DRM_AMDGPU_GEM_MMAP 0x01 -diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h -new file mode 100644 -index 0000000..22890bb ---- /dev/null -+++ b/include/uapi/drm/amdgpu_drm.h -@@ -0,0 +1 @@ -+#include "../../../drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h" --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1121-add-the-interface-of-waiting-multiple-fences-v2.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1121-add-the-interface-of-waiting-multiple-fences-v2.patch deleted file mode 100644 index 1502ec44..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1121-add-the-interface-of-waiting-multiple-fences-v2.patch +++ /dev/null @@ -1,281 +0,0 @@ -From 5f2af20ad85a19ddbdd1ea7b63b0f21ac499ed88 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Mon, 19 Sep 2016 12:31:46 +0530 -Subject: [PATCH 11/12] add the interface of waiting multiple fences (v2) - -v2: agd: rebase and squash in all the previous optimizations and -changes so everything compiles. - -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Monk Liu <monk.liu@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + - drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 171 ++++++++++++++++++++++ - drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 + - drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 27 ++++ - 4 files changed, 201 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -index 28f8481..b15b3b5 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -@@ -1861,6 +1861,8 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, - struct drm_file *filp); - int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); - int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); -+int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, -+ struct drm_file *filp); - - int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, - struct drm_file *filp); -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c -index f983846..0d1346c 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c -@@ -1021,6 +1021,177 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, - } - - /** -+ * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence -+ * -+ * @adev: amdgpu device -+ * @filp: file private -+ * @user: drm_amdgpu_fence copied from user space -+ */ -+static struct fence *amdgpu_cs_get_fence(struct amdgpu_device *adev, -+ struct drm_file *filp, -+ struct drm_amdgpu_fence *user) -+{ -+ struct amdgpu_ring *ring; -+ struct amdgpu_ctx *ctx; -+ struct fence *fence; -+ int r; -+ -+ r = amdgpu_cs_get_ring(adev, user->ip_type, user->ip_instance, -+ user->ring, &ring); -+ if (r) -+ return ERR_PTR(r); -+ -+ ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id); -+ if (ctx == NULL) -+ return ERR_PTR(-EINVAL); -+ -+ fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no); -+ amdgpu_ctx_put(ctx); -+ -+ return fence; -+} -+ -+/** -+ * amdgpu_cs_wait_all_fence - wait on all fences to signal -+ * -+ * @adev: amdgpu device -+ * @filp: file private -+ * @wait: wait parameters -+ * @fences: array of drm_amdgpu_fence -+ */ -+static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev, -+ struct drm_file *filp, -+ union drm_amdgpu_wait_fences *wait, -+ struct drm_amdgpu_fence *fences) -+{ -+ uint32_t fence_count = wait->in.fence_count; -+ unsigned i; -+ long r = 1; -+ -+ for (i = 0; i < fence_count; i++) { -+ struct fence *fence; -+ unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns); -+ -+ fence = amdgpu_cs_get_fence(adev, filp, &fences[i]); -+ if (IS_ERR(fence)) -+ return PTR_ERR(fence); -+ else if (!fence) -+ continue; -+ -+ r = fence_wait_timeout(fence, true, timeout); -+ if (r < 0) -+ return r; -+ -+ if (r == 0) -+ break; -+ } -+ -+ memset(wait, 0, sizeof(*wait)); -+ wait->out.status = (r > 0); -+ -+ return 0; -+} -+ -+/** -+ * amdgpu_cs_wait_any_fence - wait on any fence to signal -+ * -+ * @adev: amdgpu device -+ * @filp: file private -+ * @wait: wait parameters -+ * @fences: array of drm_amdgpu_fence -+ */ -+static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev, -+ struct drm_file *filp, -+ union drm_amdgpu_wait_fences *wait, -+ struct drm_amdgpu_fence *fences) -+{ -+ unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns); -+ uint32_t fence_count = wait->in.fence_count; -+ struct fence **array; -+ unsigned i; -+ long r; -+ -+ /* Prepare the fence array */ -+ array = (struct fence **)kcalloc(fence_count, sizeof(struct fence *), -+ GFP_KERNEL); -+ if (array == NULL) -+ return -ENOMEM; -+ -+ for (i = 0; i < fence_count; i++) { -+ struct fence *fence; -+ -+ fence = amdgpu_cs_get_fence(adev, filp, &fences[i]); -+ if (IS_ERR(fence)) { -+ r = PTR_ERR(fence); -+ goto err_free_fence_array; -+ } else if (fence) { -+ array[i] = fence; -+ } else { /* NULL, the fence has been already signaled */ -+ r = 1; -+ goto out; -+ } -+ } -+ -+ r = fence_wait_any_timeout(array, fence_count, true, timeout); -+ if (r < 0) -+ goto err_free_fence_array; -+ -+out: -+ memset(wait, 0, sizeof(*wait)); -+ wait->out.status = (r > 0); -+ /* set return value 0 to indicate success */ -+ r = 0; -+ -+err_free_fence_array: -+ for (i = 0; i < fence_count; i++) -+ fence_put(array[i]); -+ kfree(array); -+ -+ return r; -+} -+ -+/** -+ * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish -+ * -+ * @dev: drm device -+ * @data: data from userspace -+ * @filp: file private -+ */ -+int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, -+ struct drm_file *filp) -+{ -+ struct amdgpu_device *adev = dev->dev_private; -+ union drm_amdgpu_wait_fences *wait = data; -+ uint32_t fence_count = wait->in.fence_count; -+ struct drm_amdgpu_fence *fences_user; -+ struct drm_amdgpu_fence *fences; -+ int r; -+ -+ /* Get the fences from userspace */ -+ fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence), -+ GFP_KERNEL); -+ if (fences == NULL) -+ return -ENOMEM; -+ -+ fences_user = (void __user *)wait->in.fences; -+ if (copy_from_user(fences, fences_user, -+ sizeof(struct drm_amdgpu_fence) * fence_count)) { -+ r = -EFAULT; -+ goto err_free_fences; -+ } -+ -+ if (wait->in.wait_all) -+ r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences); -+ else -+ r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences); -+ -+err_free_fences: -+ kfree(fences); -+ -+ return r; -+} -+ -+/** - * amdgpu_cs_find_bo_va - find bo_va for VM address - * - * @parser: command submission parser context -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -index b6de8d5..3ce4ee3 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -@@ -749,6 +749,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { - DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), -+ DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), -diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -index 17c7d3f..8ff615b 100644 ---- a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -+++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -@@ -46,6 +46,7 @@ - #define DRM_AMDGPU_WAIT_CS 0x09 - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 -+#define DRM_AMDGPU_WAIT_FENCES 0x12 - #define DRM_AMDGPU_FREESYNC 0x14 - - #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) -@@ -60,6 +61,7 @@ - #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) - #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) -+#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) - - #define AMDGPU_GEM_DOMAIN_CPU 0x1 -@@ -301,6 +303,31 @@ union drm_amdgpu_wait_cs { - struct drm_amdgpu_wait_cs_out out; - }; - -+struct drm_amdgpu_fence { -+ uint32_t ctx_id; -+ uint32_t ip_type; -+ uint32_t ip_instance; -+ uint32_t ring; -+ uint64_t seq_no; -+}; -+ -+struct drm_amdgpu_wait_fences_in { -+ /** This points to uint64_t * which points to fences */ -+ uint64_t fences; -+ uint32_t fence_count; -+ uint32_t wait_all; -+ uint64_t timeout_ns; -+}; -+ -+struct drm_amdgpu_wait_fences_out { -+ uint64_t status; -+}; -+ -+union drm_amdgpu_wait_fences { -+ struct drm_amdgpu_wait_fences_in in; -+ struct drm_amdgpu_wait_fences_out out; -+}; -+ - #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 - #define AMDGPU_GEM_OP_SET_PLACEMENT 1 - --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1122-Fix-for-vulkan-decode-fail.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1122-Fix-for-vulkan-decode-fail.patch deleted file mode 100644 index 3ced8ac3..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1122-Fix-for-vulkan-decode-fail.patch +++ /dev/null @@ -1,44 +0,0 @@ -From b9951504af58c2ffefb7bcf9f420653414328fa4 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@.com> -Date: Wed, 21 Sep 2016 15:51:08 +0530 -Subject: [PATCH 12/12] Fix for vulkan decode fail - -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -index f14e4aa..849c795 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -@@ -247,6 +247,26 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) - if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) - adev->uvd.address_64_bit = true; - -+ -+ switch (adev->asic_type) { -+ case CHIP_TONGA: -+ adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; -+ break; -+ case CHIP_CARRIZO: -+ adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; -+ break; -+ case CHIP_FIJI: -+ adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; -+ break; -+ case CHIP_STONEY: -+ adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; -+ break; -+ default: -+ adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; -+ -+ } -+ -+ - return 0; - } - --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1123-ioctl-number-modified-DRM_AMDGPU_WAIT_FENCES.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1123-ioctl-number-modified-DRM_AMDGPU_WAIT_FENCES.patch deleted file mode 100644 index 99b4d727..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1123-ioctl-number-modified-DRM_AMDGPU_WAIT_FENCES.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 26488f88527f81632b56e978af744f7d697a6e06 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <Sanju.Mehta@amd.com> -Date: Tue, 27 Sep 2016 17:28:00 +0530 -Subject: [PATCH] ioctl number modified DRM_AMDGPU_WAIT_FENCES - ---- - drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -index 8ff615b..ada6576 100644 ---- a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -+++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -@@ -46,9 +46,10 @@ - #define DRM_AMDGPU_WAIT_CS 0x09 - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 --#define DRM_AMDGPU_WAIT_FENCES 0x12 - #define DRM_AMDGPU_FREESYNC 0x14 - -+#define DRM_AMDGPU_WAIT_FENCES 0x5e -+ - #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) - #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) - #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1124-add-amdgpu.cg_mask-and-amdgpu.pg_mask-parameters.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1124-add-amdgpu.cg_mask-and-amdgpu.pg_mask-parameters.patch deleted file mode 100644 index ff18aa48..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1124-add-amdgpu.cg_mask-and-amdgpu.pg_mask-parameters.patch +++ /dev/null @@ -1,77 +0,0 @@ -From b6dadf7dceff70f8a09cf57fe7f1aa29427f764f Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Thu, 13 Oct 2016 12:52:22 +0530 -Subject: [PATCH 1/2] add amdgpu.cg_mask and amdgpu.pg_mask parameters -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -They allow disabling clock and power gating from the kernel command line, -which hopefully helps with diagnosing problems in the field. - -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Nicolai Hähnle <Nicolai.Haehnle@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++ - drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++++ - 3 files changed, 13 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -index b15b3b5..d3de21d 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -@@ -89,6 +89,8 @@ extern int amdgpu_sched_hw_submission; - extern int amdgpu_powerplay; - extern unsigned amdgpu_pcie_gen_cap; - extern unsigned amdgpu_pcie_lane_cap; -+extern unsigned amdgpu_cg_mask; -+extern unsigned amdgpu_pg_mask; - - #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 - #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -index 6077ec6..ba5a67b 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -@@ -1208,6 +1208,9 @@ static int amdgpu_early_init(struct amdgpu_device *adev) - } - } - -+ adev->cg_flags &= amdgpu_cg_mask; -+ adev->pg_flags &= amdgpu_pg_mask; -+ - return 0; - } - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c -index af014c3..340d5fd 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c -@@ -83,6 +83,8 @@ int amdgpu_sched_hw_submission = 2; - int amdgpu_powerplay = -1; - unsigned amdgpu_pcie_gen_cap = 0; - unsigned amdgpu_pcie_lane_cap = 0; -+unsigned amdgpu_cg_mask = 0xffffffff; -+unsigned amdgpu_pg_mask = 0xffffffff; - - MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); - module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); -@@ -170,6 +172,12 @@ module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); - MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); - module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); - -+MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); -+module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); -+ -+MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); -+module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); -+ - static const struct pci_device_id pciidlist[] = { - #ifdef CONFIG_DRM_AMDGPU_CIK - /* Kaveri */ --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1125-drm-amdgpu-gfx8-disable-EDC.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1125-drm-amdgpu-gfx8-disable-EDC.patch deleted file mode 100644 index 2b51de5e..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1125-drm-amdgpu-gfx8-disable-EDC.patch +++ /dev/null @@ -1,42 +0,0 @@ -From b8e93c19d2aaa3d0f48a802dd779ca27e66236d2 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Thu, 13 Oct 2016 12:30:35 +0530 -Subject: [PATCH 2/2] drm/amdgpu/gfx8: disable EDC - -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 ++++++---- - 1 file changed, 6 insertions(+), 4 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -index 92f3ee6..c5a3d04 100644 ---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -@@ -1700,6 +1700,11 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) - goto fail; - } - -+ /* read back registers to clear the counters */ -+ for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) -+ RREG32(sec_ded_counter_registers[i]); -+ -+#if 0 - tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2); - tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1); - WREG32(mmGB_EDC_MODE, tmp); -@@ -1708,10 +1713,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) - tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1; - WREG32(mmCC_GC_EDC_CONFIG, tmp); - -- -- /* read back registers to clear the counters */ -- for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) -- RREG32(sec_ded_counter_registers[i]); -+#endif - - fail: - fence_put(f); --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1126-ASoC-AMD-add-ACP-2.2-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1126-ASoC-AMD-add-ACP-2.2-register-headers.patch deleted file mode 100644 index d625d781..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1126-ASoC-AMD-add-ACP-2.2-register-headers.patch +++ /dev/null @@ -1,4049 +0,0 @@ -From dd2944623f22469b05842032d161e522c1fca725 Mon Sep 17 00:00:00 2001 -From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> -Date: Fri, 18 Sep 2015 13:11:22 +0530 -Subject: [PATCH 01/17] ASoC : AMD : add ACP 2.2 register headers - -These are register headers for the ACP (Audio CoProcessor) v2.2 - -Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> ---- - drivers/base/power/domain.c | 2 + - include/sound/designware_i2s.h | 6 + - sound/soc/amd/include/acp_2_2_d.h | 609 ++++++++ - sound/soc/amd/include/acp_2_2_enum.h | 1068 ++++++++++++++ - sound/soc/amd/include/acp_2_2_sh_mask.h | 2292 +++++++++++++++++++++++++++++++ - 5 files changed, 3977 insertions(+) - create mode 100644 sound/soc/amd/include/acp_2_2_d.h - create mode 100644 sound/soc/amd/include/acp_2_2_enum.h - create mode 100644 sound/soc/amd/include/acp_2_2_sh_mask.h - -diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c -index a48824d..ac913f8 100644 ---- a/drivers/base/power/domain.c -+++ b/drivers/base/power/domain.c -@@ -1263,6 +1263,7 @@ int __pm_genpd_add_device(struct generic_pm_domain *genpd, struct device *dev, - - return ret; - } -+EXPORT_SYMBOL_GPL(__pm_genpd_add_device); - - /** - * pm_genpd_remove_device - Remove a device from an I/O PM domain. -@@ -1313,6 +1314,7 @@ int pm_genpd_remove_device(struct generic_pm_domain *genpd, - - return ret; - } -+EXPORT_SYMBOL_GPL(pm_genpd_remove_device); - - /** - * pm_genpd_add_subdomain - Add a subdomain to an I/O PM domain. -diff --git a/include/sound/designware_i2s.h b/include/sound/designware_i2s.h -index 8966ba7..f919a9b 100644 ---- a/include/sound/designware_i2s.h -+++ b/include/sound/designware_i2s.h -@@ -45,6 +45,12 @@ struct i2s_platform_data { - u32 snd_fmts; - u32 snd_rates; - -+ #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0) -+ #define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1) -+ unsigned int quirks; -+ unsigned int i2s_reg_comp1; -+ unsigned int i2s_reg_comp2; -+ - void *play_dma_data; - void *capture_dma_data; - bool (*filter)(struct dma_chan *chan, void *slave); -diff --git a/sound/soc/amd/include/acp_2_2_d.h b/sound/soc/amd/include/acp_2_2_d.h -new file mode 100644 -index 0000000..0118fe9 ---- /dev/null -+++ b/sound/soc/amd/include/acp_2_2_d.h -@@ -0,0 +1,609 @@ -+/* -+ * ACP_2_2 Register documentation -+ * -+ * Copyright (C) 2014 Advanced Micro Devices, Inc. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included -+ * in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN -+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#ifndef ACP_2_2_D_H -+#define ACP_2_2_D_H -+ -+#define mmACP_DMA_CNTL_0 0x5000 -+#define mmACP_DMA_CNTL_1 0x5001 -+#define mmACP_DMA_CNTL_2 0x5002 -+#define mmACP_DMA_CNTL_3 0x5003 -+#define mmACP_DMA_CNTL_4 0x5004 -+#define mmACP_DMA_CNTL_5 0x5005 -+#define mmACP_DMA_CNTL_6 0x5006 -+#define mmACP_DMA_CNTL_7 0x5007 -+#define mmACP_DMA_CNTL_8 0x5008 -+#define mmACP_DMA_CNTL_9 0x5009 -+#define mmACP_DMA_CNTL_10 0x500a -+#define mmACP_DMA_CNTL_11 0x500b -+#define mmACP_DMA_CNTL_12 0x500c -+#define mmACP_DMA_CNTL_13 0x500d -+#define mmACP_DMA_CNTL_14 0x500e -+#define mmACP_DMA_CNTL_15 0x500f -+#define mmACP_DMA_DSCR_STRT_IDX_0 0x5010 -+#define mmACP_DMA_DSCR_STRT_IDX_1 0x5011 -+#define mmACP_DMA_DSCR_STRT_IDX_2 0x5012 -+#define mmACP_DMA_DSCR_STRT_IDX_3 0x5013 -+#define mmACP_DMA_DSCR_STRT_IDX_4 0x5014 -+#define mmACP_DMA_DSCR_STRT_IDX_5 0x5015 -+#define mmACP_DMA_DSCR_STRT_IDX_6 0x5016 -+#define mmACP_DMA_DSCR_STRT_IDX_7 0x5017 -+#define mmACP_DMA_DSCR_STRT_IDX_8 0x5018 -+#define mmACP_DMA_DSCR_STRT_IDX_9 0x5019 -+#define mmACP_DMA_DSCR_STRT_IDX_10 0x501a -+#define mmACP_DMA_DSCR_STRT_IDX_11 0x501b -+#define mmACP_DMA_DSCR_STRT_IDX_12 0x501c -+#define mmACP_DMA_DSCR_STRT_IDX_13 0x501d -+#define mmACP_DMA_DSCR_STRT_IDX_14 0x501e -+#define mmACP_DMA_DSCR_STRT_IDX_15 0x501f -+#define mmACP_DMA_DSCR_CNT_0 0x5020 -+#define mmACP_DMA_DSCR_CNT_1 0x5021 -+#define mmACP_DMA_DSCR_CNT_2 0x5022 -+#define mmACP_DMA_DSCR_CNT_3 0x5023 -+#define mmACP_DMA_DSCR_CNT_4 0x5024 -+#define mmACP_DMA_DSCR_CNT_5 0x5025 -+#define mmACP_DMA_DSCR_CNT_6 0x5026 -+#define mmACP_DMA_DSCR_CNT_7 0x5027 -+#define mmACP_DMA_DSCR_CNT_8 0x5028 -+#define mmACP_DMA_DSCR_CNT_9 0x5029 -+#define mmACP_DMA_DSCR_CNT_10 0x502a -+#define mmACP_DMA_DSCR_CNT_11 0x502b -+#define mmACP_DMA_DSCR_CNT_12 0x502c -+#define mmACP_DMA_DSCR_CNT_13 0x502d -+#define mmACP_DMA_DSCR_CNT_14 0x502e -+#define mmACP_DMA_DSCR_CNT_15 0x502f -+#define mmACP_DMA_PRIO_0 0x5030 -+#define mmACP_DMA_PRIO_1 0x5031 -+#define mmACP_DMA_PRIO_2 0x5032 -+#define mmACP_DMA_PRIO_3 0x5033 -+#define mmACP_DMA_PRIO_4 0x5034 -+#define mmACP_DMA_PRIO_5 0x5035 -+#define mmACP_DMA_PRIO_6 0x5036 -+#define mmACP_DMA_PRIO_7 0x5037 -+#define mmACP_DMA_PRIO_8 0x5038 -+#define mmACP_DMA_PRIO_9 0x5039 -+#define mmACP_DMA_PRIO_10 0x503a -+#define mmACP_DMA_PRIO_11 0x503b -+#define mmACP_DMA_PRIO_12 0x503c -+#define mmACP_DMA_PRIO_13 0x503d -+#define mmACP_DMA_PRIO_14 0x503e -+#define mmACP_DMA_PRIO_15 0x503f -+#define mmACP_DMA_CUR_DSCR_0 0x5040 -+#define mmACP_DMA_CUR_DSCR_1 0x5041 -+#define mmACP_DMA_CUR_DSCR_2 0x5042 -+#define mmACP_DMA_CUR_DSCR_3 0x5043 -+#define mmACP_DMA_CUR_DSCR_4 0x5044 -+#define mmACP_DMA_CUR_DSCR_5 0x5045 -+#define mmACP_DMA_CUR_DSCR_6 0x5046 -+#define mmACP_DMA_CUR_DSCR_7 0x5047 -+#define mmACP_DMA_CUR_DSCR_8 0x5048 -+#define mmACP_DMA_CUR_DSCR_9 0x5049 -+#define mmACP_DMA_CUR_DSCR_10 0x504a -+#define mmACP_DMA_CUR_DSCR_11 0x504b -+#define mmACP_DMA_CUR_DSCR_12 0x504c -+#define mmACP_DMA_CUR_DSCR_13 0x504d -+#define mmACP_DMA_CUR_DSCR_14 0x504e -+#define mmACP_DMA_CUR_DSCR_15 0x504f -+#define mmACP_DMA_CUR_TRANS_CNT_0 0x5050 -+#define mmACP_DMA_CUR_TRANS_CNT_1 0x5051 -+#define mmACP_DMA_CUR_TRANS_CNT_2 0x5052 -+#define mmACP_DMA_CUR_TRANS_CNT_3 0x5053 -+#define mmACP_DMA_CUR_TRANS_CNT_4 0x5054 -+#define mmACP_DMA_CUR_TRANS_CNT_5 0x5055 -+#define mmACP_DMA_CUR_TRANS_CNT_6 0x5056 -+#define mmACP_DMA_CUR_TRANS_CNT_7 0x5057 -+#define mmACP_DMA_CUR_TRANS_CNT_8 0x5058 -+#define mmACP_DMA_CUR_TRANS_CNT_9 0x5059 -+#define mmACP_DMA_CUR_TRANS_CNT_10 0x505a -+#define mmACP_DMA_CUR_TRANS_CNT_11 0x505b -+#define mmACP_DMA_CUR_TRANS_CNT_12 0x505c -+#define mmACP_DMA_CUR_TRANS_CNT_13 0x505d -+#define mmACP_DMA_CUR_TRANS_CNT_14 0x505e -+#define mmACP_DMA_CUR_TRANS_CNT_15 0x505f -+#define mmACP_DMA_ERR_STS_0 0x5060 -+#define mmACP_DMA_ERR_STS_1 0x5061 -+#define mmACP_DMA_ERR_STS_2 0x5062 -+#define mmACP_DMA_ERR_STS_3 0x5063 -+#define mmACP_DMA_ERR_STS_4 0x5064 -+#define mmACP_DMA_ERR_STS_5 0x5065 -+#define mmACP_DMA_ERR_STS_6 0x5066 -+#define mmACP_DMA_ERR_STS_7 0x5067 -+#define mmACP_DMA_ERR_STS_8 0x5068 -+#define mmACP_DMA_ERR_STS_9 0x5069 -+#define mmACP_DMA_ERR_STS_10 0x506a -+#define mmACP_DMA_ERR_STS_11 0x506b -+#define mmACP_DMA_ERR_STS_12 0x506c -+#define mmACP_DMA_ERR_STS_13 0x506d -+#define mmACP_DMA_ERR_STS_14 0x506e -+#define mmACP_DMA_ERR_STS_15 0x506f -+#define mmACP_DMA_DESC_BASE_ADDR 0x5070 -+#define mmACP_DMA_DESC_MAX_NUM_DSCR 0x5071 -+#define mmACP_DMA_CH_STS 0x5072 -+#define mmACP_DMA_CH_GROUP 0x5073 -+#define mmACP_DSP0_CACHE_OFFSET0 0x5078 -+#define mmACP_DSP0_CACHE_SIZE0 0x5079 -+#define mmACP_DSP0_CACHE_OFFSET1 0x507a -+#define mmACP_DSP0_CACHE_SIZE1 0x507b -+#define mmACP_DSP0_CACHE_OFFSET2 0x507c -+#define mmACP_DSP0_CACHE_SIZE2 0x507d -+#define mmACP_DSP0_CACHE_OFFSET3 0x507e -+#define mmACP_DSP0_CACHE_SIZE3 0x507f -+#define mmACP_DSP0_CACHE_OFFSET4 0x5080 -+#define mmACP_DSP0_CACHE_SIZE4 0x5081 -+#define mmACP_DSP0_CACHE_OFFSET5 0x5082 -+#define mmACP_DSP0_CACHE_SIZE5 0x5083 -+#define mmACP_DSP0_CACHE_OFFSET6 0x5084 -+#define mmACP_DSP0_CACHE_SIZE6 0x5085 -+#define mmACP_DSP0_CACHE_OFFSET7 0x5086 -+#define mmACP_DSP0_CACHE_SIZE7 0x5087 -+#define mmACP_DSP0_CACHE_OFFSET8 0x5088 -+#define mmACP_DSP0_CACHE_SIZE8 0x5089 -+#define mmACP_DSP0_NONCACHE_OFFSET0 0x508a -+#define mmACP_DSP0_NONCACHE_SIZE0 0x508b -+#define mmACP_DSP0_NONCACHE_OFFSET1 0x508c -+#define mmACP_DSP0_NONCACHE_SIZE1 0x508d -+#define mmACP_DSP0_DEBUG_PC 0x508e -+#define mmACP_DSP0_NMI_SEL 0x508f -+#define mmACP_DSP0_CLKRST_CNTL 0x5090 -+#define mmACP_DSP0_RUNSTALL 0x5091 -+#define mmACP_DSP0_OCD_HALT_ON_RST 0x5092 -+#define mmACP_DSP0_WAIT_MODE 0x5093 -+#define mmACP_DSP0_VECT_SEL 0x5094 -+#define mmACP_DSP0_DEBUG_REG1 0x5095 -+#define mmACP_DSP0_DEBUG_REG2 0x5096 -+#define mmACP_DSP0_DEBUG_REG3 0x5097 -+#define mmACP_DSP1_CACHE_OFFSET0 0x509d -+#define mmACP_DSP1_CACHE_SIZE0 0x509e -+#define mmACP_DSP1_CACHE_OFFSET1 0x509f -+#define mmACP_DSP1_CACHE_SIZE1 0x50a0 -+#define mmACP_DSP1_CACHE_OFFSET2 0x50a1 -+#define mmACP_DSP1_CACHE_SIZE2 0x50a2 -+#define mmACP_DSP1_CACHE_OFFSET3 0x50a3 -+#define mmACP_DSP1_CACHE_SIZE3 0x50a4 -+#define mmACP_DSP1_CACHE_OFFSET4 0x50a5 -+#define mmACP_DSP1_CACHE_SIZE4 0x50a6 -+#define mmACP_DSP1_CACHE_OFFSET5 0x50a7 -+#define mmACP_DSP1_CACHE_SIZE5 0x50a8 -+#define mmACP_DSP1_CACHE_OFFSET6 0x50a9 -+#define mmACP_DSP1_CACHE_SIZE6 0x50aa -+#define mmACP_DSP1_CACHE_OFFSET7 0x50ab -+#define mmACP_DSP1_CACHE_SIZE7 0x50ac -+#define mmACP_DSP1_CACHE_OFFSET8 0x50ad -+#define mmACP_DSP1_CACHE_SIZE8 0x50ae -+#define mmACP_DSP1_NONCACHE_OFFSET0 0x50af -+#define mmACP_DSP1_NONCACHE_SIZE0 0x50b0 -+#define mmACP_DSP1_NONCACHE_OFFSET1 0x50b1 -+#define mmACP_DSP1_NONCACHE_SIZE1 0x50b2 -+#define mmACP_DSP1_DEBUG_PC 0x50b3 -+#define mmACP_DSP1_NMI_SEL 0x50b4 -+#define mmACP_DSP1_CLKRST_CNTL 0x50b5 -+#define mmACP_DSP1_RUNSTALL 0x50b6 -+#define mmACP_DSP1_OCD_HALT_ON_RST 0x50b7 -+#define mmACP_DSP1_WAIT_MODE 0x50b8 -+#define mmACP_DSP1_VECT_SEL 0x50b9 -+#define mmACP_DSP1_DEBUG_REG1 0x50ba -+#define mmACP_DSP1_DEBUG_REG2 0x50bb -+#define mmACP_DSP1_DEBUG_REG3 0x50bc -+#define mmACP_DSP2_CACHE_OFFSET0 0x50c2 -+#define mmACP_DSP2_CACHE_SIZE0 0x50c3 -+#define mmACP_DSP2_CACHE_OFFSET1 0x50c4 -+#define mmACP_DSP2_CACHE_SIZE1 0x50c5 -+#define mmACP_DSP2_CACHE_OFFSET2 0x50c6 -+#define mmACP_DSP2_CACHE_SIZE2 0x50c7 -+#define mmACP_DSP2_CACHE_OFFSET3 0x50c8 -+#define mmACP_DSP2_CACHE_SIZE3 0x50c9 -+#define mmACP_DSP2_CACHE_OFFSET4 0x50ca -+#define mmACP_DSP2_CACHE_SIZE4 0x50cb -+#define mmACP_DSP2_CACHE_OFFSET5 0x50cc -+#define mmACP_DSP2_CACHE_SIZE5 0x50cd -+#define mmACP_DSP2_CACHE_OFFSET6 0x50ce -+#define mmACP_DSP2_CACHE_SIZE6 0x50cf -+#define mmACP_DSP2_CACHE_OFFSET7 0x50d0 -+#define mmACP_DSP2_CACHE_SIZE7 0x50d1 -+#define mmACP_DSP2_CACHE_OFFSET8 0x50d2 -+#define mmACP_DSP2_CACHE_SIZE8 0x50d3 -+#define mmACP_DSP2_NONCACHE_OFFSET0 0x50d4 -+#define mmACP_DSP2_NONCACHE_SIZE0 0x50d5 -+#define mmACP_DSP2_NONCACHE_OFFSET1 0x50d6 -+#define mmACP_DSP2_NONCACHE_SIZE1 0x50d7 -+#define mmACP_DSP2_DEBUG_PC 0x50d8 -+#define mmACP_DSP2_NMI_SEL 0x50d9 -+#define mmACP_DSP2_CLKRST_CNTL 0x50da -+#define mmACP_DSP2_RUNSTALL 0x50db -+#define mmACP_DSP2_OCD_HALT_ON_RST 0x50dc -+#define mmACP_DSP2_WAIT_MODE 0x50dd -+#define mmACP_DSP2_VECT_SEL 0x50de -+#define mmACP_DSP2_DEBUG_REG1 0x50df -+#define mmACP_DSP2_DEBUG_REG2 0x50e0 -+#define mmACP_DSP2_DEBUG_REG3 0x50e1 -+#define mmACP_AXI2DAGB_ONION_CNTL 0x50e7 -+#define mmACP_AXI2DAGB_ONION_ERR_STATUS_WR 0x50e8 -+#define mmACP_AXI2DAGB_ONION_ERR_STATUS_RD 0x50e9 -+#define mmACP_DAGB_Onion_TransPerf_Counter_Control 0x50ea -+#define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Current 0x50eb -+#define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Peak 0x50ec -+#define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Current 0x50ed -+#define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Peak 0x50ee -+#define mmACP_AXI2DAGB_GARLIC_CNTL 0x50f3 -+#define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_WR 0x50f4 -+#define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_RD 0x50f5 -+#define mmACP_DAGB_Garlic_TransPerf_Counter_Control 0x50f6 -+#define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Current 0x50f7 -+#define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak 0x50f8 -+#define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Current 0x50f9 -+#define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak 0x50fa -+#define mmACP_DAGB_PAGE_SIZE_GRP_1 0x50ff -+#define mmACP_DAGB_BASE_ADDR_GRP_1 0x5100 -+#define mmACP_DAGB_PAGE_SIZE_GRP_2 0x5101 -+#define mmACP_DAGB_BASE_ADDR_GRP_2 0x5102 -+#define mmACP_DAGB_PAGE_SIZE_GRP_3 0x5103 -+#define mmACP_DAGB_BASE_ADDR_GRP_3 0x5104 -+#define mmACP_DAGB_PAGE_SIZE_GRP_4 0x5105 -+#define mmACP_DAGB_BASE_ADDR_GRP_4 0x5106 -+#define mmACP_DAGB_PAGE_SIZE_GRP_5 0x5107 -+#define mmACP_DAGB_BASE_ADDR_GRP_5 0x5108 -+#define mmACP_DAGB_PAGE_SIZE_GRP_6 0x5109 -+#define mmACP_DAGB_BASE_ADDR_GRP_6 0x510a -+#define mmACP_DAGB_PAGE_SIZE_GRP_7 0x510b -+#define mmACP_DAGB_BASE_ADDR_GRP_7 0x510c -+#define mmACP_DAGB_PAGE_SIZE_GRP_8 0x510d -+#define mmACP_DAGB_BASE_ADDR_GRP_8 0x510e -+#define mmACP_DAGB_ATU_CTRL 0x510f -+#define mmACP_CONTROL 0x5131 -+#define mmACP_STATUS 0x5133 -+#define mmACP_SOFT_RESET 0x5134 -+#define mmACP_PwrMgmt_CNTL 0x5135 -+#define mmACP_CAC_INDICATOR_CONTROL 0x5136 -+#define mmACP_SMU_MAILBOX 0x5137 -+#define mmACP_FUTURE_REG_SCLK_0 0x5138 -+#define mmACP_FUTURE_REG_SCLK_1 0x5139 -+#define mmACP_FUTURE_REG_SCLK_2 0x513a -+#define mmACP_FUTURE_REG_SCLK_3 0x513b -+#define mmACP_FUTURE_REG_SCLK_4 0x513c -+#define mmACP_DAGB_DEBUG_CNT_ENABLE 0x513d -+#define mmACP_DAGBG_WR_ASK_CNT 0x513e -+#define mmACP_DAGBG_WR_GO_CNT 0x513f -+#define mmACP_DAGBG_WR_EXP_RESP_CNT 0x5140 -+#define mmACP_DAGBG_WR_ACTUAL_RESP_CNT 0x5141 -+#define mmACP_DAGBG_RD_ASK_CNT 0x5142 -+#define mmACP_DAGBG_RD_GO_CNT 0x5143 -+#define mmACP_DAGBG_RD_EXP_RESP_CNT 0x5144 -+#define mmACP_DAGBG_RD_ACTUAL_RESP_CNT 0x5145 -+#define mmACP_DAGBO_WR_ASK_CNT 0x5146 -+#define mmACP_DAGBO_WR_GO_CNT 0x5147 -+#define mmACP_DAGBO_WR_EXP_RESP_CNT 0x5148 -+#define mmACP_DAGBO_WR_ACTUAL_RESP_CNT 0x5149 -+#define mmACP_DAGBO_RD_ASK_CNT 0x514a -+#define mmACP_DAGBO_RD_GO_CNT 0x514b -+#define mmACP_DAGBO_RD_EXP_RESP_CNT 0x514c -+#define mmACP_DAGBO_RD_ACTUAL_RESP_CNT 0x514d -+#define mmACP_BRB_CONTROL 0x5156 -+#define mmACP_EXTERNAL_INTR_ENB 0x5157 -+#define mmACP_EXTERNAL_INTR_CNTL 0x5158 -+#define mmACP_ERROR_SOURCE_STS 0x5159 -+#define mmACP_DSP_SW_INTR_TRIG 0x515a -+#define mmACP_DSP_SW_INTR_CNTL 0x515b -+#define mmACP_DAGBG_TIMEOUT_CNTL 0x515c -+#define mmACP_DAGBO_TIMEOUT_CNTL 0x515d -+#define mmACP_EXTERNAL_INTR_STAT 0x515e -+#define mmACP_DSP_SW_INTR_STAT 0x515f -+#define mmACP_DSP0_INTR_CNTL 0x5160 -+#define mmACP_DSP0_INTR_STAT 0x5161 -+#define mmACP_DSP0_TIMEOUT_CNTL 0x5162 -+#define mmACP_DSP1_INTR_CNTL 0x5163 -+#define mmACP_DSP1_INTR_STAT 0x5164 -+#define mmACP_DSP1_TIMEOUT_CNTL 0x5165 -+#define mmACP_DSP2_INTR_CNTL 0x5166 -+#define mmACP_DSP2_INTR_STAT 0x5167 -+#define mmACP_DSP2_TIMEOUT_CNTL 0x5168 -+#define mmACP_DSP0_EXT_TIMER_CNTL 0x5169 -+#define mmACP_DSP1_EXT_TIMER_CNTL 0x516a -+#define mmACP_DSP2_EXT_TIMER_CNTL 0x516b -+#define mmACP_AXI2DAGB_SEM_0 0x516c -+#define mmACP_AXI2DAGB_SEM_1 0x516d -+#define mmACP_AXI2DAGB_SEM_2 0x516e -+#define mmACP_AXI2DAGB_SEM_3 0x516f -+#define mmACP_AXI2DAGB_SEM_4 0x5170 -+#define mmACP_AXI2DAGB_SEM_5 0x5171 -+#define mmACP_AXI2DAGB_SEM_6 0x5172 -+#define mmACP_AXI2DAGB_SEM_7 0x5173 -+#define mmACP_AXI2DAGB_SEM_8 0x5174 -+#define mmACP_AXI2DAGB_SEM_9 0x5175 -+#define mmACP_AXI2DAGB_SEM_10 0x5176 -+#define mmACP_AXI2DAGB_SEM_11 0x5177 -+#define mmACP_AXI2DAGB_SEM_12 0x5178 -+#define mmACP_AXI2DAGB_SEM_13 0x5179 -+#define mmACP_AXI2DAGB_SEM_14 0x517a -+#define mmACP_AXI2DAGB_SEM_15 0x517b -+#define mmACP_AXI2DAGB_SEM_16 0x517c -+#define mmACP_AXI2DAGB_SEM_17 0x517d -+#define mmACP_AXI2DAGB_SEM_18 0x517e -+#define mmACP_AXI2DAGB_SEM_19 0x517f -+#define mmACP_AXI2DAGB_SEM_20 0x5180 -+#define mmACP_AXI2DAGB_SEM_21 0x5181 -+#define mmACP_AXI2DAGB_SEM_22 0x5182 -+#define mmACP_AXI2DAGB_SEM_23 0x5183 -+#define mmACP_AXI2DAGB_SEM_24 0x5184 -+#define mmACP_AXI2DAGB_SEM_25 0x5185 -+#define mmACP_AXI2DAGB_SEM_26 0x5186 -+#define mmACP_AXI2DAGB_SEM_27 0x5187 -+#define mmACP_AXI2DAGB_SEM_28 0x5188 -+#define mmACP_AXI2DAGB_SEM_29 0x5189 -+#define mmACP_AXI2DAGB_SEM_30 0x518a -+#define mmACP_AXI2DAGB_SEM_31 0x518b -+#define mmACP_AXI2DAGB_SEM_32 0x518c -+#define mmACP_AXI2DAGB_SEM_33 0x518d -+#define mmACP_AXI2DAGB_SEM_34 0x518e -+#define mmACP_AXI2DAGB_SEM_35 0x518f -+#define mmACP_AXI2DAGB_SEM_36 0x5190 -+#define mmACP_AXI2DAGB_SEM_37 0x5191 -+#define mmACP_AXI2DAGB_SEM_38 0x5192 -+#define mmACP_AXI2DAGB_SEM_39 0x5193 -+#define mmACP_AXI2DAGB_SEM_40 0x5194 -+#define mmACP_AXI2DAGB_SEM_41 0x5195 -+#define mmACP_AXI2DAGB_SEM_42 0x5196 -+#define mmACP_AXI2DAGB_SEM_43 0x5197 -+#define mmACP_AXI2DAGB_SEM_44 0x5198 -+#define mmACP_AXI2DAGB_SEM_45 0x5199 -+#define mmACP_AXI2DAGB_SEM_46 0x519a -+#define mmACP_AXI2DAGB_SEM_47 0x519b -+#define mmACP_SRBM_Client_Base_Addr 0x519c -+#define mmACP_SRBM_Client_RDDATA 0x519d -+#define mmACP_SRBM_Cycle_Sts 0x519e -+#define mmACP_SRBM_Targ_Idx_Addr 0x519f -+#define mmACP_SRBM_Targ_Idx_Data 0x51a0 -+#define mmACP_SEMA_ADDR_LOW 0x51a1 -+#define mmACP_SEMA_ADDR_HIGH 0x51a2 -+#define mmACP_SEMA_CMD 0x51a3 -+#define mmACP_SEMA_STS 0x51a4 -+#define mmACP_SEMA_REQ 0x51a5 -+#define mmACP_FW_STATUS 0x51a6 -+#define mmACP_FUTURE_REG_ACLK_0 0x51a7 -+#define mmACP_FUTURE_REG_ACLK_1 0x51a8 -+#define mmACP_FUTURE_REG_ACLK_2 0x51a9 -+#define mmACP_FUTURE_REG_ACLK_3 0x51aa -+#define mmACP_FUTURE_REG_ACLK_4 0x51ab -+#define mmACP_TIMER 0x51ac -+#define mmACP_TIMER_CNTL 0x51ad -+#define mmACP_DSP0_TIMER 0x51ae -+#define mmACP_DSP1_TIMER 0x51af -+#define mmACP_DSP2_TIMER 0x51b0 -+#define mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH 0x51b1 -+#define mmACP_I2S_TRANSMIT_BYTE_CNT_LOW 0x51b2 -+#define mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH 0x51b3 -+#define mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW 0x51b4 -+#define mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH 0x51b5 -+#define mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW 0x51b6 -+#define mmACP_DSP0_CS_STATE 0x51b7 -+#define mmACP_DSP1_CS_STATE 0x51b8 -+#define mmACP_DSP2_CS_STATE 0x51b9 -+#define mmACP_SCRATCH_REG_BASE_ADDR 0x51ba -+#define mmCC_ACP_EFUSE 0x51c8 -+#define mmACP_PGFSM_RETAIN_REG 0x51c9 -+#define mmACP_PGFSM_CONFIG_REG 0x51ca -+#define mmACP_PGFSM_WRITE_REG 0x51cb -+#define mmACP_PGFSM_READ_REG_0 0x51cc -+#define mmACP_PGFSM_READ_REG_1 0x51cd -+#define mmACP_PGFSM_READ_REG_2 0x51ce -+#define mmACP_PGFSM_READ_REG_3 0x51cf -+#define mmACP_PGFSM_READ_REG_4 0x51d0 -+#define mmACP_PGFSM_READ_REG_5 0x51d1 -+#define mmACP_IP_PGFSM_ENABLE 0x51d2 -+#define mmACP_I2S_PIN_CONFIG 0x51d3 -+#define mmACP_AZALIA_I2S_SELECT 0x51d4 -+#define mmACP_CHIP_PKG_FOR_PAD_ISOLATION 0x51d5 -+#define mmACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL 0x51d6 -+#define mmACP_BT_UART_PAD_SEL 0x51d7 -+#define mmACP_SCRATCH_REG_0 0x52c0 -+#define mmACP_SCRATCH_REG_1 0x52c1 -+#define mmACP_SCRATCH_REG_2 0x52c2 -+#define mmACP_SCRATCH_REG_3 0x52c3 -+#define mmACP_SCRATCH_REG_4 0x52c4 -+#define mmACP_SCRATCH_REG_5 0x52c5 -+#define mmACP_SCRATCH_REG_6 0x52c6 -+#define mmACP_SCRATCH_REG_7 0x52c7 -+#define mmACP_SCRATCH_REG_8 0x52c8 -+#define mmACP_SCRATCH_REG_9 0x52c9 -+#define mmACP_SCRATCH_REG_10 0x52ca -+#define mmACP_SCRATCH_REG_11 0x52cb -+#define mmACP_SCRATCH_REG_12 0x52cc -+#define mmACP_SCRATCH_REG_13 0x52cd -+#define mmACP_SCRATCH_REG_14 0x52ce -+#define mmACP_SCRATCH_REG_15 0x52cf -+#define mmACP_SCRATCH_REG_16 0x52d0 -+#define mmACP_SCRATCH_REG_17 0x52d1 -+#define mmACP_SCRATCH_REG_18 0x52d2 -+#define mmACP_SCRATCH_REG_19 0x52d3 -+#define mmACP_SCRATCH_REG_20 0x52d4 -+#define mmACP_SCRATCH_REG_21 0x52d5 -+#define mmACP_SCRATCH_REG_22 0x52d6 -+#define mmACP_SCRATCH_REG_23 0x52d7 -+#define mmACP_SCRATCH_REG_24 0x52d8 -+#define mmACP_SCRATCH_REG_25 0x52d9 -+#define mmACP_SCRATCH_REG_26 0x52da -+#define mmACP_SCRATCH_REG_27 0x52db -+#define mmACP_SCRATCH_REG_28 0x52dc -+#define mmACP_SCRATCH_REG_29 0x52dd -+#define mmACP_SCRATCH_REG_30 0x52de -+#define mmACP_SCRATCH_REG_31 0x52df -+#define mmACP_SCRATCH_REG_32 0x52e0 -+#define mmACP_SCRATCH_REG_33 0x52e1 -+#define mmACP_SCRATCH_REG_34 0x52e2 -+#define mmACP_SCRATCH_REG_35 0x52e3 -+#define mmACP_SCRATCH_REG_36 0x52e4 -+#define mmACP_SCRATCH_REG_37 0x52e5 -+#define mmACP_SCRATCH_REG_38 0x52e6 -+#define mmACP_SCRATCH_REG_39 0x52e7 -+#define mmACP_SCRATCH_REG_40 0x52e8 -+#define mmACP_SCRATCH_REG_41 0x52e9 -+#define mmACP_SCRATCH_REG_42 0x52ea -+#define mmACP_SCRATCH_REG_43 0x52eb -+#define mmACP_SCRATCH_REG_44 0x52ec -+#define mmACP_SCRATCH_REG_45 0x52ed -+#define mmACP_SCRATCH_REG_46 0x52ee -+#define mmACP_SCRATCH_REG_47 0x52ef -+#define mmACP_VOICE_WAKEUP_ENABLE 0x51e8 -+#define mmACP_VOICE_WAKEUP_STATUS 0x51e9 -+#define mmI2S_VOICE_WAKEUP_LOWER_THRESHOLD 0x51ea -+#define mmI2S_VOICE_WAKEUP_HIGHER_THRESHOLD 0x51eb -+#define mmI2S_VOICE_WAKEUP_NO_OF_SAMPLES 0x51ec -+#define mmI2S_VOICE_WAKEUP_NO_OF_PEAKS 0x51ed -+#define mmI2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS 0x51ee -+#define mmI2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION 0x51ef -+#define mmI2S_VOICE_WAKEUP_DATA_PATH_SWITCH 0x51f0 -+#define mmI2S_VOICE_WAKEUP_DATA_POINTER 0x51f1 -+#define mmI2S_VOICE_WAKEUP_AUTH_MATCH 0x51f2 -+#define mmI2S_VOICE_WAKEUP_8KB_WRAP 0x51f3 -+#define mmACP_I2S_RECEIVED_BYTE_CNT_HIGH 0x51f4 -+#define mmACP_I2S_RECEIVED_BYTE_CNT_LOW 0x51f5 -+#define mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH 0x51f6 -+#define mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW 0x51f7 -+#define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8 -+#define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9 -+#define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa -+#define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb -+#define mmACP_MEM_DEEP_SLEEP_REQ_LO 0x51fc -+#define mmACP_MEM_DEEP_SLEEP_REQ_HI 0x51fd -+#define mmACP_MEM_DEEP_SLEEP_STS_LO 0x51fe -+#define mmACP_MEM_DEEP_SLEEP_STS_HI 0x51ff -+#define mmACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO 0x5200 -+#define mmACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI 0x5201 -+#define mmACP_MEM_WAKEUP_FROM_SLEEP_LO 0x5202 -+#define mmACP_MEM_WAKEUP_FROM_SLEEP_HI 0x5203 -+#define mmACP_I2SSP_IER 0x5210 -+#define mmACP_I2SSP_IRER 0x5211 -+#define mmACP_I2SSP_ITER 0x5212 -+#define mmACP_I2SSP_CER 0x5213 -+#define mmACP_I2SSP_CCR 0x5214 -+#define mmACP_I2SSP_RXFFR 0x5215 -+#define mmACP_I2SSP_TXFFR 0x5216 -+#define mmACP_I2SSP_LRBR0 0x5218 -+#define mmACP_I2SSP_RRBR0 0x5219 -+#define mmACP_I2SSP_RER0 0x521a -+#define mmACP_I2SSP_TER0 0x521b -+#define mmACP_I2SSP_RCR0 0x521c -+#define mmACP_I2SSP_TCR0 0x521d -+#define mmACP_I2SSP_ISR0 0x521e -+#define mmACP_I2SSP_IMR0 0x521f -+#define mmACP_I2SSP_ROR0 0x5220 -+#define mmACP_I2SSP_TOR0 0x5221 -+#define mmACP_I2SSP_RFCR0 0x5222 -+#define mmACP_I2SSP_TFCR0 0x5223 -+#define mmACP_I2SSP_RFF0 0x5224 -+#define mmACP_I2SSP_TFF0 0x5225 -+#define mmACP_I2SSP_RXDMA 0x5226 -+#define mmACP_I2SSP_RRXDMA 0x5227 -+#define mmACP_I2SSP_TXDMA 0x5228 -+#define mmACP_I2SSP_RTXDMA 0x5229 -+#define mmACP_I2SSP_COMP_PARAM_2 0x522a -+#define mmACP_I2SSP_COMP_PARAM_1 0x522b -+#define mmACP_I2SSP_COMP_VERSION 0x522c -+#define mmACP_I2SSP_COMP_TYPE 0x522d -+#define mmACP_I2SMICSP_IER 0x522e -+#define mmACP_I2SMICSP_IRER 0x522f -+#define mmACP_I2SMICSP_ITER 0x5230 -+#define mmACP_I2SMICSP_CER 0x5231 -+#define mmACP_I2SMICSP_CCR 0x5232 -+#define mmACP_I2SMICSP_RXFFR 0x5233 -+#define mmACP_I2SMICSP_TXFFR 0x5234 -+#define mmACP_I2SMICSP_LRBR0 0x5236 -+#define mmACP_I2SMICSP_RRBR0 0x5237 -+#define mmACP_I2SMICSP_RER0 0x5238 -+#define mmACP_I2SMICSP_TER0 0x5239 -+#define mmACP_I2SMICSP_RCR0 0x523a -+#define mmACP_I2SMICSP_TCR0 0x523b -+#define mmACP_I2SMICSP_ISR0 0x523c -+#define mmACP_I2SMICSP_IMR0 0x523d -+#define mmACP_I2SMICSP_ROR0 0x523e -+#define mmACP_I2SMICSP_TOR0 0x523f -+#define mmACP_I2SMICSP_RFCR0 0x5240 -+#define mmACP_I2SMICSP_TFCR0 0x5241 -+#define mmACP_I2SMICSP_RFF0 0x5242 -+#define mmACP_I2SMICSP_TFF0 0x5243 -+#define mmACP_I2SMICSP_LRBR1 0x5246 -+#define mmACP_I2SMICSP_RRBR1 0x5247 -+#define mmACP_I2SMICSP_RER1 0x5248 -+#define mmACP_I2SMICSP_TER1 0x5249 -+#define mmACP_I2SMICSP_RCR1 0x524a -+#define mmACP_I2SMICSP_TCR1 0x524b -+#define mmACP_I2SMICSP_ISR1 0x524c -+#define mmACP_I2SMICSP_IMR1 0x524d -+#define mmACP_I2SMICSP_ROR1 0x524e -+#define mmACP_I2SMICSP_TOR1 0x524f -+#define mmACP_I2SMICSP_RFCR1 0x5250 -+#define mmACP_I2SMICSP_TFCR1 0x5251 -+#define mmACP_I2SMICSP_RFF1 0x5252 -+#define mmACP_I2SMICSP_TFF1 0x5253 -+#define mmACP_I2SMICSP_RXDMA 0x5254 -+#define mmACP_I2SMICSP_RRXDMA 0x5255 -+#define mmACP_I2SMICSP_TXDMA 0x5256 -+#define mmACP_I2SMICSP_RTXDMA 0x5257 -+#define mmACP_I2SMICSP_COMP_PARAM_2 0x5258 -+#define mmACP_I2SMICSP_COMP_PARAM_1 0x5259 -+#define mmACP_I2SMICSP_COMP_VERSION 0x525a -+#define mmACP_I2SMICSP_COMP_TYPE 0x525b -+#define mmACP_I2SBT_IER 0x525c -+#define mmACP_I2SBT_IRER 0x525d -+#define mmACP_I2SBT_ITER 0x525e -+#define mmACP_I2SBT_CER 0x525f -+#define mmACP_I2SBT_CCR 0x5260 -+#define mmACP_I2SBT_RXFFR 0x5261 -+#define mmACP_I2SBT_TXFFR 0x5262 -+#define mmACP_I2SBT_LRBR0 0x5264 -+#define mmACP_I2SBT_RRBR0 0x5265 -+#define mmACP_I2SBT_RER0 0x5266 -+#define mmACP_I2SBT_TER0 0x5267 -+#define mmACP_I2SBT_RCR0 0x5268 -+#define mmACP_I2SBT_TCR0 0x5269 -+#define mmACP_I2SBT_ISR0 0x526a -+#define mmACP_I2SBT_IMR0 0x526b -+#define mmACP_I2SBT_ROR0 0x526c -+#define mmACP_I2SBT_TOR0 0x526d -+#define mmACP_I2SBT_RFCR0 0x526e -+#define mmACP_I2SBT_TFCR0 0x526f -+#define mmACP_I2SBT_RFF0 0x5270 -+#define mmACP_I2SBT_TFF0 0x5271 -+#define mmACP_I2SBT_LRBR1 0x5274 -+#define mmACP_I2SBT_RRBR1 0x5275 -+#define mmACP_I2SBT_RER1 0x5276 -+#define mmACP_I2SBT_TER1 0x5277 -+#define mmACP_I2SBT_RCR1 0x5278 -+#define mmACP_I2SBT_TCR1 0x5279 -+#define mmACP_I2SBT_ISR1 0x527a -+#define mmACP_I2SBT_IMR1 0x527b -+#define mmACP_I2SBT_ROR1 0x527c -+#define mmACP_I2SBT_TOR1 0x527d -+#define mmACP_I2SBT_RFCR1 0x527e -+#define mmACP_I2SBT_TFCR1 0x527f -+#define mmACP_I2SBT_RFF1 0x5280 -+#define mmACP_I2SBT_TFF1 0x5281 -+#define mmACP_I2SBT_RXDMA 0x5282 -+#define mmACP_I2SBT_RRXDMA 0x5283 -+#define mmACP_I2SBT_TXDMA 0x5284 -+#define mmACP_I2SBT_RTXDMA 0x5285 -+#define mmACP_I2SBT_COMP_PARAM_2 0x5286 -+#define mmACP_I2SBT_COMP_PARAM_1 0x5287 -+#define mmACP_I2SBT_COMP_VERSION 0x5288 -+#define mmACP_I2SBT_COMP_TYPE 0x5289 -+ -+#endif /* ACP_2_2_D_H */ -diff --git a/sound/soc/amd/include/acp_2_2_enum.h b/sound/soc/amd/include/acp_2_2_enum.h -new file mode 100644 -index 0000000..f3577c8 ---- /dev/null -+++ b/sound/soc/amd/include/acp_2_2_enum.h -@@ -0,0 +1,1068 @@ -+/* -+ * ACP_2_2 Register documentation -+ * -+ * Copyright (C) 2014 Advanced Micro Devices, Inc. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included -+ * in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN -+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#ifndef ACP_2_2_ENUM_H -+#define ACP_2_2_ENUM_H -+ -+typedef enum DebugBlockId { -+ DBG_BLOCK_ID_RESERVED = 0x0, -+ DBG_BLOCK_ID_DBG = 0x1, -+ DBG_BLOCK_ID_VMC = 0x2, -+ DBG_BLOCK_ID_PDMA = 0x3, -+ DBG_BLOCK_ID_CG = 0x4, -+ DBG_BLOCK_ID_SRBM = 0x5, -+ DBG_BLOCK_ID_GRBM = 0x6, -+ DBG_BLOCK_ID_RLC = 0x7, -+ DBG_BLOCK_ID_CSC = 0x8, -+ DBG_BLOCK_ID_SEM = 0x9, -+ DBG_BLOCK_ID_IH = 0xa, -+ DBG_BLOCK_ID_SC = 0xb, -+ DBG_BLOCK_ID_SQ = 0xc, -+ DBG_BLOCK_ID_UVDU = 0xd, -+ DBG_BLOCK_ID_SQA = 0xe, -+ DBG_BLOCK_ID_SDMA0 = 0xf, -+ DBG_BLOCK_ID_SDMA1 = 0x10, -+ DBG_BLOCK_ID_SPIM = 0x11, -+ DBG_BLOCK_ID_GDS = 0x12, -+ DBG_BLOCK_ID_VC0 = 0x13, -+ DBG_BLOCK_ID_VC1 = 0x14, -+ DBG_BLOCK_ID_PA0 = 0x15, -+ DBG_BLOCK_ID_PA1 = 0x16, -+ DBG_BLOCK_ID_CP0 = 0x17, -+ DBG_BLOCK_ID_CP1 = 0x18, -+ DBG_BLOCK_ID_CP2 = 0x19, -+ DBG_BLOCK_ID_XBR = 0x1a, -+ DBG_BLOCK_ID_UVDM = 0x1b, -+ DBG_BLOCK_ID_VGT0 = 0x1c, -+ DBG_BLOCK_ID_VGT1 = 0x1d, -+ DBG_BLOCK_ID_IA = 0x1e, -+ DBG_BLOCK_ID_SXM0 = 0x1f, -+ DBG_BLOCK_ID_SXM1 = 0x20, -+ DBG_BLOCK_ID_SCT0 = 0x21, -+ DBG_BLOCK_ID_SCT1 = 0x22, -+ DBG_BLOCK_ID_SPM0 = 0x23, -+ DBG_BLOCK_ID_SPM1 = 0x24, -+ DBG_BLOCK_ID_UNUSED0 = 0x25, -+ DBG_BLOCK_ID_UNUSED1 = 0x26, -+ DBG_BLOCK_ID_TCAA = 0x27, -+ DBG_BLOCK_ID_TCAB = 0x28, -+ DBG_BLOCK_ID_TCCA = 0x29, -+ DBG_BLOCK_ID_TCCB = 0x2a, -+ DBG_BLOCK_ID_MCC0 = 0x2b, -+ DBG_BLOCK_ID_MCC1 = 0x2c, -+ DBG_BLOCK_ID_MCC2 = 0x2d, -+ DBG_BLOCK_ID_MCC3 = 0x2e, -+ DBG_BLOCK_ID_SXS0 = 0x2f, -+ DBG_BLOCK_ID_SXS1 = 0x30, -+ DBG_BLOCK_ID_SXS2 = 0x31, -+ DBG_BLOCK_ID_SXS3 = 0x32, -+ DBG_BLOCK_ID_SXS4 = 0x33, -+ DBG_BLOCK_ID_SXS5 = 0x34, -+ DBG_BLOCK_ID_SXS6 = 0x35, -+ DBG_BLOCK_ID_SXS7 = 0x36, -+ DBG_BLOCK_ID_SXS8 = 0x37, -+ DBG_BLOCK_ID_SXS9 = 0x38, -+ DBG_BLOCK_ID_BCI0 = 0x39, -+ DBG_BLOCK_ID_BCI1 = 0x3a, -+ DBG_BLOCK_ID_BCI2 = 0x3b, -+ DBG_BLOCK_ID_BCI3 = 0x3c, -+ DBG_BLOCK_ID_MCB = 0x3d, -+ DBG_BLOCK_ID_UNUSED6 = 0x3e, -+ DBG_BLOCK_ID_SQA00 = 0x3f, -+ DBG_BLOCK_ID_SQA01 = 0x40, -+ DBG_BLOCK_ID_SQA02 = 0x41, -+ DBG_BLOCK_ID_SQA10 = 0x42, -+ DBG_BLOCK_ID_SQA11 = 0x43, -+ DBG_BLOCK_ID_SQA12 = 0x44, -+ DBG_BLOCK_ID_UNUSED7 = 0x45, -+ DBG_BLOCK_ID_UNUSED8 = 0x46, -+ DBG_BLOCK_ID_SQB00 = 0x47, -+ DBG_BLOCK_ID_SQB01 = 0x48, -+ DBG_BLOCK_ID_SQB10 = 0x49, -+ DBG_BLOCK_ID_SQB11 = 0x4a, -+ DBG_BLOCK_ID_SQ00 = 0x4b, -+ DBG_BLOCK_ID_SQ01 = 0x4c, -+ DBG_BLOCK_ID_SQ10 = 0x4d, -+ DBG_BLOCK_ID_SQ11 = 0x4e, -+ DBG_BLOCK_ID_CB00 = 0x4f, -+ DBG_BLOCK_ID_CB01 = 0x50, -+ DBG_BLOCK_ID_CB02 = 0x51, -+ DBG_BLOCK_ID_CB03 = 0x52, -+ DBG_BLOCK_ID_CB04 = 0x53, -+ DBG_BLOCK_ID_UNUSED9 = 0x54, -+ DBG_BLOCK_ID_UNUSED10 = 0x55, -+ DBG_BLOCK_ID_UNUSED11 = 0x56, -+ DBG_BLOCK_ID_CB10 = 0x57, -+ DBG_BLOCK_ID_CB11 = 0x58, -+ DBG_BLOCK_ID_CB12 = 0x59, -+ DBG_BLOCK_ID_CB13 = 0x5a, -+ DBG_BLOCK_ID_CB14 = 0x5b, -+ DBG_BLOCK_ID_UNUSED12 = 0x5c, -+ DBG_BLOCK_ID_UNUSED13 = 0x5d, -+ DBG_BLOCK_ID_UNUSED14 = 0x5e, -+ DBG_BLOCK_ID_TCP0 = 0x5f, -+ DBG_BLOCK_ID_TCP1 = 0x60, -+ DBG_BLOCK_ID_TCP2 = 0x61, -+ DBG_BLOCK_ID_TCP3 = 0x62, -+ DBG_BLOCK_ID_TCP4 = 0x63, -+ DBG_BLOCK_ID_TCP5 = 0x64, -+ DBG_BLOCK_ID_TCP6 = 0x65, -+ DBG_BLOCK_ID_TCP7 = 0x66, -+ DBG_BLOCK_ID_TCP8 = 0x67, -+ DBG_BLOCK_ID_TCP9 = 0x68, -+ DBG_BLOCK_ID_TCP10 = 0x69, -+ DBG_BLOCK_ID_TCP11 = 0x6a, -+ DBG_BLOCK_ID_TCP12 = 0x6b, -+ DBG_BLOCK_ID_TCP13 = 0x6c, -+ DBG_BLOCK_ID_TCP14 = 0x6d, -+ DBG_BLOCK_ID_TCP15 = 0x6e, -+ DBG_BLOCK_ID_TCP16 = 0x6f, -+ DBG_BLOCK_ID_TCP17 = 0x70, -+ DBG_BLOCK_ID_TCP18 = 0x71, -+ DBG_BLOCK_ID_TCP19 = 0x72, -+ DBG_BLOCK_ID_TCP20 = 0x73, -+ DBG_BLOCK_ID_TCP21 = 0x74, -+ DBG_BLOCK_ID_TCP22 = 0x75, -+ DBG_BLOCK_ID_TCP23 = 0x76, -+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, -+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, -+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, -+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, -+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, -+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, -+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, -+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, -+ DBG_BLOCK_ID_DB00 = 0x7f, -+ DBG_BLOCK_ID_DB01 = 0x80, -+ DBG_BLOCK_ID_DB02 = 0x81, -+ DBG_BLOCK_ID_DB03 = 0x82, -+ DBG_BLOCK_ID_DB04 = 0x83, -+ DBG_BLOCK_ID_UNUSED15 = 0x84, -+ DBG_BLOCK_ID_UNUSED16 = 0x85, -+ DBG_BLOCK_ID_UNUSED17 = 0x86, -+ DBG_BLOCK_ID_DB10 = 0x87, -+ DBG_BLOCK_ID_DB11 = 0x88, -+ DBG_BLOCK_ID_DB12 = 0x89, -+ DBG_BLOCK_ID_DB13 = 0x8a, -+ DBG_BLOCK_ID_DB14 = 0x8b, -+ DBG_BLOCK_ID_UNUSED18 = 0x8c, -+ DBG_BLOCK_ID_UNUSED19 = 0x8d, -+ DBG_BLOCK_ID_UNUSED20 = 0x8e, -+ DBG_BLOCK_ID_TCC0 = 0x8f, -+ DBG_BLOCK_ID_TCC1 = 0x90, -+ DBG_BLOCK_ID_TCC2 = 0x91, -+ DBG_BLOCK_ID_TCC3 = 0x92, -+ DBG_BLOCK_ID_TCC4 = 0x93, -+ DBG_BLOCK_ID_TCC5 = 0x94, -+ DBG_BLOCK_ID_TCC6 = 0x95, -+ DBG_BLOCK_ID_TCC7 = 0x96, -+ DBG_BLOCK_ID_SPS00 = 0x97, -+ DBG_BLOCK_ID_SPS01 = 0x98, -+ DBG_BLOCK_ID_SPS02 = 0x99, -+ DBG_BLOCK_ID_SPS10 = 0x9a, -+ DBG_BLOCK_ID_SPS11 = 0x9b, -+ DBG_BLOCK_ID_SPS12 = 0x9c, -+ DBG_BLOCK_ID_UNUSED21 = 0x9d, -+ DBG_BLOCK_ID_UNUSED22 = 0x9e, -+ DBG_BLOCK_ID_TA00 = 0x9f, -+ DBG_BLOCK_ID_TA01 = 0xa0, -+ DBG_BLOCK_ID_TA02 = 0xa1, -+ DBG_BLOCK_ID_TA03 = 0xa2, -+ DBG_BLOCK_ID_TA04 = 0xa3, -+ DBG_BLOCK_ID_TA05 = 0xa4, -+ DBG_BLOCK_ID_TA06 = 0xa5, -+ DBG_BLOCK_ID_TA07 = 0xa6, -+ DBG_BLOCK_ID_TA08 = 0xa7, -+ DBG_BLOCK_ID_TA09 = 0xa8, -+ DBG_BLOCK_ID_TA0A = 0xa9, -+ DBG_BLOCK_ID_TA0B = 0xaa, -+ DBG_BLOCK_ID_UNUSED23 = 0xab, -+ DBG_BLOCK_ID_UNUSED24 = 0xac, -+ DBG_BLOCK_ID_UNUSED25 = 0xad, -+ DBG_BLOCK_ID_UNUSED26 = 0xae, -+ DBG_BLOCK_ID_TA10 = 0xaf, -+ DBG_BLOCK_ID_TA11 = 0xb0, -+ DBG_BLOCK_ID_TA12 = 0xb1, -+ DBG_BLOCK_ID_TA13 = 0xb2, -+ DBG_BLOCK_ID_TA14 = 0xb3, -+ DBG_BLOCK_ID_TA15 = 0xb4, -+ DBG_BLOCK_ID_TA16 = 0xb5, -+ DBG_BLOCK_ID_TA17 = 0xb6, -+ DBG_BLOCK_ID_TA18 = 0xb7, -+ DBG_BLOCK_ID_TA19 = 0xb8, -+ DBG_BLOCK_ID_TA1A = 0xb9, -+ DBG_BLOCK_ID_TA1B = 0xba, -+ DBG_BLOCK_ID_UNUSED27 = 0xbb, -+ DBG_BLOCK_ID_UNUSED28 = 0xbc, -+ DBG_BLOCK_ID_UNUSED29 = 0xbd, -+ DBG_BLOCK_ID_UNUSED30 = 0xbe, -+ DBG_BLOCK_ID_TD00 = 0xbf, -+ DBG_BLOCK_ID_TD01 = 0xc0, -+ DBG_BLOCK_ID_TD02 = 0xc1, -+ DBG_BLOCK_ID_TD03 = 0xc2, -+ DBG_BLOCK_ID_TD04 = 0xc3, -+ DBG_BLOCK_ID_TD05 = 0xc4, -+ DBG_BLOCK_ID_TD06 = 0xc5, -+ DBG_BLOCK_ID_TD07 = 0xc6, -+ DBG_BLOCK_ID_TD08 = 0xc7, -+ DBG_BLOCK_ID_TD09 = 0xc8, -+ DBG_BLOCK_ID_TD0A = 0xc9, -+ DBG_BLOCK_ID_TD0B = 0xca, -+ DBG_BLOCK_ID_UNUSED31 = 0xcb, -+ DBG_BLOCK_ID_UNUSED32 = 0xcc, -+ DBG_BLOCK_ID_UNUSED33 = 0xcd, -+ DBG_BLOCK_ID_UNUSED34 = 0xce, -+ DBG_BLOCK_ID_TD10 = 0xcf, -+ DBG_BLOCK_ID_TD11 = 0xd0, -+ DBG_BLOCK_ID_TD12 = 0xd1, -+ DBG_BLOCK_ID_TD13 = 0xd2, -+ DBG_BLOCK_ID_TD14 = 0xd3, -+ DBG_BLOCK_ID_TD15 = 0xd4, -+ DBG_BLOCK_ID_TD16 = 0xd5, -+ DBG_BLOCK_ID_TD17 = 0xd6, -+ DBG_BLOCK_ID_TD18 = 0xd7, -+ DBG_BLOCK_ID_TD19 = 0xd8, -+ DBG_BLOCK_ID_TD1A = 0xd9, -+ DBG_BLOCK_ID_TD1B = 0xda, -+ DBG_BLOCK_ID_UNUSED35 = 0xdb, -+ DBG_BLOCK_ID_UNUSED36 = 0xdc, -+ DBG_BLOCK_ID_UNUSED37 = 0xdd, -+ DBG_BLOCK_ID_UNUSED38 = 0xde, -+ DBG_BLOCK_ID_LDS00 = 0xdf, -+ DBG_BLOCK_ID_LDS01 = 0xe0, -+ DBG_BLOCK_ID_LDS02 = 0xe1, -+ DBG_BLOCK_ID_LDS03 = 0xe2, -+ DBG_BLOCK_ID_LDS04 = 0xe3, -+ DBG_BLOCK_ID_LDS05 = 0xe4, -+ DBG_BLOCK_ID_LDS06 = 0xe5, -+ DBG_BLOCK_ID_LDS07 = 0xe6, -+ DBG_BLOCK_ID_LDS08 = 0xe7, -+ DBG_BLOCK_ID_LDS09 = 0xe8, -+ DBG_BLOCK_ID_LDS0A = 0xe9, -+ DBG_BLOCK_ID_LDS0B = 0xea, -+ DBG_BLOCK_ID_UNUSED39 = 0xeb, -+ DBG_BLOCK_ID_UNUSED40 = 0xec, -+ DBG_BLOCK_ID_UNUSED41 = 0xed, -+ DBG_BLOCK_ID_UNUSED42 = 0xee, -+ DBG_BLOCK_ID_LDS10 = 0xef, -+ DBG_BLOCK_ID_LDS11 = 0xf0, -+ DBG_BLOCK_ID_LDS12 = 0xf1, -+ DBG_BLOCK_ID_LDS13 = 0xf2, -+ DBG_BLOCK_ID_LDS14 = 0xf3, -+ DBG_BLOCK_ID_LDS15 = 0xf4, -+ DBG_BLOCK_ID_LDS16 = 0xf5, -+ DBG_BLOCK_ID_LDS17 = 0xf6, -+ DBG_BLOCK_ID_LDS18 = 0xf7, -+ DBG_BLOCK_ID_LDS19 = 0xf8, -+ DBG_BLOCK_ID_LDS1A = 0xf9, -+ DBG_BLOCK_ID_LDS1B = 0xfa, -+ DBG_BLOCK_ID_UNUSED43 = 0xfb, -+ DBG_BLOCK_ID_UNUSED44 = 0xfc, -+ DBG_BLOCK_ID_UNUSED45 = 0xfd, -+ DBG_BLOCK_ID_UNUSED46 = 0xfe, -+} DebugBlockId; -+typedef enum DebugBlockId_BY2 { -+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0, -+ DBG_BLOCK_ID_VMC_BY2 = 0x1, -+ DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, -+ DBG_BLOCK_ID_GRBM_BY2 = 0x3, -+ DBG_BLOCK_ID_CSC_BY2 = 0x4, -+ DBG_BLOCK_ID_IH_BY2 = 0x5, -+ DBG_BLOCK_ID_SQ_BY2 = 0x6, -+ DBG_BLOCK_ID_UVD_BY2 = 0x7, -+ DBG_BLOCK_ID_SDMA0_BY2 = 0x8, -+ DBG_BLOCK_ID_SPIM_BY2 = 0x9, -+ DBG_BLOCK_ID_VC0_BY2 = 0xa, -+ DBG_BLOCK_ID_PA_BY2 = 0xb, -+ DBG_BLOCK_ID_CP0_BY2 = 0xc, -+ DBG_BLOCK_ID_CP2_BY2 = 0xd, -+ DBG_BLOCK_ID_PC0_BY2 = 0xe, -+ DBG_BLOCK_ID_BCI0_BY2 = 0xf, -+ DBG_BLOCK_ID_SXM0_BY2 = 0x10, -+ DBG_BLOCK_ID_SCT0_BY2 = 0x11, -+ DBG_BLOCK_ID_SPM0_BY2 = 0x12, -+ DBG_BLOCK_ID_BCI2_BY2 = 0x13, -+ DBG_BLOCK_ID_TCA_BY2 = 0x14, -+ DBG_BLOCK_ID_TCCA_BY2 = 0x15, -+ DBG_BLOCK_ID_MCC_BY2 = 0x16, -+ DBG_BLOCK_ID_MCC2_BY2 = 0x17, -+ DBG_BLOCK_ID_MCD_BY2 = 0x18, -+ DBG_BLOCK_ID_MCD2_BY2 = 0x19, -+ DBG_BLOCK_ID_MCD4_BY2 = 0x1a, -+ DBG_BLOCK_ID_MCB_BY2 = 0x1b, -+ DBG_BLOCK_ID_SQA_BY2 = 0x1c, -+ DBG_BLOCK_ID_SQA02_BY2 = 0x1d, -+ DBG_BLOCK_ID_SQA11_BY2 = 0x1e, -+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, -+ DBG_BLOCK_ID_SQB_BY2 = 0x20, -+ DBG_BLOCK_ID_SQB10_BY2 = 0x21, -+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, -+ DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, -+ DBG_BLOCK_ID_CB_BY2 = 0x24, -+ DBG_BLOCK_ID_CB02_BY2 = 0x25, -+ DBG_BLOCK_ID_CB10_BY2 = 0x26, -+ DBG_BLOCK_ID_CB12_BY2 = 0x27, -+ DBG_BLOCK_ID_SXS_BY2 = 0x28, -+ DBG_BLOCK_ID_SXS2_BY2 = 0x29, -+ DBG_BLOCK_ID_SXS4_BY2 = 0x2a, -+ DBG_BLOCK_ID_SXS6_BY2 = 0x2b, -+ DBG_BLOCK_ID_DB_BY2 = 0x2c, -+ DBG_BLOCK_ID_DB02_BY2 = 0x2d, -+ DBG_BLOCK_ID_DB10_BY2 = 0x2e, -+ DBG_BLOCK_ID_DB12_BY2 = 0x2f, -+ DBG_BLOCK_ID_TCP_BY2 = 0x30, -+ DBG_BLOCK_ID_TCP2_BY2 = 0x31, -+ DBG_BLOCK_ID_TCP4_BY2 = 0x32, -+ DBG_BLOCK_ID_TCP6_BY2 = 0x33, -+ DBG_BLOCK_ID_TCP8_BY2 = 0x34, -+ DBG_BLOCK_ID_TCP10_BY2 = 0x35, -+ DBG_BLOCK_ID_TCP12_BY2 = 0x36, -+ DBG_BLOCK_ID_TCP14_BY2 = 0x37, -+ DBG_BLOCK_ID_TCP16_BY2 = 0x38, -+ DBG_BLOCK_ID_TCP18_BY2 = 0x39, -+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a, -+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b, -+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, -+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, -+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, -+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, -+ DBG_BLOCK_ID_TCC_BY2 = 0x40, -+ DBG_BLOCK_ID_TCC2_BY2 = 0x41, -+ DBG_BLOCK_ID_TCC4_BY2 = 0x42, -+ DBG_BLOCK_ID_TCC6_BY2 = 0x43, -+ DBG_BLOCK_ID_SPS_BY2 = 0x44, -+ DBG_BLOCK_ID_SPS02_BY2 = 0x45, -+ DBG_BLOCK_ID_SPS11_BY2 = 0x46, -+ DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, -+ DBG_BLOCK_ID_TA_BY2 = 0x48, -+ DBG_BLOCK_ID_TA02_BY2 = 0x49, -+ DBG_BLOCK_ID_TA04_BY2 = 0x4a, -+ DBG_BLOCK_ID_TA06_BY2 = 0x4b, -+ DBG_BLOCK_ID_TA08_BY2 = 0x4c, -+ DBG_BLOCK_ID_TA0A_BY2 = 0x4d, -+ DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, -+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, -+ DBG_BLOCK_ID_TA10_BY2 = 0x50, -+ DBG_BLOCK_ID_TA12_BY2 = 0x51, -+ DBG_BLOCK_ID_TA14_BY2 = 0x52, -+ DBG_BLOCK_ID_TA16_BY2 = 0x53, -+ DBG_BLOCK_ID_TA18_BY2 = 0x54, -+ DBG_BLOCK_ID_TA1A_BY2 = 0x55, -+ DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, -+ DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, -+ DBG_BLOCK_ID_TD_BY2 = 0x58, -+ DBG_BLOCK_ID_TD02_BY2 = 0x59, -+ DBG_BLOCK_ID_TD04_BY2 = 0x5a, -+ DBG_BLOCK_ID_TD06_BY2 = 0x5b, -+ DBG_BLOCK_ID_TD08_BY2 = 0x5c, -+ DBG_BLOCK_ID_TD0A_BY2 = 0x5d, -+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, -+ DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, -+ DBG_BLOCK_ID_TD10_BY2 = 0x60, -+ DBG_BLOCK_ID_TD12_BY2 = 0x61, -+ DBG_BLOCK_ID_TD14_BY2 = 0x62, -+ DBG_BLOCK_ID_TD16_BY2 = 0x63, -+ DBG_BLOCK_ID_TD18_BY2 = 0x64, -+ DBG_BLOCK_ID_TD1A_BY2 = 0x65, -+ DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, -+ DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, -+ DBG_BLOCK_ID_LDS_BY2 = 0x68, -+ DBG_BLOCK_ID_LDS02_BY2 = 0x69, -+ DBG_BLOCK_ID_LDS04_BY2 = 0x6a, -+ DBG_BLOCK_ID_LDS06_BY2 = 0x6b, -+ DBG_BLOCK_ID_LDS08_BY2 = 0x6c, -+ DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, -+ DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, -+ DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, -+ DBG_BLOCK_ID_LDS10_BY2 = 0x70, -+ DBG_BLOCK_ID_LDS12_BY2 = 0x71, -+ DBG_BLOCK_ID_LDS14_BY2 = 0x72, -+ DBG_BLOCK_ID_LDS16_BY2 = 0x73, -+ DBG_BLOCK_ID_LDS18_BY2 = 0x74, -+ DBG_BLOCK_ID_LDS1A_BY2 = 0x75, -+ DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, -+ DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, -+} DebugBlockId_BY2; -+typedef enum DebugBlockId_BY4 { -+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0, -+ DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, -+ DBG_BLOCK_ID_CSC_BY4 = 0x2, -+ DBG_BLOCK_ID_SQ_BY4 = 0x3, -+ DBG_BLOCK_ID_SDMA0_BY4 = 0x4, -+ DBG_BLOCK_ID_VC0_BY4 = 0x5, -+ DBG_BLOCK_ID_CP0_BY4 = 0x6, -+ DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, -+ DBG_BLOCK_ID_SXM0_BY4 = 0x8, -+ DBG_BLOCK_ID_SPM0_BY4 = 0x9, -+ DBG_BLOCK_ID_TCAA_BY4 = 0xa, -+ DBG_BLOCK_ID_MCC_BY4 = 0xb, -+ DBG_BLOCK_ID_MCD_BY4 = 0xc, -+ DBG_BLOCK_ID_MCD4_BY4 = 0xd, -+ DBG_BLOCK_ID_SQA_BY4 = 0xe, -+ DBG_BLOCK_ID_SQA11_BY4 = 0xf, -+ DBG_BLOCK_ID_SQB_BY4 = 0x10, -+ DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, -+ DBG_BLOCK_ID_CB_BY4 = 0x12, -+ DBG_BLOCK_ID_CB10_BY4 = 0x13, -+ DBG_BLOCK_ID_SXS_BY4 = 0x14, -+ DBG_BLOCK_ID_SXS4_BY4 = 0x15, -+ DBG_BLOCK_ID_DB_BY4 = 0x16, -+ DBG_BLOCK_ID_DB10_BY4 = 0x17, -+ DBG_BLOCK_ID_TCP_BY4 = 0x18, -+ DBG_BLOCK_ID_TCP4_BY4 = 0x19, -+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a, -+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b, -+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c, -+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d, -+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, -+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, -+ DBG_BLOCK_ID_TCC_BY4 = 0x20, -+ DBG_BLOCK_ID_TCC4_BY4 = 0x21, -+ DBG_BLOCK_ID_SPS_BY4 = 0x22, -+ DBG_BLOCK_ID_SPS11_BY4 = 0x23, -+ DBG_BLOCK_ID_TA_BY4 = 0x24, -+ DBG_BLOCK_ID_TA04_BY4 = 0x25, -+ DBG_BLOCK_ID_TA08_BY4 = 0x26, -+ DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, -+ DBG_BLOCK_ID_TA10_BY4 = 0x28, -+ DBG_BLOCK_ID_TA14_BY4 = 0x29, -+ DBG_BLOCK_ID_TA18_BY4 = 0x2a, -+ DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, -+ DBG_BLOCK_ID_TD_BY4 = 0x2c, -+ DBG_BLOCK_ID_TD04_BY4 = 0x2d, -+ DBG_BLOCK_ID_TD08_BY4 = 0x2e, -+ DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, -+ DBG_BLOCK_ID_TD10_BY4 = 0x30, -+ DBG_BLOCK_ID_TD14_BY4 = 0x31, -+ DBG_BLOCK_ID_TD18_BY4 = 0x32, -+ DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, -+ DBG_BLOCK_ID_LDS_BY4 = 0x34, -+ DBG_BLOCK_ID_LDS04_BY4 = 0x35, -+ DBG_BLOCK_ID_LDS08_BY4 = 0x36, -+ DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, -+ DBG_BLOCK_ID_LDS10_BY4 = 0x38, -+ DBG_BLOCK_ID_LDS14_BY4 = 0x39, -+ DBG_BLOCK_ID_LDS18_BY4 = 0x3a, -+ DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, -+} DebugBlockId_BY4; -+typedef enum DebugBlockId_BY8 { -+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0, -+ DBG_BLOCK_ID_CSC_BY8 = 0x1, -+ DBG_BLOCK_ID_SDMA0_BY8 = 0x2, -+ DBG_BLOCK_ID_CP0_BY8 = 0x3, -+ DBG_BLOCK_ID_SXM0_BY8 = 0x4, -+ DBG_BLOCK_ID_TCA_BY8 = 0x5, -+ DBG_BLOCK_ID_MCD_BY8 = 0x6, -+ DBG_BLOCK_ID_SQA_BY8 = 0x7, -+ DBG_BLOCK_ID_SQB_BY8 = 0x8, -+ DBG_BLOCK_ID_CB_BY8 = 0x9, -+ DBG_BLOCK_ID_SXS_BY8 = 0xa, -+ DBG_BLOCK_ID_DB_BY8 = 0xb, -+ DBG_BLOCK_ID_TCP_BY8 = 0xc, -+ DBG_BLOCK_ID_TCP8_BY8 = 0xd, -+ DBG_BLOCK_ID_TCP16_BY8 = 0xe, -+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, -+ DBG_BLOCK_ID_TCC_BY8 = 0x10, -+ DBG_BLOCK_ID_SPS_BY8 = 0x11, -+ DBG_BLOCK_ID_TA_BY8 = 0x12, -+ DBG_BLOCK_ID_TA08_BY8 = 0x13, -+ DBG_BLOCK_ID_TA10_BY8 = 0x14, -+ DBG_BLOCK_ID_TA18_BY8 = 0x15, -+ DBG_BLOCK_ID_TD_BY8 = 0x16, -+ DBG_BLOCK_ID_TD08_BY8 = 0x17, -+ DBG_BLOCK_ID_TD10_BY8 = 0x18, -+ DBG_BLOCK_ID_TD18_BY8 = 0x19, -+ DBG_BLOCK_ID_LDS_BY8 = 0x1a, -+ DBG_BLOCK_ID_LDS08_BY8 = 0x1b, -+ DBG_BLOCK_ID_LDS10_BY8 = 0x1c, -+ DBG_BLOCK_ID_LDS18_BY8 = 0x1d, -+} DebugBlockId_BY8; -+typedef enum DebugBlockId_BY16 { -+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0, -+ DBG_BLOCK_ID_SDMA0_BY16 = 0x1, -+ DBG_BLOCK_ID_SXM_BY16 = 0x2, -+ DBG_BLOCK_ID_MCD_BY16 = 0x3, -+ DBG_BLOCK_ID_SQB_BY16 = 0x4, -+ DBG_BLOCK_ID_SXS_BY16 = 0x5, -+ DBG_BLOCK_ID_TCP_BY16 = 0x6, -+ DBG_BLOCK_ID_TCP16_BY16 = 0x7, -+ DBG_BLOCK_ID_TCC_BY16 = 0x8, -+ DBG_BLOCK_ID_TA_BY16 = 0x9, -+ DBG_BLOCK_ID_TA10_BY16 = 0xa, -+ DBG_BLOCK_ID_TD_BY16 = 0xb, -+ DBG_BLOCK_ID_TD10_BY16 = 0xc, -+ DBG_BLOCK_ID_LDS_BY16 = 0xd, -+ DBG_BLOCK_ID_LDS10_BY16 = 0xe, -+} DebugBlockId_BY16; -+typedef enum SurfaceEndian { -+ ENDIAN_NONE = 0x0, -+ ENDIAN_8IN16 = 0x1, -+ ENDIAN_8IN32 = 0x2, -+ ENDIAN_8IN64 = 0x3, -+} SurfaceEndian; -+typedef enum ArrayMode { -+ ARRAY_LINEAR_GENERAL = 0x0, -+ ARRAY_LINEAR_ALIGNED = 0x1, -+ ARRAY_1D_TILED_THIN1 = 0x2, -+ ARRAY_1D_TILED_THICK = 0x3, -+ ARRAY_2D_TILED_THIN1 = 0x4, -+ ARRAY_PRT_TILED_THIN1 = 0x5, -+ ARRAY_PRT_2D_TILED_THIN1 = 0x6, -+ ARRAY_2D_TILED_THICK = 0x7, -+ ARRAY_2D_TILED_XTHICK = 0x8, -+ ARRAY_PRT_TILED_THICK = 0x9, -+ ARRAY_PRT_2D_TILED_THICK = 0xa, -+ ARRAY_PRT_3D_TILED_THIN1 = 0xb, -+ ARRAY_3D_TILED_THIN1 = 0xc, -+ ARRAY_3D_TILED_THICK = 0xd, -+ ARRAY_3D_TILED_XTHICK = 0xe, -+ ARRAY_PRT_3D_TILED_THICK = 0xf, -+} ArrayMode; -+typedef enum PipeTiling { -+ CONFIG_1_PIPE = 0x0, -+ CONFIG_2_PIPE = 0x1, -+ CONFIG_4_PIPE = 0x2, -+ CONFIG_8_PIPE = 0x3, -+} PipeTiling; -+typedef enum BankTiling { -+ CONFIG_4_BANK = 0x0, -+ CONFIG_8_BANK = 0x1, -+} BankTiling; -+typedef enum GroupInterleave { -+ CONFIG_256B_GROUP = 0x0, -+ CONFIG_512B_GROUP = 0x1, -+} GroupInterleave; -+typedef enum RowTiling { -+ CONFIG_1KB_ROW = 0x0, -+ CONFIG_2KB_ROW = 0x1, -+ CONFIG_4KB_ROW = 0x2, -+ CONFIG_8KB_ROW = 0x3, -+ CONFIG_1KB_ROW_OPT = 0x4, -+ CONFIG_2KB_ROW_OPT = 0x5, -+ CONFIG_4KB_ROW_OPT = 0x6, -+ CONFIG_8KB_ROW_OPT = 0x7, -+} RowTiling; -+typedef enum BankSwapBytes { -+ CONFIG_128B_SWAPS = 0x0, -+ CONFIG_256B_SWAPS = 0x1, -+ CONFIG_512B_SWAPS = 0x2, -+ CONFIG_1KB_SWAPS = 0x3, -+} BankSwapBytes; -+typedef enum SampleSplitBytes { -+ CONFIG_1KB_SPLIT = 0x0, -+ CONFIG_2KB_SPLIT = 0x1, -+ CONFIG_4KB_SPLIT = 0x2, -+ CONFIG_8KB_SPLIT = 0x3, -+} SampleSplitBytes; -+typedef enum NumPipes { -+ ADDR_CONFIG_1_PIPE = 0x0, -+ ADDR_CONFIG_2_PIPE = 0x1, -+ ADDR_CONFIG_4_PIPE = 0x2, -+ ADDR_CONFIG_8_PIPE = 0x3, -+} NumPipes; -+typedef enum PipeInterleaveSize { -+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, -+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, -+} PipeInterleaveSize; -+typedef enum BankInterleaveSize { -+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, -+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, -+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, -+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, -+} BankInterleaveSize; -+typedef enum NumShaderEngines { -+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0, -+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1, -+} NumShaderEngines; -+typedef enum ShaderEngineTileSize { -+ ADDR_CONFIG_SE_TILE_16 = 0x0, -+ ADDR_CONFIG_SE_TILE_32 = 0x1, -+} ShaderEngineTileSize; -+typedef enum NumGPUs { -+ ADDR_CONFIG_1_GPU = 0x0, -+ ADDR_CONFIG_2_GPU = 0x1, -+ ADDR_CONFIG_4_GPU = 0x2, -+} NumGPUs; -+typedef enum MultiGPUTileSize { -+ ADDR_CONFIG_GPU_TILE_16 = 0x0, -+ ADDR_CONFIG_GPU_TILE_32 = 0x1, -+ ADDR_CONFIG_GPU_TILE_64 = 0x2, -+ ADDR_CONFIG_GPU_TILE_128 = 0x3, -+} MultiGPUTileSize; -+typedef enum RowSize { -+ ADDR_CONFIG_1KB_ROW = 0x0, -+ ADDR_CONFIG_2KB_ROW = 0x1, -+ ADDR_CONFIG_4KB_ROW = 0x2, -+} RowSize; -+typedef enum NumLowerPipes { -+ ADDR_CONFIG_1_LOWER_PIPES = 0x0, -+ ADDR_CONFIG_2_LOWER_PIPES = 0x1, -+} NumLowerPipes; -+typedef enum ColorTransform { -+ DCC_CT_AUTO = 0x0, -+ DCC_CT_NONE = 0x1, -+ ABGR_TO_A_BG_G_RB = 0x2, -+ BGRA_TO_BG_G_RB_A = 0x3, -+} ColorTransform; -+typedef enum CompareRef { -+ REF_NEVER = 0x0, -+ REF_LESS = 0x1, -+ REF_EQUAL = 0x2, -+ REF_LEQUAL = 0x3, -+ REF_GREATER = 0x4, -+ REF_NOTEQUAL = 0x5, -+ REF_GEQUAL = 0x6, -+ REF_ALWAYS = 0x7, -+} CompareRef; -+typedef enum ReadSize { -+ READ_256_BITS = 0x0, -+ READ_512_BITS = 0x1, -+} ReadSize; -+typedef enum DepthFormat { -+ DEPTH_INVALID = 0x0, -+ DEPTH_16 = 0x1, -+ DEPTH_X8_24 = 0x2, -+ DEPTH_8_24 = 0x3, -+ DEPTH_X8_24_FLOAT = 0x4, -+ DEPTH_8_24_FLOAT = 0x5, -+ DEPTH_32_FLOAT = 0x6, -+ DEPTH_X24_8_32_FLOAT = 0x7, -+} DepthFormat; -+typedef enum ZFormat { -+ Z_INVALID = 0x0, -+ Z_16 = 0x1, -+ Z_24 = 0x2, -+ Z_32_FLOAT = 0x3, -+} ZFormat; -+typedef enum StencilFormat { -+ STENCIL_INVALID = 0x0, -+ STENCIL_8 = 0x1, -+} StencilFormat; -+typedef enum CmaskMode { -+ CMASK_CLEAR_NONE = 0x0, -+ CMASK_CLEAR_ONE = 0x1, -+ CMASK_CLEAR_ALL = 0x2, -+ CMASK_ANY_EXPANDED = 0x3, -+ CMASK_ALPHA0_FRAG1 = 0x4, -+ CMASK_ALPHA0_FRAG2 = 0x5, -+ CMASK_ALPHA0_FRAG4 = 0x6, -+ CMASK_ALPHA0_FRAGS = 0x7, -+ CMASK_ALPHA1_FRAG1 = 0x8, -+ CMASK_ALPHA1_FRAG2 = 0x9, -+ CMASK_ALPHA1_FRAG4 = 0xa, -+ CMASK_ALPHA1_FRAGS = 0xb, -+ CMASK_ALPHAX_FRAG1 = 0xc, -+ CMASK_ALPHAX_FRAG2 = 0xd, -+ CMASK_ALPHAX_FRAG4 = 0xe, -+ CMASK_ALPHAX_FRAGS = 0xf, -+} CmaskMode; -+typedef enum QuadExportFormat { -+ EXPORT_UNUSED = 0x0, -+ EXPORT_32_R = 0x1, -+ EXPORT_32_GR = 0x2, -+ EXPORT_32_AR = 0x3, -+ EXPORT_FP16_ABGR = 0x4, -+ EXPORT_UNSIGNED16_ABGR = 0x5, -+ EXPORT_SIGNED16_ABGR = 0x6, -+ EXPORT_32_ABGR = 0x7, -+} QuadExportFormat; -+typedef enum QuadExportFormatOld { -+ EXPORT_4P_32BPC_ABGR = 0x0, -+ EXPORT_4P_16BPC_ABGR = 0x1, -+ EXPORT_4P_32BPC_GR = 0x2, -+ EXPORT_4P_32BPC_AR = 0x3, -+ EXPORT_2P_32BPC_ABGR = 0x4, -+ EXPORT_8P_32BPC_R = 0x5, -+} QuadExportFormatOld; -+typedef enum ColorFormat { -+ COLOR_INVALID = 0x0, -+ COLOR_8 = 0x1, -+ COLOR_16 = 0x2, -+ COLOR_8_8 = 0x3, -+ COLOR_32 = 0x4, -+ COLOR_16_16 = 0x5, -+ COLOR_10_11_11 = 0x6, -+ COLOR_11_11_10 = 0x7, -+ COLOR_10_10_10_2 = 0x8, -+ COLOR_2_10_10_10 = 0x9, -+ COLOR_8_8_8_8 = 0xa, -+ COLOR_32_32 = 0xb, -+ COLOR_16_16_16_16 = 0xc, -+ COLOR_RESERVED_13 = 0xd, -+ COLOR_32_32_32_32 = 0xe, -+ COLOR_RESERVED_15 = 0xf, -+ COLOR_5_6_5 = 0x10, -+ COLOR_1_5_5_5 = 0x11, -+ COLOR_5_5_5_1 = 0x12, -+ COLOR_4_4_4_4 = 0x13, -+ COLOR_8_24 = 0x14, -+ COLOR_24_8 = 0x15, -+ COLOR_X24_8_32_FLOAT = 0x16, -+ COLOR_RESERVED_23 = 0x17, -+} ColorFormat; -+typedef enum SurfaceFormat { -+ FMT_INVALID = 0x0, -+ FMT_8 = 0x1, -+ FMT_16 = 0x2, -+ FMT_8_8 = 0x3, -+ FMT_32 = 0x4, -+ FMT_16_16 = 0x5, -+ FMT_10_11_11 = 0x6, -+ FMT_11_11_10 = 0x7, -+ FMT_10_10_10_2 = 0x8, -+ FMT_2_10_10_10 = 0x9, -+ FMT_8_8_8_8 = 0xa, -+ FMT_32_32 = 0xb, -+ FMT_16_16_16_16 = 0xc, -+ FMT_32_32_32 = 0xd, -+ FMT_32_32_32_32 = 0xe, -+ FMT_RESERVED_4 = 0xf, -+ FMT_5_6_5 = 0x10, -+ FMT_1_5_5_5 = 0x11, -+ FMT_5_5_5_1 = 0x12, -+ FMT_4_4_4_4 = 0x13, -+ FMT_8_24 = 0x14, -+ FMT_24_8 = 0x15, -+ FMT_X24_8_32_FLOAT = 0x16, -+ FMT_RESERVED_33 = 0x17, -+ FMT_11_11_10_FLOAT = 0x18, -+ FMT_16_FLOAT = 0x19, -+ FMT_32_FLOAT = 0x1a, -+ FMT_16_16_FLOAT = 0x1b, -+ FMT_8_24_FLOAT = 0x1c, -+ FMT_24_8_FLOAT = 0x1d, -+ FMT_32_32_FLOAT = 0x1e, -+ FMT_10_11_11_FLOAT = 0x1f, -+ FMT_16_16_16_16_FLOAT = 0x20, -+ FMT_3_3_2 = 0x21, -+ FMT_6_5_5 = 0x22, -+ FMT_32_32_32_32_FLOAT = 0x23, -+ FMT_RESERVED_36 = 0x24, -+ FMT_1 = 0x25, -+ FMT_1_REVERSED = 0x26, -+ FMT_GB_GR = 0x27, -+ FMT_BG_RG = 0x28, -+ FMT_32_AS_8 = 0x29, -+ FMT_32_AS_8_8 = 0x2a, -+ FMT_5_9_9_9_SHAREDEXP = 0x2b, -+ FMT_8_8_8 = 0x2c, -+ FMT_16_16_16 = 0x2d, -+ FMT_16_16_16_FLOAT = 0x2e, -+ FMT_4_4 = 0x2f, -+ FMT_32_32_32_FLOAT = 0x30, -+ FMT_BC1 = 0x31, -+ FMT_BC2 = 0x32, -+ FMT_BC3 = 0x33, -+ FMT_BC4 = 0x34, -+ FMT_BC5 = 0x35, -+ FMT_BC6 = 0x36, -+ FMT_BC7 = 0x37, -+ FMT_32_AS_32_32_32_32 = 0x38, -+ FMT_APC3 = 0x39, -+ FMT_APC4 = 0x3a, -+ FMT_APC5 = 0x3b, -+ FMT_APC6 = 0x3c, -+ FMT_APC7 = 0x3d, -+ FMT_CTX1 = 0x3e, -+ FMT_RESERVED_63 = 0x3f, -+} SurfaceFormat; -+typedef enum BUF_DATA_FORMAT { -+ BUF_DATA_FORMAT_INVALID = 0x0, -+ BUF_DATA_FORMAT_8 = 0x1, -+ BUF_DATA_FORMAT_16 = 0x2, -+ BUF_DATA_FORMAT_8_8 = 0x3, -+ BUF_DATA_FORMAT_32 = 0x4, -+ BUF_DATA_FORMAT_16_16 = 0x5, -+ BUF_DATA_FORMAT_10_11_11 = 0x6, -+ BUF_DATA_FORMAT_11_11_10 = 0x7, -+ BUF_DATA_FORMAT_10_10_10_2 = 0x8, -+ BUF_DATA_FORMAT_2_10_10_10 = 0x9, -+ BUF_DATA_FORMAT_8_8_8_8 = 0xa, -+ BUF_DATA_FORMAT_32_32 = 0xb, -+ BUF_DATA_FORMAT_16_16_16_16 = 0xc, -+ BUF_DATA_FORMAT_32_32_32 = 0xd, -+ BUF_DATA_FORMAT_32_32_32_32 = 0xe, -+ BUF_DATA_FORMAT_RESERVED_15 = 0xf, -+} BUF_DATA_FORMAT; -+typedef enum IMG_DATA_FORMAT { -+ IMG_DATA_FORMAT_INVALID = 0x0, -+ IMG_DATA_FORMAT_8 = 0x1, -+ IMG_DATA_FORMAT_16 = 0x2, -+ IMG_DATA_FORMAT_8_8 = 0x3, -+ IMG_DATA_FORMAT_32 = 0x4, -+ IMG_DATA_FORMAT_16_16 = 0x5, -+ IMG_DATA_FORMAT_10_11_11 = 0x6, -+ IMG_DATA_FORMAT_11_11_10 = 0x7, -+ IMG_DATA_FORMAT_10_10_10_2 = 0x8, -+ IMG_DATA_FORMAT_2_10_10_10 = 0x9, -+ IMG_DATA_FORMAT_8_8_8_8 = 0xa, -+ IMG_DATA_FORMAT_32_32 = 0xb, -+ IMG_DATA_FORMAT_16_16_16_16 = 0xc, -+ IMG_DATA_FORMAT_32_32_32 = 0xd, -+ IMG_DATA_FORMAT_32_32_32_32 = 0xe, -+ IMG_DATA_FORMAT_RESERVED_15 = 0xf, -+ IMG_DATA_FORMAT_5_6_5 = 0x10, -+ IMG_DATA_FORMAT_1_5_5_5 = 0x11, -+ IMG_DATA_FORMAT_5_5_5_1 = 0x12, -+ IMG_DATA_FORMAT_4_4_4_4 = 0x13, -+ IMG_DATA_FORMAT_8_24 = 0x14, -+ IMG_DATA_FORMAT_24_8 = 0x15, -+ IMG_DATA_FORMAT_X24_8_32 = 0x16, -+ IMG_DATA_FORMAT_RESERVED_23 = 0x17, -+ IMG_DATA_FORMAT_RESERVED_24 = 0x18, -+ IMG_DATA_FORMAT_RESERVED_25 = 0x19, -+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a, -+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b, -+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c, -+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d, -+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e, -+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f, -+ IMG_DATA_FORMAT_GB_GR = 0x20, -+ IMG_DATA_FORMAT_BG_RG = 0x21, -+ IMG_DATA_FORMAT_5_9_9_9 = 0x22, -+ IMG_DATA_FORMAT_BC1 = 0x23, -+ IMG_DATA_FORMAT_BC2 = 0x24, -+ IMG_DATA_FORMAT_BC3 = 0x25, -+ IMG_DATA_FORMAT_BC4 = 0x26, -+ IMG_DATA_FORMAT_BC5 = 0x27, -+ IMG_DATA_FORMAT_BC6 = 0x28, -+ IMG_DATA_FORMAT_BC7 = 0x29, -+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a, -+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b, -+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, -+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, -+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, -+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, -+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, -+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, -+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, -+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, -+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, -+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, -+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, -+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, -+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, -+ IMG_DATA_FORMAT_4_4 = 0x39, -+ IMG_DATA_FORMAT_6_5_5 = 0x3a, -+ IMG_DATA_FORMAT_1 = 0x3b, -+ IMG_DATA_FORMAT_1_REVERSED = 0x3c, -+ IMG_DATA_FORMAT_32_AS_8 = 0x3d, -+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, -+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, -+} IMG_DATA_FORMAT; -+typedef enum BUF_NUM_FORMAT { -+ BUF_NUM_FORMAT_UNORM = 0x0, -+ BUF_NUM_FORMAT_SNORM = 0x1, -+ BUF_NUM_FORMAT_USCALED = 0x2, -+ BUF_NUM_FORMAT_SSCALED = 0x3, -+ BUF_NUM_FORMAT_UINT = 0x4, -+ BUF_NUM_FORMAT_SINT = 0x5, -+ BUF_NUM_FORMAT_RESERVED_6 = 0x6, -+ BUF_NUM_FORMAT_FLOAT = 0x7, -+} BUF_NUM_FORMAT; -+typedef enum IMG_NUM_FORMAT { -+ IMG_NUM_FORMAT_UNORM = 0x0, -+ IMG_NUM_FORMAT_SNORM = 0x1, -+ IMG_NUM_FORMAT_USCALED = 0x2, -+ IMG_NUM_FORMAT_SSCALED = 0x3, -+ IMG_NUM_FORMAT_UINT = 0x4, -+ IMG_NUM_FORMAT_SINT = 0x5, -+ IMG_NUM_FORMAT_RESERVED_6 = 0x6, -+ IMG_NUM_FORMAT_FLOAT = 0x7, -+ IMG_NUM_FORMAT_RESERVED_8 = 0x8, -+ IMG_NUM_FORMAT_SRGB = 0x9, -+ IMG_NUM_FORMAT_RESERVED_10 = 0xa, -+ IMG_NUM_FORMAT_RESERVED_11 = 0xb, -+ IMG_NUM_FORMAT_RESERVED_12 = 0xc, -+ IMG_NUM_FORMAT_RESERVED_13 = 0xd, -+ IMG_NUM_FORMAT_RESERVED_14 = 0xe, -+ IMG_NUM_FORMAT_RESERVED_15 = 0xf, -+} IMG_NUM_FORMAT; -+typedef enum TileType { -+ ARRAY_COLOR_TILE = 0x0, -+ ARRAY_DEPTH_TILE = 0x1, -+} TileType; -+typedef enum NonDispTilingOrder { -+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, -+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, -+} NonDispTilingOrder; -+typedef enum MicroTileMode { -+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, -+ ADDR_SURF_THIN_MICRO_TILING = 0x1, -+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2, -+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3, -+ ADDR_SURF_THICK_MICRO_TILING = 0x4, -+} MicroTileMode; -+typedef enum TileSplit { -+ ADDR_SURF_TILE_SPLIT_64B = 0x0, -+ ADDR_SURF_TILE_SPLIT_128B = 0x1, -+ ADDR_SURF_TILE_SPLIT_256B = 0x2, -+ ADDR_SURF_TILE_SPLIT_512B = 0x3, -+ ADDR_SURF_TILE_SPLIT_1KB = 0x4, -+ ADDR_SURF_TILE_SPLIT_2KB = 0x5, -+ ADDR_SURF_TILE_SPLIT_4KB = 0x6, -+} TileSplit; -+typedef enum SampleSplit { -+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, -+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, -+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, -+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, -+} SampleSplit; -+typedef enum PipeConfig { -+ ADDR_SURF_P2 = 0x0, -+ ADDR_SURF_P2_RESERVED0 = 0x1, -+ ADDR_SURF_P2_RESERVED1 = 0x2, -+ ADDR_SURF_P2_RESERVED2 = 0x3, -+ ADDR_SURF_P4_8x16 = 0x4, -+ ADDR_SURF_P4_16x16 = 0x5, -+ ADDR_SURF_P4_16x32 = 0x6, -+ ADDR_SURF_P4_32x32 = 0x7, -+ ADDR_SURF_P8_16x16_8x16 = 0x8, -+ ADDR_SURF_P8_16x32_8x16 = 0x9, -+ ADDR_SURF_P8_32x32_8x16 = 0xa, -+ ADDR_SURF_P8_16x32_16x16 = 0xb, -+ ADDR_SURF_P8_32x32_16x16 = 0xc, -+ ADDR_SURF_P8_32x32_16x32 = 0xd, -+ ADDR_SURF_P8_32x64_32x32 = 0xe, -+ ADDR_SURF_P8_RESERVED0 = 0xf, -+ ADDR_SURF_P16_32x32_8x16 = 0x10, -+ ADDR_SURF_P16_32x32_16x16 = 0x11, -+} PipeConfig; -+typedef enum NumBanks { -+ ADDR_SURF_2_BANK = 0x0, -+ ADDR_SURF_4_BANK = 0x1, -+ ADDR_SURF_8_BANK = 0x2, -+ ADDR_SURF_16_BANK = 0x3, -+} NumBanks; -+typedef enum BankWidth { -+ ADDR_SURF_BANK_WIDTH_1 = 0x0, -+ ADDR_SURF_BANK_WIDTH_2 = 0x1, -+ ADDR_SURF_BANK_WIDTH_4 = 0x2, -+ ADDR_SURF_BANK_WIDTH_8 = 0x3, -+} BankWidth; -+typedef enum BankHeight { -+ ADDR_SURF_BANK_HEIGHT_1 = 0x0, -+ ADDR_SURF_BANK_HEIGHT_2 = 0x1, -+ ADDR_SURF_BANK_HEIGHT_4 = 0x2, -+ ADDR_SURF_BANK_HEIGHT_8 = 0x3, -+} BankHeight; -+typedef enum BankWidthHeight { -+ ADDR_SURF_BANK_WH_1 = 0x0, -+ ADDR_SURF_BANK_WH_2 = 0x1, -+ ADDR_SURF_BANK_WH_4 = 0x2, -+ ADDR_SURF_BANK_WH_8 = 0x3, -+} BankWidthHeight; -+typedef enum MacroTileAspect { -+ ADDR_SURF_MACRO_ASPECT_1 = 0x0, -+ ADDR_SURF_MACRO_ASPECT_2 = 0x1, -+ ADDR_SURF_MACRO_ASPECT_4 = 0x2, -+ ADDR_SURF_MACRO_ASPECT_8 = 0x3, -+} MacroTileAspect; -+typedef enum GATCL1RequestType { -+ GATCL1_TYPE_NORMAL = 0x0, -+ GATCL1_TYPE_SHOOTDOWN = 0x1, -+ GATCL1_TYPE_BYPASS = 0x2, -+} GATCL1RequestType; -+typedef enum TCC_CACHE_POLICIES { -+ TCC_CACHE_POLICY_LRU = 0x0, -+ TCC_CACHE_POLICY_STREAM = 0x1, -+} TCC_CACHE_POLICIES; -+typedef enum MTYPE { -+ MTYPE_NC_NV = 0x0, -+ MTYPE_NC = 0x1, -+ MTYPE_CC = 0x2, -+ MTYPE_UC = 0x3, -+} MTYPE; -+typedef enum PERFMON_COUNTER_MODE { -+ PERFMON_COUNTER_MODE_ACCUM = 0x0, -+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, -+ PERFMON_COUNTER_MODE_MAX = 0x2, -+ PERFMON_COUNTER_MODE_DIRTY = 0x3, -+ PERFMON_COUNTER_MODE_SAMPLE = 0x4, -+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, -+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, -+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, -+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, -+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, -+ PERFMON_COUNTER_MODE_RESERVED = 0xf, -+} PERFMON_COUNTER_MODE; -+typedef enum PERFMON_SPM_MODE { -+ PERFMON_SPM_MODE_OFF = 0x0, -+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, -+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, -+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, -+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, -+ PERFMON_SPM_MODE_RESERVED_5 = 0x5, -+ PERFMON_SPM_MODE_RESERVED_6 = 0x6, -+ PERFMON_SPM_MODE_RESERVED_7 = 0x7, -+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, -+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, -+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, -+} PERFMON_SPM_MODE; -+typedef enum SurfaceTiling { -+ ARRAY_LINEAR = 0x0, -+ ARRAY_TILED = 0x1, -+} SurfaceTiling; -+typedef enum SurfaceArray { -+ ARRAY_1D = 0x0, -+ ARRAY_2D = 0x1, -+ ARRAY_3D = 0x2, -+ ARRAY_3D_SLICE = 0x3, -+} SurfaceArray; -+typedef enum ColorArray { -+ ARRAY_2D_ALT_COLOR = 0x0, -+ ARRAY_2D_COLOR = 0x1, -+ ARRAY_3D_SLICE_COLOR = 0x3, -+} ColorArray; -+typedef enum DepthArray { -+ ARRAY_2D_ALT_DEPTH = 0x0, -+ ARRAY_2D_DEPTH = 0x1, -+} DepthArray; -+typedef enum ENUM_NUM_SIMD_PER_CU { -+ NUM_SIMD_PER_CU = 0x4, -+} ENUM_NUM_SIMD_PER_CU; -+typedef enum MEM_PWR_FORCE_CTRL { -+ NO_FORCE_REQUEST = 0x0, -+ FORCE_LIGHT_SLEEP_REQUEST = 0x1, -+ FORCE_DEEP_SLEEP_REQUEST = 0x2, -+ FORCE_SHUT_DOWN_REQUEST = 0x3, -+} MEM_PWR_FORCE_CTRL; -+typedef enum MEM_PWR_FORCE_CTRL2 { -+ NO_FORCE_REQ = 0x0, -+ FORCE_LIGHT_SLEEP_REQ = 0x1, -+} MEM_PWR_FORCE_CTRL2; -+typedef enum MEM_PWR_DIS_CTRL { -+ ENABLE_MEM_PWR_CTRL = 0x0, -+ DISABLE_MEM_PWR_CTRL = 0x1, -+} MEM_PWR_DIS_CTRL; -+typedef enum MEM_PWR_SEL_CTRL { -+ DYNAMIC_SHUT_DOWN_ENABLE = 0x0, -+ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, -+ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, -+} MEM_PWR_SEL_CTRL; -+typedef enum MEM_PWR_SEL_CTRL2 { -+ DYNAMIC_DEEP_SLEEP_EN = 0x0, -+ DYNAMIC_LIGHT_SLEEP_EN = 0x1, -+} MEM_PWR_SEL_CTRL2; -+ -+#endif /* ACP_2_2_ENUM_H */ -diff --git a/sound/soc/amd/include/acp_2_2_sh_mask.h b/sound/soc/amd/include/acp_2_2_sh_mask.h -new file mode 100644 -index 0000000..32d2d41 ---- /dev/null -+++ b/sound/soc/amd/include/acp_2_2_sh_mask.h -@@ -0,0 +1,2292 @@ -+/* -+ * ACP_2_2 Register documentation -+ * -+ * Copyright (C) 2014 Advanced Micro Devices, Inc. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included -+ * in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN -+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#ifndef ACP_2_2_SH_MASK_H -+#define ACP_2_2_SH_MASK_H -+ -+#define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_1__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_1__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_1__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_1__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_1__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_1__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_1__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_1__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_1__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_1__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_2__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_2__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_2__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_2__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_2__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_2__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_2__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_2__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_2__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_2__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_3__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_3__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_3__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_3__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_3__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_3__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_3__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_3__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_3__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_3__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_4__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_4__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_4__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_4__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_4__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_4__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_4__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_4__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_4__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_4__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_5__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_5__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_5__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_5__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_5__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_5__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_5__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_5__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_5__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_5__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_6__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_6__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_6__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_6__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_6__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_6__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_6__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_6__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_6__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_6__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_7__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_7__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_7__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_7__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_7__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_7__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_7__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_7__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_7__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_7__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_8__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_8__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_8__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_8__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_8__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_8__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_8__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_8__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_8__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_8__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_9__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_9__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_9__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_9__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_9__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_9__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_9__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_9__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_9__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_9__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_10__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_10__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_10__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_10__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_10__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_10__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_10__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_10__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_10__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_10__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_11__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_11__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_11__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_11__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_11__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_11__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_11__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_11__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_11__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_11__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_12__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_12__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_12__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_12__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_12__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_12__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_12__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_12__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_12__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_12__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_13__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_13__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_13__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_13__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_13__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_13__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_13__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_13__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_13__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_13__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_14__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_14__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_14__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_14__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_14__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_14__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_14__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_14__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_14__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_14__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_CNTL_15__DMAChRst_MASK 0x1 -+#define ACP_DMA_CNTL_15__DMAChRst__SHIFT 0x0 -+#define ACP_DMA_CNTL_15__DMAChRun_MASK 0x2 -+#define ACP_DMA_CNTL_15__DMAChRun__SHIFT 0x1 -+#define ACP_DMA_CNTL_15__DMAChIOCEn_MASK 0x4 -+#define ACP_DMA_CNTL_15__DMAChIOCEn__SHIFT 0x2 -+#define ACP_DMA_CNTL_15__Circular_DMA_En_MASK 0x8 -+#define ACP_DMA_CNTL_15__Circular_DMA_En__SHIFT 0x3 -+#define ACP_DMA_CNTL_15__DMAChGracefulRstEn_MASK 0x10 -+#define ACP_DMA_CNTL_15__DMAChGracefulRstEn__SHIFT 0x4 -+#define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx_MASK 0x3ff -+#define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt_MASK 0x3ff -+#define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt__SHIFT 0x0 -+#define ACP_DMA_PRIO_0__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_0__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_1__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_1__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_2__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_2__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_3__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_3__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_4__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_4__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_5__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_5__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_6__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_6__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_7__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_7__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_8__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_8__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_9__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_9__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_10__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_10__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_11__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_11__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_12__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_12__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_13__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_13__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_14__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_14__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_PRIO_15__DMAChPrioLvl_MASK 0x1 -+#define ACP_DMA_PRIO_15__DMAChPrioLvl__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx_MASK 0x3ff -+#define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt_MASK 0x1ffff -+#define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_0__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_0__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_0__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_0__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_1__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_1__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_1__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_1__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_2__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_2__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_2__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_2__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_3__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_3__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_3__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_3__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_4__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_4__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_4__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_4__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_5__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_5__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_5__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_5__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_6__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_6__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_6__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_6__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_7__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_7__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_7__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_7__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_8__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_8__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_8__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_8__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_9__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_9__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_9__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_9__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_10__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_10__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_10__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_10__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_11__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_11__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_11__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_11__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_12__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_12__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_12__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_12__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_13__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_13__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_13__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_13__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_14__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_14__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_14__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_14__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_ERR_STS_15__DMAChTermErr_MASK 0x1 -+#define ACP_DMA_ERR_STS_15__DMAChTermErr__SHIFT 0x0 -+#define ACP_DMA_ERR_STS_15__DMAChErrCode_MASK 0x1e -+#define ACP_DMA_ERR_STS_15__DMAChErrCode__SHIFT 0x1 -+#define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr_MASK 0xffffffff -+#define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr__SHIFT 0x0 -+#define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr_MASK 0xf -+#define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr__SHIFT 0x0 -+#define ACP_DMA_CH_STS__DMAChSts_MASK 0xffff -+#define ACP_DMA_CH_STS__DMAChSts__SHIFT 0x0 -+#define ACP_DMA_CH_GROUP__DMAChanelGrouping_MASK 0x1 -+#define ACP_DMA_CH_GROUP__DMAChanelGrouping__SHIFT 0x0 -+#define ACP_DSP0_CACHE_OFFSET0__Offset_MASK 0xfffffff -+#define ACP_DSP0_CACHE_OFFSET0__Offset__SHIFT 0x0 -+#define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP0_CACHE_SIZE0__Size_MASK 0xffffff -+#define ACP_DSP0_CACHE_SIZE0__Size__SHIFT 0x0 -+#define ACP_DSP0_CACHE_SIZE0__PageEnable_MASK 0x80000000 -+#define ACP_DSP0_CACHE_SIZE0__PageEnable__SHIFT 0x1f -+#define ACP_DSP0_CACHE_OFFSET1__Offset_MASK 0xfffffff -+#define ACP_DSP0_CACHE_OFFSET1__Offset__SHIFT 0x0 -+#define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP0_CACHE_SIZE1__Size_MASK 0xffffff -+#define ACP_DSP0_CACHE_SIZE1__Size__SHIFT 0x0 -+#define ACP_DSP0_CACHE_SIZE1__PageEnable_MASK 0x80000000 -+#define ACP_DSP0_CACHE_SIZE1__PageEnable__SHIFT 0x1f -+#define ACP_DSP0_CACHE_OFFSET2__Offset_MASK 0xfffffff -+#define ACP_DSP0_CACHE_OFFSET2__Offset__SHIFT 0x0 -+#define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP0_CACHE_SIZE2__Size_MASK 0xffffff -+#define ACP_DSP0_CACHE_SIZE2__Size__SHIFT 0x0 -+#define ACP_DSP0_CACHE_SIZE2__PageEnable_MASK 0x80000000 -+#define ACP_DSP0_CACHE_SIZE2__PageEnable__SHIFT 0x1f -+#define ACP_DSP0_CACHE_OFFSET3__Offset_MASK 0xfffffff -+#define ACP_DSP0_CACHE_OFFSET3__Offset__SHIFT 0x0 -+#define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP0_CACHE_SIZE3__Size_MASK 0xffffff -+#define ACP_DSP0_CACHE_SIZE3__Size__SHIFT 0x0 -+#define ACP_DSP0_CACHE_SIZE3__PageEnable_MASK 0x80000000 -+#define ACP_DSP0_CACHE_SIZE3__PageEnable__SHIFT 0x1f -+#define ACP_DSP0_CACHE_OFFSET4__Offset_MASK 0xfffffff -+#define ACP_DSP0_CACHE_OFFSET4__Offset__SHIFT 0x0 -+#define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP0_CACHE_SIZE4__Size_MASK 0xffffff -+#define ACP_DSP0_CACHE_SIZE4__Size__SHIFT 0x0 -+#define ACP_DSP0_CACHE_SIZE4__PageEnable_MASK 0x80000000 -+#define ACP_DSP0_CACHE_SIZE4__PageEnable__SHIFT 0x1f -+#define ACP_DSP0_CACHE_OFFSET5__Offset_MASK 0xfffffff -+#define ACP_DSP0_CACHE_OFFSET5__Offset__SHIFT 0x0 -+#define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP0_CACHE_SIZE5__Size_MASK 0xffffff -+#define ACP_DSP0_CACHE_SIZE5__Size__SHIFT 0x0 -+#define ACP_DSP0_CACHE_SIZE5__PageEnable_MASK 0x80000000 -+#define ACP_DSP0_CACHE_SIZE5__PageEnable__SHIFT 0x1f -+#define ACP_DSP0_CACHE_OFFSET6__Offset_MASK 0xfffffff -+#define ACP_DSP0_CACHE_OFFSET6__Offset__SHIFT 0x0 -+#define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP0_CACHE_SIZE6__Size_MASK 0xffffff -+#define ACP_DSP0_CACHE_SIZE6__Size__SHIFT 0x0 -+#define ACP_DSP0_CACHE_SIZE6__PageEnable_MASK 0x80000000 -+#define ACP_DSP0_CACHE_SIZE6__PageEnable__SHIFT 0x1f -+#define ACP_DSP0_CACHE_OFFSET7__Offset_MASK 0xfffffff -+#define ACP_DSP0_CACHE_OFFSET7__Offset__SHIFT 0x0 -+#define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP0_CACHE_SIZE7__Size_MASK 0xffffff -+#define ACP_DSP0_CACHE_SIZE7__Size__SHIFT 0x0 -+#define ACP_DSP0_CACHE_SIZE7__PageEnable_MASK 0x80000000 -+#define ACP_DSP0_CACHE_SIZE7__PageEnable__SHIFT 0x1f -+#define ACP_DSP0_CACHE_OFFSET8__Offset_MASK 0xfffffff -+#define ACP_DSP0_CACHE_OFFSET8__Offset__SHIFT 0x0 -+#define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP0_CACHE_SIZE8__Size_MASK 0xffffff -+#define ACP_DSP0_CACHE_SIZE8__Size__SHIFT 0x0 -+#define ACP_DSP0_CACHE_SIZE8__PageEnable_MASK 0x80000000 -+#define ACP_DSP0_CACHE_SIZE8__PageEnable__SHIFT 0x1f -+#define ACP_DSP0_NONCACHE_OFFSET0__Offset_MASK 0xfffffff -+#define ACP_DSP0_NONCACHE_OFFSET0__Offset__SHIFT 0x0 -+#define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP0_NONCACHE_SIZE0__Size_MASK 0xffffff -+#define ACP_DSP0_NONCACHE_SIZE0__Size__SHIFT 0x0 -+#define ACP_DSP0_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 -+#define ACP_DSP0_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f -+#define ACP_DSP0_NONCACHE_OFFSET1__Offset_MASK 0xfffffff -+#define ACP_DSP0_NONCACHE_OFFSET1__Offset__SHIFT 0x0 -+#define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP0_NONCACHE_SIZE1__Size_MASK 0xffffff -+#define ACP_DSP0_NONCACHE_SIZE1__Size__SHIFT 0x0 -+#define ACP_DSP0_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 -+#define ACP_DSP0_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f -+#define ACP_DSP0_DEBUG_PC__DebugPC_MASK 0xffffffff -+#define ACP_DSP0_DEBUG_PC__DebugPC__SHIFT 0x0 -+#define ACP_DSP0_NMI_SEL__NMISel_MASK 0x1 -+#define ACP_DSP0_NMI_SEL__NMISel__SHIFT 0x0 -+#define ACP_DSP0_CLKRST_CNTL__ClkEn_MASK 0x1 -+#define ACP_DSP0_CLKRST_CNTL__ClkEn__SHIFT 0x0 -+#define ACP_DSP0_CLKRST_CNTL__SoftResetDSP_MASK 0x2 -+#define ACP_DSP0_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 -+#define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 -+#define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 -+#define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 -+#define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 -+#define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 -+#define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 -+#define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 -+#define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 -+#define ACP_DSP0_RUNSTALL__RunStallCntl_MASK 0x1 -+#define ACP_DSP0_RUNSTALL__RunStallCntl__SHIFT 0x0 -+#define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 -+#define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 -+#define ACP_DSP0_WAIT_MODE__WaitMode_MASK 0x1 -+#define ACP_DSP0_WAIT_MODE__WaitMode__SHIFT 0x0 -+#define ACP_DSP0_VECT_SEL__StaticVectorSel_MASK 0x1 -+#define ACP_DSP0_VECT_SEL__StaticVectorSel__SHIFT 0x0 -+#define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff -+#define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 -+#define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff -+#define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 -+#define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff -+#define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 -+#define ACP_DSP1_CACHE_OFFSET0__Offset_MASK 0xfffffff -+#define ACP_DSP1_CACHE_OFFSET0__Offset__SHIFT 0x0 -+#define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP1_CACHE_SIZE0__Size_MASK 0xffffff -+#define ACP_DSP1_CACHE_SIZE0__Size__SHIFT 0x0 -+#define ACP_DSP1_CACHE_SIZE0__PageEnable_MASK 0x80000000 -+#define ACP_DSP1_CACHE_SIZE0__PageEnable__SHIFT 0x1f -+#define ACP_DSP1_CACHE_OFFSET1__Offset_MASK 0xfffffff -+#define ACP_DSP1_CACHE_OFFSET1__Offset__SHIFT 0x0 -+#define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP1_CACHE_SIZE1__Size_MASK 0xffffff -+#define ACP_DSP1_CACHE_SIZE1__Size__SHIFT 0x0 -+#define ACP_DSP1_CACHE_SIZE1__PageEnable_MASK 0x80000000 -+#define ACP_DSP1_CACHE_SIZE1__PageEnable__SHIFT 0x1f -+#define ACP_DSP1_CACHE_OFFSET2__Offset_MASK 0xfffffff -+#define ACP_DSP1_CACHE_OFFSET2__Offset__SHIFT 0x0 -+#define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP1_CACHE_SIZE2__Size_MASK 0xffffff -+#define ACP_DSP1_CACHE_SIZE2__Size__SHIFT 0x0 -+#define ACP_DSP1_CACHE_SIZE2__PageEnable_MASK 0x80000000 -+#define ACP_DSP1_CACHE_SIZE2__PageEnable__SHIFT 0x1f -+#define ACP_DSP1_CACHE_OFFSET3__Offset_MASK 0xfffffff -+#define ACP_DSP1_CACHE_OFFSET3__Offset__SHIFT 0x0 -+#define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP1_CACHE_SIZE3__Size_MASK 0xffffff -+#define ACP_DSP1_CACHE_SIZE3__Size__SHIFT 0x0 -+#define ACP_DSP1_CACHE_SIZE3__PageEnable_MASK 0x80000000 -+#define ACP_DSP1_CACHE_SIZE3__PageEnable__SHIFT 0x1f -+#define ACP_DSP1_CACHE_OFFSET4__Offset_MASK 0xfffffff -+#define ACP_DSP1_CACHE_OFFSET4__Offset__SHIFT 0x0 -+#define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP1_CACHE_SIZE4__Size_MASK 0xffffff -+#define ACP_DSP1_CACHE_SIZE4__Size__SHIFT 0x0 -+#define ACP_DSP1_CACHE_SIZE4__PageEnable_MASK 0x80000000 -+#define ACP_DSP1_CACHE_SIZE4__PageEnable__SHIFT 0x1f -+#define ACP_DSP1_CACHE_OFFSET5__Offset_MASK 0xfffffff -+#define ACP_DSP1_CACHE_OFFSET5__Offset__SHIFT 0x0 -+#define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP1_CACHE_SIZE5__Size_MASK 0xffffff -+#define ACP_DSP1_CACHE_SIZE5__Size__SHIFT 0x0 -+#define ACP_DSP1_CACHE_SIZE5__PageEnable_MASK 0x80000000 -+#define ACP_DSP1_CACHE_SIZE5__PageEnable__SHIFT 0x1f -+#define ACP_DSP1_CACHE_OFFSET6__Offset_MASK 0xfffffff -+#define ACP_DSP1_CACHE_OFFSET6__Offset__SHIFT 0x0 -+#define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP1_CACHE_SIZE6__Size_MASK 0xffffff -+#define ACP_DSP1_CACHE_SIZE6__Size__SHIFT 0x0 -+#define ACP_DSP1_CACHE_SIZE6__PageEnable_MASK 0x80000000 -+#define ACP_DSP1_CACHE_SIZE6__PageEnable__SHIFT 0x1f -+#define ACP_DSP1_CACHE_OFFSET7__Offset_MASK 0xfffffff -+#define ACP_DSP1_CACHE_OFFSET7__Offset__SHIFT 0x0 -+#define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP1_CACHE_SIZE7__Size_MASK 0xffffff -+#define ACP_DSP1_CACHE_SIZE7__Size__SHIFT 0x0 -+#define ACP_DSP1_CACHE_SIZE7__PageEnable_MASK 0x80000000 -+#define ACP_DSP1_CACHE_SIZE7__PageEnable__SHIFT 0x1f -+#define ACP_DSP1_CACHE_OFFSET8__Offset_MASK 0xfffffff -+#define ACP_DSP1_CACHE_OFFSET8__Offset__SHIFT 0x0 -+#define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP1_CACHE_SIZE8__Size_MASK 0xffffff -+#define ACP_DSP1_CACHE_SIZE8__Size__SHIFT 0x0 -+#define ACP_DSP1_CACHE_SIZE8__PageEnable_MASK 0x80000000 -+#define ACP_DSP1_CACHE_SIZE8__PageEnable__SHIFT 0x1f -+#define ACP_DSP1_NONCACHE_OFFSET0__Offset_MASK 0xfffffff -+#define ACP_DSP1_NONCACHE_OFFSET0__Offset__SHIFT 0x0 -+#define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP1_NONCACHE_SIZE0__Size_MASK 0xffffff -+#define ACP_DSP1_NONCACHE_SIZE0__Size__SHIFT 0x0 -+#define ACP_DSP1_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 -+#define ACP_DSP1_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f -+#define ACP_DSP1_NONCACHE_OFFSET1__Offset_MASK 0xfffffff -+#define ACP_DSP1_NONCACHE_OFFSET1__Offset__SHIFT 0x0 -+#define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP1_NONCACHE_SIZE1__Size_MASK 0xffffff -+#define ACP_DSP1_NONCACHE_SIZE1__Size__SHIFT 0x0 -+#define ACP_DSP1_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 -+#define ACP_DSP1_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f -+#define ACP_DSP1_DEBUG_PC__DebugPC_MASK 0xffffffff -+#define ACP_DSP1_DEBUG_PC__DebugPC__SHIFT 0x0 -+#define ACP_DSP1_NMI_SEL__NMISel_MASK 0x1 -+#define ACP_DSP1_NMI_SEL__NMISel__SHIFT 0x0 -+#define ACP_DSP1_CLKRST_CNTL__ClkEn_MASK 0x1 -+#define ACP_DSP1_CLKRST_CNTL__ClkEn__SHIFT 0x0 -+#define ACP_DSP1_CLKRST_CNTL__SoftResetDSP_MASK 0x2 -+#define ACP_DSP1_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 -+#define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 -+#define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 -+#define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 -+#define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 -+#define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 -+#define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 -+#define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 -+#define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 -+#define ACP_DSP1_RUNSTALL__RunStallCntl_MASK 0x1 -+#define ACP_DSP1_RUNSTALL__RunStallCntl__SHIFT 0x0 -+#define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 -+#define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 -+#define ACP_DSP1_WAIT_MODE__WaitMode_MASK 0x1 -+#define ACP_DSP1_WAIT_MODE__WaitMode__SHIFT 0x0 -+#define ACP_DSP1_VECT_SEL__StaticVectorSel_MASK 0x1 -+#define ACP_DSP1_VECT_SEL__StaticVectorSel__SHIFT 0x0 -+#define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff -+#define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 -+#define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff -+#define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 -+#define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff -+#define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 -+#define ACP_DSP2_CACHE_OFFSET0__Offset_MASK 0xfffffff -+#define ACP_DSP2_CACHE_OFFSET0__Offset__SHIFT 0x0 -+#define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP2_CACHE_SIZE0__Size_MASK 0xffffff -+#define ACP_DSP2_CACHE_SIZE0__Size__SHIFT 0x0 -+#define ACP_DSP2_CACHE_SIZE0__PageEnable_MASK 0x80000000 -+#define ACP_DSP2_CACHE_SIZE0__PageEnable__SHIFT 0x1f -+#define ACP_DSP2_CACHE_OFFSET1__Offset_MASK 0xfffffff -+#define ACP_DSP2_CACHE_OFFSET1__Offset__SHIFT 0x0 -+#define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP2_CACHE_SIZE1__Size_MASK 0xffffff -+#define ACP_DSP2_CACHE_SIZE1__Size__SHIFT 0x0 -+#define ACP_DSP2_CACHE_SIZE1__PageEnable_MASK 0x80000000 -+#define ACP_DSP2_CACHE_SIZE1__PageEnable__SHIFT 0x1f -+#define ACP_DSP2_CACHE_OFFSET2__Offset_MASK 0xfffffff -+#define ACP_DSP2_CACHE_OFFSET2__Offset__SHIFT 0x0 -+#define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP2_CACHE_SIZE2__Size_MASK 0xffffff -+#define ACP_DSP2_CACHE_SIZE2__Size__SHIFT 0x0 -+#define ACP_DSP2_CACHE_SIZE2__PageEnable_MASK 0x80000000 -+#define ACP_DSP2_CACHE_SIZE2__PageEnable__SHIFT 0x1f -+#define ACP_DSP2_CACHE_OFFSET3__Offset_MASK 0xfffffff -+#define ACP_DSP2_CACHE_OFFSET3__Offset__SHIFT 0x0 -+#define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP2_CACHE_SIZE3__Size_MASK 0xffffff -+#define ACP_DSP2_CACHE_SIZE3__Size__SHIFT 0x0 -+#define ACP_DSP2_CACHE_SIZE3__PageEnable_MASK 0x80000000 -+#define ACP_DSP2_CACHE_SIZE3__PageEnable__SHIFT 0x1f -+#define ACP_DSP2_CACHE_OFFSET4__Offset_MASK 0xfffffff -+#define ACP_DSP2_CACHE_OFFSET4__Offset__SHIFT 0x0 -+#define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP2_CACHE_SIZE4__Size_MASK 0xffffff -+#define ACP_DSP2_CACHE_SIZE4__Size__SHIFT 0x0 -+#define ACP_DSP2_CACHE_SIZE4__PageEnable_MASK 0x80000000 -+#define ACP_DSP2_CACHE_SIZE4__PageEnable__SHIFT 0x1f -+#define ACP_DSP2_CACHE_OFFSET5__Offset_MASK 0xfffffff -+#define ACP_DSP2_CACHE_OFFSET5__Offset__SHIFT 0x0 -+#define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP2_CACHE_SIZE5__Size_MASK 0xffffff -+#define ACP_DSP2_CACHE_SIZE5__Size__SHIFT 0x0 -+#define ACP_DSP2_CACHE_SIZE5__PageEnable_MASK 0x80000000 -+#define ACP_DSP2_CACHE_SIZE5__PageEnable__SHIFT 0x1f -+#define ACP_DSP2_CACHE_OFFSET6__Offset_MASK 0xfffffff -+#define ACP_DSP2_CACHE_OFFSET6__Offset__SHIFT 0x0 -+#define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP2_CACHE_SIZE6__Size_MASK 0xffffff -+#define ACP_DSP2_CACHE_SIZE6__Size__SHIFT 0x0 -+#define ACP_DSP2_CACHE_SIZE6__PageEnable_MASK 0x80000000 -+#define ACP_DSP2_CACHE_SIZE6__PageEnable__SHIFT 0x1f -+#define ACP_DSP2_CACHE_OFFSET7__Offset_MASK 0xfffffff -+#define ACP_DSP2_CACHE_OFFSET7__Offset__SHIFT 0x0 -+#define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP2_CACHE_SIZE7__Size_MASK 0xffffff -+#define ACP_DSP2_CACHE_SIZE7__Size__SHIFT 0x0 -+#define ACP_DSP2_CACHE_SIZE7__PageEnable_MASK 0x80000000 -+#define ACP_DSP2_CACHE_SIZE7__PageEnable__SHIFT 0x1f -+#define ACP_DSP2_CACHE_OFFSET8__Offset_MASK 0xfffffff -+#define ACP_DSP2_CACHE_OFFSET8__Offset__SHIFT 0x0 -+#define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP2_CACHE_SIZE8__Size_MASK 0xffffff -+#define ACP_DSP2_CACHE_SIZE8__Size__SHIFT 0x0 -+#define ACP_DSP2_CACHE_SIZE8__PageEnable_MASK 0x80000000 -+#define ACP_DSP2_CACHE_SIZE8__PageEnable__SHIFT 0x1f -+#define ACP_DSP2_NONCACHE_OFFSET0__Offset_MASK 0xfffffff -+#define ACP_DSP2_NONCACHE_OFFSET0__Offset__SHIFT 0x0 -+#define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP2_NONCACHE_SIZE0__Size_MASK 0xffffff -+#define ACP_DSP2_NONCACHE_SIZE0__Size__SHIFT 0x0 -+#define ACP_DSP2_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 -+#define ACP_DSP2_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f -+#define ACP_DSP2_NONCACHE_OFFSET1__Offset_MASK 0xfffffff -+#define ACP_DSP2_NONCACHE_OFFSET1__Offset__SHIFT 0x0 -+#define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 -+#define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f -+#define ACP_DSP2_NONCACHE_SIZE1__Size_MASK 0xffffff -+#define ACP_DSP2_NONCACHE_SIZE1__Size__SHIFT 0x0 -+#define ACP_DSP2_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 -+#define ACP_DSP2_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f -+#define ACP_DSP2_DEBUG_PC__DebugPC_MASK 0xffffffff -+#define ACP_DSP2_DEBUG_PC__DebugPC__SHIFT 0x0 -+#define ACP_DSP2_NMI_SEL__NMISel_MASK 0x1 -+#define ACP_DSP2_NMI_SEL__NMISel__SHIFT 0x0 -+#define ACP_DSP2_CLKRST_CNTL__ClkEn_MASK 0x1 -+#define ACP_DSP2_CLKRST_CNTL__ClkEn__SHIFT 0x0 -+#define ACP_DSP2_CLKRST_CNTL__SoftResetDSP_MASK 0x2 -+#define ACP_DSP2_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 -+#define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 -+#define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 -+#define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 -+#define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 -+#define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 -+#define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 -+#define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 -+#define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 -+#define ACP_DSP2_RUNSTALL__RunStallCntl_MASK 0x1 -+#define ACP_DSP2_RUNSTALL__RunStallCntl__SHIFT 0x0 -+#define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 -+#define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 -+#define ACP_DSP2_WAIT_MODE__WaitMode_MASK 0x1 -+#define ACP_DSP2_WAIT_MODE__WaitMode__SHIFT 0x0 -+#define ACP_DSP2_VECT_SEL__StaticVectorSel_MASK 0x1 -+#define ACP_DSP2_VECT_SEL__StaticVectorSel__SHIFT 0x0 -+#define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff -+#define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 -+#define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff -+#define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 -+#define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff -+#define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap_MASK 0x3 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap__SHIFT 0x0 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb_MASK 0x80 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb__SHIFT 0x7 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb_MASK 0x100 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb_MASK 0x400 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode_MASK 0x2000 -+#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode__SHIFT 0xd -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000 -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19 -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000 -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000 -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000 -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000 -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19 -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000 -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000 -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000 -+#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f -+#define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1 -+#define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0 -+#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff -+#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 -+#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 -+#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f -+#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff -+#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 -+#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 -+#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f -+#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff -+#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 -+#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 -+#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f -+#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff -+#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 -+#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 -+#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap_MASK 0x3 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap__SHIFT 0x0 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb_MASK 0x80 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb__SHIFT 0x7 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb_MASK 0x100 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb_MASK 0x400 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode_MASK 0x2000 -+#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode__SHIFT 0xd -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000 -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19 -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000 -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000 -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000 -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000 -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19 -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000 -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000 -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000 -+#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f -+#define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1 -+#define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0 -+#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff -+#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 -+#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 -+#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f -+#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff -+#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 -+#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 -+#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f -+#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff -+#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 -+#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 -+#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f -+#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff -+#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 -+#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 -+#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f -+#define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize_MASK 0x3 -+#define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr_MASK 0xfffffff -+#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK 0x20000000 -+#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel__SHIFT 0x1d -+#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK 0x40000000 -+#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel__SHIFT 0x1e -+#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK 0x80000000 -+#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable__SHIFT 0x1f -+#define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize_MASK 0x3 -+#define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr_MASK 0xfffffff -+#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel_MASK 0x20000000 -+#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel__SHIFT 0x1d -+#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel_MASK 0x40000000 -+#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel__SHIFT 0x1e -+#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable_MASK 0x80000000 -+#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable__SHIFT 0x1f -+#define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize_MASK 0x3 -+#define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr_MASK 0xfffffff -+#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel_MASK 0x20000000 -+#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel__SHIFT 0x1d -+#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel_MASK 0x40000000 -+#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel__SHIFT 0x1e -+#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable_MASK 0x80000000 -+#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable__SHIFT 0x1f -+#define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize_MASK 0x3 -+#define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr_MASK 0xfffffff -+#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel_MASK 0x20000000 -+#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel__SHIFT 0x1d -+#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel_MASK 0x40000000 -+#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel__SHIFT 0x1e -+#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable_MASK 0x80000000 -+#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable__SHIFT 0x1f -+#define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize_MASK 0x3 -+#define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr_MASK 0xfffffff -+#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel_MASK 0x20000000 -+#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel__SHIFT 0x1d -+#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel_MASK 0x40000000 -+#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel__SHIFT 0x1e -+#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable_MASK 0x80000000 -+#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable__SHIFT 0x1f -+#define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize_MASK 0x3 -+#define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr_MASK 0xfffffff -+#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel_MASK 0x20000000 -+#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel__SHIFT 0x1d -+#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel_MASK 0x40000000 -+#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel__SHIFT 0x1e -+#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable_MASK 0x80000000 -+#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable__SHIFT 0x1f -+#define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize_MASK 0x3 -+#define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr_MASK 0xfffffff -+#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel_MASK 0x20000000 -+#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel__SHIFT 0x1d -+#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel_MASK 0x40000000 -+#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel__SHIFT 0x1e -+#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable_MASK 0x80000000 -+#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable__SHIFT 0x1f -+#define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize_MASK 0x3 -+#define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr_MASK 0xfffffff -+#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr__SHIFT 0x0 -+#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel_MASK 0x20000000 -+#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel__SHIFT 0x1d -+#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel_MASK 0x40000000 -+#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel__SHIFT 0x1e -+#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable_MASK 0x80000000 -+#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable__SHIFT 0x1f -+#define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate_MASK 0x1 -+#define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate__SHIFT 0x0 -+#define ACP_CONTROL__ClkEn_MASK 0x1 -+#define ACP_CONTROL__ClkEn__SHIFT 0x0 -+#define ACP_CONTROL__JtagEn_MASK 0x400 -+#define ACP_CONTROL__JtagEn__SHIFT 0xa -+#define ACP_STATUS__ClkOn_MASK 0x1 -+#define ACP_STATUS__ClkOn__SHIFT 0x0 -+#define ACP_STATUS__ACPRefClkSpd_MASK 0x2 -+#define ACP_STATUS__ACPRefClkSpd__SHIFT 0x1 -+#define ACP_STATUS__SMUStutterLastEdge_MASK 0x4 -+#define ACP_STATUS__SMUStutterLastEdge__SHIFT 0x2 -+#define ACP_STATUS__MCStutterLastEdge_MASK 0x8 -+#define ACP_STATUS__MCStutterLastEdge__SHIFT 0x3 -+#define ACP_SOFT_RESET__SoftResetAud_MASK 0x100 -+#define ACP_SOFT_RESET__SoftResetAud__SHIFT 0x8 -+#define ACP_SOFT_RESET__SoftResetDMA_MASK 0x200 -+#define ACP_SOFT_RESET__SoftResetDMA__SHIFT 0x9 -+#define ACP_SOFT_RESET__InternalSoftResetMode_MASK 0x4000 -+#define ACP_SOFT_RESET__InternalSoftResetMode__SHIFT 0xe -+#define ACP_SOFT_RESET__ExternalSoftResetMode_MASK 0x8000 -+#define ACP_SOFT_RESET__ExternalSoftResetMode__SHIFT 0xf -+#define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000 -+#define ACP_SOFT_RESET__SoftResetAudDone__SHIFT 0x18 -+#define ACP_SOFT_RESET__SoftResetDMADone_MASK 0x2000000 -+#define ACP_SOFT_RESET__SoftResetDMADone__SHIFT 0x19 -+#define ACP_PwrMgmt_CNTL__SCLKSleepCntl_MASK 0x3 -+#define ACP_PwrMgmt_CNTL__SCLKSleepCntl__SHIFT 0x0 -+#define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter_MASK 0xffff -+#define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter__SHIFT 0x0 -+#define ACP_SMU_MAILBOX__ACP_SMU_Mailbox_MASK 0xffffffff -+#define ACP_SMU_MAILBOX__ACP_SMU_Mailbox__SHIFT 0x0 -+#define ACP_FUTURE_REG_SCLK_0__ACPFutureReg_MASK 0xffffffff -+#define ACP_FUTURE_REG_SCLK_0__ACPFutureReg__SHIFT 0x0 -+#define ACP_FUTURE_REG_SCLK_1__ACPFutureReg_MASK 0xffffffff -+#define ACP_FUTURE_REG_SCLK_1__ACPFutureReg__SHIFT 0x0 -+#define ACP_FUTURE_REG_SCLK_2__ACPFutureReg_MASK 0xffffffff -+#define ACP_FUTURE_REG_SCLK_2__ACPFutureReg__SHIFT 0x0 -+#define ACP_FUTURE_REG_SCLK_3__ACPFutureReg_MASK 0xffffffff -+#define ACP_FUTURE_REG_SCLK_3__ACPFutureReg__SHIFT 0x0 -+#define ACP_FUTURE_REG_SCLK_4__ACPFutureReg_MASK 0xffffffff -+#define ACP_FUTURE_REG_SCLK_4__ACPFutureReg__SHIFT 0x0 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable_MASK 0x1 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable__SHIFT 0x0 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable_MASK 0x2 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable__SHIFT 0x1 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable_MASK 0x4 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable__SHIFT 0x2 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable_MASK 0x8 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable__SHIFT 0x3 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable_MASK 0x10 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable__SHIFT 0x4 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable_MASK 0x20 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable__SHIFT 0x5 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable_MASK 0x40 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable__SHIFT 0x6 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable_MASK 0x80 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable__SHIFT 0x7 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable_MASK 0x100 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable__SHIFT 0x8 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable_MASK 0x200 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable__SHIFT 0x9 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable_MASK 0x400 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable__SHIFT 0xa -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable_MASK 0x800 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable__SHIFT 0xb -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable_MASK 0x1000 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable__SHIFT 0xc -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable_MASK 0x2000 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable__SHIFT 0xd -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable_MASK 0x4000 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable__SHIFT 0xe -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable_MASK 0x8000 -+#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable__SHIFT 0xf -+#define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt_MASK 0xffff -+#define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt__SHIFT 0x0 -+#define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt_MASK 0xffff -+#define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt__SHIFT 0x0 -+#define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt_MASK 0xffff -+#define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt__SHIFT 0x0 -+#define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt_MASK 0xffff -+#define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt__SHIFT 0x0 -+#define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt_MASK 0xffff -+#define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt__SHIFT 0x0 -+#define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt_MASK 0xffff -+#define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt__SHIFT 0x0 -+#define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt_MASK 0xffff -+#define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt__SHIFT 0x0 -+#define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt_MASK 0xffff -+#define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt__SHIFT 0x0 -+#define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt_MASK 0xffff -+#define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt__SHIFT 0x0 -+#define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt_MASK 0xffff -+#define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt__SHIFT 0x0 -+#define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt_MASK 0xffff -+#define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt__SHIFT 0x0 -+#define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt_MASK 0xffff -+#define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt__SHIFT 0x0 -+#define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt_MASK 0xffff -+#define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt__SHIFT 0x0 -+#define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt_MASK 0xffff -+#define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt__SHIFT 0x0 -+#define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt_MASK 0xffff -+#define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt__SHIFT 0x0 -+#define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt_MASK 0xffff -+#define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt__SHIFT 0x0 -+#define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl_MASK 0xf -+#define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl__SHIFT 0x0 -+#define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb_MASK 0x1 -+#define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb__SHIFT 0x0 -+#define ACP_EXTERNAL_INTR_CNTL__ACPErrMask_MASK 0x1 -+#define ACP_EXTERNAL_INTR_CNTL__ACPErrMask__SHIFT 0x0 -+#define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 -+#define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 -+#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 -+#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 -+#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 -+#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 -+#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 -+#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 -+#define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask_MASK 0x40 -+#define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 -+#define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask_MASK 0x100 -+#define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask__SHIFT 0x8 -+#define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask_MASK 0x200 -+#define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask__SHIFT 0x9 -+#define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask_MASK 0x400 -+#define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask__SHIFT 0xa -+#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x800 -+#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xb -+#define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 -+#define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask__SHIFT 0x10 -+#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr_MASK 0x1 -+#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr__SHIFT 0x0 -+#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource_MASK 0xe -+#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource__SHIFT 0x1 -+#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver_MASK 0x10 -+#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver__SHIFT 0x4 -+#define ACP_ERROR_SOURCE_STS__BRBAddrErr_MASK 0x20 -+#define ACP_ERROR_SOURCE_STS__BRBAddrErr__SHIFT 0x5 -+#define ACP_ERROR_SOURCE_STS__BRBAddrErrSource_MASK 0x3c0 -+#define ACP_ERROR_SOURCE_STS__BRBAddrErrSource__SHIFT 0x6 -+#define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver_MASK 0x400 -+#define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver__SHIFT 0xa -+#define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr_MASK 0x800 -+#define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr__SHIFT 0xb -+#define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr_MASK 0x1000 -+#define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr__SHIFT 0xc -+#define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr_MASK 0x2000 -+#define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr__SHIFT 0xd -+#define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr_MASK 0x4000 -+#define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr__SHIFT 0xe -+#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr_MASK 0x8000 -+#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr__SHIFT 0xf -+#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource_MASK 0x70000 -+#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource__SHIFT 0x10 -+#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver_MASK 0x80000 -+#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver__SHIFT 0x13 -+#define ACP_ERROR_SOURCE_STS__DAGBErr_MASK 0x100000 -+#define ACP_ERROR_SOURCE_STS__DAGBErr__SHIFT 0x14 -+#define ACP_ERROR_SOURCE_STS__DAGBErrSource_MASK 0x1e00000 -+#define ACP_ERROR_SOURCE_STS__DAGBErrSource__SHIFT 0x15 -+#define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver_MASK 0x2000000 -+#define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver__SHIFT 0x19 -+#define ACP_ERROR_SOURCE_STS__DMATermOnErr_MASK 0x4000000 -+#define ACP_ERROR_SOURCE_STS__DMATermOnErr__SHIFT 0x1a -+#define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr_MASK 0x10000000 -+#define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr__SHIFT 0x1c -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0_MASK 0x1 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0__SHIFT 0x0 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1_MASK 0x2 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1__SHIFT 0x1 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2_MASK 0x4 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2__SHIFT 0x2 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0_MASK 0x100 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0__SHIFT 0x8 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1_MASK 0x200 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1__SHIFT 0x9 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2_MASK 0x400 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2__SHIFT 0xa -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host_MASK 0x10000 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host__SHIFT 0x10 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host_MASK 0x20000 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host__SHIFT 0x11 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host_MASK 0x40000 -+#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host__SHIFT 0x12 -+#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0_MASK 0x1 -+#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0__SHIFT 0x0 -+#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1_MASK 0x2 -+#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1__SHIFT 0x1 -+#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2_MASK 0x4 -+#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2__SHIFT 0x2 -+#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0_MASK 0x100 -+#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0__SHIFT 0x8 -+#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1_MASK 0x200 -+#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1__SHIFT 0x9 -+#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2_MASK 0x400 -+#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2__SHIFT 0xa -+#define ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask_MASK 0x10000 -+#define ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask__SHIFT 0x10 -+#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask_MASK 0x20000 -+#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask__SHIFT 0x11 -+#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask_MASK 0x40000 -+#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask__SHIFT 0x12 -+#define ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue_MASK 0x3ffff -+#define ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue__SHIFT 0x0 -+#define ACP_DAGBG_TIMEOUT_CNTL__CntEn_MASK 0x80000000 -+#define ACP_DAGBG_TIMEOUT_CNTL__CntEn__SHIFT 0x1f -+#define ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue_MASK 0x3ffff -+#define ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue__SHIFT 0x0 -+#define ACP_DAGBO_TIMEOUT_CNTL__CntEn_MASK 0x80000000 -+#define ACP_DAGBO_TIMEOUT_CNTL__CntEn__SHIFT 0x1f -+#define ACP_EXTERNAL_INTR_STAT__ACPErrStat_MASK 0x1 -+#define ACP_EXTERNAL_INTR_STAT__ACPErrStat__SHIFT 0x0 -+#define ACP_EXTERNAL_INTR_STAT__ACPErrAck_MASK 0x1 -+#define ACP_EXTERNAL_INTR_STAT__ACPErrAck__SHIFT 0x0 -+#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat_MASK 0x2 -+#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 -+#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck_MASK 0x2 -+#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 -+#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 -+#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 -+#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 -+#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 -+#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 -+#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 -+#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 -+#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 -+#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat_MASK 0x10 -+#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 -+#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck_MASK 0x10 -+#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 -+#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat_MASK 0x40 -+#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 -+#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck_MASK 0x40 -+#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 -+#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat_MASK 0x100 -+#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat__SHIFT 0x8 -+#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck_MASK 0x100 -+#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck__SHIFT 0x8 -+#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat_MASK 0x200 -+#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat__SHIFT 0x9 -+#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck_MASK 0x200 -+#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck__SHIFT 0x9 -+#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat_MASK 0x400 -+#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat__SHIFT 0xa -+#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck_MASK 0x400 -+#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck__SHIFT 0xa -+#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat_MASK 0x800 -+#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xb -+#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck_MASK 0x800 -+#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xb -+#define ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK 0xffff0000 -+#define ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT 0x10 -+#define ACP_EXTERNAL_INTR_STAT__DMAIOCAck_MASK 0xffff0000 -+#define ACP_EXTERNAL_INTR_STAT__DMAIOCAck__SHIFT 0x10 -+#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat_MASK 0x1 -+#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat__SHIFT 0x0 -+#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack_MASK 0x1 -+#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack__SHIFT 0x0 -+#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat_MASK 0x2 -+#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat__SHIFT 0x1 -+#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack_MASK 0x2 -+#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack__SHIFT 0x1 -+#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat_MASK 0x4 -+#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat__SHIFT 0x2 -+#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack_MASK 0x4 -+#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack__SHIFT 0x2 -+#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat_MASK 0x100 -+#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat__SHIFT 0x8 -+#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack_MASK 0x100 -+#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack__SHIFT 0x8 -+#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat_MASK 0x200 -+#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat__SHIFT 0x9 -+#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack_MASK 0x200 -+#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack__SHIFT 0x9 -+#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat_MASK 0x400 -+#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat__SHIFT 0xa -+#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack_MASK 0x400 -+#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack__SHIFT 0xa -+#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat_MASK 0x10000 -+#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat__SHIFT 0x10 -+#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack_MASK 0x10000 -+#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack__SHIFT 0x10 -+#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat_MASK 0x20000 -+#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat__SHIFT 0x11 -+#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack_MASK 0x20000 -+#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack__SHIFT 0x11 -+#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat_MASK 0x40000 -+#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat__SHIFT 0x12 -+#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack_MASK 0x40000 -+#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack__SHIFT 0x12 -+#define ACP_DSP0_INTR_CNTL__ACPErrMask_MASK 0x1 -+#define ACP_DSP0_INTR_CNTL__ACPErrMask__SHIFT 0x0 -+#define ACP_DSP0_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 -+#define ACP_DSP0_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 -+#define ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 -+#define ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 -+#define ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 -+#define ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 -+#define ACP_DSP0_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 -+#define ACP_DSP0_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 -+#define ACP_DSP0_INTR_CNTL__AzaliaIntrMask_MASK 0x40 -+#define ACP_DSP0_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 -+#define ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 -+#define ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 -+#define ACP_DSP0_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 -+#define ACP_DSP0_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 -+#define ACP_DSP0_INTR_CNTL__MCStutterStatusMask_MASK 0x400 -+#define ACP_DSP0_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa -+#define ACP_DSP0_INTR_CNTL__DSPExtTimerMask_MASK 0x800 -+#define ACP_DSP0_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb -+#define ACP_DSP0_INTR_CNTL__DSPSemRespMask_MASK 0x1000 -+#define ACP_DSP0_INTR_CNTL__DSPSemRespMask__SHIFT 0xc -+#define ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 -+#define ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd -+#define ACP_DSP0_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 -+#define ACP_DSP0_INTR_CNTL__DMAIOCMask__SHIFT 0x10 -+#define ACP_DSP0_INTR_STAT__ACPErrStat_MASK 0x1 -+#define ACP_DSP0_INTR_STAT__ACPErrStat__SHIFT 0x0 -+#define ACP_DSP0_INTR_STAT__ACPErrAck_MASK 0x1 -+#define ACP_DSP0_INTR_STAT__ACPErrAck__SHIFT 0x0 -+#define ACP_DSP0_INTR_STAT__I2SMicDataAvStat_MASK 0x2 -+#define ACP_DSP0_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 -+#define ACP_DSP0_INTR_STAT__I2SMicDataAvAck_MASK 0x2 -+#define ACP_DSP0_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 -+#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 -+#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 -+#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 -+#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 -+#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 -+#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 -+#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 -+#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 -+#define ACP_DSP0_INTR_STAT__I2SBTDataAvStat_MASK 0x10 -+#define ACP_DSP0_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 -+#define ACP_DSP0_INTR_STAT__I2SBTDataAvAck_MASK 0x10 -+#define ACP_DSP0_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 -+#define ACP_DSP0_INTR_STAT__AzaliaIntrStat_MASK 0x40 -+#define ACP_DSP0_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 -+#define ACP_DSP0_INTR_STAT__AzaliaIntrAck_MASK 0x40 -+#define ACP_DSP0_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 -+#define ACP_DSP0_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 -+#define ACP_DSP0_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 -+#define ACP_DSP0_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 -+#define ACP_DSP0_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 -+#define ACP_DSP0_INTR_STAT__SMUStutterStatusStat_MASK 0x200 -+#define ACP_DSP0_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 -+#define ACP_DSP0_INTR_STAT__SMUStutterStatusAck_MASK 0x200 -+#define ACP_DSP0_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 -+#define ACP_DSP0_INTR_STAT__MCStutterStatusStat_MASK 0x400 -+#define ACP_DSP0_INTR_STAT__MCStutterStatusStat__SHIFT 0xa -+#define ACP_DSP0_INTR_STAT__MCStutterStatusAck_MASK 0x400 -+#define ACP_DSP0_INTR_STAT__MCStutterStatusAck__SHIFT 0xa -+#define ACP_DSP0_INTR_STAT__DSPExtTimerStat_MASK 0x800 -+#define ACP_DSP0_INTR_STAT__DSPExtTimerStat__SHIFT 0xb -+#define ACP_DSP0_INTR_STAT__DSPExtTimerAck_MASK 0x800 -+#define ACP_DSP0_INTR_STAT__DSPExtTimerAck__SHIFT 0xb -+#define ACP_DSP0_INTR_STAT__DSPSemRespStat_MASK 0x1000 -+#define ACP_DSP0_INTR_STAT__DSPSemRespStat__SHIFT 0xc -+#define ACP_DSP0_INTR_STAT__DSPSemRespAck_MASK 0x1000 -+#define ACP_DSP0_INTR_STAT__DSPSemRespAck__SHIFT 0xc -+#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 -+#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd -+#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 -+#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd -+#define ACP_DSP0_INTR_STAT__DMAIOCStat_MASK 0xffff0000 -+#define ACP_DSP0_INTR_STAT__DMAIOCStat__SHIFT 0x10 -+#define ACP_DSP0_INTR_STAT__DMAIOCAck_MASK 0xffff0000 -+#define ACP_DSP0_INTR_STAT__DMAIOCAck__SHIFT 0x10 -+#define ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue_MASK 0x3ffff -+#define ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue__SHIFT 0x0 -+#define ACP_DSP0_TIMEOUT_CNTL__CntEn_MASK 0x80000000 -+#define ACP_DSP0_TIMEOUT_CNTL__CntEn__SHIFT 0x1f -+#define ACP_DSP1_INTR_CNTL__ACPErrMask_MASK 0x1 -+#define ACP_DSP1_INTR_CNTL__ACPErrMask__SHIFT 0x0 -+#define ACP_DSP1_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 -+#define ACP_DSP1_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 -+#define ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 -+#define ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 -+#define ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 -+#define ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 -+#define ACP_DSP1_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 -+#define ACP_DSP1_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 -+#define ACP_DSP1_INTR_CNTL__AzaliaIntrMask_MASK 0x40 -+#define ACP_DSP1_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 -+#define ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 -+#define ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 -+#define ACP_DSP1_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 -+#define ACP_DSP1_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 -+#define ACP_DSP1_INTR_CNTL__MCStutterStatusMask_MASK 0x400 -+#define ACP_DSP1_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa -+#define ACP_DSP1_INTR_CNTL__DSPExtTimerMask_MASK 0x800 -+#define ACP_DSP1_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb -+#define ACP_DSP1_INTR_CNTL__DSPSemRespMask_MASK 0x1000 -+#define ACP_DSP1_INTR_CNTL__DSPSemRespMask__SHIFT 0xc -+#define ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 -+#define ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd -+#define ACP_DSP1_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 -+#define ACP_DSP1_INTR_CNTL__DMAIOCMask__SHIFT 0x10 -+#define ACP_DSP1_INTR_STAT__ACPErrStat_MASK 0x1 -+#define ACP_DSP1_INTR_STAT__ACPErrStat__SHIFT 0x0 -+#define ACP_DSP1_INTR_STAT__ACPErrAck_MASK 0x1 -+#define ACP_DSP1_INTR_STAT__ACPErrAck__SHIFT 0x0 -+#define ACP_DSP1_INTR_STAT__I2SMicDataAvStat_MASK 0x2 -+#define ACP_DSP1_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 -+#define ACP_DSP1_INTR_STAT__I2SMicDataAvAck_MASK 0x2 -+#define ACP_DSP1_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 -+#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 -+#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 -+#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 -+#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 -+#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 -+#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 -+#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 -+#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 -+#define ACP_DSP1_INTR_STAT__I2SBTDataAvStat_MASK 0x10 -+#define ACP_DSP1_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 -+#define ACP_DSP1_INTR_STAT__I2SBTDataAvAck_MASK 0x10 -+#define ACP_DSP1_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 -+#define ACP_DSP1_INTR_STAT__AzaliaIntrStat_MASK 0x40 -+#define ACP_DSP1_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 -+#define ACP_DSP1_INTR_STAT__AzaliaIntrAck_MASK 0x40 -+#define ACP_DSP1_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 -+#define ACP_DSP1_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 -+#define ACP_DSP1_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 -+#define ACP_DSP1_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 -+#define ACP_DSP1_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 -+#define ACP_DSP1_INTR_STAT__SMUStutterStatusStat_MASK 0x200 -+#define ACP_DSP1_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 -+#define ACP_DSP1_INTR_STAT__SMUStutterStatusAck_MASK 0x200 -+#define ACP_DSP1_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 -+#define ACP_DSP1_INTR_STAT__MCStutterStatusStat_MASK 0x400 -+#define ACP_DSP1_INTR_STAT__MCStutterStatusStat__SHIFT 0xa -+#define ACP_DSP1_INTR_STAT__MCStutterStatusAck_MASK 0x400 -+#define ACP_DSP1_INTR_STAT__MCStutterStatusAck__SHIFT 0xa -+#define ACP_DSP1_INTR_STAT__DSPExtTimerStat_MASK 0x800 -+#define ACP_DSP1_INTR_STAT__DSPExtTimerStat__SHIFT 0xb -+#define ACP_DSP1_INTR_STAT__DSPExtTimerAck_MASK 0x800 -+#define ACP_DSP1_INTR_STAT__DSPExtTimerAck__SHIFT 0xb -+#define ACP_DSP1_INTR_STAT__DSPSemRespStat_MASK 0x1000 -+#define ACP_DSP1_INTR_STAT__DSPSemRespStat__SHIFT 0xc -+#define ACP_DSP1_INTR_STAT__DSPSemRespAck_MASK 0x1000 -+#define ACP_DSP1_INTR_STAT__DSPSemRespAck__SHIFT 0xc -+#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 -+#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd -+#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 -+#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd -+#define ACP_DSP1_INTR_STAT__DMAIOCStat_MASK 0xffff0000 -+#define ACP_DSP1_INTR_STAT__DMAIOCStat__SHIFT 0x10 -+#define ACP_DSP1_INTR_STAT__DMAIOCAck_MASK 0xffff0000 -+#define ACP_DSP1_INTR_STAT__DMAIOCAck__SHIFT 0x10 -+#define ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue_MASK 0x3ffff -+#define ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue__SHIFT 0x0 -+#define ACP_DSP1_TIMEOUT_CNTL__CntEn_MASK 0x80000000 -+#define ACP_DSP1_TIMEOUT_CNTL__CntEn__SHIFT 0x1f -+#define ACP_DSP2_INTR_CNTL__ACPErrMask_MASK 0x1 -+#define ACP_DSP2_INTR_CNTL__ACPErrMask__SHIFT 0x0 -+#define ACP_DSP2_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 -+#define ACP_DSP2_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 -+#define ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 -+#define ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 -+#define ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 -+#define ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 -+#define ACP_DSP2_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 -+#define ACP_DSP2_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 -+#define ACP_DSP2_INTR_CNTL__AzaliaIntrMask_MASK 0x40 -+#define ACP_DSP2_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 -+#define ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 -+#define ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 -+#define ACP_DSP2_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 -+#define ACP_DSP2_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 -+#define ACP_DSP2_INTR_CNTL__MCStutterStatusMask_MASK 0x400 -+#define ACP_DSP2_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa -+#define ACP_DSP2_INTR_CNTL__DSPExtTimerMask_MASK 0x800 -+#define ACP_DSP2_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb -+#define ACP_DSP2_INTR_CNTL__DSPSemRespMask_MASK 0x1000 -+#define ACP_DSP2_INTR_CNTL__DSPSemRespMask__SHIFT 0xc -+#define ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 -+#define ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd -+#define ACP_DSP2_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 -+#define ACP_DSP2_INTR_CNTL__DMAIOCMask__SHIFT 0x10 -+#define ACP_DSP2_INTR_STAT__ACPErrStat_MASK 0x1 -+#define ACP_DSP2_INTR_STAT__ACPErrStat__SHIFT 0x0 -+#define ACP_DSP2_INTR_STAT__ACPErrAck_MASK 0x1 -+#define ACP_DSP2_INTR_STAT__ACPErrAck__SHIFT 0x0 -+#define ACP_DSP2_INTR_STAT__I2SMicDataAvStat_MASK 0x2 -+#define ACP_DSP2_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 -+#define ACP_DSP2_INTR_STAT__I2SMicDataAvAck_MASK 0x2 -+#define ACP_DSP2_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 -+#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 -+#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 -+#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 -+#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 -+#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 -+#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 -+#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 -+#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 -+#define ACP_DSP2_INTR_STAT__I2SBTDataAvStat_MASK 0x10 -+#define ACP_DSP2_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 -+#define ACP_DSP2_INTR_STAT__I2SBTDataAvAck_MASK 0x10 -+#define ACP_DSP2_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 -+#define ACP_DSP2_INTR_STAT__AzaliaIntrStat_MASK 0x40 -+#define ACP_DSP2_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 -+#define ACP_DSP2_INTR_STAT__AzaliaIntrAck_MASK 0x40 -+#define ACP_DSP2_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 -+#define ACP_DSP2_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 -+#define ACP_DSP2_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 -+#define ACP_DSP2_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 -+#define ACP_DSP2_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 -+#define ACP_DSP2_INTR_STAT__SMUStutterStatusStat_MASK 0x200 -+#define ACP_DSP2_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 -+#define ACP_DSP2_INTR_STAT__SMUStutterStatusAck_MASK 0x200 -+#define ACP_DSP2_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 -+#define ACP_DSP2_INTR_STAT__MCStutterStatusStat_MASK 0x400 -+#define ACP_DSP2_INTR_STAT__MCStutterStatusStat__SHIFT 0xa -+#define ACP_DSP2_INTR_STAT__MCStutterStatusAck_MASK 0x400 -+#define ACP_DSP2_INTR_STAT__MCStutterStatusAck__SHIFT 0xa -+#define ACP_DSP2_INTR_STAT__DSPExtTimerStat_MASK 0x800 -+#define ACP_DSP2_INTR_STAT__DSPExtTimerStat__SHIFT 0xb -+#define ACP_DSP2_INTR_STAT__DSPExtTimerAck_MASK 0x800 -+#define ACP_DSP2_INTR_STAT__DSPExtTimerAck__SHIFT 0xb -+#define ACP_DSP2_INTR_STAT__DSPSemRespStat_MASK 0x1000 -+#define ACP_DSP2_INTR_STAT__DSPSemRespStat__SHIFT 0xc -+#define ACP_DSP2_INTR_STAT__DSPSemRespAck_MASK 0x1000 -+#define ACP_DSP2_INTR_STAT__DSPSemRespAck__SHIFT 0xc -+#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 -+#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd -+#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 -+#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd -+#define ACP_DSP2_INTR_STAT__DMAIOCStat_MASK 0xffff0000 -+#define ACP_DSP2_INTR_STAT__DMAIOCStat__SHIFT 0x10 -+#define ACP_DSP2_INTR_STAT__DMAIOCAck_MASK 0xffff0000 -+#define ACP_DSP2_INTR_STAT__DMAIOCAck__SHIFT 0x10 -+#define ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue_MASK 0x3ffff -+#define ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue__SHIFT 0x0 -+#define ACP_DSP2_TIMEOUT_CNTL__CntEn_MASK 0x80000000 -+#define ACP_DSP2_TIMEOUT_CNTL__CntEn__SHIFT 0x1f -+#define ACP_DSP0_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff -+#define ACP_DSP0_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 -+#define ACP_DSP0_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 -+#define ACP_DSP0_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e -+#define ACP_DSP1_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff -+#define ACP_DSP1_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 -+#define ACP_DSP1_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 -+#define ACP_DSP1_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e -+#define ACP_DSP2_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff -+#define ACP_DSP2_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 -+#define ACP_DSP2_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 -+#define ACP_DSP2_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e -+#define ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg_MASK 0x1 -+#define ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg__SHIFT 0x0 -+#define ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr_MASK 0xff -+#define ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr__SHIFT 0x0 -+#define ACP_SRBM_Client_RDDATA__ReadData_MASK 0xffffffff -+#define ACP_SRBM_Client_RDDATA__ReadData__SHIFT 0x0 -+#define ACP_SRBM_Cycle_Sts__SRBM_Client_Sts_MASK 0x1 -+#define ACP_SRBM_Cycle_Sts__SRBM_Client_Sts__SHIFT 0x0 -+#define ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr_MASK 0x7ffffff -+#define ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr__SHIFT 0x0 -+#define ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data_MASK 0xffffffff -+#define ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data__SHIFT 0x0 -+#define ACP_SEMA_ADDR_LOW__ADDR_9_3_MASK 0x7f -+#define ACP_SEMA_ADDR_LOW__ADDR_9_3__SHIFT 0x0 -+#define ACP_SEMA_ADDR_HIGH__ADDR_39_10_MASK 0x3fffffff -+#define ACP_SEMA_ADDR_HIGH__ADDR_39_10__SHIFT 0x0 -+#define ACP_SEMA_CMD__REQ_CMD_MASK 0xf -+#define ACP_SEMA_CMD__REQ_CMD__SHIFT 0x0 -+#define ACP_SEMA_CMD__WR_PHASE_MASK 0x30 -+#define ACP_SEMA_CMD__WR_PHASE__SHIFT 0x4 -+#define ACP_SEMA_CMD__VMID_EN_MASK 0x80 -+#define ACP_SEMA_CMD__VMID_EN__SHIFT 0x7 -+#define ACP_SEMA_CMD__VMID_MASK 0xf00 -+#define ACP_SEMA_CMD__VMID__SHIFT 0x8 -+#define ACP_SEMA_CMD__ATC_MASK 0x1000 -+#define ACP_SEMA_CMD__ATC__SHIFT 0xc -+#define ACP_SEMA_STS__REQ_STS_MASK 0x3 -+#define ACP_SEMA_STS__REQ_STS__SHIFT 0x0 -+#define ACP_SEMA_STS__REQ_RESP_AVAIL_MASK 0x100 -+#define ACP_SEMA_STS__REQ_RESP_AVAIL__SHIFT 0x8 -+#define ACP_SEMA_REQ__ISSUE_POLL_REQ_MASK 0x1 -+#define ACP_SEMA_REQ__ISSUE_POLL_REQ__SHIFT 0x0 -+#define ACP_FW_STATUS__RUN_MASK 0x1 -+#define ACP_FW_STATUS__RUN__SHIFT 0x0 -+#define ACP_FUTURE_REG_ACLK_0__ACPFutureReg_MASK 0xffffffff -+#define ACP_FUTURE_REG_ACLK_0__ACPFutureReg__SHIFT 0x0 -+#define ACP_FUTURE_REG_ACLK_1__ACPFutureReg_MASK 0xffffffff -+#define ACP_FUTURE_REG_ACLK_1__ACPFutureReg__SHIFT 0x0 -+#define ACP_FUTURE_REG_ACLK_2__ACPFutureReg_MASK 0xffffffff -+#define ACP_FUTURE_REG_ACLK_2__ACPFutureReg__SHIFT 0x0 -+#define ACP_FUTURE_REG_ACLK_3__ACPFutureReg_MASK 0xffffffff -+#define ACP_FUTURE_REG_ACLK_3__ACPFutureReg__SHIFT 0x0 -+#define ACP_FUTURE_REG_ACLK_4__ACPFutureReg_MASK 0xffffffff -+#define ACP_FUTURE_REG_ACLK_4__ACPFutureReg__SHIFT 0x0 -+#define ACP_TIMER__ACP_Timer_count_MASK 0xffffffff -+#define ACP_TIMER__ACP_Timer_count__SHIFT 0x0 -+#define ACP_TIMER_CNTL__ACP_Timer_control_MASK 0x1 -+#define ACP_TIMER_CNTL__ACP_Timer_control__SHIFT 0x0 -+#define ACP_DSP0_TIMER__ACP_DSP0_timer_MASK 0xffffff -+#define ACP_DSP0_TIMER__ACP_DSP0_timer__SHIFT 0x0 -+#define ACP_DSP1_TIMER__ACP_DSP1_timer_MASK 0xffffff -+#define ACP_DSP1_TIMER__ACP_DSP1_timer__SHIFT 0x0 -+#define ACP_DSP2_TIMER__ACP_DSP2_timer_MASK 0xffffff -+#define ACP_DSP2_TIMER__ACP_DSP2_timer__SHIFT 0x0 -+#define ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high_MASK 0xffffffff -+#define ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high__SHIFT 0x0 -+#define ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low_MASK 0xffffffff -+#define ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low__SHIFT 0x0 -+#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high_MASK 0xffffffff -+#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high__SHIFT 0x0 -+#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low_MASK 0xffffffff -+#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low__SHIFT 0x0 -+#define ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high_MASK 0xffffffff -+#define ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high__SHIFT 0x0 -+#define ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low_MASK 0xffffffff -+#define ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low__SHIFT 0x0 -+#define ACP_DSP0_CS_STATE__DSP0_CS_state_MASK 0x1 -+#define ACP_DSP0_CS_STATE__DSP0_CS_state__SHIFT 0x0 -+#define ACP_DSP1_CS_STATE__DSP1_CS_state_MASK 0x1 -+#define ACP_DSP1_CS_STATE__DSP1_CS_state__SHIFT 0x0 -+#define ACP_DSP2_CS_STATE__DSP2_CS_state_MASK 0x1 -+#define ACP_DSP2_CS_STATE__DSP2_CS_state__SHIFT 0x0 -+#define ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR_MASK 0x7ffff -+#define ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR__SHIFT 0x0 -+#define CC_ACP_EFUSE__DSP0_DISABLE_MASK 0x2 -+#define CC_ACP_EFUSE__DSP0_DISABLE__SHIFT 0x1 -+#define CC_ACP_EFUSE__DSP1_DISABLE_MASK 0x4 -+#define CC_ACP_EFUSE__DSP1_DISABLE__SHIFT 0x2 -+#define CC_ACP_EFUSE__DSP2_DISABLE_MASK 0x8 -+#define CC_ACP_EFUSE__DSP2_DISABLE__SHIFT 0x3 -+#define CC_ACP_EFUSE__ACP_DISABLE_MASK 0x10 -+#define CC_ACP_EFUSE__ACP_DISABLE__SHIFT 0x4 -+#define ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF_MASK 0x1 -+#define ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF__SHIFT 0x0 -+#define ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF_MASK 0x2 -+#define ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF__SHIFT 0x1 -+#define ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF_MASK 0x4 -+#define ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF__SHIFT 0x2 -+#define ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF_MASK 0x8 -+#define ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF__SHIFT 0x3 -+#define ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF_MASK 0x10 -+#define ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF__SHIFT 0x4 -+#define ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF_MASK 0x20 -+#define ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF__SHIFT 0x5 -+#define ACP_PGFSM_CONFIG_REG__FSM_ADDR_MASK 0xff -+#define ACP_PGFSM_CONFIG_REG__FSM_ADDR__SHIFT 0x0 -+#define ACP_PGFSM_CONFIG_REG__Power_Down_MASK 0x100 -+#define ACP_PGFSM_CONFIG_REG__Power_Down__SHIFT 0x8 -+#define ACP_PGFSM_CONFIG_REG__Power_Up_MASK 0x200 -+#define ACP_PGFSM_CONFIG_REG__Power_Up__SHIFT 0x9 -+#define ACP_PGFSM_CONFIG_REG__P1_Select_MASK 0x400 -+#define ACP_PGFSM_CONFIG_REG__P1_Select__SHIFT 0xa -+#define ACP_PGFSM_CONFIG_REG__P2_Select_MASK 0x800 -+#define ACP_PGFSM_CONFIG_REG__P2_Select__SHIFT 0xb -+#define ACP_PGFSM_CONFIG_REG__Wr_MASK 0x1000 -+#define ACP_PGFSM_CONFIG_REG__Wr__SHIFT 0xc -+#define ACP_PGFSM_CONFIG_REG__Rd_MASK 0x2000 -+#define ACP_PGFSM_CONFIG_REG__Rd__SHIFT 0xd -+#define ACP_PGFSM_CONFIG_REG__RdData_Reset_MASK 0x4000 -+#define ACP_PGFSM_CONFIG_REG__RdData_Reset__SHIFT 0xe -+#define ACP_PGFSM_CONFIG_REG__Short_Format_MASK 0x8000 -+#define ACP_PGFSM_CONFIG_REG__Short_Format__SHIFT 0xf -+#define ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG_MASK 0x3ff0000 -+#define ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG__SHIFT 0x10 -+#define ACP_PGFSM_CONFIG_REG__SRBM_override_MASK 0x4000000 -+#define ACP_PGFSM_CONFIG_REG__SRBM_override__SHIFT 0x1a -+#define ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr_MASK 0x8000000 -+#define ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr__SHIFT 0x1b -+#define ACP_PGFSM_CONFIG_REG__REG_ADDR_MASK 0xf0000000 -+#define ACP_PGFSM_CONFIG_REG__REG_ADDR__SHIFT 0x1c -+#define ACP_PGFSM_WRITE_REG__Write_value_MASK 0xffffffff -+#define ACP_PGFSM_WRITE_REG__Write_value__SHIFT 0x0 -+#define ACP_PGFSM_READ_REG_0__Read_value_MASK 0xffffff -+#define ACP_PGFSM_READ_REG_0__Read_value__SHIFT 0x0 -+#define ACP_PGFSM_READ_REG_1__Read_value_MASK 0xffffff -+#define ACP_PGFSM_READ_REG_1__Read_value__SHIFT 0x0 -+#define ACP_PGFSM_READ_REG_2__Read_value_MASK 0xffffff -+#define ACP_PGFSM_READ_REG_2__Read_value__SHIFT 0x0 -+#define ACP_PGFSM_READ_REG_3__Read_value_MASK 0xffffff -+#define ACP_PGFSM_READ_REG_3__Read_value__SHIFT 0x0 -+#define ACP_PGFSM_READ_REG_4__Read_value_MASK 0xffffff -+#define ACP_PGFSM_READ_REG_4__Read_value__SHIFT 0x0 -+#define ACP_PGFSM_READ_REG_5__Read_value_MASK 0xffffff -+#define ACP_PGFSM_READ_REG_5__Read_value__SHIFT 0x0 -+#define ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS_MASK 0x1 -+#define ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS__SHIFT 0x0 -+#define ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG_MASK 0x3 -+#define ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG__SHIFT 0x0 -+#define ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT_MASK 0x1 -+#define ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT__SHIFT 0x0 -+#define ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package_MASK 0x1 -+#define ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package__SHIFT 0x0 -+#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable_MASK 0x7ff -+#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable__SHIFT 0x0 -+#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable_MASK 0x7ff0000 -+#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable__SHIFT 0x10 -+#define ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL_MASK 0x1 -+#define ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL__SHIFT 0x0 -+#define ACP_SCRATCH_REG_0__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_0__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_1__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_1__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_2__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_2__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_3__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_3__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_4__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_4__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_5__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_5__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_6__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_6__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_7__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_7__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_8__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_8__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_9__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_9__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_10__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_10__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_11__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_11__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_12__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_12__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_13__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_13__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_14__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_14__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_15__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_15__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_16__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_16__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_17__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_17__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_18__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_18__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_19__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_19__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_20__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_20__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_21__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_21__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_22__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_22__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_23__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_23__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_24__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_24__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_25__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_25__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_26__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_26__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_27__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_27__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_28__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_28__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_29__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_29__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_30__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_30__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_31__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_31__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_32__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_32__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_33__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_33__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_34__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_34__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_35__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_35__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_36__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_36__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_37__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_37__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_38__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_38__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_39__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_39__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_40__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_40__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_41__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_41__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_42__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_42__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_43__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_43__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_44__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_44__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_45__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_45__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_46__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_46__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_SCRATCH_REG_47__ACP_SCRATCH_REG_MASK 0xffffffff -+#define ACP_SCRATCH_REG_47__ACP_SCRATCH_REG__SHIFT 0x0 -+#define ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable_MASK 0x1 -+#define ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable__SHIFT 0x0 -+#define ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status_MASK 0x1 -+#define ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status__SHIFT 0x0 -+#define I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold_MASK 0xffffffff -+#define I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold__SHIFT 0x0 -+#define I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold_MASK 0xffffffff -+#define I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold__SHIFT 0x0 -+#define I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples_MASK 0xffff -+#define I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples__SHIFT 0x0 -+#define I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks_MASK 0xffff -+#define I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks__SHIFT 0x0 -+#define I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks_MASK 0xffffffff -+#define I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks__SHIFT 0x0 -+#define I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en_MASK 0x1 -+#define I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en__SHIFT 0x0 -+#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req_MASK 0x1 -+#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req__SHIFT 0x0 -+#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack_MASK 0x2 -+#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack__SHIFT 0x1 -+#define I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer_MASK 0xffffffff -+#define I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer__SHIFT 0x0 -+#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid_MASK 0x1 -+#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid__SHIFT 0x0 -+#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match_MASK 0x2 -+#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match__SHIFT 0x1 -+#define I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap_MASK 0x1 -+#define I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap__SHIFT 0x0 -+#define ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high_MASK 0xffffffff -+#define ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high__SHIFT 0x0 -+#define ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low_MASK 0xffffffff -+#define ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low__SHIFT 0x0 -+#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high_MASK 0xffffffff -+#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high__SHIFT 0x0 -+#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low_MASK 0xffffffff -+#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low__SHIFT 0x0 -+#define ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML_MASK 0xffffffff -+#define ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML__SHIFT 0x0 -+#define ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH_MASK 0xffff -+#define ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH__SHIFT 0x0 -+#define ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML_MASK 0xffffffff -+#define ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML__SHIFT 0x0 -+#define ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH_MASK 0xffff -+#define ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH__SHIFT 0x0 -+#define ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML_MASK 0xffffffff -+#define ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML__SHIFT 0x0 -+#define ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH_MASK 0xffff -+#define ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH__SHIFT 0x0 -+#define ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML_MASK 0xffffffff -+#define ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML__SHIFT 0x0 -+#define ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH_MASK 0xffff -+#define ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH__SHIFT 0x0 -+#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo_MASK 0xffffffff -+#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo__SHIFT 0x0 -+#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi_MASK 0xffff -+#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi__SHIFT 0x0 -+#define ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo_MASK 0xffffffff -+#define ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo__SHIFT 0x0 -+#define ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi_MASK 0xffff -+#define ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi__SHIFT 0x0 -+#define ACP_I2SSP_IER__I2SSP_IEN_MASK 0x1 -+#define ACP_I2SSP_IER__I2SSP_IEN__SHIFT 0x0 -+#define ACP_I2SSP_IRER__I2SSP_RXEN_MASK 0x1 -+#define ACP_I2SSP_IRER__I2SSP_RXEN__SHIFT 0x0 -+#define ACP_I2SSP_ITER__I2SSP_TXEN_MASK 0x1 -+#define ACP_I2SSP_ITER__I2SSP_TXEN__SHIFT 0x0 -+#define ACP_I2SSP_CER__I2SSP_CLKEN_MASK 0x1 -+#define ACP_I2SSP_CER__I2SSP_CLKEN__SHIFT 0x0 -+#define ACP_I2SSP_CCR__I2SSP_SCLKG_MASK 0x7 -+#define ACP_I2SSP_CCR__I2SSP_SCLKG__SHIFT 0x0 -+#define ACP_I2SSP_CCR__I2SSP_WSS_MASK 0x18 -+#define ACP_I2SSP_CCR__I2SSP_WSS__SHIFT 0x3 -+#define ACP_I2SSP_RXFFR__I2SSP_RXFFR_MASK 0x1 -+#define ACP_I2SSP_RXFFR__I2SSP_RXFFR__SHIFT 0x0 -+#define ACP_I2SSP_TXFFR__I2SSP_TXFFR_MASK 0x1 -+#define ACP_I2SSP_TXFFR__I2SSP_TXFFR__SHIFT 0x0 -+#define ACP_I2SSP_LRBR0__I2SSP_LRBR0_MASK 0xffffffff -+#define ACP_I2SSP_LRBR0__I2SSP_LRBR0__SHIFT 0x0 -+#define ACP_I2SSP_RRBR0__I2SSP_RRBR0_MASK 0xffffffff -+#define ACP_I2SSP_RRBR0__I2SSP_RRBR0__SHIFT 0x0 -+#define ACP_I2SSP_RER0__I2SSP_RXCHEN0_MASK 0x1 -+#define ACP_I2SSP_RER0__I2SSP_RXCHEN0__SHIFT 0x0 -+#define ACP_I2SSP_TER0__I2SSP_TXCHEN0_MASK 0x1 -+#define ACP_I2SSP_TER0__I2SSP_TXCHEN0__SHIFT 0x0 -+#define ACP_I2SSP_RCR0__I2SSP_WLEN_MASK 0x7 -+#define ACP_I2SSP_RCR0__I2SSP_WLEN__SHIFT 0x0 -+#define ACP_I2SSP_TCR0__I2SSP_WLEN_MASK 0x7 -+#define ACP_I2SSP_TCR0__I2SSP_WLEN__SHIFT 0x0 -+#define ACP_I2SSP_ISR0__I2SSP_RXDA_MASK 0x1 -+#define ACP_I2SSP_ISR0__I2SSP_RXDA__SHIFT 0x0 -+#define ACP_I2SSP_ISR0__I2SSP_RXFO_MASK 0x2 -+#define ACP_I2SSP_ISR0__I2SSP_RXFO__SHIFT 0x1 -+#define ACP_I2SSP_ISR0__I2SSP_TXFE_MASK 0x10 -+#define ACP_I2SSP_ISR0__I2SSP_TXFE__SHIFT 0x4 -+#define ACP_I2SSP_ISR0__I2SSP_TXFO_MASK 0x20 -+#define ACP_I2SSP_ISR0__I2SSP_TXFO__SHIFT 0x5 -+#define ACP_I2SSP_IMR0__I2SSP_RXDAM_MASK 0x1 -+#define ACP_I2SSP_IMR0__I2SSP_RXDAM__SHIFT 0x0 -+#define ACP_I2SSP_IMR0__I2SSP_RXFOM_MASK 0x2 -+#define ACP_I2SSP_IMR0__I2SSP_RXFOM__SHIFT 0x1 -+#define ACP_I2SSP_IMR0__I2SSP_TXFEM_MASK 0x10 -+#define ACP_I2SSP_IMR0__I2SSP_TXFEM__SHIFT 0x4 -+#define ACP_I2SSP_IMR0__I2SSP_TXFOM_MASK 0x20 -+#define ACP_I2SSP_IMR0__I2SSP_TXFOM__SHIFT 0x5 -+#define ACP_I2SSP_ROR0__I2SSP_RXCHO_MASK 0x1 -+#define ACP_I2SSP_ROR0__I2SSP_RXCHO__SHIFT 0x0 -+#define ACP_I2SSP_TOR0__I2SSP_TXCHO_MASK 0x1 -+#define ACP_I2SSP_TOR0__I2SSP_TXCHO__SHIFT 0x0 -+#define ACP_I2SSP_RFCR0__I2SSP_RXCHDT_MASK 0xf -+#define ACP_I2SSP_RFCR0__I2SSP_RXCHDT__SHIFT 0x0 -+#define ACP_I2SSP_TFCR0__I2SSP_TXCHET_MASK 0xf -+#define ACP_I2SSP_TFCR0__I2SSP_TXCHET__SHIFT 0x0 -+#define ACP_I2SSP_RFF0__I2SSP_RXCHFR_MASK 0x1 -+#define ACP_I2SSP_RFF0__I2SSP_RXCHFR__SHIFT 0x0 -+#define ACP_I2SSP_TFF0__I2SSP_TXCHFR_MASK 0x1 -+#define ACP_I2SSP_TFF0__I2SSP_TXCHFR__SHIFT 0x0 -+#define ACP_I2SSP_RXDMA__I2SSP_RXDMA_MASK 0xffffffff -+#define ACP_I2SSP_RXDMA__I2SSP_RXDMA__SHIFT 0x0 -+#define ACP_I2SSP_RRXDMA__I2SSP_RRXDMA_MASK 0x1 -+#define ACP_I2SSP_RRXDMA__I2SSP_RRXDMA__SHIFT 0x0 -+#define ACP_I2SSP_TXDMA__I2SSP_TXDMA_MASK 0xffffffff -+#define ACP_I2SSP_TXDMA__I2SSP_TXDMA__SHIFT 0x0 -+#define ACP_I2SSP_RTXDMA__I2SSP_RTXDMA_MASK 0x1 -+#define ACP_I2SSP_RTXDMA__I2SSP_RTXDMA__SHIFT 0x0 -+#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0_MASK 0x7 -+#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0__SHIFT 0x0 -+#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1_MASK 0x38 -+#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1__SHIFT 0x3 -+#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2_MASK 0x380 -+#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2__SHIFT 0x7 -+#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3_MASK 0x1c00 -+#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3__SHIFT 0xa -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH_MASK 0x3 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH__SHIFT 0x0 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL_MASK 0xc -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL__SHIFT 0x2 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN_MASK 0x10 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN__SHIFT 0x4 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK_MASK 0x20 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK__SHIFT 0x5 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK_MASK 0x40 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK__SHIFT 0x6 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES_MASK 0x180 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES__SHIFT 0x7 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES_MASK 0x600 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES__SHIFT 0x9 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0_MASK 0x70000 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0__SHIFT 0x10 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1_MASK 0x380000 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1__SHIFT 0x13 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2_MASK 0x1c00000 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2__SHIFT 0x16 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3_MASK 0xe000000 -+#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3__SHIFT 0x19 -+#define ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH_MASK 0xffffffff -+#define ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH__SHIFT 0x0 -+#define ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE_MASK 0xffffffff -+#define ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE__SHIFT 0x0 -+#define ACP_I2SMICSP_IER__I2SMICSP_IEN_MASK 0x1 -+#define ACP_I2SMICSP_IER__I2SMICSP_IEN__SHIFT 0x0 -+#define ACP_I2SMICSP_IRER__I2SMICSP_RXEN_MASK 0x1 -+#define ACP_I2SMICSP_IRER__I2SMICSP_RXEN__SHIFT 0x0 -+#define ACP_I2SMICSP_ITER__I2SMICSP_TXEN_MASK 0x1 -+#define ACP_I2SMICSP_ITER__I2SMICSP_TXEN__SHIFT 0x0 -+#define ACP_I2SMICSP_CER__I2SMICSP_CLKEN_MASK 0x1 -+#define ACP_I2SMICSP_CER__I2SMICSP_CLKEN__SHIFT 0x0 -+#define ACP_I2SMICSP_CCR__I2SMICSP_SCLKG_MASK 0x7 -+#define ACP_I2SMICSP_CCR__I2SMICSP_SCLKG__SHIFT 0x0 -+#define ACP_I2SMICSP_CCR__I2SMICSP_WSS_MASK 0x18 -+#define ACP_I2SMICSP_CCR__I2SMICSP_WSS__SHIFT 0x3 -+#define ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR_MASK 0x1 -+#define ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR__SHIFT 0x0 -+#define ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR_MASK 0x1 -+#define ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR__SHIFT 0x0 -+#define ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0_MASK 0xffffffff -+#define ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0__SHIFT 0x0 -+#define ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0_MASK 0xffffffff -+#define ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0__SHIFT 0x0 -+#define ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0_MASK 0x1 -+#define ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0__SHIFT 0x0 -+#define ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0_MASK 0x1 -+#define ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0__SHIFT 0x0 -+#define ACP_I2SMICSP_RCR0__I2SMICSP_WLEN_MASK 0x7 -+#define ACP_I2SMICSP_RCR0__I2SMICSP_WLEN__SHIFT 0x0 -+#define ACP_I2SMICSP_TCR0__I2SMICSP_WLEN_MASK 0x7 -+#define ACP_I2SMICSP_TCR0__I2SMICSP_WLEN__SHIFT 0x0 -+#define ACP_I2SMICSP_ISR0__I2SMICSP_RXDA_MASK 0x1 -+#define ACP_I2SMICSP_ISR0__I2SMICSP_RXDA__SHIFT 0x0 -+#define ACP_I2SMICSP_ISR0__I2SMICSP_RXFO_MASK 0x2 -+#define ACP_I2SMICSP_ISR0__I2SMICSP_RXFO__SHIFT 0x1 -+#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFE_MASK 0x10 -+#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFE__SHIFT 0x4 -+#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFO_MASK 0x20 -+#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFO__SHIFT 0x5 -+#define ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM_MASK 0x1 -+#define ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM__SHIFT 0x0 -+#define ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM_MASK 0x2 -+#define ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM__SHIFT 0x1 -+#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM_MASK 0x10 -+#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM__SHIFT 0x4 -+#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM_MASK 0x20 -+#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM__SHIFT 0x5 -+#define ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO_MASK 0x1 -+#define ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO__SHIFT 0x0 -+#define ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO_MASK 0x1 -+#define ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO__SHIFT 0x0 -+#define ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT_MASK 0xf -+#define ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT__SHIFT 0x0 -+#define ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET_MASK 0xf -+#define ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET__SHIFT 0x0 -+#define ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR_MASK 0x1 -+#define ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR__SHIFT 0x0 -+#define ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR_MASK 0x1 -+#define ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR__SHIFT 0x0 -+#define ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1_MASK 0xffffffff -+#define ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1__SHIFT 0x0 -+#define ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1_MASK 0xffffffff -+#define ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1__SHIFT 0x0 -+#define ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1_MASK 0x1 -+#define ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1__SHIFT 0x0 -+#define ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1_MASK 0x1 -+#define ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1__SHIFT 0x0 -+#define ACP_I2SMICSP_RCR1__I2SMICSP_WLEN_MASK 0x7 -+#define ACP_I2SMICSP_RCR1__I2SMICSP_WLEN__SHIFT 0x0 -+#define ACP_I2SMICSP_TCR1__I2SMICSP_WLEN_MASK 0x7 -+#define ACP_I2SMICSP_TCR1__I2SMICSP_WLEN__SHIFT 0x0 -+#define ACP_I2SMICSP_ISR1__I2SMICSP_RXDA_MASK 0x1 -+#define ACP_I2SMICSP_ISR1__I2SMICSP_RXDA__SHIFT 0x0 -+#define ACP_I2SMICSP_ISR1__I2SMICSP_RXFO_MASK 0x2 -+#define ACP_I2SMICSP_ISR1__I2SMICSP_RXFO__SHIFT 0x1 -+#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFE_MASK 0x10 -+#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFE__SHIFT 0x4 -+#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFO_MASK 0x20 -+#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFO__SHIFT 0x5 -+#define ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK 0x1 -+#define ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM__SHIFT 0x0 -+#define ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK 0x2 -+#define ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM__SHIFT 0x1 -+#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM_MASK 0x10 -+#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM__SHIFT 0x4 -+#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM_MASK 0x20 -+#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM__SHIFT 0x5 -+#define ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO_MASK 0x1 -+#define ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO__SHIFT 0x0 -+#define ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO_MASK 0x1 -+#define ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO__SHIFT 0x0 -+#define ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT_MASK 0xf -+#define ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT__SHIFT 0x0 -+#define ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET_MASK 0xf -+#define ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET__SHIFT 0x0 -+#define ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR_MASK 0x1 -+#define ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR__SHIFT 0x0 -+#define ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR_MASK 0x1 -+#define ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR__SHIFT 0x0 -+#define ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA_MASK 0xffffffff -+#define ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA__SHIFT 0x0 -+#define ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA_MASK 0x1 -+#define ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA__SHIFT 0x0 -+#define ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA_MASK 0xffffffff -+#define ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA__SHIFT 0x0 -+#define ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA_MASK 0x1 -+#define ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA__SHIFT 0x0 -+#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0_MASK 0x7 -+#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0__SHIFT 0x0 -+#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1_MASK 0x38 -+#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1__SHIFT 0x3 -+#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2_MASK 0x380 -+#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2__SHIFT 0x7 -+#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3_MASK 0x1c00 -+#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3__SHIFT 0xa -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH_MASK 0x3 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH__SHIFT 0x0 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL_MASK 0xc -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL__SHIFT 0x2 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN_MASK 0x10 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN__SHIFT 0x4 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK_MASK 0x20 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK__SHIFT 0x5 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK_MASK 0x40 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK__SHIFT 0x6 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES_MASK 0x180 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES__SHIFT 0x7 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES_MASK 0x600 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES__SHIFT 0x9 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0_MASK 0x70000 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0__SHIFT 0x10 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1_MASK 0x380000 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1__SHIFT 0x13 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2_MASK 0x1c00000 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2__SHIFT 0x16 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3_MASK 0xe000000 -+#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3__SHIFT 0x19 -+#define ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH_MASK 0xffffffff -+#define ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH__SHIFT 0x0 -+#define ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE_MASK 0xffffffff -+#define ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE__SHIFT 0x0 -+#define ACP_I2SBT_IER__I2SBT_IEN_MASK 0x1 -+#define ACP_I2SBT_IER__I2SBT_IEN__SHIFT 0x0 -+#define ACP_I2SBT_IRER__I2SBT_RXEN_MASK 0x1 -+#define ACP_I2SBT_IRER__I2SBT_RXEN__SHIFT 0x0 -+#define ACP_I2SBT_ITER__I2SBT_TXEN_MASK 0x1 -+#define ACP_I2SBT_ITER__I2SBT_TXEN__SHIFT 0x0 -+#define ACP_I2SBT_CER__I2SBT_CLKEN_MASK 0x1 -+#define ACP_I2SBT_CER__I2SBT_CLKEN__SHIFT 0x0 -+#define ACP_I2SBT_CCR__I2SBT_SCLKG_MASK 0x7 -+#define ACP_I2SBT_CCR__I2SBT_SCLKG__SHIFT 0x0 -+#define ACP_I2SBT_CCR__I2SBT_WSS_MASK 0x18 -+#define ACP_I2SBT_CCR__I2SBT_WSS__SHIFT 0x3 -+#define ACP_I2SBT_RXFFR__I2SBT_RXFFR_MASK 0x1 -+#define ACP_I2SBT_RXFFR__I2SBT_RXFFR__SHIFT 0x0 -+#define ACP_I2SBT_TXFFR__I2SBT_TXFFR_MASK 0x1 -+#define ACP_I2SBT_TXFFR__I2SBT_TXFFR__SHIFT 0x0 -+#define ACP_I2SBT_LRBR0__I2SBT_LRBR0_MASK 0xffffffff -+#define ACP_I2SBT_LRBR0__I2SBT_LRBR0__SHIFT 0x0 -+#define ACP_I2SBT_RRBR0__I2SBT_RRBR0_MASK 0xffffffff -+#define ACP_I2SBT_RRBR0__I2SBT_RRBR0__SHIFT 0x0 -+#define ACP_I2SBT_RER0__I2SBT_RXCHEN0_MASK 0x1 -+#define ACP_I2SBT_RER0__I2SBT_RXCHEN0__SHIFT 0x0 -+#define ACP_I2SBT_TER0__I2SBT_TXCHEN0_MASK 0x1 -+#define ACP_I2SBT_TER0__I2SBT_TXCHEN0__SHIFT 0x0 -+#define ACP_I2SBT_RCR0__I2SBT_WLEN_MASK 0x7 -+#define ACP_I2SBT_RCR0__I2SBT_WLEN__SHIFT 0x0 -+#define ACP_I2SBT_TCR0__I2SBT_WLEN_MASK 0x7 -+#define ACP_I2SBT_TCR0__I2SBT_WLEN__SHIFT 0x0 -+#define ACP_I2SBT_ISR0__I2SBT_RXDA_MASK 0x1 -+#define ACP_I2SBT_ISR0__I2SBT_RXDA__SHIFT 0x0 -+#define ACP_I2SBT_ISR0__I2SBT_RXFO_MASK 0x2 -+#define ACP_I2SBT_ISR0__I2SBT_RXFO__SHIFT 0x1 -+#define ACP_I2SBT_ISR0__I2SBT_TXFE_MASK 0x10 -+#define ACP_I2SBT_ISR0__I2SBT_TXFE__SHIFT 0x4 -+#define ACP_I2SBT_ISR0__I2SBT_TXFO_MASK 0x20 -+#define ACP_I2SBT_ISR0__I2SBT_TXFO__SHIFT 0x5 -+#define ACP_I2SBT_IMR0__I2SBT_RXDAM_MASK 0x1 -+#define ACP_I2SBT_IMR0__I2SBT_RXDAM__SHIFT 0x0 -+#define ACP_I2SBT_IMR0__I2SBT_RXFOM_MASK 0x2 -+#define ACP_I2SBT_IMR0__I2SBT_RXFOM__SHIFT 0x1 -+#define ACP_I2SBT_IMR0__I2SBT_TXFEM_MASK 0x10 -+#define ACP_I2SBT_IMR0__I2SBT_TXFEM__SHIFT 0x4 -+#define ACP_I2SBT_IMR0__I2SBT_TXFOM_MASK 0x20 -+#define ACP_I2SBT_IMR0__I2SBT_TXFOM__SHIFT 0x5 -+#define ACP_I2SBT_ROR0__I2SBT_RXCHO_MASK 0x1 -+#define ACP_I2SBT_ROR0__I2SBT_RXCHO__SHIFT 0x0 -+#define ACP_I2SBT_TOR0__I2SBT_TXCHO_MASK 0x1 -+#define ACP_I2SBT_TOR0__I2SBT_TXCHO__SHIFT 0x0 -+#define ACP_I2SBT_RFCR0__I2SBT_RXCHDT_MASK 0xf -+#define ACP_I2SBT_RFCR0__I2SBT_RXCHDT__SHIFT 0x0 -+#define ACP_I2SBT_TFCR0__I2SBT_TXCHET_MASK 0xf -+#define ACP_I2SBT_TFCR0__I2SBT_TXCHET__SHIFT 0x0 -+#define ACP_I2SBT_RFF0__I2SBT_RXCHFR_MASK 0x1 -+#define ACP_I2SBT_RFF0__I2SBT_RXCHFR__SHIFT 0x0 -+#define ACP_I2SBT_TFF0__I2SBT_TXCHFR_MASK 0x1 -+#define ACP_I2SBT_TFF0__I2SBT_TXCHFR__SHIFT 0x0 -+#define ACP_I2SBT_LRBR1__I2SBT_LRBR1_MASK 0xffffffff -+#define ACP_I2SBT_LRBR1__I2SBT_LRBR1__SHIFT 0x0 -+#define ACP_I2SBT_RRBR1__I2SBT_RRBR1_MASK 0xffffffff -+#define ACP_I2SBT_RRBR1__I2SBT_RRBR1__SHIFT 0x0 -+#define ACP_I2SBT_RER1__I2SBT_RXCHEN1_MASK 0x1 -+#define ACP_I2SBT_RER1__I2SBT_RXCHEN1__SHIFT 0x0 -+#define ACP_I2SBT_TER1__I2SBT_TXCHEN1_MASK 0x1 -+#define ACP_I2SBT_TER1__I2SBT_TXCHEN1__SHIFT 0x0 -+#define ACP_I2SBT_RCR1__I2SBT_WLEN_MASK 0x7 -+#define ACP_I2SBT_RCR1__I2SBT_WLEN__SHIFT 0x0 -+#define ACP_I2SBT_TCR1__I2SBT_WLEN_MASK 0x7 -+#define ACP_I2SBT_TCR1__I2SBT_WLEN__SHIFT 0x0 -+#define ACP_I2SBT_ISR1__I2SBT_RXDA_MASK 0x1 -+#define ACP_I2SBT_ISR1__I2SBT_RXDA__SHIFT 0x0 -+#define ACP_I2SBT_ISR1__I2SBT_RXFO_MASK 0x2 -+#define ACP_I2SBT_ISR1__I2SBT_RXFO__SHIFT 0x1 -+#define ACP_I2SBT_ISR1__I2SBT_TXFE_MASK 0x10 -+#define ACP_I2SBT_ISR1__I2SBT_TXFE__SHIFT 0x4 -+#define ACP_I2SBT_ISR1__I2SBT_TXFO_MASK 0x20 -+#define ACP_I2SBT_ISR1__I2SBT_TXFO__SHIFT 0x5 -+#define ACP_I2SBT_IMR1__I2SBT_RXDAM_MASK 0x1 -+#define ACP_I2SBT_IMR1__I2SBT_RXDAM__SHIFT 0x0 -+#define ACP_I2SBT_IMR1__I2SBT_RXFOM_MASK 0x2 -+#define ACP_I2SBT_IMR1__I2SBT_RXFOM__SHIFT 0x1 -+#define ACP_I2SBT_IMR1__I2SBT_TXFEM_MASK 0x10 -+#define ACP_I2SBT_IMR1__I2SBT_TXFEM__SHIFT 0x4 -+#define ACP_I2SBT_IMR1__I2SBT_TXFOM_MASK 0x20 -+#define ACP_I2SBT_IMR1__I2SBT_TXFOM__SHIFT 0x5 -+#define ACP_I2SBT_ROR1__I2SBT_RXCHO_MASK 0x1 -+#define ACP_I2SBT_ROR1__I2SBT_RXCHO__SHIFT 0x0 -+#define ACP_I2SBT_TOR1__I2SBT_TXCHO_MASK 0x1 -+#define ACP_I2SBT_TOR1__I2SBT_TXCHO__SHIFT 0x0 -+#define ACP_I2SBT_RFCR1__I2SBT_RXCHDT_MASK 0xf -+#define ACP_I2SBT_RFCR1__I2SBT_RXCHDT__SHIFT 0x0 -+#define ACP_I2SBT_TFCR1__I2SBT_TXCHET_MASK 0xf -+#define ACP_I2SBT_TFCR1__I2SBT_TXCHET__SHIFT 0x0 -+#define ACP_I2SBT_RFF1__I2SBT_RXCHFR_MASK 0x1 -+#define ACP_I2SBT_RFF1__I2SBT_RXCHFR__SHIFT 0x0 -+#define ACP_I2SBT_TFF1__I2SBT_TXCHFR_MASK 0x1 -+#define ACP_I2SBT_TFF1__I2SBT_TXCHFR__SHIFT 0x0 -+#define ACP_I2SBT_RXDMA__I2SBT_RXDMA_MASK 0xffffffff -+#define ACP_I2SBT_RXDMA__I2SBT_RXDMA__SHIFT 0x0 -+#define ACP_I2SBT_RRXDMA__I2SBT_RRXDMA_MASK 0x1 -+#define ACP_I2SBT_RRXDMA__I2SBT_RRXDMA__SHIFT 0x0 -+#define ACP_I2SBT_TXDMA__I2SBT_TXDMA_MASK 0xffffffff -+#define ACP_I2SBT_TXDMA__I2SBT_TXDMA__SHIFT 0x0 -+#define ACP_I2SBT_RTXDMA__I2SBT_RTXDMA_MASK 0x1 -+#define ACP_I2SBT_RTXDMA__I2SBT_RTXDMA__SHIFT 0x0 -+#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0_MASK 0x7 -+#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0__SHIFT 0x0 -+#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1_MASK 0x38 -+#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1__SHIFT 0x3 -+#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2_MASK 0x380 -+#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2__SHIFT 0x7 -+#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3_MASK 0x1c00 -+#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3__SHIFT 0xa -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH_MASK 0x3 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH__SHIFT 0x0 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL_MASK 0xc -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL__SHIFT 0x2 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN_MASK 0x10 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN__SHIFT 0x4 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK_MASK 0x20 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK__SHIFT 0x5 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK_MASK 0x40 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK__SHIFT 0x6 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES_MASK 0x180 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES__SHIFT 0x7 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES_MASK 0x600 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES__SHIFT 0x9 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0_MASK 0x70000 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0__SHIFT 0x10 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1_MASK 0x380000 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1__SHIFT 0x13 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2_MASK 0x1c00000 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2__SHIFT 0x16 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3_MASK 0xe000000 -+#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3__SHIFT 0x19 -+#define ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH_MASK 0xffffffff -+#define ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH__SHIFT 0x0 -+#define ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE_MASK 0xffffffff -+#define ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE__SHIFT 0x0 -+ -+#endif /* ACP_2_2_SH_MASK_H */ --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1127-ASoC-AMD-add-AMD-ASoC-ACP-2.x-DMA-driver.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1127-ASoC-AMD-add-AMD-ASoC-ACP-2.x-DMA-driver.patch deleted file mode 100644 index 6ad546e3..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1127-ASoC-AMD-add-AMD-ASoC-ACP-2.x-DMA-driver.patch +++ /dev/null @@ -1,1092 +0,0 @@ -From e3a10e5c1dd68d0a0133023084f15aa05662090c Mon Sep 17 00:00:00 2001 -From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> -Date: Tue, 24 Nov 2015 11:54:50 +0530 -Subject: [PATCH 02/17] ASoC: AMD: add AMD ASoC ACP 2.x DMA driver - -ACP IP has internal DMA controller with multiple channels which -can be programmed in cyclic/non cyclic manner. ACP can generate -interrupt upon completion of DMA transfer, if required. -The PCM driver provides the platform DMA component to ALSA core. - -Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Reviewed-by: Murali Krishna Vemuri <murali-krishna.vemuri@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> ---- - sound/soc/amd/Kconfig | 4 + - sound/soc/amd/Makefile | 3 + - sound/soc/amd/acp-pcm-dma.c | 914 ++++++++++++++++++++++++++++++++++++++++++++ - sound/soc/amd/acp.h | 118 ++++++ - 4 files changed, 1039 insertions(+) - create mode 100644 sound/soc/amd/Kconfig - create mode 100644 sound/soc/amd/Makefile - create mode 100644 sound/soc/amd/acp-pcm-dma.c - create mode 100644 sound/soc/amd/acp.h - -diff --git a/sound/soc/amd/Kconfig b/sound/soc/amd/Kconfig -new file mode 100644 -index 0000000..78187eb ---- /dev/null -+++ b/sound/soc/amd/Kconfig -@@ -0,0 +1,4 @@ -+config SND_SOC_AMD_ACP -+ tristate "AMD Audio Coprocessor support" -+ help -+ This option enables ACP DMA support on AMD platform. -diff --git a/sound/soc/amd/Makefile b/sound/soc/amd/Makefile -new file mode 100644 -index 0000000..1a66ec0 ---- /dev/null -+++ b/sound/soc/amd/Makefile -@@ -0,0 +1,3 @@ -+snd-soc-acp-pcm-objs := acp-pcm-dma.o -+ -+obj-$(CONFIG_SND_SOC_AMD_ACP) += snd-soc-acp-pcm.o -diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c -new file mode 100644 -index 0000000..0724d78 ---- /dev/null -+++ b/sound/soc/amd/acp-pcm-dma.c -@@ -0,0 +1,914 @@ -+/* -+ * AMD ALSA SoC PCM Driver for ACP 2.x -+ * -+ * Copyright 2014-2015 Advanced Micro Devices, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ */ -+ -+#include <linux/module.h> -+#include <linux/delay.h> -+#include <linux/sizes.h> -+ -+#include <sound/soc.h> -+ -+#include "acp.h" -+ -+#define PLAYBACK_MIN_NUM_PERIODS 2 -+#define PLAYBACK_MAX_NUM_PERIODS 2 -+#define PLAYBACK_MAX_PERIOD_SIZE 16384 -+#define PLAYBACK_MIN_PERIOD_SIZE 1024 -+#define CAPTURE_MIN_NUM_PERIODS 2 -+#define CAPTURE_MAX_NUM_PERIODS 2 -+#define CAPTURE_MAX_PERIOD_SIZE 16384 -+#define CAPTURE_MIN_PERIOD_SIZE 1024 -+ -+#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) -+#define MIN_BUFFER MAX_BUFFER -+ -+static const struct snd_pcm_hardware acp_pcm_hardware_playback = { -+ .info = SNDRV_PCM_INFO_INTERLEAVED | -+ SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | -+ SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | -+ SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE | -+ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, -+ .channels_min = 1, -+ .channels_max = 8, -+ .rates = SNDRV_PCM_RATE_8000_96000, -+ .rate_min = 8000, -+ .rate_max = 96000, -+ .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, -+ .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, -+ .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, -+ .periods_min = PLAYBACK_MIN_NUM_PERIODS, -+ .periods_max = PLAYBACK_MAX_NUM_PERIODS, -+}; -+ -+static const struct snd_pcm_hardware acp_pcm_hardware_capture = { -+ .info = SNDRV_PCM_INFO_INTERLEAVED | -+ SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | -+ SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | -+ SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE | -+ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, -+ .channels_min = 1, -+ .channels_max = 2, -+ .rates = SNDRV_PCM_RATE_8000_48000, -+ .rate_min = 8000, -+ .rate_max = 48000, -+ .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, -+ .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, -+ .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, -+ .periods_min = CAPTURE_MIN_NUM_PERIODS, -+ .periods_max = CAPTURE_MAX_NUM_PERIODS, -+}; -+ -+struct audio_drv_data { -+ struct snd_pcm_substream *play_stream; -+ struct snd_pcm_substream *capture_stream; -+ void __iomem *acp_mmio; -+}; -+ -+static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) -+{ -+ return readl(acp_mmio + (reg * 4)); -+} -+ -+static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) -+{ -+ writel(val, acp_mmio + (reg * 4)); -+} -+ -+/* Configure a given dma channel parameters - enable/disble, -+ * number of descriptors, priority -+ */ -+static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, -+ u16 dscr_strt_idx, u16 num_dscrs, -+ enum acp_dma_priority_level priority_level) -+{ -+ u32 dma_ctrl; -+ -+ /* disable the channel run field */ -+ dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); -+ dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; -+ acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); -+ -+ /* program a DMA channel with first descriptor to be processed. */ -+ acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK -+ & dscr_strt_idx), -+ acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num); -+ -+ /* program a DMA channel with the number of descriptors to be -+ * processed in the transfer -+ */ -+ acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs, -+ acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num); -+ -+ /* set DMA channel priority */ -+ acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); -+} -+ -+/* Initialize a dma descriptor in SRAM based on descritor information passed */ -+static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, -+ u16 descr_idx, -+ acp_dma_dscr_transfer_t *descr_info) -+{ -+ u32 sram_offset; -+ -+ sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t)); -+ -+ /* program the source base address. */ -+ acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); -+ acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data); -+ /* program the destination base address. */ -+ acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); -+ acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data); -+ -+ /* program the number of bytes to be transferred for this descriptor. */ -+ acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); -+ acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); -+} -+ -+/* Initialize the DMA descriptor information for transfer between -+ * system memory <-> ACP SRAM -+ */ -+static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, -+ u32 size, int direction, -+ u32 pte_offset) -+{ -+ u16 i; -+ u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; -+ acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; -+ -+ for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { -+ dmadscr[i].xfer_val = 0; -+ if (direction == SNDRV_PCM_STREAM_PLAYBACK) { -+ dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12 + i; -+ dmadscr[i].dest = ACP_SHARED_RAM_BANK_1_ADDRESS + -+ (size / 2) - (i * (size/2)); -+ dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS -+ + (pte_offset * SZ_4K) + (i * (size/2)); -+ dmadscr[i].xfer_val |= -+ (ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM << 16) | -+ (size / 2); -+ } else { -+ dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14 + i; -+ dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS + -+ (i * (size/2)); -+ dmadscr[i].dest = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS -+ + (pte_offset * SZ_4K) + -+ (i * (size/2)); -+ dmadscr[i].xfer_val |= -+ BIT(22) | -+ (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) | -+ (size / 2); -+ } -+ config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, -+ &dmadscr[i]); -+ } -+ if (direction == SNDRV_PCM_STREAM_PLAYBACK) -+ config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, -+ PLAYBACK_START_DMA_DESCR_CH12, -+ NUM_DSCRS_PER_CHANNEL, -+ ACP_DMA_PRIORITY_LEVEL_NORMAL); -+ else -+ config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, -+ CAPTURE_START_DMA_DESCR_CH14, -+ NUM_DSCRS_PER_CHANNEL, -+ ACP_DMA_PRIORITY_LEVEL_NORMAL); -+} -+ -+/* Initialize the DMA descriptor information for transfer between -+ * ACP SRAM <-> I2S -+ */ -+static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, -+ u32 size, int direction) -+{ -+ -+ u16 i; -+ u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13; -+ acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; -+ -+ for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { -+ dmadscr[i].xfer_val = 0; -+ if (direction == SNDRV_PCM_STREAM_PLAYBACK) { -+ dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13 + i; -+ dmadscr[i].src = ACP_SHARED_RAM_BANK_1_ADDRESS + -+ (i * (size/2)); -+ /* dmadscr[i].dest is unused by hardware. */ -+ dmadscr[i].dest = 0; -+ dmadscr[i].xfer_val |= BIT(22) | (TO_ACP_I2S_1 << 16) | -+ (size / 2); -+ } else { -+ dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15 + i; -+ /* dmadscr[i].src is unused by hardware. */ -+ dmadscr[i].src = 0; -+ dmadscr[i].dest = ACP_SHARED_RAM_BANK_5_ADDRESS + -+ (i * (size / 2)); -+ dmadscr[i].xfer_val |= BIT(22) | -+ (FROM_ACP_I2S_1 << 16) | (size / 2); -+ } -+ config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, -+ &dmadscr[i]); -+ } -+ /* Configure the DMA channel with the above descriptore */ -+ if (direction == SNDRV_PCM_STREAM_PLAYBACK) -+ config_acp_dma_channel(acp_mmio, ACP_TO_I2S_DMA_CH_NUM, -+ PLAYBACK_START_DMA_DESCR_CH13, -+ NUM_DSCRS_PER_CHANNEL, -+ ACP_DMA_PRIORITY_LEVEL_NORMAL); -+ else -+ config_acp_dma_channel(acp_mmio, I2S_TO_ACP_DMA_CH_NUM, -+ CAPTURE_START_DMA_DESCR_CH15, -+ NUM_DSCRS_PER_CHANNEL, -+ ACP_DMA_PRIORITY_LEVEL_NORMAL); -+} -+ -+/* Create page table entries in ACP SRAM for the allocated memory */ -+static void acp_pte_config(void __iomem *acp_mmio, struct page *pg, -+ u16 num_of_pages, u32 pte_offset) -+{ -+ u16 page_idx; -+ u64 addr; -+ u32 low; -+ u32 high; -+ u32 offset; -+ -+ offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8); -+ for (page_idx = 0; page_idx < (num_of_pages); page_idx++) { -+ /* Load the low address of page int ACP SRAM through SRBM */ -+ acp_reg_write((offset + (page_idx * 8)), -+ acp_mmio, mmACP_SRBM_Targ_Idx_Addr); -+ addr = page_to_phys(pg); -+ -+ low = lower_32_bits(addr); -+ high = upper_32_bits(addr); -+ -+ acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data); -+ -+ /* Load the High address of page int ACP SRAM through SRBM */ -+ acp_reg_write((offset + (page_idx * 8) + 4), -+ acp_mmio, mmACP_SRBM_Targ_Idx_Addr); -+ -+ /* page enable in ACP */ -+ high |= BIT(31); -+ acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); -+ -+ /* Move to next physically contiguos page */ -+ pg++; -+ } -+} -+ -+static void config_acp_dma(void __iomem *acp_mmio, -+ struct audio_substream_data *audio_config) -+{ -+ u32 pte_offset; -+ -+ if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) -+ pte_offset = ACP_PLAYBACK_PTE_OFFSET; -+ else -+ pte_offset = ACP_CAPTURE_PTE_OFFSET; -+ -+ acp_pte_config(acp_mmio, audio_config->pg, audio_config->num_of_pages, -+ pte_offset); -+ -+ /* Configure System memory <-> ACP SRAM DMA descriptors */ -+ set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size, -+ audio_config->direction, pte_offset); -+ -+ /* Configure ACP SRAM <-> I2S DMA descriptors */ -+ set_acp_to_i2s_dma_descriptors(acp_mmio, audio_config->size, -+ audio_config->direction); -+} -+ -+/* Start a given DMA channel transfer */ -+static void acp_dma_start(void __iomem *acp_mmio, -+ u16 ch_num, bool is_circular) -+{ -+ u32 dma_ctrl; -+ -+ /* read the dma control register and disable the channel run field */ -+ dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); -+ -+ /* Invalidating the DAGB cache */ -+ acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL); -+ -+ /* configure the DMA channel and start the DMA transfer -+ * set dmachrun bit to start the transfer and enable the -+ * interrupt on completion of the dma transfer -+ */ -+ dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK; -+ -+ switch (ch_num) { -+ case ACP_TO_I2S_DMA_CH_NUM: -+ case ACP_TO_SYSRAM_CH_NUM: -+ case I2S_TO_ACP_DMA_CH_NUM: -+ dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; -+ break; -+ default: -+ dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; -+ break; -+ } -+ -+ /* enable for ACP SRAM to/from I2S DMA channel */ -+ if (is_circular == true) -+ dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK; -+ else -+ dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK; -+ -+ acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); -+} -+ -+/* Stop a given DMA channel transfer */ -+static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) -+{ -+ u32 dma_ctrl; -+ u32 dma_ch_sts; -+ u32 count = ACP_DMA_RESET_TIME; -+ -+ dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); -+ -+ /* clear the dma control register fields before writing zero -+ * in reset bit -+ */ -+ dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; -+ dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; -+ -+ acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); -+ dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); -+ -+ if (dma_ch_sts & BIT(ch_num)) { -+ /* set the reset bit for this channel to stop the dma -+ * transfer -+ */ -+ dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK; -+ acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); -+ } -+ -+ /* check the channel status bit for some time and return the status */ -+ while (true) { -+ dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); -+ if (!(dma_ch_sts & BIT(ch_num))) { -+ /* clear the reset flag after successfully stopping -+ * the dma transfer and break from the loop -+ */ -+ dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; -+ -+ acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 -+ + ch_num); -+ break; -+ } -+ if (--count == 0) { -+ pr_err("Failed to stop ACP DMA channel : %d\n", ch_num); -+ return -ETIMEDOUT; -+ } -+ udelay(100); -+ } -+ return 0; -+} -+ -+/* Initialize and bring ACP hardware to default state. */ -+static int acp_init(void __iomem *acp_mmio) -+{ -+ u32 val, count, sram_pte_offset; -+ -+ /* Assert Soft reset of ACP */ -+ val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); -+ -+ val |= ACP_SOFT_RESET__SoftResetAud_MASK; -+ acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); -+ -+ count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; -+ while (true) { -+ val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); -+ if (ACP_SOFT_RESET__SoftResetAudDone_MASK == -+ (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) -+ break; -+ if (--count == 0) { -+ pr_err("Failed to reset ACP\n"); -+ return -ETIMEDOUT; -+ } -+ udelay(100); -+ } -+ -+ /* Enable clock to ACP and wait until the clock is enabled */ -+ val = acp_reg_read(acp_mmio, mmACP_CONTROL); -+ val = val | ACP_CONTROL__ClkEn_MASK; -+ acp_reg_write(val, acp_mmio, mmACP_CONTROL); -+ -+ count = ACP_CLOCK_EN_TIME_OUT_VALUE; -+ -+ while (true) { -+ val = acp_reg_read(acp_mmio, mmACP_STATUS); -+ if (val & (u32) 0x1) -+ break; -+ if (--count == 0) { -+ pr_err("Failed to reset ACP\n"); -+ return -ETIMEDOUT; -+ } -+ udelay(100); -+ } -+ -+ /* Deassert the SOFT RESET flags */ -+ val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); -+ val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; -+ acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); -+ -+ /* initiailize Onion control DAGB register */ -+ acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, -+ mmACP_AXI2DAGB_ONION_CNTL); -+ -+ /* initiailize Garlic control DAGB registers */ -+ acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, -+ mmACP_AXI2DAGB_GARLIC_CNTL); -+ -+ sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS | -+ ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK | -+ ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK | -+ ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK; -+ acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1); -+ acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio, -+ mmACP_DAGB_PAGE_SIZE_GRP_1); -+ -+ acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, -+ mmACP_DMA_DESC_BASE_ADDR); -+ -+ /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */ -+ acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); -+ acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, -+ acp_mmio, mmACP_EXTERNAL_INTR_CNTL); -+ -+ return 0; -+} -+ -+/* Deintialize ACP */ -+static int acp_deinit(void __iomem *acp_mmio) -+{ -+ u32 val; -+ u32 count; -+ -+ /* Assert Soft reset of ACP */ -+ val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); -+ -+ val |= ACP_SOFT_RESET__SoftResetAud_MASK; -+ acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); -+ -+ count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; -+ while (true) { -+ val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); -+ if (ACP_SOFT_RESET__SoftResetAudDone_MASK == -+ (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) -+ break; -+ if (--count == 0) { -+ pr_err("Failed to reset ACP\n"); -+ return -ETIMEDOUT; -+ } -+ udelay(100); -+ } -+ /** Disable ACP clock */ -+ val = acp_reg_read(acp_mmio, mmACP_CONTROL); -+ val &= ~ACP_CONTROL__ClkEn_MASK; -+ acp_reg_write(val, acp_mmio, mmACP_CONTROL); -+ -+ count = ACP_CLOCK_EN_TIME_OUT_VALUE; -+ -+ while (true) { -+ val = acp_reg_read(acp_mmio, mmACP_STATUS); -+ if (!(val & (u32) 0x1)) -+ break; -+ if (--count == 0) { -+ pr_err("Failed to reset ACP\n"); -+ return -ETIMEDOUT; -+ } -+ udelay(100); -+ } -+ return 0; -+} -+ -+/* ACP DMA irq handler routine for playback, capture usecases */ -+static irqreturn_t dma_irq_handler(int irq, void *arg) -+{ -+ u16 dscr_idx; -+ u32 intr_flag, ext_intr_status; -+ struct audio_drv_data *irq_data; -+ void __iomem *acp_mmio; -+ struct device *dev = arg; -+ bool valid_irq = false; -+ -+ irq_data = dev_get_drvdata(dev); -+ acp_mmio = irq_data->acp_mmio; -+ -+ ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT); -+ intr_flag = (((ext_intr_status & -+ ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >> -+ ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT)); -+ -+ if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { -+ valid_irq = true; -+ if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_13) == -+ PLAYBACK_START_DMA_DESCR_CH13) -+ dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; -+ else -+ dscr_idx = PLAYBACK_END_DMA_DESCR_CH12; -+ config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, dscr_idx, -+ 1, 0); -+ acp_dma_start(acp_mmio, SYSRAM_TO_ACP_CH_NUM, false); -+ -+ snd_pcm_period_elapsed(irq_data->play_stream); -+ -+ acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, -+ acp_mmio, mmACP_EXTERNAL_INTR_STAT); -+ } -+ -+ if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { -+ valid_irq = true; -+ if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_15) == -+ CAPTURE_START_DMA_DESCR_CH15) -+ dscr_idx = CAPTURE_END_DMA_DESCR_CH14; -+ else -+ dscr_idx = CAPTURE_START_DMA_DESCR_CH14; -+ config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx, -+ 1, 0); -+ acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false); -+ -+ acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16, -+ acp_mmio, mmACP_EXTERNAL_INTR_STAT); -+ } -+ -+ if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) { -+ valid_irq = true; -+ snd_pcm_period_elapsed(irq_data->capture_stream); -+ acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16, -+ acp_mmio, mmACP_EXTERNAL_INTR_STAT); -+ } -+ -+ if (valid_irq) -+ return IRQ_HANDLED; -+ else -+ return IRQ_NONE; -+} -+ -+static int acp_dma_open(struct snd_pcm_substream *substream) -+{ -+ int ret = 0; -+ struct snd_pcm_runtime *runtime = substream->runtime; -+ struct snd_soc_pcm_runtime *prtd = substream->private_data; -+ struct audio_drv_data *intr_data = dev_get_drvdata(prtd->platform->dev); -+ -+ struct audio_substream_data *adata = -+ kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); -+ if (adata == NULL) -+ return -ENOMEM; -+ -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) -+ runtime->hw = acp_pcm_hardware_playback; -+ else -+ runtime->hw = acp_pcm_hardware_capture; -+ -+ ret = snd_pcm_hw_constraint_integer(runtime, -+ SNDRV_PCM_HW_PARAM_PERIODS); -+ if (ret < 0) { -+ dev_err(prtd->platform->dev, "set integer constraint failed\n"); -+ return ret; -+ } -+ -+ adata->acp_mmio = intr_data->acp_mmio; -+ runtime->private_data = adata; -+ -+ /* Enable ACP irq, when neither playback or capture streams are -+ * active by the time when a new stream is being opened. -+ * This enablement is not required for another stream, if current -+ * stream is not closed -+ */ -+ if (!intr_data->play_stream && !intr_data->capture_stream) -+ acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); -+ -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) -+ intr_data->play_stream = substream; -+ else -+ intr_data->capture_stream = substream; -+ -+ return 0; -+} -+ -+static int acp_dma_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params) -+{ -+ int status; -+ uint64_t size; -+ struct snd_dma_buffer *dma_buffer; -+ struct page *pg; -+ struct snd_pcm_runtime *runtime; -+ struct audio_substream_data *rtd; -+ -+ dma_buffer = &substream->dma_buffer; -+ -+ runtime = substream->runtime; -+ rtd = runtime->private_data; -+ -+ if (WARN_ON(!rtd)) -+ return -EINVAL; -+ -+ size = params_buffer_bytes(params); -+ status = snd_pcm_lib_malloc_pages(substream, size); -+ if (status < 0) -+ return status; -+ -+ memset(substream->runtime->dma_area, 0, params_buffer_bytes(params)); -+ pg = virt_to_page(substream->dma_buffer.area); -+ -+ if (pg != NULL) { -+ /* Save for runtime private data */ -+ rtd->pg = pg; -+ rtd->order = get_order(size); -+ -+ /* Fill the page table entries in ACP SRAM */ -+ rtd->pg = pg; -+ rtd->size = size; -+ rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; -+ rtd->direction = substream->stream; -+ -+ config_acp_dma(rtd->acp_mmio, rtd); -+ status = 0; -+ } else { -+ status = -ENOMEM; -+ } -+ return status; -+} -+ -+static int acp_dma_hw_free(struct snd_pcm_substream *substream) -+{ -+ return snd_pcm_lib_free_pages(substream); -+} -+ -+static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream) -+{ -+ u16 dscr; -+ u32 mul, dma_config, period_bytes; -+ u32 pos = 0; -+ -+ struct snd_pcm_runtime *runtime = substream->runtime; -+ struct audio_substream_data *rtd = runtime->private_data; -+ -+ period_bytes = frames_to_bytes(runtime, runtime->period_size); -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { -+ dscr = acp_reg_read(rtd->acp_mmio, mmACP_DMA_CUR_DSCR_13); -+ -+ if (dscr == PLAYBACK_START_DMA_DESCR_CH13) -+ mul = 0; -+ else -+ mul = 1; -+ pos = (mul * period_bytes); -+ } else { -+ dma_config = acp_reg_read(rtd->acp_mmio, mmACP_DMA_CNTL_14); -+ if (dma_config != 0) { -+ dscr = acp_reg_read(rtd->acp_mmio, -+ mmACP_DMA_CUR_DSCR_14); -+ if (dscr == CAPTURE_START_DMA_DESCR_CH14) -+ mul = 1; -+ else -+ mul = 2; -+ pos = (mul * period_bytes); -+ } -+ -+ if (pos >= (2 * period_bytes)) -+ pos = 0; -+ -+ } -+ return bytes_to_frames(runtime, pos); -+} -+ -+static int acp_dma_mmap(struct snd_pcm_substream *substream, -+ struct vm_area_struct *vma) -+{ -+ return snd_pcm_lib_default_mmap(substream, vma); -+} -+ -+static int acp_dma_prepare(struct snd_pcm_substream *substream) -+{ -+ struct snd_pcm_runtime *runtime = substream->runtime; -+ struct audio_substream_data *rtd = runtime->private_data; -+ -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { -+ config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, -+ PLAYBACK_START_DMA_DESCR_CH12, -+ NUM_DSCRS_PER_CHANNEL, 0); -+ config_acp_dma_channel(rtd->acp_mmio, ACP_TO_I2S_DMA_CH_NUM, -+ PLAYBACK_START_DMA_DESCR_CH13, -+ NUM_DSCRS_PER_CHANNEL, 0); -+ /* Fill ACP SRAM (2 periods) with zeros from System RAM -+ * which is zero-ed in hw_params -+ */ -+ acp_dma_start(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, false); -+ -+ /* ACP SRAM (2 periods of buffer size) is intially filled with -+ * zeros. Before rendering starts, 2nd half of SRAM will be -+ * filled with valid audio data DMA'ed from first half of system -+ * RAM and 1st half of SRAM will be filled with Zeros. This is -+ * the initial scenario when redering starts from SRAM. Later -+ * on, 2nd half of system memory will be DMA'ed to 1st half of -+ * SRAM, 1st half of system memory will be DMA'ed to 2nd half of -+ * SRAM in ping-pong way till rendering stops. -+ */ -+ config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, -+ PLAYBACK_START_DMA_DESCR_CH12, -+ 1, 0); -+ } else { -+ config_acp_dma_channel(rtd->acp_mmio, ACP_TO_SYSRAM_CH_NUM, -+ CAPTURE_START_DMA_DESCR_CH14, -+ NUM_DSCRS_PER_CHANNEL, 0); -+ config_acp_dma_channel(rtd->acp_mmio, I2S_TO_ACP_DMA_CH_NUM, -+ CAPTURE_START_DMA_DESCR_CH15, -+ NUM_DSCRS_PER_CHANNEL, 0); -+ } -+ return 0; -+} -+ -+static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) -+{ -+ int ret; -+ u32 loops = 1000; -+ -+ struct snd_pcm_runtime *runtime = substream->runtime; -+ struct snd_soc_pcm_runtime *prtd = substream->private_data; -+ struct audio_substream_data *rtd = runtime->private_data; -+ -+ if (!rtd) -+ return -EINVAL; -+ switch (cmd) { -+ case SNDRV_PCM_TRIGGER_START: -+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: -+ case SNDRV_PCM_TRIGGER_RESUME: -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { -+ acp_dma_start(rtd->acp_mmio, -+ SYSRAM_TO_ACP_CH_NUM, false); -+ while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) & -+ BIT(SYSRAM_TO_ACP_CH_NUM)) { -+ if (!loops--) { -+ dev_err(prtd->platform->dev, -+ "acp dma start timeout\n"); -+ return -ETIMEDOUT; -+ } -+ cpu_relax(); -+ } -+ -+ acp_dma_start(rtd->acp_mmio, -+ ACP_TO_I2S_DMA_CH_NUM, true); -+ -+ } else { -+ acp_dma_start(rtd->acp_mmio, -+ I2S_TO_ACP_DMA_CH_NUM, true); -+ } -+ ret = 0; -+ break; -+ case SNDRV_PCM_TRIGGER_STOP: -+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: -+ case SNDRV_PCM_TRIGGER_SUSPEND: -+ /* Need to stop only circular DMA channels : -+ * ACP_TO_I2S_DMA_CH_NUM / I2S_TO_ACP_DMA_CH_NUM. Non-circular -+ * channels will stopped automatically after its transfer -+ * completes : SYSRAM_TO_ACP_CH_NUM / ACP_TO_SYSRAM_CH_NUM -+ */ -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) -+ ret = acp_dma_stop(rtd->acp_mmio, -+ ACP_TO_I2S_DMA_CH_NUM); -+ else -+ ret = acp_dma_stop(rtd->acp_mmio, -+ I2S_TO_ACP_DMA_CH_NUM); -+ break; -+ default: -+ ret = -EINVAL; -+ -+ } -+ return ret; -+} -+ -+static int acp_dma_new(struct snd_soc_pcm_runtime *rtd) -+{ -+ return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, -+ SNDRV_DMA_TYPE_DEV, -+ NULL, MIN_BUFFER, -+ MAX_BUFFER); -+} -+ -+static int acp_dma_close(struct snd_pcm_substream *substream) -+{ -+ struct snd_pcm_runtime *runtime = substream->runtime; -+ struct audio_substream_data *rtd = runtime->private_data; -+ struct snd_soc_pcm_runtime *prtd = substream->private_data; -+ struct audio_drv_data *adata = dev_get_drvdata(prtd->platform->dev); -+ -+ kfree(rtd); -+ -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) -+ adata->play_stream = NULL; -+ else -+ adata->capture_stream = NULL; -+ -+ /* Disable ACP irq, when the current stream is being closed and -+ * another stream is also not active. -+ */ -+ if (!adata->play_stream && !adata->capture_stream) -+ acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); -+ -+ return 0; -+} -+ -+static struct snd_pcm_ops acp_dma_ops = { -+ .open = acp_dma_open, -+ .close = acp_dma_close, -+ .ioctl = snd_pcm_lib_ioctl, -+ .hw_params = acp_dma_hw_params, -+ .hw_free = acp_dma_hw_free, -+ .trigger = acp_dma_trigger, -+ .pointer = acp_dma_pointer, -+ .mmap = acp_dma_mmap, -+ .prepare = acp_dma_prepare, -+}; -+ -+static struct snd_soc_platform_driver acp_asoc_platform = { -+ .ops = &acp_dma_ops, -+ .pcm_new = acp_dma_new, -+}; -+ -+static int acp_audio_probe(struct platform_device *pdev) -+{ -+ int status; -+ struct audio_drv_data *audio_drv_data; -+ struct resource *res; -+ -+ audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), -+ GFP_KERNEL); -+ if (audio_drv_data == NULL) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res); -+ -+ /* The following members gets populated in device 'open' -+ * function. Till then interrupts are disabled in 'acp_init' -+ * and device doesn't generate any interrupts. -+ */ -+ -+ audio_drv_data->play_stream = NULL; -+ audio_drv_data->capture_stream = NULL; -+ -+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -+ if (!res) { -+ dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); -+ return -ENODEV; -+ } -+ -+ status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler, -+ 0, "ACP_IRQ", &pdev->dev); -+ if (status) { -+ dev_err(&pdev->dev, "ACP IRQ request failed\n"); -+ return status; -+ } -+ -+ dev_set_drvdata(&pdev->dev, audio_drv_data); -+ -+ /* Initialize the ACP */ -+ acp_init(audio_drv_data->acp_mmio); -+ -+ status = snd_soc_register_platform(&pdev->dev, &acp_asoc_platform); -+ if (status != 0) { -+ dev_err(&pdev->dev, "Fail to register ALSA platform device\n"); -+ return status; -+ } -+ -+ return status; -+} -+ -+static int acp_audio_remove(struct platform_device *pdev) -+{ -+ struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev); -+ -+ acp_deinit(adata->acp_mmio); -+ snd_soc_unregister_platform(&pdev->dev); -+ -+ return 0; -+} -+ -+static struct platform_driver acp_dma_driver = { -+ .probe = acp_audio_probe, -+ .remove = acp_audio_remove, -+ .driver = { -+ .name = "acp_audio_dma", -+ }, -+}; -+ -+module_platform_driver(acp_dma_driver); -+ -+MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); -+MODULE_DESCRIPTION("AMD ACP PCM Driver"); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:acp-dma-audio"); -diff --git a/sound/soc/amd/acp.h b/sound/soc/amd/acp.h -new file mode 100644 -index 0000000..330832e ---- /dev/null -+++ b/sound/soc/amd/acp.h -@@ -0,0 +1,118 @@ -+#ifndef __ACP_HW_H -+#define __ACP_HW_H -+ -+#include "include/acp_2_2_d.h" -+#include "include/acp_2_2_sh_mask.h" -+ -+#define ACP_PAGE_SIZE_4K_ENABLE 0x02 -+ -+#define ACP_PLAYBACK_PTE_OFFSET 10 -+#define ACP_CAPTURE_PTE_OFFSET 0 -+ -+#define ACP_GARLIC_CNTL_DEFAULT 0x00000FB4 -+#define ACP_ONION_CNTL_DEFAULT 0x00000FB4 -+ -+#define ACP_PHYSICAL_BASE 0x14000 -+ -+/* Playback SRAM address (as a destination in dma descriptor) */ -+#define ACP_SHARED_RAM_BANK_1_ADDRESS 0x4002000 -+ -+/* Capture SRAM address (as a source in dma descriptor) */ -+#define ACP_SHARED_RAM_BANK_5_ADDRESS 0x400A000 -+ -+#define ACP_DMA_RESET_TIME 10000 -+#define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF -+#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF -+#define ACP_DMA_COMPLETE_TIME_OUT_VALUE 0x000000FF -+ -+#define ACP_SRAM_BASE_ADDRESS 0x4000000 -+#define ACP_DAGB_GRP_SRAM_BASE_ADDRESS 0x4001000 -+#define ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET 0x1000 -+#define ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 0x00000000 -+#define ACP_INTERNAL_APERTURE_WINDOW_4_ADDRESS 0x01800000 -+ -+#define TO_ACP_I2S_1 0x2 -+#define TO_ACP_I2S_2 0x4 -+#define FROM_ACP_I2S_1 0xa -+#define FROM_ACP_I2S_2 0xb -+ -+#define ACP_TILE_ON_MASK 0x03 -+#define ACP_TILE_OFF_MASK 0x02 -+#define ACP_TILE_ON_RETAIN_REG_MASK 0x1f -+#define ACP_TILE_OFF_RETAIN_REG_MASK 0x20 -+ -+#define ACP_TILE_P1_MASK 0x3e -+#define ACP_TILE_P2_MASK 0x3d -+#define ACP_TILE_DSP0_MASK 0x3b -+#define ACP_TILE_DSP1_MASK 0x37 -+ -+#define ACP_TILE_DSP2_MASK 0x2f -+/* Playback DMA channels */ -+#define SYSRAM_TO_ACP_CH_NUM 12 -+#define ACP_TO_I2S_DMA_CH_NUM 13 -+ -+/* Capture DMA channels */ -+#define ACP_TO_SYSRAM_CH_NUM 14 -+#define I2S_TO_ACP_DMA_CH_NUM 15 -+ -+#define NUM_DSCRS_PER_CHANNEL 2 -+ -+#define PLAYBACK_START_DMA_DESCR_CH12 0 -+#define PLAYBACK_END_DMA_DESCR_CH12 1 -+#define PLAYBACK_START_DMA_DESCR_CH13 2 -+#define PLAYBACK_END_DMA_DESCR_CH13 3 -+ -+#define CAPTURE_START_DMA_DESCR_CH14 4 -+#define CAPTURE_END_DMA_DESCR_CH14 5 -+#define CAPTURE_START_DMA_DESCR_CH15 6 -+#define CAPTURE_END_DMA_DESCR_CH15 7 -+ -+enum acp_dma_priority_level { -+ /* 0x0 Specifies the DMA channel is given normal priority */ -+ ACP_DMA_PRIORITY_LEVEL_NORMAL = 0x0, -+ /* 0x1 Specifies the DMA channel is given high priority */ -+ ACP_DMA_PRIORITY_LEVEL_HIGH = 0x1, -+ ACP_DMA_PRIORITY_LEVEL_FORCESIZE = 0xFF -+}; -+ -+struct audio_substream_data { -+ struct page *pg; -+ unsigned int order; -+ u16 num_of_pages; -+ u16 direction; -+ uint64_t size; -+ void __iomem *acp_mmio; -+}; -+ -+enum { -+ ACP_TILE_P1 = 0, -+ ACP_TILE_P2, -+ ACP_TILE_DSP0, -+ ACP_TILE_DSP1, -+ ACP_TILE_DSP2, -+}; -+ -+enum { -+ ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION = 0x0, -+ ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC = 0x1, -+ ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM = 0x8, -+ ACP_DMA_ATTRIBUTES_DAGB_GARLIC_TO_SHAREDMEM = 0x9, -+ ACP_DMA_ATTRIBUTES_FORCE_SIZE = 0xF -+}; -+ -+typedef struct acp_dma_dscr_transfer { -+ /* Specifies the source memory location for the DMA data transfer. */ -+ u32 src; -+ /* Specifies the destination memory location to where the data will -+ * be transferred. -+ */ -+ u32 dest; -+ /* Specifies the number of bytes need to be transferred -+ * from source to destination memory.Transfer direction & IOC enable -+ */ -+ u32 xfer_val; -+ /* Reserved for future use */ -+ u32 reserved; -+} acp_dma_dscr_transfer_t; -+ -+#endif /*__ACP_HW_H */ --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1128-ASoC-AMD-add-pm-ops.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1128-ASoC-AMD-add-pm-ops.patch deleted file mode 100644 index cf6d3eda..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1128-ASoC-AMD-add-pm-ops.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 2cb46c7ba1f892f2bf66f0e050434dd18bd0c2ed Mon Sep 17 00:00:00 2001 -From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> -Date: Mon, 21 Dec 2015 15:37:47 +0530 -Subject: [PATCH 03/17] ASoC: AMD: add pm ops - -genpd will power off/on ACP to manage runtime ACP PM. ACP runtime PM -hooks are added to get it deinitialized and initialized respectively, -after it is powered off/on. - -When system goes to suspend when audio usecase is active, ACP will -be powered off through genpd. When it resumes, ACP needs to be -initialized and reconfigured. - -Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> ---- - sound/soc/amd/acp-pcm-dma.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 48 insertions(+) - -diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c -index 0724d78..c0819b5 100644 ---- a/sound/soc/amd/acp-pcm-dma.c -+++ b/sound/soc/amd/acp-pcm-dma.c -@@ -16,6 +16,7 @@ - #include <linux/module.h> - #include <linux/delay.h> - #include <linux/sizes.h> -+#include <linux/pm_runtime.h> - - #include <sound/soc.h> - -@@ -885,6 +886,10 @@ static int acp_audio_probe(struct platform_device *pdev) - return status; - } - -+ pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); -+ pm_runtime_use_autosuspend(&pdev->dev); -+ pm_runtime_enable(&pdev->dev); -+ - return status; - } - -@@ -894,15 +899,58 @@ static int acp_audio_remove(struct platform_device *pdev) - - acp_deinit(adata->acp_mmio); - snd_soc_unregister_platform(&pdev->dev); -+ pm_runtime_disable(&pdev->dev); - - return 0; - } - -+static int acp_pcm_resume(struct device *dev) -+{ -+ struct audio_drv_data *adata = dev_get_drvdata(dev); -+ -+ acp_init(adata->acp_mmio); -+ -+ if (adata->play_stream && adata->play_stream->runtime) -+ config_acp_dma(adata->acp_mmio, -+ adata->play_stream->runtime->private_data); -+ if (adata->capture_stream && adata->capture_stream->runtime) -+ config_acp_dma(adata->acp_mmio, -+ adata->capture_stream->runtime->private_data); -+ -+ acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); -+ return 0; -+} -+ -+static int acp_pcm_runtime_suspend(struct device *dev) -+{ -+ struct audio_drv_data *adata = dev_get_drvdata(dev); -+ -+ acp_deinit(adata->acp_mmio); -+ acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); -+ return 0; -+} -+ -+static int acp_pcm_runtime_resume(struct device *dev) -+{ -+ struct audio_drv_data *adata = dev_get_drvdata(dev); -+ -+ acp_init(adata->acp_mmio); -+ acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); -+ return 0; -+} -+ -+static const struct dev_pm_ops acp_pm_ops = { -+ .resume = acp_pcm_resume, -+ .runtime_suspend = acp_pcm_runtime_suspend, -+ .runtime_resume = acp_pcm_runtime_resume, -+}; -+ - static struct platform_driver acp_dma_driver = { - .probe = acp_audio_probe, - .remove = acp_audio_remove, - .driver = { - .name = "acp_audio_dma", -+ .pm = &acp_pm_ops, - }, - }; - --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1129-ASoC-AMD-Manage-ACP-2.x-SRAM-banks-power.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1129-ASoC-AMD-Manage-ACP-2.x-SRAM-banks-power.patch deleted file mode 100644 index 76135b6e..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1129-ASoC-AMD-Manage-ACP-2.x-SRAM-banks-power.patch +++ /dev/null @@ -1,190 +0,0 @@ -From 21a602911b8e34e680a969e28db3f9966567612d Mon Sep 17 00:00:00 2001 -From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> -Date: Mon, 21 Dec 2015 16:13:29 +0530 -Subject: [PATCH 04/17] ASoC: AMD: Manage ACP 2.x SRAM banks power - -ACP SRAM banks gets turned on when ACP is powered on. -Not all banks are used for playback/capture. So, power on -required banks during audio device open and power off during -audio device close. - -Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> ---- - sound/soc/amd/acp-pcm-dma.c | 94 +++++++++++++++++++++++++++++++++++++++++---- - 1 file changed, 87 insertions(+), 7 deletions(-) - -diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c -index c0819b5..cc8b841 100644 ---- a/sound/soc/amd/acp-pcm-dma.c -+++ b/sound/soc/amd/acp-pcm-dma.c -@@ -376,9 +376,57 @@ static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) - return 0; - } - -+static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, -+ bool power_on) -+{ -+ u32 val, req_reg, sts_reg, sts_reg_mask; -+ u32 loops = 1000; -+ -+ if (bank < 32) { -+ req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO; -+ sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO; -+ sts_reg_mask = 0xFFFFFFFF; -+ -+ } else { -+ bank -= 32; -+ req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI; -+ sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI; -+ sts_reg_mask = 0x0000FFFF; -+ } -+ -+ val = acp_reg_read(acp_mmio, req_reg); -+ if (val & (1 << bank)) { -+ /* bank is in off state */ -+ if (power_on == true) -+ /* request to on */ -+ val &= ~(1 << bank); -+ else -+ /* request to off */ -+ return; -+ } else { -+ /* bank is in on state */ -+ if (power_on == false) -+ /* request to off */ -+ val |= 1 << bank; -+ else -+ /* request to on */ -+ return; -+ } -+ acp_reg_write(val, acp_mmio, req_reg); -+ -+ while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) { -+ if (!loops--) { -+ pr_err("ACP SRAM bank %d state change failed\n", bank); -+ break; -+ } -+ cpu_relax(); -+ } -+} -+ - /* Initialize and bring ACP hardware to default state. */ - static int acp_init(void __iomem *acp_mmio) - { -+ u16 bank; - u32 val, count, sram_pte_offset; - - /* Assert Soft reset of ACP */ -@@ -447,6 +495,13 @@ static int acp_init(void __iomem *acp_mmio) - acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, - acp_mmio, mmACP_EXTERNAL_INTR_CNTL); - -+ /* When ACP_TILE_P1 is turned on, all SRAM banks get turned on. -+ * Now, turn off all of them. This can't be done in 'poweron' of -+ * ACP pm domain, as this requires ACP to be initialized. -+ */ -+ for (bank = 1; bank < 48; bank++) -+ acp_set_sram_bank_state(acp_mmio, bank, false); -+ - return 0; - } - -@@ -559,6 +614,7 @@ static irqreturn_t dma_irq_handler(int irq, void *arg) - - static int acp_dma_open(struct snd_pcm_substream *substream) - { -+ u16 bank; - int ret = 0; - struct snd_pcm_runtime *runtime = substream->runtime; - struct snd_soc_pcm_runtime *prtd = substream->private_data; -@@ -592,10 +648,17 @@ static int acp_dma_open(struct snd_pcm_substream *substream) - if (!intr_data->play_stream && !intr_data->capture_stream) - acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); - -- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - intr_data->play_stream = substream; -- else -+ for (bank = 1; bank <= 4; bank++) -+ acp_set_sram_bank_state(intr_data->acp_mmio, bank, -+ true); -+ } else { - intr_data->capture_stream = substream; -+ for (bank = 5; bank <= 8; bank++) -+ acp_set_sram_bank_state(intr_data->acp_mmio, bank, -+ true); -+ } - - return 0; - } -@@ -627,6 +690,7 @@ static int acp_dma_hw_params(struct snd_pcm_substream *substream, - pg = virt_to_page(substream->dma_buffer.area); - - if (pg != NULL) { -+ acp_set_sram_bank_state(rtd->acp_mmio, 0, true); - /* Save for runtime private data */ - rtd->pg = pg; - rtd->order = get_order(size); -@@ -802,6 +866,7 @@ static int acp_dma_new(struct snd_soc_pcm_runtime *rtd) - - static int acp_dma_close(struct snd_pcm_substream *substream) - { -+ u16 bank; - struct snd_pcm_runtime *runtime = substream->runtime; - struct audio_substream_data *rtd = runtime->private_data; - struct snd_soc_pcm_runtime *prtd = substream->private_data; -@@ -809,10 +874,17 @@ static int acp_dma_close(struct snd_pcm_substream *substream) - - kfree(rtd); - -- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - adata->play_stream = NULL; -- else -+ for (bank = 1; bank <= 4; bank++) -+ acp_set_sram_bank_state(adata->acp_mmio, bank, -+ false); -+ } else { - adata->capture_stream = NULL; -+ for (bank = 5; bank <= 8; bank++) -+ acp_set_sram_bank_state(adata->acp_mmio, bank, -+ false); -+ } - - /* Disable ACP irq, when the current stream is being closed and - * another stream is also not active. -@@ -906,17 +978,25 @@ static int acp_audio_remove(struct platform_device *pdev) - - static int acp_pcm_resume(struct device *dev) - { -+ u16 bank; - struct audio_drv_data *adata = dev_get_drvdata(dev); - - acp_init(adata->acp_mmio); - -- if (adata->play_stream && adata->play_stream->runtime) -+ if (adata->play_stream && adata->play_stream->runtime) { -+ for (bank = 1; bank <= 4; bank++) -+ acp_set_sram_bank_state(adata->acp_mmio, bank, -+ true); - config_acp_dma(adata->acp_mmio, - adata->play_stream->runtime->private_data); -- if (adata->capture_stream && adata->capture_stream->runtime) -+ } -+ if (adata->capture_stream && adata->capture_stream->runtime) { -+ for (bank = 5; bank <= 8; bank++) -+ acp_set_sram_bank_state(adata->acp_mmio, bank, -+ true); - config_acp_dma(adata->acp_mmio, - adata->capture_stream->runtime->private_data); -- -+ } - acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); - return 0; - } --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1130-ASoc-AMD-Machine-driver-for-AMD-ACP-Audio-engine-usi.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1130-ASoc-AMD-Machine-driver-for-AMD-ACP-Audio-engine-usi.patch deleted file mode 100644 index 03e85464..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1130-ASoc-AMD-Machine-driver-for-AMD-ACP-Audio-engine-usi.patch +++ /dev/null @@ -1,251 +0,0 @@ -From 13a790e8d490f59170004fd20d74c0267d08c69e Mon Sep 17 00:00:00 2001 -From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> -Date: Fri, 1 Jul 2016 12:47:49 +0530 -Subject: [PATCH 05/17] ASoc: AMD: Machine driver for AMD ACP Audio engine - using Realtek RT286 codec - -Added machine driver support in the Kconfig file and the Makefile - -Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> ---- - sound/soc/Kconfig | 1 + - sound/soc/Makefile | 1 + - sound/soc/amd/Kconfig | 7 ++ - sound/soc/amd/Makefile | 2 + - sound/soc/amd/acp-rt286.c | 175 ++++++++++++++++++++++++++++++++++++++++++++++ - 5 files changed, 186 insertions(+) - create mode 100644 sound/soc/amd/acp-rt286.c - -diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig -index 7ff7d88..a34e9e9 100644 ---- a/sound/soc/Kconfig -+++ b/sound/soc/Kconfig -@@ -38,6 +38,7 @@ config SND_SOC_TOPOLOGY - - # All the supported SoCs - source "sound/soc/adi/Kconfig" -+source "sound/soc/amd/Kconfig" - source "sound/soc/atmel/Kconfig" - source "sound/soc/au1x/Kconfig" - source "sound/soc/bcm/Kconfig" -diff --git a/sound/soc/Makefile b/sound/soc/Makefile -index 8eb06db..3ab378b 100644 ---- a/sound/soc/Makefile -+++ b/sound/soc/Makefile -@@ -18,6 +18,7 @@ obj-$(CONFIG_SND_SOC) += snd-soc-core.o - obj-$(CONFIG_SND_SOC) += codecs/ - obj-$(CONFIG_SND_SOC) += generic/ - obj-$(CONFIG_SND_SOC) += adi/ -+obj-$(CONFIG_SND_SOC) += amd/ - obj-$(CONFIG_SND_SOC) += atmel/ - obj-$(CONFIG_SND_SOC) += au1x/ - obj-$(CONFIG_SND_SOC) += bcm/ -diff --git a/sound/soc/amd/Kconfig b/sound/soc/amd/Kconfig -index 78187eb..3724f54 100644 ---- a/sound/soc/amd/Kconfig -+++ b/sound/soc/amd/Kconfig -@@ -1,3 +1,10 @@ -+config SND_SOC_AMD_CZ_RT286_MACH -+ tristate "AMD ASoC Audio driver for Carrizo with rt286 codec" -+ select SND_SOC_RT286 -+ select SND_SOC_AMD_ACP -+ depends on I2C_DESIGNWARE_PLATFORM -+ help -+ This option enables AMD I2S Audio support on Carrizo with ALC288 codec. - config SND_SOC_AMD_ACP - tristate "AMD Audio Coprocessor support" - help -diff --git a/sound/soc/amd/Makefile b/sound/soc/amd/Makefile -index 1a66ec0..a75574d 100644 ---- a/sound/soc/amd/Makefile -+++ b/sound/soc/amd/Makefile -@@ -1,3 +1,5 @@ - snd-soc-acp-pcm-objs := acp-pcm-dma.o -+snd-soc-acp-rt286-mach-objs := acp-rt286.o - - obj-$(CONFIG_SND_SOC_AMD_ACP) += snd-soc-acp-pcm.o -+obj-$(CONFIG_SND_SOC_AMD_CZ_RT286_MACH) += snd-soc-acp-rt286-mach.o -diff --git a/sound/soc/amd/acp-rt286.c b/sound/soc/amd/acp-rt286.c -new file mode 100644 -index 0000000..3fa714e ---- /dev/null -+++ b/sound/soc/amd/acp-rt286.c -@@ -0,0 +1,175 @@ -+/* -+ * Machine driver for AMD ACP Audio engine using Realtek RT286 codec -+ * -+ * Copyright 2014-2015 Advanced Micro Devices, Inc. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included in -+ * all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ * -+ * -+ */ -+ -+#include <sound/core.h> -+#include <sound/soc.h> -+#include <sound/pcm.h> -+#include <sound/pcm_params.h> -+#include <sound/soc-dapm.h> -+#include <sound/jack.h> -+#include <linux/gpio.h> -+#include <linux/module.h> -+#include <linux/i2c.h> -+#include <linux/acpi.h> -+ -+#include "../codecs/rt286.h" -+ -+static struct snd_soc_jack cz_jack; -+static struct snd_soc_jack_pin cz_pins[] = { -+ { -+ .pin = "Analog Mic", -+ .mask = SND_JACK_MICROPHONE, -+ }, -+ { -+ .pin = "Headphones", -+ .mask = SND_JACK_HEADPHONE, -+ }, -+}; -+ -+static int cz_init(struct snd_soc_pcm_runtime *rtd) -+{ -+ int ret; -+ struct snd_soc_card *card; -+ struct snd_soc_codec *codec; -+ struct snd_soc_dai *codec_dai = rtd->codec_dai; -+ -+ codec = rtd->codec; -+ card = rtd->card; -+ -+ ret = snd_soc_dai_set_sysclk(codec_dai, RT286_SCLK_S_PLL, 24000000, -+ SND_SOC_CLOCK_OUT); -+ if (ret < 0) { -+ dev_err(card->dev, "unable to set codec dai clock\n"); -+ return ret; -+ } -+ ret = snd_soc_card_jack_new(card, "Headset", -+ SND_JACK_HEADSET, &cz_jack, cz_pins, ARRAY_SIZE(cz_pins)); -+ -+ if (ret) -+ return ret; -+ -+ rt286_mic_detect(codec, &cz_jack); -+ return 0; -+} -+ -+static struct snd_soc_dai_link cz_dai_rt286[] = { -+ { -+ .name = "amd-rt286-play", -+ .stream_name = "RT286_AIF1", -+ .platform_name = "acp_audio_dma.0.auto", -+ .cpu_dai_name = "designware-i2s.1.auto", -+ .codec_dai_name = "rt286-aif1", -+ .codec_name = "i2c-RTK0000:00", -+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF -+ | SND_SOC_DAIFMT_CBM_CFM, -+ .init = cz_init, -+ }, -+ { -+ -+ .name = "amd-rt286-cap", -+ .stream_name = "RT286_AIF1", -+ .platform_name = "acp_audio_dma.0.auto", -+ .cpu_dai_name = "designware-i2s.2.auto", -+ .codec_dai_name = "rt286-aif1", -+ .codec_name = "i2c-RTK0000:00", -+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF -+ | SND_SOC_DAIFMT_CBM_CFM, -+ .init = cz_init, -+ }, -+ -+}; -+ -+static const struct snd_soc_dapm_widget cz_widgets[] = { -+ SND_SOC_DAPM_HP("Headphones", NULL), -+ SND_SOC_DAPM_MIC("Analog Mic", NULL), -+}; -+ -+static const struct snd_soc_dapm_route cz_audio_route[] = { -+ {"Headphones", NULL, "HPO L"}, -+ {"Headphones", NULL, "HPO R"}, -+ {"MIC1", NULL, "Analog Mic"}, -+}; -+ -+static struct snd_soc_card cz_card = { -+ .name = "acp-rt286", -+ .owner = THIS_MODULE, -+ .dai_link = cz_dai_rt286, -+ .num_links = 2, -+ -+ .dapm_widgets = cz_widgets, -+ .num_dapm_widgets = ARRAY_SIZE(cz_widgets), -+ .dapm_routes = cz_audio_route, -+ .num_dapm_routes = ARRAY_SIZE(cz_audio_route), -+}; -+ -+static int cz_probe(struct platform_device *pdev) -+{ -+ int ret; -+ struct snd_soc_card *card; -+ -+ card = &cz_card; -+ cz_card.dev = &pdev->dev; -+ platform_set_drvdata(pdev, card); -+ ret = snd_soc_register_card(card); -+ if (ret) { -+ dev_err(&pdev->dev, -+ "snd_soc_register_card(%s) failed: %d\n", -+ cz_card.name, ret); -+ return ret; -+ } -+ return 0; -+} -+ -+static int cz_remove(struct platform_device *pdev) -+{ -+ struct snd_soc_card *card; -+ -+ card = platform_get_drvdata(pdev); -+ snd_soc_unregister_card(card); -+ -+ return 0; -+} -+ -+static const struct acpi_device_id cz_audio_acpi_match[] = { -+ { "I2SC1002", 0 }, -+ {}, -+}; -+ -+static struct platform_driver cz_pcm_driver = { -+ .driver = { -+ .name = "cz-rt288", -+ .acpi_match_table = ACPI_PTR(cz_audio_acpi_match), -+ .pm = &snd_soc_pm_ops, -+ }, -+ .probe = cz_probe, -+ .remove = cz_remove, -+}; -+ -+module_platform_driver(cz_pcm_driver); -+ -+MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); -+MODULE_DESCRIPTION("cz-rt288 audio support"); -+MODULE_LICENSE("GPL v2"); --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1131-drm-amd-Adding-ACP-driver-support-for-AMDGPU.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1131-drm-amd-Adding-ACP-driver-support-for-AMDGPU.patch deleted file mode 100644 index 5ae2536d..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1131-drm-amd-Adding-ACP-driver-support-for-AMDGPU.patch +++ /dev/null @@ -1,383 +0,0 @@ -From 58e6e67a2e65c339cbb6803463b19aaab92303c5 Mon Sep 17 00:00:00 2001 -From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> -Date: Sat, 24 Sep 2016 12:57:36 +0530 -Subject: [PATCH 06/17] drm/amd: Adding ACP driver support for AMDGPU - -Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> -Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> ---- - drivers/gpu/drm/amd/acp/Kconfig | 1 + - drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +- - drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 216 ++----------------------------- - drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h | 2 +- - drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 4 +- - drivers/gpu/drm/amd/include/amd_shared.h | 2 + - 6 files changed, 18 insertions(+), 212 deletions(-) - -diff --git a/drivers/gpu/drm/amd/acp/Kconfig b/drivers/gpu/drm/amd/acp/Kconfig -index ca77ec1..b8a0605 100644 ---- a/drivers/gpu/drm/amd/acp/Kconfig -+++ b/drivers/gpu/drm/amd/acp/Kconfig -@@ -2,6 +2,7 @@ menu "ACP (Audio CoProcessor) Configuration" - - config DRM_AMD_ACP - bool "Enable AMD Audio CoProcessor IP support" -+ default y - select MFD_CORE - select PM_GENERIC_DOMAINS if PM - help -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -index 551f763..86894ec 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -@@ -1928,8 +1928,9 @@ struct amdgpu_atcs { - /* - * CGS - */ --struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); --void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); -+void *amdgpu_cgs_create_device(struct amdgpu_device *adev); -+void amdgpu_cgs_destroy_device(void *cgs_device); -+ - - - /* GPU virtualization */ -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -index 043ba60..cbbc31a8 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -@@ -24,7 +24,6 @@ - */ - - #include <linux/irqdomain.h> --#include <linux/pm_domain.h> - #include <linux/platform_device.h> - #include <sound/designware_i2s.h> - #include <sound/pcm.h> -@@ -103,153 +102,6 @@ static int acp_sw_fini(void *handle) - return 0; - } - --/* power off a tile/block within ACP */ --static int acp_suspend_tile(void *cgs_dev, int tile) --{ -- u32 val = 0; -- u32 count = 0; -- -- if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) { -- pr_err("Invalid ACP tile : %d to suspend\n", tile); -- return -1; -- } -- -- val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile); -- val &= ACP_TILE_ON_MASK; -- -- if (val == 0x0) { -- val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG); -- val = val | (1 << tile); -- cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val); -- cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG, -- 0x500 + tile); -- -- count = ACP_TIMEOUT_LOOP; -- while (true) { -- val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 -- + tile); -- val = val & ACP_TILE_ON_MASK; -- if (val == ACP_TILE_OFF_MASK) -- break; -- if (--count == 0) { -- pr_err("Timeout reading ACP PGFSM status\n"); -- return -ETIMEDOUT; -- } -- udelay(100); -- } -- -- val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG); -- -- val |= ACP_TILE_OFF_RETAIN_REG_MASK; -- cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val); -- } -- return 0; --} -- --/* power on a tile/block within ACP */ --static int acp_resume_tile(void *cgs_dev, int tile) --{ -- u32 val = 0; -- u32 count = 0; -- -- if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) { -- pr_err("Invalid ACP tile to resume\n"); -- return -1; -- } -- -- val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile); -- val = val & ACP_TILE_ON_MASK; -- -- if (val != 0x0) { -- cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG, -- 0x600 + tile); -- count = ACP_TIMEOUT_LOOP; -- while (true) { -- val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 -- + tile); -- val = val & ACP_TILE_ON_MASK; -- if (val == 0x0) -- break; -- if (--count == 0) { -- pr_err("Timeout reading ACP PGFSM status\n"); -- return -ETIMEDOUT; -- } -- udelay(100); -- } -- val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG); -- if (tile == ACP_TILE_P1) -- val = val & (ACP_TILE_P1_MASK); -- else if (tile == ACP_TILE_P2) -- val = val & (ACP_TILE_P2_MASK); -- -- cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val); -- } -- return 0; --} -- --struct acp_pm_domain { -- void *cgs_dev; -- struct generic_pm_domain gpd; --}; -- --static int acp_poweroff(struct generic_pm_domain *genpd) --{ -- int i, ret; -- struct acp_pm_domain *apd; -- -- apd = container_of(genpd, struct acp_pm_domain, gpd); -- if (apd != NULL) { -- /* Donot return abruptly if any of power tile fails to suspend. -- * Log it and continue powering off other tile -- */ -- for (i = 4; i >= 0 ; i--) { -- ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_P1 + i); -- if (ret) -- pr_err("ACP tile %d tile suspend failed\n", i); -- } -- } -- return 0; --} -- --static int acp_poweron(struct generic_pm_domain *genpd) --{ -- int i, ret; -- struct acp_pm_domain *apd; -- -- apd = container_of(genpd, struct acp_pm_domain, gpd); -- if (apd != NULL) { -- for (i = 0; i < 2; i++) { -- ret = acp_resume_tile(apd->cgs_dev, ACP_TILE_P1 + i); -- if (ret) { -- pr_err("ACP tile %d resume failed\n", i); -- break; -- } -- } -- -- /* Disable DSPs which are not going to be used */ -- for (i = 0; i < 3; i++) { -- ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_DSP0 + i); -- /* Continue suspending other DSP, even if one fails */ -- if (ret) -- pr_err("ACP DSP %d suspend failed\n", i); -- } -- } -- return 0; --} -- --static struct device *get_mfd_cell_dev(const char *device_name, int r) --{ -- char auto_dev_name[25]; -- struct device *dev; -- -- snprintf(auto_dev_name, sizeof(auto_dev_name), -- "%s.%d.auto", device_name, r); -- dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name); -- dev_info(dev, "device %s added to pm domain\n", auto_dev_name); -- -- return dev; --} -- - /** - * acp_hw_init - start and test ACP block - * -@@ -258,9 +110,8 @@ static struct device *get_mfd_cell_dev(const char *device_name, int r) - */ - static int acp_hw_init(void *handle) - { -- int r, i; -+ int r; - uint64_t acp_base; -- struct device *dev; - struct i2s_platform_data *i2s_pdata; - - struct amdgpu_device *adev = (struct amdgpu_device *)handle; -@@ -286,19 +137,6 @@ static int acp_hw_init(void *handle) - else if (r) - return r; - -- adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL); -- if (adev->acp.acp_genpd == NULL) -- return -ENOMEM; -- -- adev->acp.acp_genpd->gpd.name = "ACP_AUDIO"; -- adev->acp.acp_genpd->gpd.power_off = acp_poweroff; -- adev->acp.acp_genpd->gpd.power_on = acp_poweron; -- -- -- adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device; -- -- pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false); -- - adev->acp.acp_cell = kzalloc(sizeof(struct mfd_cell) * ACP_DEVS, - GFP_KERNEL); - -@@ -373,15 +211,6 @@ static int acp_hw_init(void *handle) - if (r) - return r; - -- for (i = 0; i < ACP_DEVS ; i++) { -- dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); -- r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev); -- if (r) { -- dev_err(dev, "Failed to add dev to genpd\n"); -- return r; -- } -- } -- - return 0; - } - -@@ -393,22 +222,10 @@ static int acp_hw_init(void *handle) - */ - static int acp_hw_fini(void *handle) - { -- int i, ret; -- struct device *dev; -- - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - -- for (i = 0; i < ACP_DEVS ; i++) { -- dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); -- ret = pm_genpd_remove_device(&adev->acp.acp_genpd->gpd, dev); -- /* If removal fails, dont giveup and try rest */ -- if (ret) -- dev_err(dev, "remove dev from genpd failed\n"); -- } -- - mfd_remove_devices(adev->acp.parent); - kfree(adev->acp.acp_res); -- kfree(adev->acp.acp_genpd); - kfree(adev->acp.acp_cell); - - return 0; -@@ -421,29 +238,6 @@ static int acp_suspend(void *handle) - - static int acp_resume(void *handle) - { -- int i, ret; -- struct acp_pm_domain *apd; -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- /* return early if no ACP */ -- if (!adev->acp.acp_genpd) -- return 0; -- -- /* SMU block will power on ACP irrespective of ACP runtime status. -- * Power off explicitly based on genpd ACP runtime status so that ACP -- * hw and ACP-genpd status are in sync. -- * 'suspend_power_off' represents "Power status before system suspend" -- */ -- if (adev->acp.acp_genpd->gpd.suspend_power_off == true) { -- apd = container_of(&adev->acp.acp_genpd->gpd, -- struct acp_pm_domain, gpd); -- -- for (i = 4; i >= 0 ; i--) { -- ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_P1 + i); -- if (ret) -- pr_err("ACP tile %d tile suspend failed\n", i); -- } -- } - return 0; - } - -@@ -467,6 +261,13 @@ static int acp_soft_reset(void *handle) - return 0; - } - -+static void acp_print_status(void *handle) -+{ -+ struct amdgpu_device *adev = (struct amdgpu_device *)handle; -+ -+ dev_info(adev->dev, "ACP STATUS\n"); -+} -+ - static int acp_set_clockgating_state(void *handle, - enum amd_clockgating_state state) - { -@@ -492,6 +293,7 @@ const struct amd_ip_funcs acp_ip_funcs = { - .is_idle = acp_is_idle, - .wait_for_idle = acp_wait_for_idle, - .soft_reset = acp_soft_reset, -+ .print_status = acp_print_status, - .set_clockgating_state = acp_set_clockgating_state, - .set_powergating_state = acp_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h -index 8a39631..f6e32a6 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h -@@ -30,7 +30,7 @@ - - struct amdgpu_acp { - struct device *parent; -- struct cgs_device *cgs_device; -+ void *cgs_device; - struct amd_acp_private *private; - struct mfd_cell *acp_cell; - struct resource *acp_res; -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c -index 490464e..88625b5 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c -@@ -1141,7 +1141,7 @@ static const struct cgs_os_ops amdgpu_cgs_os_ops = { - amdgpu_cgs_irq_put - }; - --struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev) -+void *amdgpu_cgs_create_device(struct amdgpu_device *adev) - { - struct amdgpu_cgs_device *cgs_device = - kmalloc(sizeof(*cgs_device), GFP_KERNEL); -@@ -1158,7 +1158,7 @@ struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev) - return (struct cgs_device *)cgs_device; - } - --void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device) -+void amdgpu_cgs_destroy_device(void *cgs_device) - { - kfree(cgs_device); - } -diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h -index afce1ed..d83baf3 100644 ---- a/drivers/gpu/drm/amd/include/amd_shared.h -+++ b/drivers/gpu/drm/amd/include/amd_shared.h -@@ -168,6 +168,8 @@ struct amd_ip_funcs { - int (*wait_for_idle)(void *handle); - /* soft reset the IP block */ - int (*soft_reset)(void *handle); -+ /* dump the IP block status registers */ -+ void (*print_status)(void *handle); - /* enable/disable cg for the IP block */ - int (*set_clockgating_state)(void *handle, - enum amd_clockgating_state state); --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1132-drm-amd-Power-management-related-modifications-in-th.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1132-drm-amd-Power-management-related-modifications-in-th.patch deleted file mode 100644 index f1a7886b..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1132-drm-amd-Power-management-related-modifications-in-th.patch +++ /dev/null @@ -1,280 +0,0 @@ -From 70cc896479d8491bb6892312b54613439af01316 Mon Sep 17 00:00:00 2001 -From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> -Date: Fri, 23 Sep 2016 17:35:10 +0530 -Subject: [PATCH 07/17] drm/amd: Power management related modifications in the - -amdgpu ACP driver. - -Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> -Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 206 +++++++++++++++++++++++++++++++- - 1 file changed, 205 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -index cbbc31a8..37ecc36 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -@@ -24,6 +24,7 @@ - */ - - #include <linux/irqdomain.h> -+#include <linux/pm_domain.h> - #include <linux/platform_device.h> - #include <sound/designware_i2s.h> - #include <sound/pcm.h> -@@ -102,6 +103,155 @@ static int acp_sw_fini(void *handle) - return 0; - } - -+/* power off a tile/block within ACP */ -+static int acp_suspend_tile(void *cgs_dev, int tile) -+{ -+ u32 val = 0; -+ u32 count = 0; -+ -+ if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) { -+ pr_err("Invalid ACP tile : %d to suspend\n", tile); -+ return -1; -+ } -+ -+ val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile); -+ val &= ACP_TILE_ON_MASK; -+ -+ if (val == 0x0) { -+ val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG); -+ val = val | (1 << tile); -+ cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val); -+ cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG, -+ 0x500 + tile); -+ -+ count = ACP_TIMEOUT_LOOP; -+ while (true) { -+ val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 -+ + tile); -+ val = val & ACP_TILE_ON_MASK; -+ if (val == ACP_TILE_OFF_MASK) -+ break; -+ if (--count == 0) { -+ pr_err("Timeout reading ACP PGFSM status\n"); -+ return -ETIMEDOUT; -+ } -+ udelay(100); -+ } -+ -+ val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG); -+ -+ val |= ACP_TILE_OFF_RETAIN_REG_MASK; -+ cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val); -+ } -+ return 0; -+} -+ -+/* power on a tile/block within ACP */ -+static int acp_resume_tile(void *cgs_dev, int tile) -+{ -+ u32 val = 0; -+ u32 count = 0; -+ -+ if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) { -+ pr_err("Invalid ACP tile to resume\n"); -+ return -1; -+ } -+ -+ val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile); -+ val = val & ACP_TILE_ON_MASK; -+ -+ if (val != 0x0) { -+ cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG, -+ 0x600 + tile); -+ count = ACP_TIMEOUT_LOOP; -+ while (true) { -+ val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 -+ + tile); -+ val = val & ACP_TILE_ON_MASK; -+ if (val == 0x0) -+ break; -+ if (--count == 0) { -+ pr_err("Timeout reading ACP PGFSM status\n"); -+ return -ETIMEDOUT; -+ } -+ udelay(100); -+ } -+ val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG); -+ if (tile == ACP_TILE_P1) -+ val = val & (ACP_TILE_P1_MASK); -+ else if (tile == ACP_TILE_P2) -+ val = val & (ACP_TILE_P2_MASK); -+ -+ cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val); -+ } -+ return 0; -+} -+ -+struct acp_pm_domain { -+ void *cgs_dev; -+ struct generic_pm_domain gpd; -+}; -+ -+static int acp_poweroff(struct generic_pm_domain *genpd) -+{ -+ int i, ret; -+ struct acp_pm_domain *apd; -+ -+ apd = container_of(genpd, struct acp_pm_domain, gpd); -+ if (apd != NULL) { -+ /* Donot return abruptly if any of power tile fails to suspend. -+ * Log it and continue powering off other tile -+ */ -+ for (i = 4; i >= 0 ; i--) { -+ ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_P1 + i); -+ if (ret) -+ pr_err("ACP tile %d tile suspend failed\n", i); -+ } -+ } -+ return 0; -+} -+ -+static int acp_poweron(struct generic_pm_domain *genpd) -+{ -+ int i, ret; -+ struct acp_pm_domain *apd; -+ -+ apd = container_of(genpd, struct acp_pm_domain, gpd); -+ if (apd != NULL) { -+ for (i = 0; i < 2; i++) { -+ ret = acp_resume_tile(apd->cgs_dev, ACP_TILE_P1 + i); -+ if (ret) { -+ pr_err("ACP tile %d resume failed\n", i); -+ break; -+ } -+ } -+ -+ /* Disable DSPs which are not going to be used */ -+ for (i = 0; i < 3; i++) { -+ ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_DSP0 + i); -+ /* Continue suspending other DSP, even if one fails */ -+ if (ret) -+ pr_err("ACP DSP %d suspend failed\n", i); -+ } -+ } -+ return 0; -+} -+ -+static struct device *get_mfd_cell_dev(const char *device_name, int r) -+{ -+ char auto_dev_name[25]; -+ char buf[8]; -+ struct device *dev; -+ -+ sprintf(buf, ".%d.auto", r); -+ strcpy(auto_dev_name, device_name); -+ strcat(auto_dev_name, buf); -+ dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name); -+ dev_info(dev, "device %s added to pm domain\n", auto_dev_name); -+ -+ return dev; -+} -+ - /** - * acp_hw_init - start and test ACP block - * -@@ -110,8 +260,9 @@ static int acp_sw_fini(void *handle) - */ - static int acp_hw_init(void *handle) - { -- int r; -+ int r, i; - uint64_t acp_base; -+ struct device *dev; - struct i2s_platform_data *i2s_pdata; - - struct amdgpu_device *adev = (struct amdgpu_device *)handle; -@@ -137,6 +288,19 @@ static int acp_hw_init(void *handle) - else if (r) - return r; - -+ adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL); -+ if (adev->acp.acp_genpd == NULL) -+ return -ENOMEM; -+ -+ adev->acp.acp_genpd->gpd.name = "ACP_AUDIO"; -+ adev->acp.acp_genpd->gpd.power_off = acp_poweroff; -+ adev->acp.acp_genpd->gpd.power_on = acp_poweron; -+ -+ -+ adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device; -+ -+ pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false); -+ - adev->acp.acp_cell = kzalloc(sizeof(struct mfd_cell) * ACP_DEVS, - GFP_KERNEL); - -@@ -211,6 +375,15 @@ static int acp_hw_init(void *handle) - if (r) - return r; - -+ for (i = 0; i < ACP_DEVS ; i++) { -+ dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); -+ r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev); -+ if (r) { -+ dev_err(dev, "Failed to add dev to genpd\n"); -+ return r; -+ } -+ } -+ - return 0; - } - -@@ -222,10 +395,22 @@ static int acp_hw_init(void *handle) - */ - static int acp_hw_fini(void *handle) - { -+ int i, ret; -+ struct device *dev; -+ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - -+ for (i = 0; i < ACP_DEVS ; i++) { -+ dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); -+ ret = pm_genpd_remove_device(&adev->acp.acp_genpd->gpd, dev); -+ /* If removal fails, dont giveup and try rest */ -+ if (ret) -+ dev_err(dev, "remove dev from genpd failed\n"); -+ } -+ - mfd_remove_devices(adev->acp.parent); - kfree(adev->acp.acp_res); -+ kfree(adev->acp.acp_genpd); - kfree(adev->acp.acp_cell); - - return 0; -@@ -238,6 +423,25 @@ static int acp_suspend(void *handle) - - static int acp_resume(void *handle) - { -+ int i, ret; -+ struct acp_pm_domain *apd; -+ struct amdgpu_device *adev = (struct amdgpu_device *)handle; -+ -+ /* SMU block will power on ACP irrespective of ACP runtime status. -+ * Power off explicitly based on genpd ACP runtime status so that ACP -+ * hw and ACP-genpd status are in sync. -+ * 'suspend_power_off' represents "Power status before system suspend" -+ */ -+ if (adev->acp.acp_genpd->gpd.suspend_power_off == true) { -+ apd = container_of(&adev->acp.acp_genpd->gpd, -+ struct acp_pm_domain, gpd); -+ -+ for (i = 4; i >= 0 ; i--) { -+ ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_P1 + i); -+ if (ret) -+ pr_err("ACP tile %d tile suspend failed\n", i); -+ } -+ } - return 0; - } - --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1133-ASoC-dwc-add-quirk-for-different-register-offset.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1133-ASoC-dwc-add-quirk-for-different-register-offset.patch deleted file mode 100644 index f0fc5753..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1133-ASoC-dwc-add-quirk-for-different-register-offset.patch +++ /dev/null @@ -1,64 +0,0 @@ -From c9d301e1d02d7b741f9f3d1799ad9b2306c393f1 Mon Sep 17 00:00:00 2001 -From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> -Date: Fri, 23 Sep 2016 17:51:13 +0530 -Subject: [PATCH 08/17] ASoC:dwc add quirk for different register offset - -Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> -Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> ---- - sound/soc/dwc/designware_i2s.c | 18 +++++++++++++++--- - 1 file changed, 15 insertions(+), 3 deletions(-) - -diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c -index 6e6a70c..4f8f074 100644 ---- a/sound/soc/dwc/designware_i2s.c -+++ b/sound/soc/dwc/designware_i2s.c -@@ -93,6 +93,10 @@ struct dw_i2s_dev { - struct clk *clk; - int active; - unsigned int capability; -+ #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0) -+ unsigned int quirks; -+ unsigned int i2s_reg_comp1; -+ unsigned int i2s_reg_comp2; - struct device *dev; - - /* data related to DMA transfers b/w i2s and DMAC */ -@@ -459,8 +463,8 @@ static int dw_configure_dai(struct dw_i2s_dev *dev, - * Read component parameter registers to extract - * the I2S block's configuration. - */ -- u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); -- u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); -+ u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); -+ u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); - u32 idx; - - if (COMP1_TX_ENABLED(comp1)) { -@@ -503,7 +507,7 @@ static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev, - struct resource *res, - const struct i2s_platform_data *pdata) - { -- u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); -+ u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); - u32 idx = COMP1_APB_DATA_WIDTH(comp1); - int ret; - -@@ -607,6 +611,14 @@ static int dw_i2s_probe(struct platform_device *pdev) - if (pdata) { - dev->capability = pdata->cap; - clk_id = NULL; -+ dev->quirks = pdata->quirks; -+ if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) { -+ dev->i2s_reg_comp1 = pdata->i2s_reg_comp1; -+ dev->i2s_reg_comp2 = pdata->i2s_reg_comp2; -+ } else { -+ dev->i2s_reg_comp1 = I2S_COMP_PARAM_1; -+ dev->i2s_reg_comp2 = I2S_COMP_PARAM_2; -+ } - ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata); - } else { - clk_id = "i2sclk"; --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1134-ASoC-dwc-reconfigure-dwc-in-resume-from-suspend.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1134-ASoC-dwc-reconfigure-dwc-in-resume-from-suspend.patch deleted file mode 100644 index 4ed5331c..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1134-ASoC-dwc-reconfigure-dwc-in-resume-from-suspend.patch +++ /dev/null @@ -1,141 +0,0 @@ -From ae2005698a4268461512386e741b489254e46915 Mon Sep 17 00:00:00 2001 -From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> -Date: Mon, 23 Nov 2015 20:08:21 +0530 -Subject: [PATCH 09/17] ASoC: dwc: reconfigure dwc in 'resume' from 'suspend' - -DWC IP can be powered off during system suspend in some platforms. -After system is resumed, dwc needs to be programmed again to continue -audio use case. - -Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> ---- - sound/soc/dwc/designware_i2s.c | 70 ++++++++++++++++++++++++++---------------- - 1 file changed, 43 insertions(+), 27 deletions(-) - -diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c -index 4f8f074..4e40a44 100644 ---- a/sound/soc/dwc/designware_i2s.c -+++ b/sound/soc/dwc/designware_i2s.c -@@ -98,6 +98,8 @@ struct dw_i2s_dev { - unsigned int i2s_reg_comp1; - unsigned int i2s_reg_comp2; - struct device *dev; -+ u32 ccr; -+ u32 xfer_resolution; - - /* data related to DMA transfers b/w i2s and DMAC */ - union dw_i2s_snd_dma_data play_dma_data; -@@ -217,31 +219,58 @@ static int dw_i2s_startup(struct snd_pcm_substream *substream, - return 0; - } - -+static void dw_i2s_config(struct dw_i2s_dev *dev, int stream) -+{ -+ u32 ch_reg, irq; -+ struct i2s_clk_config_data *config = &dev->config; -+ -+ -+ i2s_disable_channels(dev, stream); -+ -+ for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { -+ if (stream == SNDRV_PCM_STREAM_PLAYBACK) { -+ i2s_write_reg(dev->i2s_base, TCR(ch_reg), -+ dev->xfer_resolution); -+ i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); -+ irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); -+ i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); -+ i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); -+ } else { -+ i2s_write_reg(dev->i2s_base, RCR(ch_reg), -+ dev->xfer_resolution); -+ i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); -+ irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); -+ i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03); -+ i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); -+ } -+ -+ } -+} -+ - static int dw_i2s_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) - { - struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); - struct i2s_clk_config_data *config = &dev->config; -- u32 ccr, xfer_resolution, ch_reg, irq; - int ret; - - switch (params_format(params)) { - case SNDRV_PCM_FORMAT_S16_LE: - config->data_width = 16; -- ccr = 0x00; -- xfer_resolution = 0x02; -+ dev->ccr = 0x00; -+ dev->xfer_resolution = 0x02; - break; - - case SNDRV_PCM_FORMAT_S24_LE: - config->data_width = 24; -- ccr = 0x08; -- xfer_resolution = 0x04; -+ dev->ccr = 0x08; -+ dev->xfer_resolution = 0x04; - break; - - case SNDRV_PCM_FORMAT_S32_LE: - config->data_width = 32; -- ccr = 0x10; -- xfer_resolution = 0x05; -+ dev->ccr = 0x10; -+ dev->xfer_resolution = 0x05; - break; - - default: -@@ -262,27 +291,9 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream, - return -EINVAL; - } - -- i2s_disable_channels(dev, substream->stream); -+ dw_i2s_config(dev, substream->stream); - -- for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { -- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { -- i2s_write_reg(dev->i2s_base, TCR(ch_reg), -- xfer_resolution); -- i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); -- irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); -- i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); -- i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); -- } else { -- i2s_write_reg(dev->i2s_base, RCR(ch_reg), -- xfer_resolution); -- i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); -- irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); -- i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03); -- i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); -- } -- } -- -- i2s_write_reg(dev->i2s_base, CCR, ccr); -+ i2s_write_reg(dev->i2s_base, CCR, dev->ccr); - - config->sample_rate = params_rate(params); - -@@ -414,6 +425,11 @@ static int dw_i2s_resume(struct snd_soc_dai *dai) - - if (dev->capability & DW_I2S_MASTER) - clk_enable(dev->clk); -+ -+ if (dai->playback_active) -+ dw_i2s_config(dev, SNDRV_PCM_STREAM_PLAYBACK); -+ if (dai->capture_active) -+ dw_i2s_config(dev, SNDRV_PCM_STREAM_CAPTURE); - return 0; - } - --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1135-ASoC-dwc-add-quirk-to-override-COMP_PARAM_1-register.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1135-ASoC-dwc-add-quirk-to-override-COMP_PARAM_1-register.patch deleted file mode 100644 index 4458d8aa..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1135-ASoC-dwc-add-quirk-to-override-COMP_PARAM_1-register.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 686d42a81aa86027c0232dd7caf5f0ae2a0984b6 Mon Sep 17 00:00:00 2001 -From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> -Date: Wed, 6 Jan 2016 20:37:15 +0530 -Subject: [PATCH 10/17] ASoC: dwc: add quirk to override COMP_PARAM_1 register - -DWC for capture in ACP 2.x IP reports playback and capture capabilities -though it supports only capture. Added a quirk to override default value -to represent capture capability only. - -Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> ---- - sound/soc/dwc/designware_i2s.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c -index 4e40a44..20156b4 100644 ---- a/sound/soc/dwc/designware_i2s.c -+++ b/sound/soc/dwc/designware_i2s.c -@@ -483,6 +483,10 @@ static int dw_configure_dai(struct dw_i2s_dev *dev, - u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); - u32 idx; - -+ if (dev->capability & DWC_I2S_RECORD && -+ dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) -+ comp1 = comp1 & ~BIT(5); -+ - if (COMP1_TX_ENABLED(comp1)) { - dev_dbg(dev->dev, " designware: play supported\n"); - idx = COMP1_TX_WORDSIZE_0(comp1); --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1136-ALSA-Soc-RT286Codec-Modifications-to-ALSA-SOC-Audio.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1136-ALSA-Soc-RT286Codec-Modifications-to-ALSA-SOC-Audio.patch deleted file mode 100644 index 8e1a80c0..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1136-ALSA-Soc-RT286Codec-Modifications-to-ALSA-SOC-Audio.patch +++ /dev/null @@ -1,370 +0,0 @@ -From b4b235644a4e6a1d81da5c40dc492f1be70dcaeb Mon Sep 17 00:00:00 2001 -From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> -Date: Fri, 1 Jul 2016 13:33:43 +0530 -Subject: [PATCH 11/17] ALSA:Soc:RT286Codec :Modifications to ALSA SOC Audio - -Codec Driver. - -Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> -Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> ---- - sound/soc/codecs/rt286.c | 197 ++++++++++++++++++++++++++++++++++++++++------- - 1 file changed, 169 insertions(+), 28 deletions(-) - -diff --git a/sound/soc/codecs/rt286.c b/sound/soc/codecs/rt286.c -index af2ed77..c67317b 100644 ---- a/sound/soc/codecs/rt286.c -+++ b/sound/soc/codecs/rt286.c -@@ -19,6 +19,7 @@ - #include <linux/spi/spi.h> - #include <linux/dmi.h> - #include <linux/acpi.h> -+#include <linux/gpio.h> - #include <sound/core.h> - #include <sound/pcm.h> - #include <sound/pcm_params.h> -@@ -29,16 +30,14 @@ - #include <sound/jack.h> - #include <linux/workqueue.h> - #include <sound/rt286.h> -+#include <sound/hda_verbs.h> - --#include "rl6347a.h" - #include "rt286.h" - - #define RT286_VENDOR_ID 0x10ec0286 - #define RT288_VENDOR_ID 0x10ec0288 - - struct rt286_priv { -- struct reg_default *index_cache; -- int index_cache_size; - struct regmap *regmap; - struct snd_soc_codec *codec; - struct rt286_platform_data pdata; -@@ -47,9 +46,10 @@ struct rt286_priv { - struct delayed_work jack_detect_work; - int sys_clk; - int clk_id; -+ struct reg_default *index_cache; - }; - --static const struct reg_default rt286_index_def[] = { -+static struct reg_default rt286_index_def[] = { - { 0x01, 0xaaaa }, - { 0x02, 0x8aaa }, - { 0x03, 0x0002 }, -@@ -186,6 +186,94 @@ static bool rt286_readable_register(struct device *dev, unsigned int reg) - } - } - -+static int rt286_hw_write(void *context, unsigned int reg, unsigned int value) -+{ -+ struct i2c_client *client = context; -+ struct rt286_priv *rt286 = i2c_get_clientdata(client); -+ u8 data[4]; -+ int ret, i; -+ -+ /* handle index registers */ -+ if (reg <= 0xff) { -+ rt286_hw_write(client, RT286_COEF_INDEX, reg); -+ for (i = 0; i < INDEX_CACHE_SIZE; i++) { -+ if (reg == rt286->index_cache[i].reg) { -+ rt286->index_cache[i].def = value; -+ break; -+ } -+ -+ } -+ reg = RT286_PROC_COEF; -+ } -+ -+ data[0] = (reg >> 24) & 0xff; -+ data[1] = (reg >> 16) & 0xff; -+ /* -+ * 4 bit VID: reg should be 0 -+ * 12 bit VID: value should be 0 -+ * So we use an OR operator to handle it rather than use if condition. -+ */ -+ data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff); -+ data[3] = value & 0xff; -+ -+ ret = i2c_master_send(client, data, 4); -+ -+ if (ret == 4) -+ return 0; -+ else -+ pr_err("ret=%d\n", ret); -+ if (ret < 0) -+ return ret; -+ else -+ return -EIO; -+} -+ -+static int rt286_hw_read(void *context, unsigned int reg, unsigned int *value) -+{ -+ struct i2c_client *client = context; -+ struct i2c_msg xfer[2]; -+ int ret; -+ __be32 be_reg; -+ unsigned int index, vid, buf = 0x0; -+ -+ /* handle index registers */ -+ if (reg <= 0xff) { -+ rt286_hw_write(client, RT286_COEF_INDEX, reg); -+ reg = RT286_PROC_COEF; -+ } -+ -+ reg = reg | 0x80000; -+ vid = (reg >> 8) & 0xfff; -+ -+ if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) { -+ index = (reg >> 8) & 0xf; -+ reg = (reg & ~0xf0f) | index; -+ } -+ be_reg = cpu_to_be32(reg); -+ -+ /* Write register */ -+ xfer[0].addr = client->addr; -+ xfer[0].flags = 0; -+ xfer[0].len = 4; -+ xfer[0].buf = (u8 *)&be_reg; -+ -+ /* Read data */ -+ xfer[1].addr = client->addr; -+ xfer[1].flags = I2C_M_RD; -+ xfer[1].len = 4; -+ xfer[1].buf = (u8 *)&buf; -+ -+ ret = i2c_transfer(client->adapter, xfer, 2); -+ if (ret < 0) -+ return ret; -+ else if (ret != 2) -+ return -EIO; -+ -+ *value = be32_to_cpu(buf); -+ -+ return 0; -+} -+ - #ifdef CONFIG_PM - static void rt286_index_sync(struct snd_soc_codec *codec) - { -@@ -272,6 +360,15 @@ static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic) - *hp = buf & 0x80000000; - regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf); - *mic = buf & 0x80000000; -+ if (*mic) { -+ regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24); -+ msleep(50); -+ -+ regmap_update_bits(rt286->regmap, -+ RT286_CBJ_CTRL1, -+ 0xfcc0, 0xd400); -+ msleep(300); -+ } - } - - snd_soc_dapm_disable_pin(dapm, "HV"); -@@ -695,6 +792,7 @@ static int rt286_hw_params(struct snd_pcm_substream *substream, - unsigned int val = 0; - int d_len_code; - -+ pr_err("%s : rate : %d clk %d ch %d width %d\n",__func__,params_rate(params),rt286->sys_clk, params_channels(params), params_width(params)); - switch (params_rate(params)) { - /* bit 14 0:48K 1:44.1K */ - case 44100: -@@ -763,7 +861,8 @@ static int rt286_hw_params(struct snd_pcm_substream *substream, - - snd_soc_update_bits(codec, - RT286_I2S_CTRL1, 0x0018, d_len_code << 3); -- dev_dbg(codec->dev, "format val = 0x%x\n", val); -+ //dev_dbg(codec->dev, "format val = 0x%x\n", val); -+ pr_err("format val = 0x%x\n", val); - - snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val); - snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val); -@@ -927,6 +1026,7 @@ static int rt286_set_bias_level(struct snd_soc_codec *codec, - default: - break; - } -+ //codec->dapm.bias_level = level; - - return 0; - } -@@ -992,7 +1092,6 @@ static int rt286_suspend(struct snd_soc_codec *codec) - - regcache_cache_only(rt286->regmap, true); - regcache_mark_dirty(rt286->regmap); -- - return 0; - } - -@@ -1003,7 +1102,6 @@ static int rt286_resume(struct snd_soc_codec *codec) - regcache_cache_only(rt286->regmap, false); - rt286_index_sync(codec); - regcache_sync(rt286->regmap); -- - return 0; - } - #else -@@ -1013,7 +1111,8 @@ static int rt286_resume(struct snd_soc_codec *codec) - - #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) - #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ -- SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) -+ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) | \ -+ SNDRV_PCM_FMTBIT_S32_LE - - static const struct snd_soc_dai_ops rt286_aif_dai_ops = { - .hw_params = rt286_hw_params, -@@ -1087,8 +1186,8 @@ static const struct regmap_config rt286_regmap = { - .max_register = 0x02370100, - .volatile_reg = rt286_volatile_register, - .readable_reg = rt286_readable_register, -- .reg_write = rl6347a_hw_write, -- .reg_read = rl6347a_hw_read, -+ .reg_write = rt286_hw_write, -+ .reg_read = rt286_hw_read, - .cache_type = REGCACHE_RBTREE, - .reg_defaults = rt286_reg, - .num_reg_defaults = ARRAY_SIZE(rt286_reg), -@@ -1103,11 +1202,12 @@ MODULE_DEVICE_TABLE(i2c, rt286_i2c_id); - - static const struct acpi_device_id rt286_acpi_match[] = { - { "INT343A", 0 }, -+ { "RTK0000", 0}, - {}, - }; - MODULE_DEVICE_TABLE(acpi, rt286_acpi_match); - --static const struct dmi_system_id force_combo_jack_table[] = { -+static struct dmi_system_id force_combo_jack_table[] = { - { - .ident = "Intel Wilson Beach", - .matches = { -@@ -1117,7 +1217,7 @@ static const struct dmi_system_id force_combo_jack_table[] = { - { } - }; - --static const struct dmi_system_id dmi_dell_dino[] = { -+static struct dmi_system_id dmi_dell_dino[] = { - { - .ident = "Dell Dino", - .matches = { -@@ -1128,13 +1228,53 @@ static const struct dmi_system_id dmi_dell_dino[] = { - { } - }; - -+static struct rt286_platform_data rt286_acpi_data = { -+ .cbj_en = false, -+ .gpio2_en = false, -+}; -+ -+#if defined(CONFIG_ACPI) && defined(CONFIG_GPIOLIB) -+ -+static int get_gpio_irq(struct acpi_resource *ares, void *data) -+{ -+ if ((ares->type == ACPI_RESOURCE_GPIO_TYPE_INT) || -+ (ares->type == ACPI_RESOURCE_TYPE_GPIO)) { -+ int *irq = data; -+ *irq = gpio_to_irq(ares->data.gpio.pin_table[0]); -+ } -+ return 1; -+} -+ -+static int acpi_get_gpio_irq_res(struct device *idev) -+{ -+ int irq; -+ struct acpi_device *adev; -+ struct list_head resource_list; -+ acpi_handle handle; -+ -+ INIT_LIST_HEAD(&resource_list); -+ handle = ACPI_HANDLE(idev); -+ -+ if (!handle || acpi_bus_get_device(handle, &adev)) -+ return -ENODEV; -+ -+ acpi_dev_get_resources(adev, &resource_list, -+ get_gpio_irq, &irq); -+ acpi_dev_free_resource_list(&resource_list); -+ -+ return irq; -+} -+ -+#endif -+ - static int rt286_i2c_probe(struct i2c_client *i2c, - const struct i2c_device_id *id) - { -- struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev); -+ struct rt286_platform_data *pdata = &rt286_acpi_data; - struct rt286_priv *rt286; - int i, ret, val; - -+ pr_err("%s : called\n",__func__); - rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286), - GFP_KERNEL); - if (NULL == rt286) -@@ -1156,16 +1296,11 @@ static int rt286_i2c_probe(struct i2c_client *i2c, - } - if (val != RT286_VENDOR_ID && val != RT288_VENDOR_ID) { - dev_err(&i2c->dev, -- "Device with ID register %#x is not rt286\n", val); -+ "Device with ID register %x is not rt286\n", val); - return -ENODEV; - } - -- rt286->index_cache = devm_kmemdup(&i2c->dev, rt286_index_def, -- sizeof(rt286_index_def), GFP_KERNEL); -- if (!rt286->index_cache) -- return -ENOMEM; -- -- rt286->index_cache_size = INDEX_CACHE_SIZE; -+ rt286->index_cache = rt286_index_def; - rt286->i2c = i2c; - i2c_set_clientdata(i2c, rt286); - -@@ -1231,19 +1366,24 @@ static int rt286_i2c_probe(struct i2c_client *i2c, - RT286_GPIO_CTRL, 0xc, 0x8); - } - -- if (rt286->i2c->irq) { -- ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq, -- IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286); -- if (ret != 0) { -- dev_err(&i2c->dev, -- "Failed to reguest IRQ: %d\n", ret); -- return ret; -- } -+ if (rt286->i2c->irq < 0) { -+ rt286->i2c->irq = acpi_get_gpio_irq_res(&rt286->i2c->dev); -+ if (rt286->i2c->irq < 0) -+ return -ENODEV; -+ } -+ ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq, -+ IRQF_TRIGGER_RISING | IRQF_ONESHOT, "rt286", rt286); -+ if (ret != 0) { -+ dev_err(&i2c->dev, -+ "Failed to reguest IRQ: %d\n", ret); -+ return ret; - } - - ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286, - rt286_dai, ARRAY_SIZE(rt286_dai)); - -+ pr_err("%s : ret = %d\n",__func__,ret); -+ - return ret; - } - -@@ -1262,6 +1402,7 @@ static int rt286_i2c_remove(struct i2c_client *i2c) - static struct i2c_driver rt286_i2c_driver = { - .driver = { - .name = "rt286", -+ .owner = THIS_MODULE, - .acpi_match_table = ACPI_PTR(rt286_acpi_match), - }, - .probe = rt286_i2c_probe, --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1137-drm-amdgpu-acp-fix-resume-on-CZ-systems-with-AZ-audi.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1137-drm-amdgpu-acp-fix-resume-on-CZ-systems-with-AZ-audi.patch deleted file mode 100644 index 2c2739b9..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1137-drm-amdgpu-acp-fix-resume-on-CZ-systems-with-AZ-audi.patch +++ /dev/null @@ -1,31 +0,0 @@ -From c0e62d528ca2557326eedc2f43460b6f4afcdf7b Mon Sep 17 00:00:00 2001 -From: Alex Deucher <alexander.deucher@amd.com> -Date: Wed, 13 Apr 2016 23:37:42 -0400 -Subject: [PATCH 17/17] drm/amdgpu/acp: fix resume on CZ systems with AZ audio - -Nothing to do on resume on systems with AZ audio. - -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -index 37ecc36..6549b3c 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -@@ -427,6 +427,10 @@ static int acp_resume(void *handle) - struct acp_pm_domain *apd; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - -+ /* return early if no ACP */ -+ if (!adev->acp.acp_genpd) -+ return 0; -+ - /* SMU block will power on ACP irrespective of ACP runtime status. - * Power off explicitly based on genpd ACP runtime status so that ACP - * hw and ACP-genpd status are in sync. --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1138-add-new-semaphore-object-in-kernel-side.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1138-add-new-semaphore-object-in-kernel-side.patch deleted file mode 100644 index f27f1afc..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1138-add-new-semaphore-object-in-kernel-side.patch +++ /dev/null @@ -1,504 +0,0 @@ -From d29a89414316f4c54a1a619527398714b091d3db Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Mon, 14 Nov 2016 12:26:18 +0530 -Subject: [PATCH] add new semaphore object in kernel side - -So that semaphore can be shared across porcess across devices. - -Change-Id: Ie82cace6af81e2ddf45f4bbf9f3c0dafd6bcc499 -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- - drivers/gpu/drm/amd/amdgpu/amdgpu.h | 11 + - drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- - drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 6 +- - drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +- - drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c | 267 ++++++++++++++++++++++ - drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h | 44 ++++ - drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 29 +++ - 8 files changed, 361 insertions(+), 4 deletions(-) - create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c - create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h - -diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile -index 28e8e4c..2acc7c1 100644 ---- a/drivers/gpu/drm/amd/amdgpu/Makefile -+++ b/drivers/gpu/drm/amd/amdgpu/Makefile -@@ -31,7 +31,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ - amdgpu_pm.o atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \ - atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ - amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ -- amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o -+ amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \ -+ amdgpu_sem.o - - # add asic specific block - amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -index d3de21d..3f5d2ad 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -@@ -1000,6 +1000,8 @@ struct amdgpu_ctx_ring { - uint64_t sequence; - struct fence **fences; - struct amd_sched_entity entity; -+ struct list_head sem_list; -+ struct mutex sem_lock; - /* client id */ - u64 client_id; - }; -@@ -1699,6 +1701,8 @@ struct amdgpu_vce { - struct amdgpu_irq_src irq; - unsigned harvest_config; - struct amd_sched_entity entity; -+ struct list_head sem_list; -+ struct mutex sem_lock; - }; - - /* -@@ -1872,6 +1876,13 @@ int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, - int amdgpu_freesync_ioctl(struct drm_device *dev, void *data, - struct drm_file *filp); - -+int amdgpu_sem_ioctl(struct drm_device *dev, void *data, -+ struct drm_file *filp); -+ -+int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, -+ struct amdgpu_sync *sync); -+ -+ - /* VRAM scratch page for HDP bug, default vram page */ - struct amdgpu_vram_scratch { - struct amdgpu_bo *robj; -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c -index 0d1346c..bb6057a 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c -@@ -882,7 +882,7 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev, - } - } - -- return 0; -+ return amdgpu_sem_add_cs(p->ctx, p->job->ring, &p->job->sync); - } - - static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c -index 17e1362..a020e22 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c -@@ -42,6 +42,8 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx) - for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { - ctx->rings[i].sequence = 1; - ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i]; -+ INIT_LIST_HEAD(&ctx->rings[i].sem_list); -+ mutex_init(&ctx->rings[i].sem_lock); - } - /* create context entity for each ring */ - for (i = 0; i < adev->num_rings; i++) { -@@ -74,8 +76,10 @@ static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) - return; - - for (i = 0; i < AMDGPU_MAX_RINGS; ++i) -- for (j = 0; j < amdgpu_sched_jobs; ++j) -+ for (j = 0; j < amdgpu_sched_jobs; ++j) { - fence_put(ctx->rings[i].fences[j]); -+ mutex_destroy(&ctx->rings[i].sem_lock); -+ } - kfree(ctx->fences); - - for (i = 0; i < adev->num_rings; i++) -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -index f6ae587..a48783e 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -@@ -786,6 +786,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { - DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), -- DRM_IOCTL_DEF_DRV(AMDGPU_FREESYNC, amdgpu_freesync_ioctl, DRM_MASTER) -+ DRM_IOCTL_DEF_DRV(AMDGPU_FREESYNC, amdgpu_freesync_ioctl, DRM_MASTER), -+ DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - }; - const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c -new file mode 100644 -index 0000000..db16baa ---- /dev/null -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c -@@ -0,0 +1,267 @@ -+/* -+ * Copyright 2016 Advanced Micro Devices, Inc. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included in -+ * all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ * -+ * Authors: -+ * Chunming Zhou <david1.zhou@amd.com> -+ */ -+#include <linux/file.h> -+#include <linux/fs.h> -+#include <linux/kernel.h> -+#include <linux/poll.h> -+#include <linux/seq_file.h> -+#include <linux/export.h> -+#include <linux/sched.h> -+#include <linux/slab.h> -+#include <linux/uaccess.h> -+#include <linux/anon_inodes.h> -+#include "amdgpu_sem.h" -+#include "amdgpu.h" -+#include <drm/drmP.h> -+ -+static int amdgpu_sem_cring_add(struct amdgpu_fpriv *fpriv, -+ struct drm_amdgpu_sem_in *in, -+ struct amdgpu_sem *sem); -+ -+static const struct file_operations amdgpu_sem_fops; -+ -+static struct amdgpu_sem *amdgpu_sem_alloc(struct fence *fence) -+{ -+ struct amdgpu_sem *sem; -+ -+ sem = kzalloc(sizeof(struct amdgpu_sem), GFP_KERNEL); -+ if (!sem) -+ return NULL; -+ -+ sem->file = anon_inode_getfile("sem_file", -+ &amdgpu_sem_fops, -+ sem, 0); -+ if (IS_ERR(sem->file)) -+ goto err; -+ -+ kref_init(&sem->kref); -+ INIT_LIST_HEAD(&sem->list); -+ /* fence should be get before passing here */ -+ sem->fence = fence; -+ -+ return sem; -+err: -+ kfree(sem); -+ return NULL; -+} -+ -+static void amdgpu_sem_free(struct kref *kref) -+{ -+ struct amdgpu_sem *sem = container_of( -+ kref, struct amdgpu_sem, kref); -+ -+ fence_put(sem->fence); -+ kfree(sem); -+} -+ -+static int amdgpu_sem_release(struct inode *inode, struct file *file) -+{ -+ struct amdgpu_sem *sem = file->private_data; -+ -+ kref_put(&sem->kref, amdgpu_sem_free); -+ return 0; -+} -+ -+static unsigned int amdgpu_sem_poll(struct file *file, poll_table *wait) -+{ -+ return 0; -+} -+ -+static long amdgpu_sem_file_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ return 0; -+} -+ -+static const struct file_operations amdgpu_sem_fops = { -+ .release = amdgpu_sem_release, -+ .poll = amdgpu_sem_poll, -+ .unlocked_ioctl = amdgpu_sem_file_ioctl, -+ .compat_ioctl = amdgpu_sem_file_ioctl, -+}; -+ -+static int amdgpu_sem_create(void) -+{ -+ return get_unused_fd_flags(O_CLOEXEC); -+} -+ -+static int amdgpu_sem_signal(int fd, struct fence *fence) -+{ -+ struct amdgpu_sem *sem; -+ -+ sem = amdgpu_sem_alloc(fence); -+ if (!sem) -+ return -ENOMEM; -+ fd_install(fd, sem->file); -+ -+ return 0; -+} -+ -+static int amdgpu_sem_wait(int fd, struct amdgpu_fpriv *fpriv, -+ struct drm_amdgpu_sem_in *in) -+{ -+ struct file *file = fget(fd); -+ struct amdgpu_sem *sem; -+ int r; -+ -+ if (!file) -+ return -EINVAL; -+ -+ sem = file->private_data; -+ if (!sem) { -+ r = -EINVAL; -+ goto err; -+ } -+ r = amdgpu_sem_cring_add(fpriv, in, sem); -+err: -+ fput(file); -+ return r; -+} -+ -+static void amdgpu_sem_destroy(void) -+{ -+ /* userspace should close fd when they try to destroy sem, -+ * closing fd will free semaphore object. -+ */ -+} -+ -+static struct fence *amdgpu_sem_get_fence(struct amdgpu_fpriv *fpriv, -+ struct drm_amdgpu_sem_in *in) -+{ -+ struct amdgpu_ring *out_ring; -+ struct amdgpu_ctx *ctx; -+ struct fence *fence; -+ uint32_t ctx_id, ip_type, ip_instance, ring; -+ int r; -+ -+ ctx_id = in->ctx_id; -+ ip_type = in->ip_type; -+ ip_instance = in->ip_instance; -+ ring = in->ring; -+ ctx = amdgpu_ctx_get(fpriv, ctx_id); -+ if (!ctx) -+ return NULL; -+ r = amdgpu_cs_get_ring(ctx->adev, ip_type, ip_instance, ring, -+ &out_ring); -+ if (r) { -+ amdgpu_ctx_put(ctx); -+ return NULL; -+ } -+ /* get the last fence of this entity */ -+ fence = amdgpu_ctx_get_fence(ctx, out_ring, -+ in->seq ? in->seq : -+ ctx->rings[out_ring->idx].sequence - 1); -+ amdgpu_ctx_put(ctx); -+ -+ return fence; -+} -+ -+static int amdgpu_sem_cring_add(struct amdgpu_fpriv *fpriv, -+ struct drm_amdgpu_sem_in *in, -+ struct amdgpu_sem *sem) -+{ -+ struct amdgpu_ring *out_ring; -+ struct amdgpu_ctx *ctx; -+ uint32_t ctx_id, ip_type, ip_instance, ring; -+ int r; -+ -+ ctx_id = in->ctx_id; -+ ip_type = in->ip_type; -+ ip_instance = in->ip_instance; -+ ring = in->ring; -+ ctx = amdgpu_ctx_get(fpriv, ctx_id); -+ if (!ctx) -+ return -EINVAL; -+ r = amdgpu_cs_get_ring(ctx->adev, ip_type, ip_instance, ring, -+ &out_ring); -+ if (r) -+ goto err; -+ mutex_lock(&ctx->rings[out_ring->idx].sem_lock); -+ list_add(&sem->list, &ctx->rings[out_ring->idx].sem_list); -+ mutex_unlock(&ctx->rings[out_ring->idx].sem_lock); -+ -+err: -+ amdgpu_ctx_put(ctx); -+ return r; -+} -+ -+int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, -+ struct amdgpu_sync *sync) -+{ -+ struct amdgpu_sem *sem, *tmp; -+ int r = 0; -+ -+ if (list_empty(&ctx->rings[ring->idx].sem_list)) -+ return 0; -+ -+ mutex_lock(&ctx->rings[ring->idx].sem_lock); -+ list_for_each_entry_safe(sem, tmp, &ctx->rings[ring->idx].sem_list, -+ list) { -+ r = amdgpu_sync_fence(ctx->adev, sync, sem->fence); -+ fence_put(sem->fence); -+ if (r) -+ goto err; -+ list_del(&sem->list); -+ kfree(sem); -+ } -+err: -+ mutex_unlock(&ctx->rings[ring->idx].sem_lock); -+ return r; -+} -+ -+int amdgpu_sem_ioctl(struct drm_device *dev, void *data, -+ struct drm_file *filp) -+{ -+ union drm_amdgpu_sem *args = data; -+ struct amdgpu_fpriv *fpriv = filp->driver_priv; -+ struct fence *fence; -+ int r = 0; -+ int fd = args->in.fd; -+ -+ switch (args->in.op) { -+ case AMDGPU_SEM_OP_CREATE_SEM: -+ args->out.fd = amdgpu_sem_create(); -+ break; -+ case AMDGPU_SEM_OP_WAIT_SEM: -+ r = amdgpu_sem_wait(fd, fpriv, &args->in); -+ break; -+ case AMDGPU_SEM_OP_SIGNAL_SEM: -+ fence = amdgpu_sem_get_fence(fpriv, &args->in); -+ if (IS_ERR(fence)) { -+ r = PTR_ERR(fence); -+ return r; -+ } -+ r = amdgpu_sem_signal(fd, fence); -+ fence_put(fence); -+ break; -+ case AMDGPU_SEM_OP_DESTROY_SEM: -+ amdgpu_sem_destroy(); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return r; -+} -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h -new file mode 100644 -index 0000000..56d59d3 ---- /dev/null -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h -@@ -0,0 +1,44 @@ -+/* -+ * Copyright 2016 Advanced Micro Devices, Inc. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included in -+ * all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ * -+ * Authors: Chunming Zhou <david1.zhou@amd.com> -+ * -+ */ -+ -+ -+#ifndef _LINUX_AMDGPU_SEM_H -+#define _LINUX_AMDGPU_SEM_H -+ -+#include <linux/types.h> -+#include <linux/kref.h> -+#include <linux/ktime.h> -+#include <linux/list.h> -+#include <linux/spinlock.h> -+#include <linux/fence.h> -+ -+struct amdgpu_sem { -+ struct file *file; -+ struct kref kref; -+ struct fence *fence; -+ struct list_head list; -+}; -+ -+#endif /* _LINUX_AMDGPU_SEM_H */ -diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -index b06e3dc..65153bf 100644 ---- a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -+++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -@@ -46,6 +46,7 @@ - #define DRM_AMDGPU_WAIT_CS 0x09 - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 -+#define DRM_AMDGPU_SEM 0x5b - #define DRM_AMDGPU_FREESYNC 0x14 - - #define DRM_AMDGPU_WAIT_FENCES 0x5e -@@ -64,6 +65,7 @@ - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) -+#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) - - #define AMDGPU_GEM_DOMAIN_CPU 0x1 - #define AMDGPU_GEM_DOMAIN_GTT 0x2 -@@ -185,6 +187,33 @@ union drm_amdgpu_ctx { - union drm_amdgpu_ctx_out out; - }; - -+/* sem related */ -+#define AMDGPU_SEM_OP_CREATE_SEM 1 -+#define AMDGPU_SEM_OP_WAIT_SEM 2 -+#define AMDGPU_SEM_OP_SIGNAL_SEM 3 -+#define AMDGPU_SEM_OP_DESTROY_SEM 4 -+ -+struct drm_amdgpu_sem_in { -+ /** AMDGPU_SEM_OP_* */ -+ uint32_t op; -+ int32_t fd; -+ uint32_t ctx_id; -+ uint32_t ip_type; -+ uint32_t ip_instance; -+ uint32_t ring; -+ uint64_t seq; -+}; -+ -+union drm_amdgpu_sem_out { -+ int32_t fd; -+ uint32_t _pad; -+}; -+ -+union drm_amdgpu_sem { -+ struct drm_amdgpu_sem_in in; -+ union drm_amdgpu_sem_out out; -+}; -+ - /* - * This is not a reliable API and you should expect it to fail for any - * number of reasons and have fallback path that do not use userptr to --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1139-unify-memory-query-info-interface.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1139-unify-memory-query-info-interface.patch deleted file mode 100644 index b7c965a3..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1139-unify-memory-query-info-interface.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 314642915b4a2bda146fb9d900ca99eabeab36c0 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Mon, 14 Nov 2016 12:13:41 +0530 -Subject: [PATCH 01/10] unify memory query info interface -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I74d2b7379bc4febe714a91daf4e1786895de90f2 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Marek Olšák <marek.olsak@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 32 +++++++++++++++++++++++ - drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 32 +++++++++++++++++++++++ - 2 files changed, 64 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -index 31c20ba..a48783e 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c -@@ -390,6 +390,38 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file - return copy_to_user(out, &vram_gtt, - min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; - } -+ -+ case AMDGPU_INFO_MEMORY: { -+ struct drm_amdgpu_memory_info mem; -+ -+ memset(&mem, 0, sizeof(mem)); -+ mem.vram.total_heap_size = adev->mc.real_vram_size; -+ mem.vram.usable_heap_size = -+ adev->mc.real_vram_size - adev->vram_pin_size; -+ mem.vram.heap_usage = atomic64_read(&adev->vram_usage); -+ mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; -+ -+ mem.cpu_accessible_vram.total_heap_size = -+ adev->mc.visible_vram_size; -+ mem.cpu_accessible_vram.usable_heap_size = -+ adev->mc.visible_vram_size - -+ (adev->vram_pin_size - adev->invisible_pin_size); -+ mem.cpu_accessible_vram.heap_usage = -+ atomic64_read(&adev->vram_vis_usage); -+ mem.cpu_accessible_vram.max_allocation = -+ mem.cpu_accessible_vram.usable_heap_size * 3 / 4; -+ -+ mem.gtt.total_heap_size = adev->mc.gtt_size; -+ mem.gtt.usable_heap_size = -+ adev->mc.gtt_size - adev->gart_pin_size; -+ mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage); -+ mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; -+ -+ return copy_to_user(out, &mem, -+ min((size_t)size, sizeof(mem))) -+ ? -EFAULT : 0; -+ } -+ - case AMDGPU_INFO_READ_MMR_REG: { - unsigned n, alloc_size; - uint32_t *regs; -diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -index 4d7d982..3f13a87 100644 ---- a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -+++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -@@ -540,6 +540,10 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 - /* virtual range */ - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 -+ -+/* Query memory about VRAM and GTT domains */ -+#define AMDGPU_INFO_MEMORY 0x19 -+ - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 - /* query pin memory capability */ -@@ -705,6 +709,34 @@ struct drm_amdgpu_info_hw_ip { - __u32 _pad; - }; - -+struct drm_amdgpu_heap_info { -+ /** max. physical memory */ -+ __u64 total_heap_size; -+ -+ /** Theoretical max. available memory in the given heap */ -+ __u64 usable_heap_size; -+ -+ /** -+ * Number of bytes allocated in the heap. This includes all processes -+ * and private allocations in the kernel. It changes when new buffers -+ * are allocated, freed, and moved. It cannot be larger than -+ * heap_size. -+ */ -+ __u64 heap_usage; -+ -+ /** -+ * Theoretical possible max. size of buffer which -+ * could be allocated in the given heap -+ */ -+ __u64 max_allocation; -+}; -+ -+struct drm_amdgpu_memory_info { -+ struct drm_amdgpu_heap_info vram; -+ struct drm_amdgpu_heap_info cpu_accessible_vram; -+ struct drm_amdgpu_heap_info gtt; -+}; -+ - /* - * Supported GPU families - */ --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1140-dma-buf-return-index-of-the-first-signaled-fence.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1140-dma-buf-return-index-of-the-first-signaled-fence.patch deleted file mode 100644 index 76815764..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1140-dma-buf-return-index-of-the-first-signaled-fence.patch +++ /dev/null @@ -1,188 +0,0 @@ -From 7e06443930ab2fabda1977c20ff82ff6bc42e3be Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Tue, 15 Nov 2016 14:30:58 +0530 -Subject: [PATCH 02/10] dma-buf: return index of the first signaled fence - -Return the index of the first signaled fence. This information -is useful in some APIs like Vulkan. - -Signed-off-by: monk.liu <monk.liu@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Cc: Sumit Semwal <sumit.semwal@linaro.org> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/dma-buf/fence.c | 19 ++++++++++++++----- - drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 +++- - drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c | 2 +- - drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 21 +++++++++++---------- - include/linux/fence.h | 2 +- - 5 files changed, 30 insertions(+), 18 deletions(-) - -diff --git a/drivers/dma-buf/fence.c b/drivers/dma-buf/fence.c -index 7b05dbe..192f99b 100644 ---- a/drivers/dma-buf/fence.c -+++ b/drivers/dma-buf/fence.c -@@ -398,14 +398,17 @@ out: - EXPORT_SYMBOL(fence_default_wait); - - static bool --fence_test_signaled_any(struct fence **fences, uint32_t count) -+fence_test_signaled_any(struct fence **fences, uint32_t count, uint32_t *idx) - { - int i; - - for (i = 0; i < count; ++i) { - struct fence *fence = fences[i]; -- if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags)) -+ if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { -+ if (idx) -+ *idx = i; - return true; -+ } - } - return false; - } -@@ -417,6 +420,7 @@ fence_test_signaled_any(struct fence **fences, uint32_t count) - * @count: [in] number of fences to wait on - * @intr: [in] if true, do an interruptible wait - * @timeout: [in] timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT -+ * @idx: [out] the first signaled fence index, meaninful only on Returns positive - * - * Returns -EINVAL on custom fence wait implementation, -ERESTARTSYS if - * interrupted, 0 if the wait timed out, or the remaining timeout in jiffies -@@ -428,7 +432,7 @@ fence_test_signaled_any(struct fence **fences, uint32_t count) - */ - signed long - fence_wait_any_timeout(struct fence **fences, uint32_t count, -- bool intr, signed long timeout) -+ bool intr, signed long timeout, uint32_t *idx) - { - struct default_wait_cb *cb; - signed long ret = timeout; -@@ -439,8 +443,11 @@ fence_wait_any_timeout(struct fence **fences, uint32_t count, - - if (timeout == 0) { - for (i = 0; i < count; ++i) -- if (fence_is_signaled(fences[i])) -+ if (fence_is_signaled(fences[i])) { -+ if (idx) -+ *idx = i; - return 1; -+ } - - return 0; - } -@@ -463,6 +470,8 @@ fence_wait_any_timeout(struct fence **fences, uint32_t count, - if (fence_add_callback(fence, &cb[i].base, - fence_default_wait_cb)) { - /* This fence is already signaled */ -+ if (idx) -+ *idx = i; - goto fence_rm_cb; - } - } -@@ -473,7 +482,7 @@ fence_wait_any_timeout(struct fence **fences, uint32_t count, - else - set_current_state(TASK_UNINTERRUPTIBLE); - -- if (fence_test_signaled_any(fences, count)) -+ if (fence_test_signaled_any(fences, count, idx)) - break; - - ret = schedule_timeout(ret); -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c -index bb6057a..181e2b7 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c -@@ -1107,6 +1107,7 @@ static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev, - { - unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns); - uint32_t fence_count = wait->in.fence_count; -+ uint32_t first = ~0; - struct fence **array; - unsigned i; - long r; -@@ -1132,13 +1133,14 @@ static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev, - } - } - -- r = fence_wait_any_timeout(array, fence_count, true, timeout); -+ r = fence_wait_any_timeout(array, fence_count, true, timeout, &first); - if (r < 0) - goto err_free_fence_array; - - out: - memset(wait, 0, sizeof(*wait)); - wait->out.status = (r > 0); -+ wait->out.first_signaled = first; - /* set return value 0 to indicate success */ - r = 0; - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c -index 8bf84ef..9f4311c 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c -@@ -360,7 +360,7 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, - if (count) { - spin_unlock(&sa_manager->wq.lock); - t = fence_wait_any_timeout(fences, count, false, -- MAX_SCHEDULE_TIMEOUT); -+ MAX_SCHEDULE_TIMEOUT, NULL); - for (i = 0; i < count; ++i) - fence_put(fences[i]); - -diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -index 3f13a87..c2f06eb 100644 ---- a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -+++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h -@@ -334,23 +334,24 @@ union drm_amdgpu_wait_cs { - }; - - struct drm_amdgpu_fence { -- uint32_t ctx_id; -- uint32_t ip_type; -- uint32_t ip_instance; -- uint32_t ring; -- uint64_t seq_no; -+ __u32 ctx_id; -+ __u32 ip_type; -+ __u32 ip_instance; -+ __u32 ring; -+ __u64 seq_no; - }; - - struct drm_amdgpu_wait_fences_in { - /** This points to uint64_t * which points to fences */ -- uint64_t fences; -- uint32_t fence_count; -- uint32_t wait_all; -- uint64_t timeout_ns; -+ __u64 fences; -+ __u32 fence_count; -+ __u32 wait_all; -+ __u64 timeout_ns; - }; - - struct drm_amdgpu_wait_fences_out { -- uint64_t status; -+ __u32 status; -+ __u32 first_signaled; - }; - - union drm_amdgpu_wait_fences { -diff --git a/include/linux/fence.h b/include/linux/fence.h -index bb52201..b8da489 100644 ---- a/include/linux/fence.h -+++ b/include/linux/fence.h -@@ -322,7 +322,7 @@ static inline struct fence *fence_later(struct fence *f1, struct fence *f2) - - signed long fence_wait_timeout(struct fence *, bool intr, signed long timeout); - signed long fence_wait_any_timeout(struct fence **fences, uint32_t count, -- bool intr, signed long timeout); -+ bool intr, signed long timeout, uint32_t *idx); - - /** - * fence_wait - sleep until the fence gets signaled --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1142-add-additional-cached-gca-config-variables.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1142-add-additional-cached-gca-config-variables.patch deleted file mode 100644 index c9c426f9..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1142-add-additional-cached-gca-config-variables.patch +++ /dev/null @@ -1,51 +0,0 @@ -From caa6b72d0c01491114f017fe3bca7adc05194611 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Tue, 6 Dec 2016 17:07:10 +0530 -Subject: [PATCH 04/10] add additional cached gca config variables -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -We need to cache some additional values to handle SR-IOV -and PG. - -Reviewed-by: Christian König <christian.koenig@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -index 3f5d2ad..40497c2 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -@@ -1135,6 +1135,16 @@ struct amdgpu_scratch { - /* - * GFX configurations - */ -+#define AMDGPU_GFX_MAX_SE 4 -+#define AMDGPU_GFX_MAX_SH_PER_SE 2 -+ -+struct amdgpu_rb_config { -+ uint32_t rb_backend_disable; -+ uint32_t user_rb_backend_disable; -+ uint32_t raster_config; -+ uint32_t raster_config_1; -+}; -+ - struct amdgpu_gca_config { - unsigned max_shader_engines; - unsigned max_tile_pipes; -@@ -1163,6 +1173,8 @@ struct amdgpu_gca_config { - - uint32_t tile_mode_array[32]; - uint32_t macrotile_mode_array[16]; -+ -+ struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; - }; - - struct amdgpu_gfx { --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1143-implement-raster-configuration-for-gfx-v8.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1143-implement-raster-configuration-for-gfx-v8.patch deleted file mode 100644 index c1a271f2..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1143-implement-raster-configuration-for-gfx-v8.patch +++ /dev/null @@ -1,262 +0,0 @@ -From 705f105de150240594945703df70f82d5ab861ce Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Tue, 6 Dec 2016 19:33:01 +0530 -Subject: [PATCH 05/10] implement raster configuration for gfx v8 - -This patch is to implement the raster configuration and harvested -configuration of gfx v8. - -Signed-off-by: Huang Rui <ray.huang@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 168 +++++++++++++++++++++++++++++++++- - drivers/gpu/drm/amd/amdgpu/vid.h | 37 ++++++++ - 2 files changed, 204 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -index c5a3d04..20ac07f 100644 ---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -@@ -3484,13 +3484,163 @@ static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev) - return (~data) & mask; - } - -+static void -+gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) -+{ -+ switch (adev->asic_type) { -+ case CHIP_FIJI: -+ *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) | -+ RB_XSEL2(1) | PKR_MAP(2) | -+ PKR_XSEL(1) | PKR_YSEL(1) | -+ SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3); -+ *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) | -+ SE_PAIR_YSEL(2); -+ break; -+ case CHIP_TONGA: -+ case CHIP_POLARIS10: -+ *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | -+ SE_XSEL(1) | SE_YSEL(1); -+ *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) | -+ SE_PAIR_YSEL(2); -+ break; -+ case CHIP_TOPAZ: -+ case CHIP_CARRIZO: -+ *rconf |= RB_MAP_PKR0(2); -+ *rconf1 |= 0x0; -+ break; -+ case CHIP_POLARIS11: -+ *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | -+ SE_XSEL(1) | SE_YSEL(1); -+ *rconf1 |= 0x0; -+ break; -+ case CHIP_STONEY: -+ *rconf |= 0x0; -+ *rconf1 |= 0x0; -+ break; -+ default: -+ DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); -+ break; -+ } -+} -+ -+static void -+gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev, -+ u32 raster_config, u32 raster_config_1, -+ unsigned rb_mask, unsigned num_rb) -+{ -+ unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); -+ unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); -+ unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); -+ unsigned rb_per_se = num_rb / num_se; -+ unsigned se_mask[4]; -+ unsigned se; -+ -+ se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; -+ se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; -+ se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; -+ se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; -+ -+ WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); -+ WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); -+ WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); -+ -+ if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || -+ (!se_mask[2] && !se_mask[3]))) { -+ raster_config_1 &= ~SE_PAIR_MAP_MASK; -+ -+ if (!se_mask[0] && !se_mask[1]) { -+ raster_config_1 |= -+ SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3); -+ } else { -+ raster_config_1 |= -+ SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0); -+ } -+ } -+ -+ for (se = 0; se < num_se; se++) { -+ unsigned raster_config_se = raster_config; -+ unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); -+ unsigned pkr1_mask = pkr0_mask << rb_per_pkr; -+ int idx = (se / 2) * 2; -+ -+ if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { -+ raster_config_se &= ~SE_MAP_MASK; -+ -+ if (!se_mask[idx]) { -+ raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); -+ } else { -+ raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); -+ } -+ } -+ -+ pkr0_mask &= rb_mask; -+ pkr1_mask &= rb_mask; -+ if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { -+ raster_config_se &= ~PKR_MAP_MASK; -+ -+ if (!pkr0_mask) { -+ raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); -+ } else { -+ raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); -+ } -+ } -+ -+ if (rb_per_se >= 2) { -+ unsigned rb0_mask = 1 << (se * rb_per_se); -+ unsigned rb1_mask = rb0_mask << 1; -+ -+ rb0_mask &= rb_mask; -+ rb1_mask &= rb_mask; -+ if (!rb0_mask || !rb1_mask) { -+ raster_config_se &= ~RB_MAP_PKR0_MASK; -+ -+ if (!rb0_mask) { -+ raster_config_se |= -+ RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); -+ } else { -+ raster_config_se |= -+ RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); -+ } -+ } -+ -+ if (rb_per_se > 2) { -+ rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); -+ rb1_mask = rb0_mask << 1; -+ rb0_mask &= rb_mask; -+ rb1_mask &= rb_mask; -+ if (!rb0_mask || !rb1_mask) { -+ raster_config_se &= ~RB_MAP_PKR1_MASK; -+ -+ if (!rb0_mask) { -+ raster_config_se |= -+ RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); -+ } else { -+ raster_config_se |= -+ RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); -+ } -+ } -+ } -+ } -+ -+ /* GRBM_GFX_INDEX has a different offset on VI */ -+ gfx_v8_0_select_se_sh(adev, se, 0xffffffff); -+ WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); -+ WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); -+ } -+ -+ /* GRBM_GFX_INDEX has a different offset on VI */ -+ gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); -+} -+ - static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) - { - int i, j; - u32 data; -+ u32 raster_config = 0, raster_config_1 = 0; - u32 active_rbs = 0; - u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / - adev->gfx.config.max_sh_per_se; -+ unsigned num_rb_pipes; - - mutex_lock(&adev->grbm_idx_mutex); - for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { -@@ -3502,10 +3652,26 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) - } - } - gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); -- mutex_unlock(&adev->grbm_idx_mutex); - - adev->gfx.config.backend_enable_mask = active_rbs; - adev->gfx.config.num_rbs = hweight32(active_rbs); -+ -+ num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * -+ adev->gfx.config.max_shader_engines, 16); -+ -+ gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1); -+ -+ if (!adev->gfx.config.backend_enable_mask || -+ adev->gfx.config.num_rbs >= num_rb_pipes) { -+ WREG32(mmPA_SC_RASTER_CONFIG, raster_config); -+ WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); -+ } else { -+ gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1, -+ adev->gfx.config.backend_enable_mask, -+ num_rb_pipes); -+ } -+ -+ mutex_unlock(&adev->grbm_idx_mutex); - } - - /** -diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h -index 3bf7172..4bd2bfd 100644 ---- a/drivers/gpu/drm/amd/amdgpu/vid.h -+++ b/drivers/gpu/drm/amd/amdgpu/vid.h -@@ -368,4 +368,41 @@ - #define VCE_CMD_IB_AUTO 0x00000005 - #define VCE_CMD_SEMAPHORE 0x00000006 - -+ -+/* mmPA_SC_RASTER_CONFIG mask */ -+#define RB_MAP_PKR0(x) ((x) << 0) -+#define RB_MAP_PKR0_MASK (0x3 << 0) -+#define RB_MAP_PKR1(x) ((x) << 2) -+#define RB_MAP_PKR1_MASK (0x3 << 2) -+#define RB_XSEL2(x) ((x) << 4) -+#define RB_XSEL2_MASK (0x3 << 4) -+#define RB_XSEL (1 << 6) -+#define RB_YSEL (1 << 7) -+#define PKR_MAP(x) ((x) << 8) -+#define PKR_MAP_MASK (0x3 << 8) -+#define PKR_XSEL(x) ((x) << 10) -+#define PKR_XSEL_MASK (0x3 << 10) -+#define PKR_YSEL(x) ((x) << 12) -+#define PKR_YSEL_MASK (0x3 << 12) -+#define SC_MAP(x) ((x) << 16) -+#define SC_MAP_MASK (0x3 << 16) -+#define SC_XSEL(x) ((x) << 18) -+#define SC_XSEL_MASK (0x3 << 18) -+#define SC_YSEL(x) ((x) << 20) -+#define SC_YSEL_MASK (0x3 << 20) -+#define SE_MAP(x) ((x) << 24) -+#define SE_MAP_MASK (0x3 << 24) -+#define SE_XSEL(x) ((x) << 26) -+#define SE_XSEL_MASK (0x3 << 26) -+#define SE_YSEL(x) ((x) << 28) -+#define SE_YSEL_MASK (0x3 << 28) -+ -+/* mmPA_SC_RASTER_CONFIG_1 mask */ -+#define SE_PAIR_MAP(x) ((x) << 0) -+#define SE_PAIR_MAP_MASK (0x3 << 0) -+#define SE_PAIR_XSEL(x) ((x) << 2) -+#define SE_PAIR_XSEL_MASK (0x3 << 2) -+#define SE_PAIR_YSEL(x) ((x) << 4) -+#define SE_PAIR_YSEL_MASK (0x3 << 4) -+ - #endif --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1144-cache-rb-config-values.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1144-cache-rb-config-values.patch deleted file mode 100644 index 0c8fe273..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1144-cache-rb-config-values.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 0aaf3d10e376981da3d92f037c6e36a5c4e8d348 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Tue, 6 Dec 2016 19:40:46 +0530 -Subject: [PATCH 06/10] cache rb config values -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Needed when for SR-IOV and when PG is enabled. - -Reviewed-by: Christian König <christian.koenig@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -index 20ac07f..479047e 100644 ---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -@@ -3671,6 +3671,21 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) - num_rb_pipes); - } - -+ /* cache the values for userspace */ -+ for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { -+ for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { -+ gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); -+ adev->gfx.config.rb_config[i][j].rb_backend_disable = -+ RREG32(mmCC_RB_BACKEND_DISABLE); -+ adev->gfx.config.rb_config[i][j].user_rb_backend_disable = -+ RREG32(mmGC_USER_RB_BACKEND_DISABLE); -+ adev->gfx.config.rb_config[i][j].raster_config = -+ RREG32(mmPA_SC_RASTER_CONFIG); -+ adev->gfx.config.rb_config[i][j].raster_config_1 = -+ RREG32(mmPA_SC_RASTER_CONFIG_1); -+ } -+ } -+ gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); - mutex_unlock(&adev->grbm_idx_mutex); - } - --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1145-use-cached-raster-config-values-in-csb.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1145-use-cached-raster-config-values-in-csb.patch deleted file mode 100644 index b3b19e7b..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1145-use-cached-raster-config-values-in-csb.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 9fcd43d6a79011dd9ab3837d38ba27454be747ad Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Tue, 6 Dec 2016 20:14:23 +0530 -Subject: [PATCH 07/10] use cached raster config values in csb -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Simplify the code and properly set the csb for harvest values. - -Reviewed-by: Christian König <christian.koenig@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 30 ++---------------------------- - 1 file changed, 2 insertions(+), 28 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -index 479047e..dcc59f3 100644 ---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -@@ -1110,34 +1110,8 @@ static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, - buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); - buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - - PACKET3_SET_CONTEXT_REG_START); -- switch (adev->asic_type) { -- case CHIP_TONGA: -- case CHIP_POLARIS10: -- buffer[count++] = cpu_to_le32(0x16000012); -- buffer[count++] = cpu_to_le32(0x0000002A); -- break; -- case CHIP_POLARIS11: -- buffer[count++] = cpu_to_le32(0x16000012); -- buffer[count++] = cpu_to_le32(0x00000000); -- break; -- case CHIP_FIJI: -- buffer[count++] = cpu_to_le32(0x3a00161a); -- buffer[count++] = cpu_to_le32(0x0000002e); -- break; -- case CHIP_TOPAZ: -- case CHIP_CARRIZO: -- buffer[count++] = cpu_to_le32(0x00000002); -- buffer[count++] = cpu_to_le32(0x00000000); -- break; -- case CHIP_STONEY: -- buffer[count++] = cpu_to_le32(0x00000000); -- buffer[count++] = cpu_to_le32(0x00000000); -- break; -- default: -- buffer[count++] = cpu_to_le32(0x00000000); -- buffer[count++] = cpu_to_le32(0x00000000); -- break; -- } -+ buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); -+ buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); - - buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); - buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1146-used-cached-gca-values-for-vi_read_register.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1146-used-cached-gca-values-for-vi_read_register.patch deleted file mode 100644 index ed7262c9..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1146-used-cached-gca-values-for-vi_read_register.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 2ce0f44274368b2a6640c3062eb119a0de8c1056 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Wed, 7 Dec 2016 15:07:53 +0530 -Subject: [PATCH 08/10] used cached gca values for vi_read_register -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Using the cached values has less latency for bare metal -and SR-IOV, and prevents reading back bogus values if the -engine is powergated. - -Reviewed-by: Christian König <christian.koenig@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/vi.c | 115 +++++++++++++++++++++++++++++++++------- - 1 file changed, 96 insertions(+), 19 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c -index 02ba429..3a42e83 100644 ---- a/drivers/gpu/drm/amd/amdgpu/vi.c -+++ b/drivers/gpu/drm/amd/amdgpu/vi.c -@@ -513,21 +513,100 @@ static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = - {mmPA_SC_RASTER_CONFIG_1, false, true}, - }; - --static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num, -- u32 sh_num, u32 reg_offset) -+static uint32_t vi_get_register_value(struct amdgpu_device *adev, -+ bool indexed, u32 se_num, -+ u32 sh_num, u32 reg_offset) - { -- uint32_t val; -+ if (indexed) { -+ uint32_t val; -+ unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; -+ unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; -+ -+ switch (reg_offset) { -+ case mmCC_RB_BACKEND_DISABLE: -+ return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; -+ case mmGC_USER_RB_BACKEND_DISABLE: -+ return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; -+ case mmPA_SC_RASTER_CONFIG: -+ return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; -+ case mmPA_SC_RASTER_CONFIG_1: -+ return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1; -+ } - -- mutex_lock(&adev->grbm_idx_mutex); -- if (se_num != 0xffffffff || sh_num != 0xffffffff) -- gfx_v8_0_select_se_sh(adev, se_num, sh_num); -+ mutex_lock(&adev->grbm_idx_mutex); -+ if (se_num != 0xffffffff || sh_num != 0xffffffff) -+ gfx_v8_0_select_se_sh(adev, se_num, sh_num); - -- val = RREG32(reg_offset); -+ val = RREG32(reg_offset); - -- if (se_num != 0xffffffff || sh_num != 0xffffffff) -- gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); -- mutex_unlock(&adev->grbm_idx_mutex); -- return val; -+ if (se_num != 0xffffffff || sh_num != 0xffffffff) -+ gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); -+ mutex_unlock(&adev->grbm_idx_mutex); -+ return val; -+ } else { -+ unsigned idx; -+ -+ switch (reg_offset) { -+ case mmGB_ADDR_CONFIG: -+ return adev->gfx.config.gb_addr_config; -+ case mmMC_ARB_RAMCFG: -+ return adev->gfx.config.mc_arb_ramcfg; -+ case mmGB_TILE_MODE0: -+ case mmGB_TILE_MODE1: -+ case mmGB_TILE_MODE2: -+ case mmGB_TILE_MODE3: -+ case mmGB_TILE_MODE4: -+ case mmGB_TILE_MODE5: -+ case mmGB_TILE_MODE6: -+ case mmGB_TILE_MODE7: -+ case mmGB_TILE_MODE8: -+ case mmGB_TILE_MODE9: -+ case mmGB_TILE_MODE10: -+ case mmGB_TILE_MODE11: -+ case mmGB_TILE_MODE12: -+ case mmGB_TILE_MODE13: -+ case mmGB_TILE_MODE14: -+ case mmGB_TILE_MODE15: -+ case mmGB_TILE_MODE16: -+ case mmGB_TILE_MODE17: -+ case mmGB_TILE_MODE18: -+ case mmGB_TILE_MODE19: -+ case mmGB_TILE_MODE20: -+ case mmGB_TILE_MODE21: -+ case mmGB_TILE_MODE22: -+ case mmGB_TILE_MODE23: -+ case mmGB_TILE_MODE24: -+ case mmGB_TILE_MODE25: -+ case mmGB_TILE_MODE26: -+ case mmGB_TILE_MODE27: -+ case mmGB_TILE_MODE28: -+ case mmGB_TILE_MODE29: -+ case mmGB_TILE_MODE30: -+ case mmGB_TILE_MODE31: -+ idx = (reg_offset - mmGB_TILE_MODE0); -+ return adev->gfx.config.tile_mode_array[idx]; -+ case mmGB_MACROTILE_MODE0: -+ case mmGB_MACROTILE_MODE1: -+ case mmGB_MACROTILE_MODE2: -+ case mmGB_MACROTILE_MODE3: -+ case mmGB_MACROTILE_MODE4: -+ case mmGB_MACROTILE_MODE5: -+ case mmGB_MACROTILE_MODE6: -+ case mmGB_MACROTILE_MODE7: -+ case mmGB_MACROTILE_MODE8: -+ case mmGB_MACROTILE_MODE9: -+ case mmGB_MACROTILE_MODE10: -+ case mmGB_MACROTILE_MODE11: -+ case mmGB_MACROTILE_MODE12: -+ case mmGB_MACROTILE_MODE13: -+ case mmGB_MACROTILE_MODE14: -+ case mmGB_MACROTILE_MODE15: -+ idx = (reg_offset - mmGB_MACROTILE_MODE0); -+ return adev->gfx.config.macrotile_mode_array[idx]; -+ default: -+ return RREG32(reg_offset); -+ } -+ } - } - - static int vi_read_register(struct amdgpu_device *adev, u32 se_num, -@@ -562,10 +641,9 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, - if (reg_offset != asic_register_entry->reg_offset) - continue; - if (!asic_register_entry->untouched) -- *value = asic_register_entry->grbm_indexed ? -- vi_read_indexed_register(adev, se_num, -- sh_num, reg_offset) : -- RREG32(reg_offset); -+ *value = vi_get_register_value(adev, -+ asic_register_entry->grbm_indexed, -+ se_num, sh_num, reg_offset); - return 0; - } - } -@@ -575,10 +653,9 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, - continue; - - if (!vi_allowed_read_registers[i].untouched) -- *value = vi_allowed_read_registers[i].grbm_indexed ? -- vi_read_indexed_register(adev, se_num, -- sh_num, reg_offset) : -- RREG32(reg_offset); -+ *value = vi_get_register_value(adev, -+ vi_allowed_read_registers[i].grbm_indexed, -+ se_num, sh_num, reg_offset); - return 0; - } - return -EINVAL; --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1147-Removed-extra-parameter.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1147-Removed-extra-parameter.patch deleted file mode 100644 index 3ee7aa52..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1147-Removed-extra-parameter.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 7dc74a872ca0a5502f2c8e56fdfd9af97b8da1b6 Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Wed, 7 Dec 2016 21:00:00 +0530 -Subject: [PATCH 09/10] Removed extra parameter - -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -index dcc59f3..d1cb4db 100644 ---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -@@ -3648,7 +3648,7 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) - /* cache the values for userspace */ - for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { - for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { -- gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); -+ gfx_v8_0_select_se_sh(adev, i, j); - adev->gfx.config.rb_config[i][j].rb_backend_disable = - RREG32(mmCC_RB_BACKEND_DISABLE); - adev->gfx.config.rb_config[i][j].user_rb_backend_disable = --- -2.7.4 - diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-extra-config.cfg b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-extra-config.cfg deleted file mode 100644 index a6c1de08..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-extra-config.cfg +++ /dev/null @@ -1,433 +0,0 @@ -CONFIG_PERF_EVENTS_INTEL_UNCORE=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_USELIB=y -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y -CONFIG_SRCU=y -# CONFIG_TASKS_RCU is not set -CONFIG_RCU_KTHREAD_PRIO=0 -# CONFIG_RCU_EXPEDITE_BOOT is not set -CONFIG_BUILD_BIN2C=y -CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 -CONFIG_PAGE_COUNTER=y -CONFIG_BPF=y -CONFIG_MULTIUSER=y -CONFIG_SGETMASK_SYSCALL=y -CONFIG_SYSFS_SYSCALL=y -# CONFIG_BPF_SYSCALL is not set -CONFIG_ADVISE_SYSCALLS=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_ARCH_HUGE_VMAP=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -# CONFIG_MODULE_COMPRESS is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_ARCH_USE_QUEUE_RWLOCK=y -CONFIG_QUEUE_RWLOCK=y -CONFIG_X86_FEATURE_NAMES=y -# CONFIG_X86_GOLDFISH is not set -CONFIG_IOSF_MBI=m -# CONFIG_IOSF_MBI_DEBUG is not set -CONFIG_X86_VSYSCALL_EMULATION=y -CONFIG_X86_DIRECT_GBPAGES=y -CONFIG_MEMORY_BALLOON=y -# CONFIG_ZSWAP is not set -# CONFIG_ZPOOL is not set -# CONFIG_ZBUD is not set -CONFIG_GENERIC_EARLY_IOREMAP=y -# CONFIG_X86_PMEM_LEGACY is not set -# CONFIG_X86_INTEL_MPX is not set -# CONFIG_EFI_MIXED is not set -CONFIG_HAVE_LIVEPATCH=y -# CONFIG_LIVEPATCH is not set -CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y -CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y -CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y -CONFIG_ACPI_HOTPLUG_IOAPIC=y -# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set -CONFIG_HAVE_ACPI_APEI=y -CONFIG_HAVE_ACPI_APEI_NMI=y -# CONFIG_PMIC_OPREGION is not set -CONFIG_PCI_BUS_ADDR_T_64BIT=y -CONFIG_PMC_ATOM=y -CONFIG_NET_UDP_TUNNEL=m -# CONFIG_NET_FOU is not set -# CONFIG_NET_FOU_IP_TUNNELS is not set -# CONFIG_GENEVE is not set -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_BRIDGE_NETFILTER=m -CONFIG_NF_NAT_REDIRECT=m -# CONFIG_NETFILTER_XT_NAT is not set -# CONFIG_NF_LOG_ARP is not set -# CONFIG_NF_LOG_IPV4 is not set -CONFIG_NF_REJECT_IPV4=m -CONFIG_NF_NAT_IPV4=m -# CONFIG_NF_NAT_MASQUERADE_IPV4 is not set -CONFIG_NF_NAT_PROTO_GRE=m -CONFIG_NF_NAT_PPTP=m -CONFIG_NF_NAT_H323=m -# CONFIG_IP_NF_NAT is not set -# CONFIG_NF_REJECT_IPV6 is not set -# CONFIG_NF_LOG_IPV6 is not set -CONFIG_TIPC_MEDIA_UDP=y -# CONFIG_NET_ACT_VLAN is not set -# CONFIG_NET_ACT_BPF is not set -# CONFIG_NET_ACT_CONNMARK is not set -# CONFIG_MPLS is not set -# CONFIG_NET_SWITCHDEV is not set -CONFIG_BT_BREDR=y -CONFIG_BT_LE=y -# CONFIG_BT_SELFTEST is not set -CONFIG_BT_DEBUGFS=y -CONFIG_BT_INTEL=m -CONFIG_BT_BCM=m -CONFIG_BT_HCIBTUSB_BCM=y -# CONFIG_BT_HCIUART_INTEL is not set -# CONFIG_BT_HCIUART_BCM is not set -# CONFIG_MAC80211_RC_MINSTREL_VHT is not set -CONFIG_UEVENT_HELPER=y -# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set -CONFIG_ALLOW_DEV_COREDUMP=y -# CONFIG_FENCE_TRACE is not set -# CONFIG_BLK_DEV_PMEM is not set -# CONFIG_INTEL_MEI_TXE is not set -# CONFIG_INTEL_MIC_BUS is not set -# CONFIG_ECHO is not set -# CONFIG_CXL_BASE is not set -# CONFIG_SCSI_MQ_DEFAULT is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_WD719X is not set -# CONFIG_DM_MQ_DEFAULT is not set -# CONFIG_DM_ERA is not set -# CONFIG_DM_LOG_WRITES is not set -# CONFIG_IPVLAN is not set -# CONFIG_NET_VENDOR_AGERE is not set -# CONFIG_ET131X is not set -# CONFIG_ALTERA_TSE is not set -# CONFIG_BCMGENET is not set -# CONFIG_CX_ECAT is not set -# CONFIG_FM10K is not set -# CONFIG_NET_VENDOR_QUALCOMM is not set -# CONFIG_NET_VENDOR_ROCKER is not set -# CONFIG_NET_VENDOR_SAMSUNG is not set -# CONFIG_SXGBE_ETH is not set -# CONFIG_TI_CPSW_ALE is not set -# CONFIG_BCM7XXX_PHY is not set -# CONFIG_MDIO_BCM_UNIMAC is not set -CONFIG_USB_NET_DRIVERS=y -# CONFIG_ATH9K_DYNACK is not set -# CONFIG_ATH9K_CHANNEL_CONTEXT is not set -CONFIG_ATH9K_PCOEM=y -CONFIG_BRCMFMAC_PROTO_BCDC=y -# CONFIG_BRCMFMAC_PCIE is not set -CONFIG_IWLWIFI_LEDS=y -# CONFIG_RTL8723BE is not set -# CONFIG_RTL8192EE is not set -# CONFIG_RTL8821AE is not set -# CONFIG_RSI_91X is not set -# CONFIG_MOUSE_PS2_FOCALTECH is not set -# CONFIG_MOUSE_ELAN_I2C is not set -# CONFIG_TABLET_SERIAL_WACOM4 is not set -# CONFIG_TOUCHSCREEN_GOODIX is not set -# CONFIG_TOUCHSCREEN_ELAN is not set -# CONFIG_TOUCHSCREEN_SX8654 is not set -CONFIG_DEVMEM=y -CONFIG_SERIAL_EARLYCON=y -# CONFIG_SERIAL_8250_FINTEK is not set -# CONFIG_SERIAL_SC16IS7XX is not set -# CONFIG_IPMI_SSIF is not set -# CONFIG_TCG_CRB is not set -# CONFIG_TCG_TIS_ST33ZP24 is not set -# CONFIG_XILLYBUS is not set -CONFIG_ACPI_I2C_OPREGION=y -# CONFIG_I2C_SLAVE is not set -# CONFIG_SPI_CADENCE is not set -# CONFIG_SPMI is not set -# CONFIG_PINCTRL_BAYTRAIL is not set -# CONFIG_PINCTRL_CHERRYVIEW is not set -# CONFIG_PINCTRL_SUNRISEPOINT is not set -CONFIG_GPIOLIB_IRQCHIP=y -# CONFIG_GPIO_DWAPB is not set -# CONFIG_GPIO_F7188X is not set -# CONFIG_GPIO_ICH is not set -# CONFIG_GPIO_LYNXPOINT is not set -# CONFIG_GPIO_SCH311X is not set -# CONFIG_GPIO_ADP5588 is not set -# CONFIG_GPIO_BT8XX is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_BATTERY_GAUGE_LTC2941 is not set -# CONFIG_SENSORS_APPLESMC is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_G762 is not set -# CONFIG_SENSORS_I5500 is not set -# CONFIG_SENSORS_CORETEMP is not set -# CONFIG_SENSORS_POWR1220 is not set -# CONFIG_SENSORS_LTC2945 is not set -# CONFIG_SENSORS_LTC4151 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4222 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LTC4260 is not set -# CONFIG_SENSORS_LTC4261 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX16065 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX1668 is not set -# CONFIG_SENSORS_MAX197 is not set -# CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_MAX6697 is not set -# CONFIG_SENSORS_HTU21 is not set -# CONFIG_SENSORS_MCP3021 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_NTC_THERMISTOR is not set -# CONFIG_SENSORS_NCT6683 is not set -# CONFIG_SENSORS_NCT6775 is not set -# CONFIG_SENSORS_NCT7802 is not set -# CONFIG_SENSORS_NCT7904 is not set -# CONFIG_SENSORS_SHTC1 is not set -# CONFIG_SENSORS_SMM665 is not set -# CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_TMP103 is not set -# CONFIG_THERMAL_GOV_BANG_BANG is not set -# CONFIG_INTEL_SOC_DTS_THERMAL is not set -# CONFIG_INT340X_THERMAL is not set -# CONFIG_XILINX_WATCHDOG is not set -# CONFIG_CADENCE_WATCHDOG is not set -CONFIG_BCMA_DRIVER_PCI=y -# CONFIG_MFD_BCM590XX is not set -# CONFIG_MFD_AXP20X is not set -# CONFIG_MFD_DA9150 is not set -# CONFIG_MFD_DLN2 is not set -# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set -# CONFIG_INTEL_SOC_PMIC is not set -# CONFIG_MFD_MAX77843 is not set -# CONFIG_MFD_MT6397 is not set -# CONFIG_MFD_MENF21BMC is not set -# CONFIG_MFD_RT5033 is not set -# CONFIG_MFD_RTSX_USB is not set -# CONFIG_MFD_RN5T618 is not set -# CONFIG_MFD_SKY81452 is not set -# CONFIG_MFD_TPS65218 is not set -# CONFIG_MEDIA_SDR_SUPPORT is not set -# CONFIG_USB_GSPCA_DTCS033 is not set -# CONFIG_USB_GSPCA_TOUPTEK is not set -# CONFIG_DRM_I2C_ADV7511 is not set -# CONFIG_DRM_AMD_POWERPLAY is not set -# CONFIG_DRM_VGEM is not set -# CONFIG_HSA_AMD is not set -CONFIG_FB_CMDLINE=y -CONFIG_HDMI=y -CONFIG_DUMMY_CONSOLE_COLUMNS=80 -CONFIG_DUMMY_CONSOLE_ROWS=25 -CONFIG_SND_DMAENGINE_PCM=m -# CONFIG_SND_SE6X is not set -CONFIG_SND_HDA=y -CONFIG_SND_HDA_PREALLOC_SIZE=64 -# CONFIG_SND_HDA_CODEC_CA0132_DSP is not set -CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 -CONFIG_SND_HDA_CORE=y -# CONFIG_SND_BCD2000 is not set -# CONFIG_SND_USB_POD is not set -# CONFIG_SND_USB_PODHD is not set -# CONFIG_SND_USB_TONEPORT is not set -# CONFIG_SND_USB_VARIAX is not set -CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y -# CONFIG_SND_SOC_FSL_ASRC is not set -# CONFIG_SND_SOC_FSL_SAI is not set -# CONFIG_SND_SOC_FSL_SSI is not set -# CONFIG_SND_SOC_FSL_SPDIF is not set -# CONFIG_SND_SOC_FSL_ESAI is not set -# CONFIG_SND_SOC_IMX_AUDMUX is not set -# CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH is not set -# CONFIG_SND_SOC_QCOM is not set -# CONFIG_SND_SOC_XTFPGA_I2S is not set -# CONFIG_SND_SOC_ADAU1701 is not set -# CONFIG_SND_SOC_AK4104 is not set -# CONFIG_SND_SOC_AK4554 is not set -# CONFIG_SND_SOC_AK4642 is not set -# CONFIG_SND_SOC_AK5386 is not set -# CONFIG_SND_SOC_ALC5623 is not set -# CONFIG_SND_SOC_CS35L32 is not set -# CONFIG_SND_SOC_CS42L51_I2C is not set -# CONFIG_SND_SOC_CS42L52 is not set -# CONFIG_SND_SOC_CS42L56 is not set -# CONFIG_SND_SOC_CS42L73 is not set -# CONFIG_SND_SOC_CS4265 is not set -# CONFIG_SND_SOC_CS4270 is not set -# CONFIG_SND_SOC_CS4271_I2C is not set -# CONFIG_SND_SOC_CS4271_SPI is not set -# CONFIG_SND_SOC_CS42XX8_I2C is not set -# CONFIG_SND_SOC_HDMI_CODEC is not set -# CONFIG_SND_SOC_ES8328 is not set -# CONFIG_SND_SOC_PCM1681 is not set -# CONFIG_SND_SOC_PCM1792A is not set -# CONFIG_SND_SOC_PCM512x_I2C is not set -# CONFIG_SND_SOC_PCM512x_SPI is not set -# CONFIG_SND_SOC_RT5631 is not set -# CONFIG_SND_SOC_RT5677_SPI is not set -# CONFIG_SND_SOC_SGTL5000 is not set -# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set -# CONFIG_SND_SOC_SPDIF is not set -# CONFIG_SND_SOC_SSM2602_SPI is not set -# CONFIG_SND_SOC_SSM2602_I2C is not set -# CONFIG_SND_SOC_SSM4567 is not set -# CONFIG_SND_SOC_STA32X is not set -# CONFIG_SND_SOC_STA350 is not set -# CONFIG_SND_SOC_TAS2552 is not set -# CONFIG_SND_SOC_TAS5086 is not set -# CONFIG_SND_SOC_TFA9879 is not set -# CONFIG_SND_SOC_TLV320AIC23_I2C is not set -# CONFIG_SND_SOC_TLV320AIC23_SPI is not set -# CONFIG_SND_SOC_TLV320AIC31XX is not set -# CONFIG_SND_SOC_TLV320AIC3X is not set -# CONFIG_SND_SOC_TS3A227E is not set -# CONFIG_SND_SOC_WM8510 is not set -# CONFIG_SND_SOC_WM8523 is not set -# CONFIG_SND_SOC_WM8580 is not set -# CONFIG_SND_SOC_WM8711 is not set -# CONFIG_SND_SOC_WM8728 is not set -# CONFIG_SND_SOC_WM8731 is not set -# CONFIG_SND_SOC_WM8737 is not set -# CONFIG_SND_SOC_WM8741 is not set -# CONFIG_SND_SOC_WM8750 is not set -# CONFIG_SND_SOC_WM8753 is not set -# CONFIG_SND_SOC_WM8770 is not set -# CONFIG_SND_SOC_WM8776 is not set -# CONFIG_SND_SOC_WM8804_I2C is not set -# CONFIG_SND_SOC_WM8804_SPI is not set -# CONFIG_SND_SOC_WM8903 is not set -# CONFIG_SND_SOC_WM8962 is not set -# CONFIG_SND_SOC_WM8978 is not set -# CONFIG_SND_SOC_TPA6130A2 is not set -# CONFIG_HID_BETOP_FF is not set -# CONFIG_HID_CP2112 is not set -# CONFIG_HID_GT683R is not set -# CONFIG_HID_LENOVO is not set -# CONFIG_HID_LOGITECH_HIDPP is not set -# CONFIG_HID_PENMOUNT is not set -# CONFIG_HID_PLANTRONICS is not set -# CONFIG_HID_RMI is not set -# CONFIG_USB_OTG_FSM is not set -CONFIG_USB_XHCI_PCI=y -# CONFIG_USB_MAX3421_HCD is not set -# CONFIG_USB_UAS is not set -# CONFIG_USBIP_CORE is not set -# CONFIG_USB_ISP1760 is not set -# CONFIG_USB_LINK_LAYER_TEST is not set -# CONFIG_USB_CHAOSKEY is not set -# CONFIG_USB_LED_TRIG is not set -# CONFIG_MMC_USDHI6ROL0 is not set -# CONFIG_MMC_TOSHIBA_PCI is not set -# CONFIG_LEDS_CLASS_FLASH is not set -# CONFIG_LEDS_LP8860 is not set -# CONFIG_LEDS_PM8941_WLED is not set -# CONFIG_EDAC_IE31200 is not set -# CONFIG_RTC_DRV_ABB5ZES3 is not set -# CONFIG_RTC_DRV_ABX80X is not set -# CONFIG_RTC_DRV_PCF85063 is not set -# CONFIG_RTC_DRV_DS1343 is not set -# CONFIG_RTC_DRV_DS1347 is not set -# CONFIG_RTC_DRV_MCP795 is not set -# CONFIG_RTC_DRV_DS1685_FAMILY is not set -# CONFIG_RTC_DRV_DS2404 is not set -# CONFIG_RTC_DRV_XGENE is not set -CONFIG_VIRTIO_PCI_LEGACY=y -# CONFIG_VIRTIO_INPUT is not set -# CONFIG_R8723AU is not set -# CONFIG_FB_SM750 is not set -# CONFIG_GS_FPGABOOT is not set -# CONFIG_CRYPTO_SKEIN is not set -# CONFIG_UNISYSSPAR is not set -# CONFIG_FB_TFT is not set -CONFIG_I2O=m -CONFIG_I2O_LCT_NOTIFY_ON_CHANGES=y -CONFIG_I2O_EXT_ADAPTEC=y -CONFIG_I2O_EXT_ADAPTEC_DMA64=y -CONFIG_I2O_CONFIG=m -CONFIG_I2O_CONFIG_OLD_IOCTL=y -# CONFIG_I2O_BUS is not set -CONFIG_I2O_BLOCK=m -CONFIG_I2O_SCSI=m -CONFIG_I2O_PROC=m -# CONFIG_DELL_SMO8800 is not set -# CONFIG_TOSHIBA_HAPS is not set -# CONFIG_COMMON_CLK_PXA is not set -# CONFIG_COMMON_CLK_CDCE706 is not set -# CONFIG_ATMEL_PIT is not set -# CONFIG_SH_TIMER_CMT is not set -# CONFIG_SH_TIMER_MTU2 is not set -# CONFIG_SH_TIMER_TMU is not set -# CONFIG_EM_TIMER_STI is not set -# CONFIG_SOC_TI is not set -# CONFIG_PM_DEVFREQ_EVENT is not set -# CONFIG_BCM_KONA_USB2_PHY is not set -# CONFIG_MCB is not set -CONFIG_RAS=y -# CONFIG_THUNDERBOLT is not set -# CONFIG_ANDROID is not set -CONFIG_EFI_RUNTIME_WRAPPERS=y -# CONFIG_EXT4_ENCRYPTION is not set -# CONFIG_F2FS_FS is not set -# CONFIG_FS_DAX is not set -# CONFIG_OVERLAY_FS is not set -CONFIG_KERNFS=y -CONFIG_EFIVAR_FS=m -# CONFIG_SQUASHFS_LZ4 is not set -# CONFIG_PSTORE_PMSG is not set -# CONFIG_AUFS_XATTR is not set -# CONFIG_NFSD_PNFS is not set -CONFIG_GRACE_PERIOD=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 -# CONFIG_DEBUG_INFO_SPLIT is not set -# CONFIG_DEBUG_INFO_DWARF4 is not set -# CONFIG_GDB_SCRIPTS is not set -# CONFIG_PAGE_OWNER is not set -# CONFIG_PAGE_EXTENSION is not set -CONFIG_HAVE_ARCH_KASAN=y -# CONFIG_KASAN is not set -CONFIG_KASAN_SHADOW_OFFSET=0xdffffc0000000000 -# CONFIG_SCHED_STACK_END_CHECK is not set -# CONFIG_DEBUG_TIMEKEEPING is not set -# CONFIG_LOCK_TORTURE_TEST is not set -# CONFIG_DEBUG_PI_LIST is not set -# CONFIG_PROVE_RCU is not set -# CONFIG_TORTURE_TEST is not set -# CONFIG_TRACEPOINT_BENCHMARK is not set -# CONFIG_TRACE_ENUM_MAP_FILE is not set -# CONFIG_TEST_HEXDUMP is not set -# CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_LKM is not set -# CONFIG_TEST_BPF is not set -# CONFIG_TEST_FIRMWARE is not set -# CONFIG_TEST_UDELAY is not set -# CONFIG_MEMTEST is not set -CONFIG_INTEGRITY=y -# CONFIG_INTEGRITY_SIGNATURE is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_MCRYPTD is not set -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_GHASH=m -# CONFIG_CRYPTO_SHA1_MB is not set -# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set -# CONFIG_CRYPTO_DRBG_MENU is not set -# CONFIG_CRYPTO_USER_API_RNG is not set -# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set -CONFIG_KVM_COMPAT=y -# CONFIG_HAVE_ARCH_BITREVERSE is not set -CONFIG_RATIONAL=y -CONFIG_ARCH_HAS_FAST_MULTIPLIER=y -# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set -CONFIG_HAS_IOPORT_MAP=y -CONFIG_GLOB=y -# CONFIG_GLOB_SELFTEST is not set -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_MICROCODE_EARLY=y -# CONFIG_MICROCODE_INTEL_EARLY is not set -# CONFIG_PINMUX is not set diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-gpu-config.cfg b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-gpu-config.cfg deleted file mode 100644 index 4a4028d2..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-gpu-config.cfg +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_DRM_AMDGPU=m -CONFIG_DRM_AMDGPU_USERPTR=y -CONFIG_DRM_AMD_DAL=y -CONFIG_DRM_AMD_DAL_VBIOS_PRESENT=y -CONFIG_DRM_AMD_DAL_DCE11_0=y -CONFIG_DRM_AMD_POWERPLAY=y -CONFIG_SND_SOC_AMD_ACP=m -CONFIG_SND_SOC_AMD_CZ_RT286_MACH=m diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-standard-only.cfg b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-standard-only.cfg deleted file mode 100644 index bfc1701d..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-standard-only.cfg +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y -CONFIG_X86_POWERNOW_K8=y diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-config.cfg b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-config.cfg deleted file mode 100644 index 021e993e..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-config.cfg +++ /dev/null @@ -1,192 +0,0 @@ -CONFIG_GPIO_DEVRES=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_ACPI=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_GENERIC=m -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_SPIDEV=m -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_ALGOBIT=m -CONFIG_I2C_PIIX4=m -CONFIG_IGB=m -CONFIG_SENSORS_K10TEMP=m -CONFIG_X86_MCE=y -CONFIG_X86_MCE_AMD=y -CONFIG_SND_USB=y -CONFIG_SND_HWDEP=y -CONFIG_SND_JACK=y -CONFIG_SND_SEQ_HRTIMER_DEFAULT=y -CONFIG_SND_HDA_RECONFIG=y -CONFIG_SND_HDA_INPUT_BEEP_MODE=1 -CONFIG_SERIAL_NONSTANDARD=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_NR_UARTS=48 -CONFIG_SERIAL_8250_RUNTIME_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_RSA=y -CONFIG_X86_AMD_PLATFORM_DEVICE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_RCU_FAST_NO_HZ=y -CONFIG_CGROUP_PERF=y -CONFIG_CHECKPOINT_RESTORE=y -CONFIG_SCHED_AUTOGROUP=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLK_DEV_BSGLIB=y -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_THROTTLING=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_CFQ_GROUP_IOSCHED=y -CONFIG_DEFAULT_DEADLINE=y -CONFIG_DEFAULT_IOSCHED="deadline" -CONFIG_PROCESSOR_SELECT=y -CONFIG_GART_IOMMU=y -CONFIG_CALGARY_IOMMU=y -CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y -CONFIG_NR_CPUS=24 -CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y -CONFIG_X86_MCE_INJECT=m -CONFIG_MICROCODE=y -CONFIG_X86_MSR=m -CONFIG_X86_CPUID=m -CONFIG_NUMA=y -CONFIG_AMD_NUMA=y -CONFIG_X86_64_ACPI_NUMA=y -CONFIG_NODES_SPAN_OTHER_NODES=y -CONFIG_NODES_SHIFT=6 -CONFIG_ARCH_MEMORY_PROBE=y -CONFIG_NEED_MULTIPLE_NODES=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_HAVE_BOOTMEM_INFO_NODE=y -CONFIG_MEMORY_HOTPLUG=y -CONFIG_MEMORY_HOTPLUG_SPARSE=y -CONFIG_MEMORY_HOTREMOVE=y -CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y -CONFIG_NEED_BOUNCE_POOL=y -CONFIG_MMU_NOTIFIER=y -CONFIG_KSM=y -CONFIG_MEMORY_FAILURE=y -CONFIG_CLEANCACHE=y -CONFIG_FRONTSWAP=y -CONFIG_KEXEC=y -CONFIG_CRASH_DUMP=y -CONFIG_PHYSICAL_ALIGN=0x1000000 -CONFIG_COMPAT_VDSO=y -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y -CONFIG_USE_PERCPU_NUMA_NODE_ID=y -CONFIG_ARCH_HIBERNATION_HEADER=y -CONFIG_HIBERNATE_CALLBACKS=y -CONFIG_HIBERNATION=y -CONFIG_PM_STD_PARTITION="" -CONFIG_PM_TRACE=y -CONFIG_PM_TRACE_RTC=y -CONFIG_ACPI_VIDEO=m -CONFIG_ACPI_NUMA=y -CONFIG_ACPI_SBS=m -CONFIG_ACPI_HED=y -CONFIG_ACPI_BGRT=y -CONFIG_ACPI_APEI=y -CONFIG_ACPI_APEI_GHES=y -CONFIG_ACPI_APEI_PCIEAER=y -CONFIG_ACPI_APEI_MEMORY_FAILURE=y -CONFIG_ACPI_APEI_EINJ=m -CONFIG_ACPI_APEI_ERST_DEBUG=m -CONFIG_SFI=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_X86_PCC_CPUFREQ=m -CONFIG_X86_SPEEDSTEP_CENTRINO=y -CONFIG_X86_P4_CLOCKMOD=m -CONFIG_X86_SPEEDSTEP_LIB=m -CONFIG_PCI_MMCONFIG=y -CONFIG_PCI_REALLOC_ENABLE_AUTO=y -CONFIG_PCI_STUB=m -CONFIG_PCI_ATS=y -CONFIG_PCI_IOV=y -CONFIG_PCI_PRI=y -CONFIG_PCI_PASID=y -CONFIG_HOTPLUG_PCI_CPCI=y -CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m -CONFIG_HOTPLUG_PCI_SHPC=m -CONFIG_X86_SYSFB=y -CONFIG_NET_SCH_FQ=m -CONFIG_ENCLOSURE_SERVICES=m -CONFIG_EEPROM_LEGACY=m -CONFIG_SATA_AHCI_PLATFORM=m -CONFIG_E1000=m -CONFIG_E1000E=m -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_IPMI_HANDLER=m -CONFIG_HW_RANDOM_TPM=m -CONFIG_NVRAM=m -CONFIG_HANGCHECK_TIMER=m -CONFIG_TCG_TPM=y -CONFIG_GPIO_GENERIC_PLATFORM=m -CONFIG_SENSORS_K8TEMP=m -CONFIG_SENSORS_FAM15H_POWER=m -CONFIG_SENSORS_ACPI_POWER=m -CONFIG_AGP_AMD64=y -CONFIG_VGA_SWITCHEROO=y -CONFIG_VIDEO_OUTPUT_CONTROL=m -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_OHCI_HCD_PCI=m -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_MMC_SPI=m -CONFIG_EDAC=y -CONFIG_EDAC_LEGACY_SYSFS=y -CONFIG_EDAC_DECODE_MCE=y -CONFIG_EDAC_MCE_INJ=m -CONFIG_EDAC_MM_EDAC=m -CONFIG_EDAC_AMD64=m -CONFIG_AUXDISPLAY=y -CONFIG_IOMMU_API=y -CONFIG_AMD_IOMMU=y -CONFIG_AMD_IOMMU_STATS=y -CONFIG_AMD_IOMMU_V2=m -CONFIG_DMAR_TABLE=y -CONFIG_IRQ_REMAP=y -CONFIG_PM_DEVFREQ=y -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_DEVFREQ_GOV_PERFORMANCE=y -CONFIG_DEVFREQ_GOV_POWERSAVE=y -CONFIG_DEVFREQ_GOV_USERSPACE=y -CONFIG_MEMORY=y -CONFIG_EDD=y -CONFIG_EDD_OFF=y -CONFIG_DMI_SYSFS=m -CONFIG_EFI_VARS=y -CONFIG_EFI_VARS_PSTORE=y -CONFIG_EFI_RUNTIME_MAP=y -CONFIG_UEFI_CPER=y -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y -CONFIG_PROC_VMCORE=y -CONFIG_HUGETLBFS=y -CONFIG_HUGETLB_PAGE=y -CONFIG_PSTORE=y -CONFIG_SECURITYFS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_INTERVAL_TREE=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=8 -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_PINCTRL_AMD=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_SND_DESIGNWARE_I2S=m -CONFIG_SND_SIMPLE_CARD=m -CONFIG_GPIO_ML_IOH=m -CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y -CONFIG_I2C_DESIGNWARE_PCI=m -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_DEBUG_RODATA is not set diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-features.scc b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-features.scc deleted file mode 100644 index e69de29b..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-features.scc +++ /dev/null diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc deleted file mode 100644 index aa2b0095..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc +++ /dev/null @@ -1,39 +0,0 @@ -patch 1113-enable-UVD-context-buffer-for-older-HW-MIME-Version-.patch -patch 1114-fix-default-UVD-context-size.patch -patch 1115-fix-IB-alignment-for-UVD.patch -patch 1116-fix-VCE-ib-alignment-value.patch -patch 1117-add-support-for-UVD_NO_OP-register.patch -patch 1118-switch-UVD-code-to-use-UVD_NO_OP-for-padding.patch -patch 1119-move-amdgpu_drm.h-to-driver-include-dir.patch -patch 1120-fix-amdgpu_drm.h-include-problem.patch -patch 1121-add-the-interface-of-waiting-multiple-fences-v2.patch -patch 1122-Fix-for-vulkan-decode-fail.patch -patch 1123-ioctl-number-modified-DRM_AMDGPU_WAIT_FENCES.patch -patch 1124-add-amdgpu.cg_mask-and-amdgpu.pg_mask-parameters.patch -patch 1125-drm-amdgpu-gfx8-disable-EDC.patch -patch 1126-ASoC-AMD-add-ACP-2.2-register-headers.patch -patch 1127-ASoC-AMD-add-AMD-ASoC-ACP-2.x-DMA-driver.patch -patch 1128-ASoC-AMD-add-pm-ops.patch -patch 1129-ASoC-AMD-Manage-ACP-2.x-SRAM-banks-power.patch -patch 1130-ASoc-AMD-Machine-driver-for-AMD-ACP-Audio-engine-usi.patch -patch 1131-drm-amd-Adding-ACP-driver-support-for-AMDGPU.patch -patch 1132-drm-amd-Power-management-related-modifications-in-th.patch -patch 1133-ASoC-dwc-add-quirk-for-different-register-offset.patch -patch 1134-ASoC-dwc-reconfigure-dwc-in-resume-from-suspend.patch -patch 1135-ASoC-dwc-add-quirk-to-override-COMP_PARAM_1-register.patch -patch 1136-ALSA-Soc-RT286Codec-Modifications-to-ALSA-SOC-Audio.patch -patch 1137-drm-amdgpu-acp-fix-resume-on-CZ-systems-with-AZ-audi.patch -patch 0001-amdgpu-fix-various-compilation-issues.patch -patch 1138-add-new-semaphore-object-in-kernel-side.patch -patch 1139-unify-memory-query-info-interface.patch -patch 1140-dma-buf-return-index-of-the-first-signaled-fence.patch -patch 1142-add-additional-cached-gca-config-variables.patch -patch 1143-implement-raster-configuration-for-gfx-v8.patch -patch 1144-cache-rb-config-values.patch -patch 1145-use-cached-raster-config-values-in-csb.patch -patch 1146-used-cached-gca-values-for-vi_read_register.patch -patch 1147-Removed-extra-parameter.patch -patch 0001-fix-hang-issue-when-enable-CONFIG_DRM_AMD_ACP.patch -patch 0001-ethernet-integrate-r8168-driver.patch -patch 0002-r8168-incorporate-changes-from-the-8.041.01-version.patch -patch 0001-PATCH-amdgpu-get-maximum-and-used-UVD-handles.patch diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86.cfg b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86.cfg deleted file mode 100644 index 277d1e46..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86.cfg +++ /dev/null @@ -1,61 +0,0 @@ -CONFIG_PRINTK=y - -# Basic hardware support for the box - network, USB, PCI, sound -CONFIG_NETDEVICES=y -CONFIG_ATA=y -CONFIG_ATA_GENERIC=y -CONFIG_ATA_SFF=y -CONFIG_PCI=y -CONFIG_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PCI=y -CONFIG_USB_SUPPORT=y -CONFIG_USB=y -# CONFIG_R8169 is not set -CONFIG_R8168=y -CONFIG_PATA_SCH=y -CONFIG_USB_EHCI_HCD=y -CONFIG_PCIEPORTBUS=y -CONFIG_NET=y -CONFIG_USB_UHCI_HCD=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y - -# Make sure these are on, otherwise the bootup won't be fun -CONFIG_EXT3_FS=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_MODULES=y -CONFIG_SHMEM=y -CONFIG_TMPFS=y -CONFIG_PACKET=y - -CONFIG_I2C=y -CONFIG_AGP=y -CONFIG_PM=y -CONFIG_ACPI=y -CONFIG_INPUT=y - -# Needed for booting (and using) USB memory sticks -CONFIG_BLK_DEV_LOOP=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y - -CONFIG_RD_GZIP=y - -# Filesystems -CONFIG_EXT2_FS_SECURITY=y -CONFIG_NFSD=m -CONFIG_NFSD_V3=y -CONFIG_NFSD_V4=y -CONFIG_QFMT_V2 -CONFIG_QUOTA=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -CONFIG_QUOTA_TREE=m -CONFIG_QUOTACTL=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_XATTR=y -CONFIG_SQUASHFS_ZLIB=y -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TMPFS_XATTR=y diff --git a/meta-amdfalconx86/recipes-kernel/linux/linux-yocto-amdfalconx86_4.4.inc b/meta-amdfalconx86/recipes-kernel/linux/linux-yocto-amdfalconx86_4.4.inc deleted file mode 100644 index cabde7a6..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/linux-yocto-amdfalconx86_4.4.inc +++ /dev/null @@ -1,10 +0,0 @@ -FILESEXTRAPATHS_prepend := "${THISDIR}/files:" - -SRC_URI_append_amdfalconx86 += "file://amdfalconx86-user-features.scc \ - file://amdfalconx86-user-patches.scc \ - file://amdfalconx86.cfg \ - file://amdfalconx86-user-config.cfg \ - file://amdfalconx86-extra-config.cfg \ -" - -COMPATIBLE_MACHINE_amdfalconx86 = "amdfalconx86" diff --git a/meta-amdfalconx86/recipes-kernel/linux/linux-yocto-rt_4.4.bbappend b/meta-amdfalconx86/recipes-kernel/linux/linux-yocto-rt_4.4.bbappend deleted file mode 100644 index 5b3d5f04..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/linux-yocto-rt_4.4.bbappend +++ /dev/null @@ -1 +0,0 @@ -require linux-yocto-amdfalconx86_4.4.inc diff --git a/meta-amdfalconx86/recipes-kernel/linux/linux-yocto_4.4.bbappend b/meta-amdfalconx86/recipes-kernel/linux/linux-yocto_4.4.bbappend deleted file mode 100644 index 5beb27e8..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/linux-yocto_4.4.bbappend +++ /dev/null @@ -1,5 +0,0 @@ -require linux-yocto-amdfalconx86_4.4.inc - -SRC_URI_append_amdfalconx86 += "file://amdfalconx86-gpu-config.cfg \ - file://amdfalconx86-standard-only.cfg \ -" |