diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0967-drm-amd-display-Use-function-pointer-for-update_plan.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0967-drm-amd-display-Use-function-pointer-for-update_plan.patch | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0967-drm-amd-display-Use-function-pointer-for-update_plan.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0967-drm-amd-display-Use-function-pointer-for-update_plan.patch new file mode 100644 index 00000000..3fb7778d --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0967-drm-amd-display-Use-function-pointer-for-update_plan.patch @@ -0,0 +1,74 @@ +From 958b709823b58bb55f332cbee34bf58c116e26bd Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Thu, 3 Aug 2017 10:19:58 -0400 +Subject: [PATCH 0967/4131] drm/amd/display: Use function pointer for + update_plane_addr + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- + drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 1 + + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 +++--- + 3 files changed, 5 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index 2453d36..f6fb19a 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -132,7 +132,7 @@ struct resource_pool *dc_create_resource_pool( + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + res_pool = dcn10_create_resource_pool( +- num_virtual_links, dc); ++ num_virtual_links, dc); + break; + #endif + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +index cc707bd..922af2d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +@@ -615,6 +615,7 @@ static uint32_t dce110_get_pll_pixel_rate_in_hz( + + /* This function need separate to different DCE version, before separate, just use pixel clock */ + return pipe_ctx->stream->phy_pix_clk; ++ + } + + static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll( +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 7b943e1..184627c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -1246,7 +1246,7 @@ static void toggle_watermark_change_req(struct dce_hwseq *hws) + DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req); + } + +-static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) ++static void dcn10_update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) + { + bool addr_patched = false; + PHYSICAL_ADDRESS_LOC addr; +@@ -2115,7 +2115,7 @@ static void update_dchubp_dpp( + */ + REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst); + +- update_plane_addr(dc, pipe_ctx); ++ dc->hwss.update_plane_addr(dc, pipe_ctx); + + mi->funcs->mem_input_setup( + mi, +@@ -2687,7 +2687,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { + .apply_ctx_to_hw = dce110_apply_ctx_to_hw, + .apply_ctx_for_surface = dcn10_apply_ctx_for_surface, + .set_plane_config = set_plane_config, +- .update_plane_addr = update_plane_addr, ++ .update_plane_addr = dcn10_update_plane_addr, + .update_dchub = dcn10_update_dchub, + .update_pending_status = dcn10_update_pending_status, + .set_input_transfer_func = dcn10_set_input_transfer_func, +-- +2.7.4 + |