diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0963-drm-amd-display-change-bw_dceip-and-bw_vbios-into-po.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0963-drm-amd-display-change-bw_dceip-and-bw_vbios-into-po.patch | 367 |
1 files changed, 367 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0963-drm-amd-display-change-bw_dceip-and-bw_vbios-into-po.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0963-drm-amd-display-change-bw_dceip-and-bw_vbios-into-po.patch new file mode 100644 index 00000000..79cd6979 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0963-drm-amd-display-change-bw_dceip-and-bw_vbios-into-po.patch @@ -0,0 +1,367 @@ +From f7ba8fb783f3bfe8aa8f1942c4dfc912a708bee1 Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Wed, 2 Aug 2017 16:56:03 -0400 +Subject: [PATCH 0963/4131] drm/amd/display: change bw_dceip and bw_vbios into + pointers + +-Change bw_calcs_dceip into pointer +-Change bw_calcs_vbios into pointer + +This is needed for flattening of core_dc into dc, as without this the +diags build fails + +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 26 +++++++++++ + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- + .../drm/amd/display/dc/dce110/dce110_resource.c | 34 +++++++-------- + .../drm/amd/display/dc/dce112/dce112_resource.c | 50 +++++++++++----------- + .../drm/amd/display/dc/dce120/dce120_resource.c | 24 +++++------ + drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 4 +- + 6 files changed, 83 insertions(+), 57 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index b04447b..6b29ea5 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -433,6 +433,13 @@ static void destruct(struct core_dc *dc) + + dm_free(dc->ctx); + dc->ctx = NULL; ++ ++ dm_free(dc->bw_vbios); ++ dc->bw_vbios = NULL; ++ ++ dm_free(dc->bw_dceip); ++ dc->bw_dceip = NULL; ++ + } + + static bool construct(struct core_dc *dc, +@@ -440,8 +447,25 @@ static bool construct(struct core_dc *dc, + { + struct dal_logger *logger; + struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx)); ++ struct bw_calcs_dceip *dc_dceip = dm_alloc(sizeof(*dc_dceip)); ++ struct bw_calcs_vbios *dc_vbios = dm_alloc(sizeof(*dc_vbios)); ++ + enum dce_version dc_version = DCE_VERSION_UNKNOWN; + ++ if (!dc_dceip) { ++ dm_error("%s: failed to create dceip\n", __func__); ++ goto dceip_fail; ++ } ++ ++ dc->bw_dceip = dc_dceip; ++ ++ if (!dc_vbios) { ++ dm_error("%s: failed to create vbios\n", __func__); ++ goto vbios_fail; ++ } ++ ++ dc->bw_vbios = dc_vbios; ++ + if (!dc_ctx) { + dm_error("%s: failed to create ctx\n", __func__); + goto ctx_fail; +@@ -544,6 +568,8 @@ static bool construct(struct core_dc *dc, + logger_fail: + val_ctx_fail: + ctx_fail: ++dceip_fail: ++vbios_fail: + destruct(dc); + return false; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index e590f9d..ef987ac 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -1259,7 +1259,7 @@ void dce110_set_displaymarks( + continue; + + total_dest_line_time_ns = compute_pstate_blackout_duration( +- dc->bw_vbios.blackout_duration, pipe_ctx->stream); ++ dc->bw_vbios->blackout_duration, pipe_ctx->stream); + pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( + pipe_ctx->plane_res.mi, + context->bw.dce.nbp_state_change_wm_ns[num_pipes], +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +index a7f30dc..56be84c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +@@ -826,8 +826,8 @@ static bool dce110_validate_bandwidth( + + if (bw_calcs( + dc->ctx, +- &dc->bw_dceip, +- &dc->bw_vbios, ++ dc->bw_dceip, ++ dc->bw_vbios, + context->res_ctx.pipe_ctx, + dc->res_pool->pipe_count, + &context->bw.dce)) +@@ -1127,21 +1127,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) + DM_PP_CLOCK_TYPE_ENGINE_CLK, + &clks); + /* convert all the clock fro kHz to fix point mHz */ +- dc->bw_vbios.high_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->high_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels-1], 1000); +- dc->bw_vbios.mid1_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels/8], 1000); +- dc->bw_vbios.mid2_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*2/8], 1000); +- dc->bw_vbios.mid3_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*3/8], 1000); +- dc->bw_vbios.mid4_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*4/8], 1000); +- dc->bw_vbios.mid5_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*5/8], 1000); +- dc->bw_vbios.mid6_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*6/8], 1000); +- dc->bw_vbios.low_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->low_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[0], 1000); + dc->sclk_lvls = clks; + +@@ -1150,11 +1150,11 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) + dc->ctx, + DM_PP_CLOCK_TYPE_DISPLAY_CLK, + &clks); +- dc->bw_vbios.high_voltage_max_dispclk = bw_frc_to_fixed( ++ dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels-1], 1000); +- dc->bw_vbios.mid_voltage_max_dispclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels>>1], 1000); +- dc->bw_vbios.low_voltage_max_dispclk = bw_frc_to_fixed( ++ dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( + clks.clocks_in_khz[0], 1000); + + /*do memory clock*/ +@@ -1163,12 +1163,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) + DM_PP_CLOCK_TYPE_MEMORY_CLK, + &clks); + +- dc->bw_vbios.low_yclk = bw_frc_to_fixed( ++ dc->bw_vbios->low_yclk = bw_frc_to_fixed( + clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); +- dc->bw_vbios.mid_yclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid_yclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, + 1000); +- dc->bw_vbios.high_yclk = bw_frc_to_fixed( ++ dc->bw_vbios->high_yclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, + 1000); + } +@@ -1353,7 +1353,7 @@ static bool construct( + + dc->public.caps.max_planes = pool->base.pipe_count; + +- bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); ++ bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); + + bw_calcs_data_update_from_pplib(dc); + +diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +index 420434d..d6e58a25 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +@@ -771,8 +771,8 @@ bool dce112_validate_bandwidth( + + if (bw_calcs( + dc->ctx, +- &dc->bw_dceip, +- &dc->bw_vbios, ++ dc->bw_dceip, ++ dc->bw_vbios, + context->res_ctx.pipe_ctx, + dc->res_pool->pipe_count, + &context->bw.dce)) +@@ -1018,21 +1018,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) + DM_PP_CLOCK_TYPE_ENGINE_CLK, + &clks); + /* convert all the clock fro kHz to fix point mHz */ +- dc->bw_vbios.high_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->high_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels-1], 1000); +- dc->bw_vbios.mid1_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels/8], 1000); +- dc->bw_vbios.mid2_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*2/8], 1000); +- dc->bw_vbios.mid3_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*3/8], 1000); +- dc->bw_vbios.mid4_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*4/8], 1000); +- dc->bw_vbios.mid5_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*5/8], 1000); +- dc->bw_vbios.mid6_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels*6/8], 1000); +- dc->bw_vbios.low_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->low_sclk = bw_frc_to_fixed( + clks.clocks_in_khz[0], 1000); + + /*do memory clock*/ +@@ -1041,12 +1041,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) + DM_PP_CLOCK_TYPE_MEMORY_CLK, + &clks); + +- dc->bw_vbios.low_yclk = bw_frc_to_fixed( ++ dc->bw_vbios->low_yclk = bw_frc_to_fixed( + clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); +- dc->bw_vbios.mid_yclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid_yclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, + 1000); +- dc->bw_vbios.high_yclk = bw_frc_to_fixed( ++ dc->bw_vbios->high_yclk = bw_frc_to_fixed( + clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, + 1000); + +@@ -1054,21 +1054,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) + } + + /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ +- dc->bw_vbios.high_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->high_sclk = bw_frc_to_fixed( + eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); +- dc->bw_vbios.mid1_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( + eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); +- dc->bw_vbios.mid2_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( + eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); +- dc->bw_vbios.mid3_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( + eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); +- dc->bw_vbios.mid4_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( + eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); +- dc->bw_vbios.mid5_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( + eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); +- dc->bw_vbios.mid6_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( + eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); +- dc->bw_vbios.low_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->low_sclk = bw_frc_to_fixed( + eng_clks.data[0].clocks_in_khz, 1000); + + /*do memory clock*/ +@@ -1082,12 +1082,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) + * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): + * YCLK = UMACLK*m_memoryTypeMultiplier + */ +- dc->bw_vbios.low_yclk = bw_frc_to_fixed( ++ dc->bw_vbios->low_yclk = bw_frc_to_fixed( + mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); +- dc->bw_vbios.mid_yclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid_yclk = bw_frc_to_fixed( + mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, + 1000); +- dc->bw_vbios.high_yclk = bw_frc_to_fixed( ++ dc->bw_vbios->high_yclk = bw_frc_to_fixed( + mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, + 1000); + +@@ -1325,7 +1325,7 @@ static bool construct( + if (!dce112_hw_sequencer_construct(dc)) + goto res_create_fail; + +- bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); ++ bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); + + bw_calcs_data_update_from_pplib(dc); + +diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +index d4e9627..562ae22 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +@@ -729,21 +729,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) + } + + /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ +- dc->bw_vbios.high_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->high_sclk = bw_frc_to_fixed( + eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); +- dc->bw_vbios.mid1_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( + eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); +- dc->bw_vbios.mid2_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( + eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); +- dc->bw_vbios.mid3_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( + eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); +- dc->bw_vbios.mid4_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( + eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); +- dc->bw_vbios.mid5_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( + eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); +- dc->bw_vbios.mid6_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( + eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); +- dc->bw_vbios.low_sclk = bw_frc_to_fixed( ++ dc->bw_vbios->low_sclk = bw_frc_to_fixed( + eng_clks.data[0].clocks_in_khz, 1000); + + /*do memory clock*/ +@@ -770,12 +770,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) + * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): + * YCLK = UMACLK*m_memoryTypeMultiplier + */ +- dc->bw_vbios.low_yclk = bw_frc_to_fixed( ++ dc->bw_vbios->low_yclk = bw_frc_to_fixed( + mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); +- dc->bw_vbios.mid_yclk = bw_frc_to_fixed( ++ dc->bw_vbios->mid_yclk = bw_frc_to_fixed( + mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, + 1000); +- dc->bw_vbios.high_yclk = bw_frc_to_fixed( ++ dc->bw_vbios->high_yclk = bw_frc_to_fixed( + mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, + 1000); + +@@ -984,7 +984,7 @@ static bool construct( + + dc->public.caps.max_planes = pool->base.pipe_count; + +- bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); ++ bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); + + bw_calcs_data_update_from_pplib(dc); + +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +index 408ed3a..7568376 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +@@ -33,8 +33,8 @@ struct core_dc { + struct dm_pp_clock_levels sclk_lvls; + + /* Inputs into BW and WM calculations. */ +- struct bw_calcs_dceip bw_dceip; +- struct bw_calcs_vbios bw_vbios; ++ struct bw_calcs_dceip *bw_dceip; ++ struct bw_calcs_vbios *bw_vbios; + #ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct dcn_soc_bounding_box dcn_soc; + struct dcn_ip_params dcn_ip; +-- +2.7.4 + |