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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0735-drm-amd-display-log-underflow.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0735-drm-amd-display-log-underflow.patch130
1 files changed, 0 insertions, 130 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0735-drm-amd-display-log-underflow.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0735-drm-amd-display-log-underflow.patch
deleted file mode 100644
index 52fdc7ba..00000000
--- a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0735-drm-amd-display-log-underflow.patch
+++ /dev/null
@@ -1,130 +0,0 @@
-From 7fc70cbf59337468704586ce8fd8764b11354ad2 Mon Sep 17 00:00:00 2001
-From: Tony Cheng <tony.cheng@amd.com>
-Date: Thu, 3 Aug 2017 09:22:14 -0400
-Subject: [PATCH 0735/4131] drm/amd/display: log underflow
-
-as well as convert output in ref_cycle to nano sec
-
-Signed-off-by: Tony Cheng <tony.cheng@amd.com>
-Reviewed-by: Logatharshan Thothiralingam <Logatharshan.Thothiralingam@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 33 ++++++++++++++++------
- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 5 ++--
- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 3 ++
- 3 files changed, 31 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
-index 30ddf92..a4c0c33 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
-@@ -65,6 +65,20 @@ static void log_mpc_crc(struct core_dc *dc)
- REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
- }
-
-+void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
-+{
-+ static const uint32_t ref_clk_mhz = 48;
-+ static const unsigned int frac = 10;
-+ uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
-+
-+ DTN_INFO("%d.%d \t ",
-+ us_x10 / frac,
-+ us_x10 % frac);
-+}
-+
-+#define DTN_INFO_MICRO_SEC(ref_cycle) \
-+ print_microsec(dc_ctx, ref_cycle)
-+
- static void dcn10_log_hw_state(struct core_dc *dc)
- {
- struct dc_context *dc_ctx = dc->ctx;
-@@ -73,8 +87,9 @@ static void dcn10_log_hw_state(struct core_dc *dc)
-
- DTN_INFO_BEGIN();
-
-- DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t rotation \t"
-- "mirror \t sw_mode \t dcc_en \t blank_en \t ttu_dis \t"
-+ DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
-+ "rotation \t mirror \t sw_mode \t "
-+ "dcc_en \t blank_en \t ttu_dis \t underflow \t "
- "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
-
- for (i = 0; i < pool->pipe_count; i++) {
-@@ -83,9 +98,9 @@ static void dcn10_log_hw_state(struct core_dc *dc)
-
- dcn10_mem_input_read_state(TO_DCN10_MEM_INPUT(mi), &s);
-
-- DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t %xh \t %xh \t "
-- "%d \t %d \t %d \t %d \t"
-- "%d \t %d \t %d \n",
-+ DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
-+ "%xh \t %xh \t %xh \t "
-+ "%d \t %d \t %d \t %xh \t",
- i,
- s.pixel_format,
- s.inuse_addr_hi,
-@@ -97,9 +112,11 @@ static void dcn10_log_hw_state(struct core_dc *dc)
- s.dcc_en,
- s.blank_en,
- s.ttu_disable,
-- s.min_ttu_vblank,
-- s.qos_level_low_wm,
-- s.qos_level_high_wm);
-+ s.underflow_status);
-+ DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
-+ DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
-+ DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
-+ DTN_INFO("\n");
- }
- DTN_INFO("\n");
-
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
-index 0d40fa7..f36585d 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
-@@ -841,9 +841,10 @@ void dcn10_mem_input_read_state(struct dcn10_mem_input *mi,
- REG_GET(DCSURF_SURFACE_CONTROL,
- PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
-
-- REG_GET_2(DCHUBP_CNTL,
-+ REG_GET_3(DCHUBP_CNTL,
- HUBP_BLANK_EN, &s->blank_en,
-- HUBP_TTU_DISABLE, &s->ttu_disable);
-+ HUBP_TTU_DISABLE, &s->ttu_disable,
-+ HUBP_UNDERFLOW_STATUS, &s->underflow_status);
-
- REG_GET(DCN_GLOBAL_TTU_CNTL,
- MIN_TTU_VBLANK, &s->min_ttu_vblank);
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
-index e2eba25..b3ec16c 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
-@@ -250,6 +250,7 @@ struct dcn_mi_registers {
- #define MI_MASK_SH_LIST_DCN(mask_sh)\
- MI_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
- MI_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
-+ MI_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
- MI_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
- MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
- MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
-@@ -402,6 +403,7 @@ struct dcn_mi_registers {
- type HUBP_BLANK_EN;\
- type HUBP_TTU_DISABLE;\
- type HUBP_NO_OUTSTANDING_REQ;\
-+ type HUBP_UNDERFLOW_STATUS;\
- type NUM_PIPES;\
- type NUM_BANKS;\
- type PIPE_INTERLEAVE;\
-@@ -591,6 +593,7 @@ struct dcn_hubp_state {
- uint32_t sw_mode;
- uint32_t dcc_en;
- uint32_t blank_en;
-+ uint32_t underflow_status;
- uint32_t ttu_disable;
- uint32_t min_ttu_vblank;
- uint32_t qos_level_low_wm;
---
-2.7.4
-