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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0038-drm-amd-display-remove-get_min_clocks_state.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0038-drm-amd-display-remove-get_min_clocks_state.patch331
1 files changed, 331 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0038-drm-amd-display-remove-get_min_clocks_state.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0038-drm-amd-display-remove-get_min_clocks_state.patch
new file mode 100644
index 00000000..c4d49666
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0038-drm-amd-display-remove-get_min_clocks_state.patch
@@ -0,0 +1,331 @@
+From 6ad54a5d488d51b47d0e2da56a60c81d80683e9d Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 30 Nov 2016 15:45:51 -0500
+Subject: [PATCH 0038/4131] drm/amd/display: remove get_min_clocks_state
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 10 +----
+ .../display/dc/gpu/dce110/display_clock_dce110.c | 42 +++++++++++---------
+ .../display/dc/gpu/dce112/display_clock_dce112.c | 45 ++++++++++++----------
+ .../display/dc/gpu/dce112/display_clock_dce112.h | 2 +-
+ .../amd/display/dc/gpu/dce80/display_clock_dce80.c | 30 ++++++++-------
+ .../amd/display/include/display_clock_interface.h | 2 -
+ 6 files changed, 67 insertions(+), 64 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index ab4efde..558eeef 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1208,7 +1208,6 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
+ struct core_link *link = stream->sink->link;
+ struct dc_link_settings link_settings = {0};
+ enum dp_panel_mode panel_mode;
+- enum clocks_state cur_min_clock_state;
+ enum dc_link_rate max_link_rate = LINK_RATE_HIGH2;
+
+ /* get link settings for video mode timing */
+@@ -1221,13 +1220,8 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
+ max_link_rate = LINK_RATE_HIGH3;
+
+ if (link_settings.link_rate == max_link_rate) {
+- cur_min_clock_state = CLOCKS_STATE_INVALID;
+-
+- if (pipe_ctx->dis_clk->funcs->get_min_clocks_state) {
+- cur_min_clock_state =
+- pipe_ctx->dis_clk->funcs->get_min_clocks_state(
+- pipe_ctx->dis_clk);
+- if (cur_min_clock_state < CLOCKS_STATE_NOMINAL)
++ if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) {
++ if (pipe_ctx->dis_clk->cur_min_clks_state < CLOCKS_STATE_NOMINAL)
+ pipe_ctx->dis_clk->funcs->set_min_clocks_state(
+ pipe_ctx->dis_clk, CLOCKS_STATE_NOMINAL);
+ } else {
+diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
+index ad7ebc1..8386020 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
++++ b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
+@@ -103,25 +103,19 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
+ * static functions
+ *****************************************************************************/
+
+-static enum clocks_state get_min_clocks_state(struct display_clock *base)
+-{
+- return base->cur_min_clks_state;
+-}
+-
+-static bool set_min_clocks_state(
+- struct display_clock *base,
++static bool dce110_set_min_clocks_state(
++ struct display_clock *dc,
+ enum clocks_state clocks_state)
+ {
+- struct display_clock_dce110 *dc = DCLCK110_FROM_BASE(base);
+ struct dm_pp_power_level_change_request level_change_req = {
+ DM_PP_POWER_LEVEL_INVALID};
+
+- if (clocks_state > base->max_clks_state) {
++ if (clocks_state > dc->max_clks_state) {
+ /*Requested state exceeds max supported state.*/
+- dm_logger_write(base->ctx->logger, LOG_WARNING,
++ dm_logger_write(dc->ctx->logger, LOG_WARNING,
+ "Requested state exceeds max supported state");
+ return false;
+- } else if (clocks_state == base->cur_min_clks_state) {
++ } else if (clocks_state == dc->cur_min_clks_state) {
+ /*if we're trying to set the same state, we can just return
+ * since nothing needs to be done*/
+ return true;
+@@ -140,17 +134,28 @@ static bool set_min_clocks_state(
+ case CLOCKS_STATE_PERFORMANCE:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE;
+ break;
++ case CLOCKS_DPM_STATE_LEVEL_4:
++ level_change_req.power_level = DM_PP_POWER_LEVEL_4;
++ break;
++ case CLOCKS_DPM_STATE_LEVEL_5:
++ level_change_req.power_level = DM_PP_POWER_LEVEL_5;
++ break;
++ case CLOCKS_DPM_STATE_LEVEL_6:
++ level_change_req.power_level = DM_PP_POWER_LEVEL_6;
++ break;
++ case CLOCKS_DPM_STATE_LEVEL_7:
++ level_change_req.power_level = DM_PP_POWER_LEVEL_7;
++ break;
+ case CLOCKS_STATE_INVALID:
+ default:
+- dm_logger_write(base->ctx->logger, LOG_WARNING,
++ dm_logger_write(dc->ctx->logger, LOG_WARNING,
+ "Requested state invalid state");
+ return false;
+ }
+
+ /* get max clock state from PPLIB */
+- if (dm_pp_apply_power_level_change_request(
+- base->ctx, &level_change_req))
+- base->cur_min_clks_state = clocks_state;
++ if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req))
++ dc->cur_min_clks_state = clocks_state;
+
+ return true;
+ }
+@@ -384,7 +389,7 @@ static void psr_wait_loop(struct dc_context *ctx, unsigned int display_clk_khz)
+ dm_write_reg(ctx, mmMASTER_COMM_CNTL_REG, masterComCntl);
+ }
+
+-static void set_clock(
++static void dce110_set_clock(
+ struct display_clock *base,
+ uint32_t requested_clk_khz)
+ {
+@@ -424,10 +429,9 @@ static void set_clock(
+ static const struct display_clock_funcs funcs = {
+ .destroy = destroy,
+ .get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
+- .get_min_clocks_state = get_min_clocks_state,
+ .get_required_clocks_state = get_required_clocks_state,
+- .set_clock = set_clock,
+- .set_min_clocks_state = set_min_clocks_state
++ .set_clock = dce110_set_clock,
++ .set_min_clocks_state = dce110_set_min_clocks_state
+ };
+
+ static bool dal_display_clock_dce110_construct(
+diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
+index d8c8d8a..4488497 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
++++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
+@@ -73,26 +73,19 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
+
+ #define dce112_DFS_BYPASS_THRESHOLD_KHZ 400000
+
+-enum clocks_state dispclk_dce112_get_min_clocks_state(
+- struct display_clock *base)
+-{
+- return base->cur_min_clks_state;
+-}
+-
+-bool dispclk_dce112_set_min_clocks_state(
+- struct display_clock *base,
++static bool dce112_set_min_clocks_state(
++ struct display_clock *dc,
+ enum clocks_state clocks_state)
+ {
+- struct display_clock_dce112 *dc = DCLCK112_FROM_BASE(base);
+ struct dm_pp_power_level_change_request level_change_req = {
+- DM_PP_POWER_LEVEL_INVALID};
++ DM_PP_POWER_LEVEL_INVALID };
+
+- if (clocks_state > base->max_clks_state) {
++ if (clocks_state > dc->max_clks_state) {
+ /*Requested state exceeds max supported state.*/
+- dm_logger_write(base->ctx->logger, LOG_WARNING,
++ dm_logger_write(dc->ctx->logger, LOG_WARNING,
+ "Requested state exceeds max supported state");
+ return false;
+- } else if (clocks_state == base->cur_min_clks_state) {
++ } else if (clocks_state == dc->cur_min_clks_state) {
+ /*if we're trying to set the same state, we can just return
+ * since nothing needs to be done*/
+ return true;
+@@ -111,17 +104,28 @@ bool dispclk_dce112_set_min_clocks_state(
+ case CLOCKS_STATE_PERFORMANCE:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE;
+ break;
++ case CLOCKS_DPM_STATE_LEVEL_4:
++ level_change_req.power_level = DM_PP_POWER_LEVEL_4;
++ break;
++ case CLOCKS_DPM_STATE_LEVEL_5:
++ level_change_req.power_level = DM_PP_POWER_LEVEL_5;
++ break;
++ case CLOCKS_DPM_STATE_LEVEL_6:
++ level_change_req.power_level = DM_PP_POWER_LEVEL_6;
++ break;
++ case CLOCKS_DPM_STATE_LEVEL_7:
++ level_change_req.power_level = DM_PP_POWER_LEVEL_7;
++ break;
+ case CLOCKS_STATE_INVALID:
+ default:
+- dm_logger_write(base->ctx->logger, LOG_WARNING,
++ dm_logger_write(dc->ctx->logger, LOG_WARNING,
+ "Requested state invalid state");
+ return false;
+ }
+
+ /* get max clock state from PPLIB */
+- if (dm_pp_apply_power_level_change_request(
+- base->ctx, &level_change_req))
+- base->cur_min_clks_state = clocks_state;
++ if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req))
++ dc->cur_min_clks_state = clocks_state;
+
+ return true;
+ }
+@@ -293,7 +297,7 @@ enum clocks_state dispclk_dce112_get_required_clocks_state(
+ return low_req_clk;
+ }
+
+-void dispclk_dce112_set_clock(
++void dce112_set_clock(
+ struct display_clock *base,
+ uint32_t requested_clk_khz)
+ {
+@@ -333,10 +337,9 @@ void dispclk_dce112_set_clock(
+ static const struct display_clock_funcs funcs = {
+ .destroy = dispclk_dce112_destroy,
+ .get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
+- .get_min_clocks_state = dispclk_dce112_get_min_clocks_state,
+ .get_required_clocks_state = dispclk_dce112_get_required_clocks_state,
+- .set_clock = dispclk_dce112_set_clock,
+- .set_min_clocks_state = dispclk_dce112_set_min_clocks_state
++ .set_clock = dce112_set_clock,
++ .set_min_clocks_state = dce112_set_min_clocks_state
+ };
+
+ bool dal_display_clock_dce112_construct(
+diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
+index 398af34..0246f93 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
++++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
+@@ -78,7 +78,7 @@ enum clocks_state dispclk_dce112_get_required_clocks_state(
+ struct display_clock *dc,
+ struct state_dependent_clocks *req_clocks);
+
+-void dispclk_dce112_set_clock(
++void dce112_set_clock(
+ struct display_clock *base,
+ uint32_t requested_clk_khz);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
+index b101f7d..60570427 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
++++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
+@@ -90,7 +90,7 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
+ #define FROM_DISPLAY_CLOCK(base) \
+ container_of(base, struct display_clock_dce80, disp_clk)
+
+-static void set_clock(
++static void dce80_set_clock(
+ struct display_clock *dc,
+ uint32_t requested_clk_khz)
+ {
+@@ -111,13 +111,6 @@ static void set_clock(
+ dc->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
+ }
+
+-static enum clocks_state get_min_clocks_state(struct display_clock *dc)
+-{
+- struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
+-
+- return disp_clk->cur_min_clks_state;
+-}
+-
+ static enum clocks_state get_required_clocks_state
+ (struct display_clock *dc,
+ struct state_dependent_clocks *req_clocks)
+@@ -145,12 +138,12 @@ static enum clocks_state get_required_clocks_state
+ return low_req_clk;
+ }
+
+-static bool set_min_clocks_state(
++static bool dce80_set_min_clocks_state(
+ struct display_clock *dc,
+ enum clocks_state clocks_state)
+ {
+ struct dm_pp_power_level_change_request level_change_req = {
+- DM_PP_POWER_LEVEL_INVALID};
++ DM_PP_POWER_LEVEL_INVALID };
+
+ if (clocks_state > dc->max_clks_state) {
+ /*Requested state exceeds max supported state.*/
+@@ -176,6 +169,18 @@ static bool set_min_clocks_state(
+ case CLOCKS_STATE_PERFORMANCE:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE;
+ break;
++ case CLOCKS_DPM_STATE_LEVEL_4:
++ level_change_req.power_level = DM_PP_POWER_LEVEL_4;
++ break;
++ case CLOCKS_DPM_STATE_LEVEL_5:
++ level_change_req.power_level = DM_PP_POWER_LEVEL_5;
++ break;
++ case CLOCKS_DPM_STATE_LEVEL_6:
++ level_change_req.power_level = DM_PP_POWER_LEVEL_6;
++ break;
++ case CLOCKS_DPM_STATE_LEVEL_7:
++ level_change_req.power_level = DM_PP_POWER_LEVEL_7;
++ break;
+ case CLOCKS_STATE_INVALID:
+ default:
+ dm_logger_write(dc->ctx->logger, LOG_WARNING,
+@@ -375,10 +380,9 @@ static void destroy(struct display_clock **dc)
+ static const struct display_clock_funcs funcs = {
+ .destroy = destroy,
+ .get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
+- .get_min_clocks_state = get_min_clocks_state,
+ .get_required_clocks_state = get_required_clocks_state,
+- .set_clock = set_clock,
+- .set_min_clocks_state = set_min_clocks_state
++ .set_clock = dce80_set_clock,
++ .set_min_clocks_state = dce80_set_min_clocks_state
+ };
+
+
+diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
+index bc678a5..f2deafb 100644
+--- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h
++++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
+@@ -70,8 +70,6 @@ struct display_clock_funcs {
+ void (*destroy)(struct display_clock **to_destroy);
+ void (*set_clock)(struct display_clock *disp_clk,
+ uint32_t requested_clock_khz);
+- enum clocks_state (*get_min_clocks_state)(
+- struct display_clock *disp_clk);
+ enum clocks_state (*get_required_clocks_state)(
+ struct display_clock *disp_clk,
+ struct state_dependent_clocks *req_clocks);
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-23 08:10:55 +0000