diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1325-drm-amd-powerplay-support-retrieving-clock-informati.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1325-drm-amd-powerplay-support-retrieving-clock-informati.patch | 126 |
1 files changed, 126 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1325-drm-amd-powerplay-support-retrieving-clock-informati.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1325-drm-amd-powerplay-support-retrieving-clock-informati.patch new file mode 100644 index 00000000..bbbafb50 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1325-drm-amd-powerplay-support-retrieving-clock-informati.patch @@ -0,0 +1,126 @@ +From 95fafe2397da7cded93d817f3b8d64aef2c77f7f Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Wed, 20 Feb 2019 17:13:16 +0800 +Subject: [PATCH 1325/2940] drm/amd/powerplay: support retrieving clock + information from other sysplls + +There will be some needs to retrieve clock information from other +sysplls also except default 0. + +Change-Id: I312f11679b5c146f7315d096fab1d051ce6ecc6c +Signed-off-by: Evan Quan <evan.quan@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 27 ++++++++++--------- + .../drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 3 ++- + .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4 +-- + 3 files changed, 18 insertions(+), 16 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c +index 4588bddf8b33..a28192bfb035 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c +@@ -489,15 +489,16 @@ int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr, + } + + int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, +- uint8_t id, uint32_t *frequency) ++ uint8_t clk_id, uint8_t syspll_id, ++ uint32_t *frequency) + { + struct amdgpu_device *adev = hwmgr->adev; + struct atom_get_smu_clock_info_parameters_v3_1 parameters; + struct atom_get_smu_clock_info_output_parameters_v3_1 *output; + uint32_t ix; + +- parameters.clk_id = id; +- parameters.syspll_id = 0; ++ parameters.clk_id = clk_id; ++ parameters.syspll_id = syspll_id; + parameters.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; + parameters.dfsdid = 0; + +@@ -530,19 +531,19 @@ static void pp_atomfwctrl_copy_vbios_bootup_values_3_2(struct pp_hwmgr *hwmgr, + boot_values->ulSocClk = 0; + boot_values->ulDCEFClk = 0; + +- if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_SOCCLK_ID, &frequency)) ++ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_SOCCLK_ID, SMU11_SYSPLL0_ID, &frequency)) + boot_values->ulSocClk = frequency; + +- if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_DCEFCLK_ID, &frequency)) ++ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_DCEFCLK_ID, SMU11_SYSPLL0_ID, &frequency)) + boot_values->ulDCEFClk = frequency; + +- if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_ECLK_ID, &frequency)) ++ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_ECLK_ID, SMU11_SYSPLL0_ID, &frequency)) + boot_values->ulEClk = frequency; + +- if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_VCLK_ID, &frequency)) ++ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_VCLK_ID, SMU11_SYSPLL0_ID, &frequency)) + boot_values->ulVClk = frequency; + +- if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_DCLK_ID, &frequency)) ++ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_DCLK_ID, SMU11_SYSPLL0_ID, &frequency)) + boot_values->ulDClk = frequency; + } + +@@ -563,19 +564,19 @@ static void pp_atomfwctrl_copy_vbios_bootup_values_3_1(struct pp_hwmgr *hwmgr, + boot_values->ulSocClk = 0; + boot_values->ulDCEFClk = 0; + +- if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_SOCCLK_ID, &frequency)) ++ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_SOCCLK_ID, 0, &frequency)) + boot_values->ulSocClk = frequency; + +- if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCEFCLK_ID, &frequency)) ++ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCEFCLK_ID, 0, &frequency)) + boot_values->ulDCEFClk = frequency; + +- if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_ECLK_ID, &frequency)) ++ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_ECLK_ID, 0, &frequency)) + boot_values->ulEClk = frequency; + +- if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_VCLK_ID, &frequency)) ++ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_VCLK_ID, 0, &frequency)) + boot_values->ulVClk = frequency; + +- if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCLK_ID, &frequency)) ++ if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCLK_ID, 0, &frequency)) + boot_values->ulDClk = frequency; + } + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h +index fe9e8ceef50e..9bafd00324a9 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h +@@ -236,7 +236,8 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, + int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr, + struct pp_atomfwctrl_smc_dpm_parameters *param); + int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, +- uint8_t id, uint32_t *frequency); ++ uint8_t clk_id, uint8_t syspll_id, ++ uint32_t *frequency); + + #endif + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index 39cc4031b2ab..45c672993fe9 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -2575,10 +2575,10 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) + data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; + data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; + pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, +- SMU9_SYSPLL0_SOCCLK_ID, &boot_up_values.ulSocClk); ++ SMU9_SYSPLL0_SOCCLK_ID, 0, &boot_up_values.ulSocClk); + + pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, +- SMU9_SYSPLL0_DCEFCLK_ID, &boot_up_values.ulDCEFClk); ++ SMU9_SYSPLL0_DCEFCLK_ID, 0, &boot_up_values.ulDCEFClk); + + data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; + data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; +-- +2.17.1 + |