diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1228-drm-amd-display-add-seamless-boot-flag-to-stream.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1228-drm-amd-display-add-seamless-boot-flag-to-stream.patch | 185 |
1 files changed, 185 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1228-drm-amd-display-add-seamless-boot-flag-to-stream.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1228-drm-amd-display-add-seamless-boot-flag-to-stream.patch new file mode 100644 index 00000000..7eb55bea --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1228-drm-amd-display-add-seamless-boot-flag-to-stream.patch @@ -0,0 +1,185 @@ +From 7a830ce7c781ffeddb9ff3b597cc3e340518b96f Mon Sep 17 00:00:00 2001 +From: Anthony Koo <Anthony.Koo@amd.com> +Date: Sun, 20 Jan 2019 01:41:44 -0500 +Subject: [PATCH 1228/2940] drm/amd/display: add seamless boot flag to stream + +[Why] +If we determine the stream we are trying to commit +matches HW, we want to try to optimize. + +[How] +Try to acquire the HW resources that are already enabled +and optimize. +Also skip backend reprogramming + +Change-Id: Ia3b66c4ccf3e23bf1d91b9d30645abb54306d1ba +Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> +Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Chaudhary Amit Kumar <Chaudharyamit.Kumar@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 3 + + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 14 ++++- + .../gpu/drm/amd/display/dc/core/dc_resource.c | 56 ++++++++++++++++++- + drivers/gpu/drm/amd/display/dc/dc_stream.h | 4 +- + .../display/dc/dce110/dce110_hw_sequencer.c | 4 +- + 5 files changed, 75 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index d32eb04156ca..3625624bb1e7 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1096,6 +1096,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c + const struct dc_link *link = context->streams[i]->link; + struct dc_stream_status *status; + ++ if (context->streams[i]->apply_seamless_boot_optimization) ++ context->streams[i]->apply_seamless_boot_optimization = false; ++ + if (!context->streams[i]->mode_changed) + continue; + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +index 6058436642e9..829319abaa2a 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +@@ -2579,13 +2579,23 @@ void core_link_enable_stream( + &stream->timing); + + if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { ++ bool apply_edp_fast_boot_optimization = ++ pipe_ctx->stream->apply_edp_fast_boot_optimization; ++ ++ pipe_ctx->stream->apply_edp_fast_boot_optimization = false; ++ + resource_build_info_frame(pipe_ctx); + core_dc->hwss.update_info_frame(pipe_ctx); + ++ /* Do not touch link on seamless boot optimization. */ ++ if (pipe_ctx->stream->apply_seamless_boot_optimization) { ++ pipe_ctx->stream->dpms_off = false; ++ return; ++ } ++ + /* eDP lit up by bios already, no need to enable again. */ + if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && +- pipe_ctx->stream->apply_edp_fast_boot_optimization) { +- pipe_ctx->stream->apply_edp_fast_boot_optimization = false; ++ apply_edp_fast_boot_optimization) { + pipe_ctx->stream->dpms_off = false; + return; + } +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index 969a9e81b8cc..7cd3e130067e 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -1800,6 +1800,51 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream) + stream->phy_pix_clk *= 2; + } + ++static int acquire_resource_from_hw_enabled_state( ++ struct resource_context *res_ctx, ++ const struct resource_pool *pool, ++ struct dc_stream_state *stream) ++{ ++ struct dc_link *link = stream->link; ++ unsigned int inst; ++ ++ /* Check for enabled DIG to identify enabled display */ ++ if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) ++ return -1; ++ ++ /* Check for which front end is used by this encoder. ++ * Note the inst is 1 indexed, where 0 is undefined. ++ * Note that DIG_FE can source from different OTG but our ++ * current implementation always map 1-to-1, so this code makes ++ * the same assumption and doesn't check OTG source. ++ */ ++ inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1; ++ ++ /* Instance should be within the range of the pool */ ++ if (inst >= pool->pipe_count) ++ return -1; ++ ++ if (!res_ctx->pipe_ctx[inst].stream) { ++ struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[inst]; ++ ++ pipe_ctx->stream_res.tg = pool->timing_generators[inst]; ++ pipe_ctx->plane_res.mi = pool->mis[inst]; ++ pipe_ctx->plane_res.hubp = pool->hubps[inst]; ++ pipe_ctx->plane_res.ipp = pool->ipps[inst]; ++ pipe_ctx->plane_res.xfm = pool->transforms[inst]; ++ pipe_ctx->plane_res.dpp = pool->dpps[inst]; ++ pipe_ctx->stream_res.opp = pool->opps[inst]; ++ if (pool->dpps[inst]) ++ pipe_ctx->plane_res.mpcc_inst = pool->dpps[inst]->inst; ++ pipe_ctx->pipe_idx = inst; ++ ++ pipe_ctx->stream = stream; ++ return inst; ++ } ++ ++ return -1; ++} ++ + enum dc_status resource_map_pool_resources( + const struct dc *dc, + struct dc_state *context, +@@ -1824,8 +1869,15 @@ enum dc_status resource_map_pool_resources( + + calculate_phy_pix_clks(stream); + +- /* acquire new resources */ +- pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); ++ if (stream->apply_seamless_boot_optimization) ++ pipe_idx = acquire_resource_from_hw_enabled_state( ++ &context->res_ctx, ++ pool, ++ stream); ++ ++ if (pipe_idx < 0) ++ /* acquire new resources */ ++ pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); + + #ifdef CONFIG_X86 + if (pipe_idx < 0) +diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h +index 90f019eb54b3..a798694992b9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h +@@ -119,7 +119,6 @@ struct dc_stream_state { + int phy_pix_clk; + enum signal_type signal; + bool dpms_off; +- bool apply_edp_fast_boot_optimization; + + void *dm_stream_context; + +@@ -146,6 +145,9 @@ struct dc_stream_state { + uint8_t otg_offset; + } out; + ++ bool apply_edp_fast_boot_optimization; ++ bool apply_seamless_boot_optimization; ++ + uint32_t stream_id; + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 16321307c795..9e2de86eb796 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -1339,7 +1339,9 @@ static enum dc_status apply_single_controller_ctx_to_hw( + } + + /* */ +- dc->hwss.enable_stream_timing(pipe_ctx, context, dc); ++ /* Do not touch stream timing on seamless boot optimization. */ ++ if (!pipe_ctx->stream->apply_seamless_boot_optimization) ++ dc->hwss.enable_stream_timing(pipe_ctx, context, dc); + + if (pipe_ctx->stream_res.tg->funcs->program_vupdate_interrupt) + pipe_ctx->stream_res.tg->funcs->program_vupdate_interrupt( +-- +2.17.1 + |