aboutsummaryrefslogtreecommitdiffstats
path: root/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1176-drm-amd-display-Fix-fclk-idle-state.patch
diff options
context:
space:
mode:
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1176-drm-amd-display-Fix-fclk-idle-state.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1176-drm-amd-display-Fix-fclk-idle-state.patch43
1 files changed, 43 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1176-drm-amd-display-Fix-fclk-idle-state.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1176-drm-amd-display-Fix-fclk-idle-state.patch
new file mode 100644
index 00000000..63c174cc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1176-drm-amd-display-Fix-fclk-idle-state.patch
@@ -0,0 +1,43 @@
+From 791c6d490fe919366fa72e501c34353588e028ee Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Thu, 17 Jan 2019 15:47:54 -0500
+Subject: [PATCH 1176/2940] drm/amd/display: Fix fclk idle state
+
+[Why]
+The earlier change 'Fix 6x4K displays' led to fclk value
+idling at higher DPM level.
+
+[How]
+Apply the fix only to respective multi-display configuration.
+
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
+index 2c64333fa8f8..e164d61951ea 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
+@@ -624,7 +624,15 @@ static void dce11_pplib_apply_display_requirements(
+ dc,
+ context->bw.dce.sclk_khz);
+
+- pp_display_cfg->min_dcfclock_khz = pp_display_cfg->min_engine_clock_khz;
++ /*
++ * As workaround for >4x4K lightup set dcfclock to min_engine_clock value.
++ * This is not required for less than 5 displays,
++ * thus don't request decfclk in dc to avoid impact
++ * on power saving.
++ *
++ */
++ pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4)?
++ pp_display_cfg->min_engine_clock_khz : 0;
+
+ pp_display_cfg->min_engine_clock_deep_sleep_khz
+ = context->bw.dce.sclk_deep_sleep_khz;
+--
+2.17.1
+