diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1153-drm-amd-powerplay-support-Vega10-SOCclk-and-DCEFclk-.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1153-drm-amd-powerplay-support-Vega10-SOCclk-and-DCEFclk-.patch | 160 |
1 files changed, 160 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1153-drm-amd-powerplay-support-Vega10-SOCclk-and-DCEFclk-.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1153-drm-amd-powerplay-support-Vega10-SOCclk-and-DCEFclk-.patch new file mode 100644 index 00000000..f818b93e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1153-drm-amd-powerplay-support-Vega10-SOCclk-and-DCEFclk-.patch @@ -0,0 +1,160 @@ +From 0d057589be70e8ff3f13aefd20261d9339bcbac8 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Fri, 25 Jan 2019 14:09:40 +0800 +Subject: [PATCH 1153/2940] drm/amd/powerplay: support Vega10 SOCclk and + DCEFclk dpm level settings + +Enable SOCclk and DCEFclk dpm level retrieving and setting on Vega10. + +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 83 +++++++++++++++++++ + .../drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 1 + + 2 files changed, 84 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index d1e262844619..8c1871907c6f 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -72,6 +72,21 @@ static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2}; + #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L + #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L + ++typedef enum { ++ CLK_SMNCLK = 0, ++ CLK_SOCCLK, ++ CLK_MP0CLK, ++ CLK_MP1CLK, ++ CLK_LCLK, ++ CLK_DCEFCLK, ++ CLK_VCLK, ++ CLK_DCLK, ++ CLK_ECLK, ++ CLK_UCLK, ++ CLK_GFXCLK, ++ CLK_COUNT, ++} CLOCK_ID_e; ++ + static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic); + + struct vega10_power_state *cast_phw_vega10_power_state( +@@ -3486,6 +3501,17 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) + } + } + ++ if (!data->registry_data.socclk_dpm_key_disabled) { ++ if (data->smc_state_table.soc_boot_level != ++ data->dpm_table.soc_table.dpm_state.soft_min_level) { ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_SetSoftMinSocclkByIndex, ++ data->smc_state_table.soc_boot_level); ++ data->dpm_table.soc_table.dpm_state.soft_min_level = ++ data->smc_state_table.soc_boot_level; ++ } ++ } ++ + return 0; + } + +@@ -3517,6 +3543,17 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr) + } + } + ++ if (!data->registry_data.socclk_dpm_key_disabled) { ++ if (data->smc_state_table.soc_max_level != ++ data->dpm_table.soc_table.dpm_state.soft_max_level) { ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_SetSoftMaxSocclkByIndex, ++ data->smc_state_table.soc_max_level); ++ data->dpm_table.soc_table.dpm_state.soft_max_level = ++ data->smc_state_table.soc_max_level; ++ } ++ } ++ + return 0; + } + +@@ -4029,6 +4066,24 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, + + break; + ++ case PP_SOCCLK: ++ data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0; ++ data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0; ++ ++ PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), ++ "Failed to upload boot level to lowest!", ++ return -EINVAL); ++ ++ PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), ++ "Failed to upload dpm max level to highest!", ++ return -EINVAL); ++ ++ break; ++ ++ case PP_DCEFCLK: ++ pr_info("Setting DCEFCLK min/max dpm level is not supported!\n"); ++ break; ++ + case PP_PCIE: + default: + break; +@@ -4274,6 +4329,8 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, + struct vega10_hwmgr *data = hwmgr->backend; + struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); + struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); ++ struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table); ++ struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table); + struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); + struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL; + +@@ -4304,6 +4361,32 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, + i, mclk_table->dpm_levels[i].value / 100, + (i == now) ? "*" : ""); + break; ++ case PP_SOCCLK: ++ if (data->registry_data.socclk_dpm_key_disabled) ++ break; ++ ++ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex); ++ now = smum_get_argument(hwmgr); ++ ++ for (i = 0; i < soc_table->count; i++) ++ size += sprintf(buf + size, "%d: %uMhz %s\n", ++ i, soc_table->dpm_levels[i].value / 100, ++ (i == now) ? "*" : ""); ++ break; ++ case PP_DCEFCLK: ++ if (data->registry_data.dcefclk_dpm_key_disabled) ++ break; ++ ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK); ++ now = smum_get_argument(hwmgr); ++ ++ for (i = 0; i < dcef_table->count; i++) ++ size += sprintf(buf + size, "%d: %uMhz %s\n", ++ i, dcef_table->dpm_levels[i].value / 100, ++ (dcef_table->dpm_levels[i].value / 100 == now) ? ++ "*" : ""); ++ break; + case PP_PCIE: + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex); + now = smum_get_argument(hwmgr); +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h +index 89870556de1b..f752b4ad0c8a 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h +@@ -199,6 +199,7 @@ struct vega10_smc_state_table { + uint32_t vce_boot_level; + uint32_t gfx_max_level; + uint32_t mem_max_level; ++ uint32_t soc_max_level; + uint8_t vr_hot_gpio; + uint8_t ac_dc_gpio; + uint8_t therm_out_gpio; +-- +2.17.1 + |