diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1084-drm-amd-display-Check-if-registers-are-available-bef.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1084-drm-amd-display-Check-if-registers-are-available-bef.patch | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1084-drm-amd-display-Check-if-registers-are-available-bef.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1084-drm-amd-display-Check-if-registers-are-available-bef.patch new file mode 100644 index 00000000..54d5c636 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1084-drm-amd-display-Check-if-registers-are-available-bef.patch @@ -0,0 +1,88 @@ +From 1aaa8a90b322bdae9c485a093fbc658299ce6ca3 Mon Sep 17 00:00:00 2001 +From: Eric Bernstein <eric.bernstein@amd.com> +Date: Mon, 19 Nov 2018 10:52:10 -0500 +Subject: [PATCH 1084/2940] drm/amd/display: Check if registers are available + before accessing + +Check if VERT_FILTER_INIT_BOT and BLACK_OFFSET registers +exists in the DCN SCL IP block before trying to access. + +Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 42 +++++++++++-------- + 1 file changed, 24 insertions(+), 18 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +index 4a863a5dab41..c7642e748297 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +@@ -597,11 +597,13 @@ static void dpp1_dscl_set_manual_ratio_init( + SCL_V_INIT_FRAC, init_frac, + SCL_V_INIT_INT, init_int); + +- init_frac = dc_fixpt_u0d19(data->inits.v_bot) << 5; +- init_int = dc_fixpt_floor(data->inits.v_bot); +- REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0, +- SCL_V_INIT_FRAC_BOT, init_frac, +- SCL_V_INIT_INT_BOT, init_int); ++ if (REG(SCL_VERT_FILTER_INIT_BOT)) { ++ init_frac = dc_fixpt_u0d19(data->inits.v_bot) << 5; ++ init_int = dc_fixpt_floor(data->inits.v_bot); ++ REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0, ++ SCL_V_INIT_FRAC_BOT, init_frac, ++ SCL_V_INIT_INT_BOT, init_int); ++ } + + init_frac = dc_fixpt_u0d19(data->inits.v_c) << 5; + init_int = dc_fixpt_floor(data->inits.v_c); +@@ -609,11 +611,13 @@ static void dpp1_dscl_set_manual_ratio_init( + SCL_V_INIT_FRAC_C, init_frac, + SCL_V_INIT_INT_C, init_int); + +- init_frac = dc_fixpt_u0d19(data->inits.v_c_bot) << 5; +- init_int = dc_fixpt_floor(data->inits.v_c_bot); +- REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0, +- SCL_V_INIT_FRAC_BOT_C, init_frac, +- SCL_V_INIT_INT_BOT_C, init_int); ++ if (REG(SCL_VERT_FILTER_INIT_BOT_C)) { ++ init_frac = dc_fixpt_u0d19(data->inits.v_c_bot) << 5; ++ init_int = dc_fixpt_floor(data->inits.v_c_bot); ++ REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0, ++ SCL_V_INIT_FRAC_BOT_C, init_frac, ++ SCL_V_INIT_INT_BOT_C, init_int); ++ } + } + + +@@ -688,15 +692,17 @@ void dpp1_dscl_set_scaler_manual_scale( + return; + + /* Black offsets */ +- if (ycbcr) +- REG_SET_2(SCL_BLACK_OFFSET, 0, +- SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y, +- SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR); +- else ++ if (REG(SCL_BLACK_OFFSET)) { ++ if (ycbcr) ++ REG_SET_2(SCL_BLACK_OFFSET, 0, ++ SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y, ++ SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR); ++ else + +- REG_SET_2(SCL_BLACK_OFFSET, 0, +- SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y, +- SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y); ++ REG_SET_2(SCL_BLACK_OFFSET, 0, ++ SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y, ++ SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y); ++ } + + /* Manually calculate scale ratio and init values */ + dpp1_dscl_set_manual_ratio_init(dpp, scl_data); +-- +2.17.1 + |