diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1036-drm-amdgpu-simplify-IH-programming.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1036-drm-amdgpu-simplify-IH-programming.patch | 438 |
1 files changed, 438 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1036-drm-amdgpu-simplify-IH-programming.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1036-drm-amdgpu-simplify-IH-programming.patch new file mode 100644 index 00000000..17a3d48f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1036-drm-amdgpu-simplify-IH-programming.patch @@ -0,0 +1,438 @@ +From a9ab78be2272be165128b1ef290b90090e3f909f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Tue, 18 Sep 2018 14:24:49 +0200 +Subject: [PATCH 1036/2940] drm/amdgpu: simplify IH programming +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Calculate all the addresses and pointers in amdgpu_ih.c + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 34 +++++++++++++++-------- + drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 23 +++++++++------- + drivers/gpu/drm/amd/amdgpu/cik_ih.c | 9 +++---- + drivers/gpu/drm/amd/amdgpu/cz_ih.c | 11 ++++---- + drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 9 +++---- + drivers/gpu/drm/amd/amdgpu/si_ih.c | 9 +++---- + drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 27 +++++-------------- + drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 36 +++++++++---------------- + 8 files changed, 73 insertions(+), 85 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +index fb8dd6179926..d0a5db777b6d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +@@ -52,6 +52,8 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, + ih->use_bus_addr = use_bus_addr; + + if (use_bus_addr) { ++ dma_addr_t dma_addr; ++ + if (ih->ring) + return 0; + +@@ -59,21 +61,26 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, + * add them to the end of the ring allocation. + */ + ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8, +- &ih->rb_dma_addr, GFP_KERNEL); ++ &dma_addr, GFP_KERNEL); + if (ih->ring == NULL) + return -ENOMEM; + + memset((void *)ih->ring, 0, ih->ring_size + 8); +- ih->wptr_offs = (ih->ring_size / 4) + 0; +- ih->rptr_offs = (ih->ring_size / 4) + 1; ++ ih->gpu_addr = dma_addr; ++ ih->wptr_addr = dma_addr + ih->ring_size; ++ ih->wptr_cpu = &ih->ring[ih->ring_size / 4]; ++ ih->rptr_addr = dma_addr + ih->ring_size + 4; ++ ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1]; + } else { +- r = amdgpu_device_wb_get(adev, &ih->wptr_offs); ++ unsigned wptr_offs, rptr_offs; ++ ++ r = amdgpu_device_wb_get(adev, &wptr_offs); + if (r) + return r; + +- r = amdgpu_device_wb_get(adev, &ih->rptr_offs); ++ r = amdgpu_device_wb_get(adev, &rptr_offs); + if (r) { +- amdgpu_device_wb_free(adev, ih->wptr_offs); ++ amdgpu_device_wb_free(adev, wptr_offs); + return r; + } + +@@ -82,10 +89,15 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, + &ih->ring_obj, &ih->gpu_addr, + (void **)&ih->ring); + if (r) { +- amdgpu_device_wb_free(adev, ih->rptr_offs); +- amdgpu_device_wb_free(adev, ih->wptr_offs); ++ amdgpu_device_wb_free(adev, rptr_offs); ++ amdgpu_device_wb_free(adev, wptr_offs); + return r; + } ++ ++ ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; ++ ih->wptr_cpu = &adev->wb.wb[wptr_offs]; ++ ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; ++ ih->rptr_cpu = &adev->wb.wb[rptr_offs]; + } + return 0; + } +@@ -109,13 +121,13 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) + * add them to the end of the ring allocation. + */ + dma_free_coherent(adev->dev, ih->ring_size + 8, +- (void *)ih->ring, ih->rb_dma_addr); ++ (void *)ih->ring, ih->gpu_addr); + ih->ring = NULL; + } else { + amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, + (void **)&ih->ring); +- amdgpu_device_wb_free(adev, ih->wptr_offs); +- amdgpu_device_wb_free(adev, ih->rptr_offs); ++ amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); ++ amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); + } + } + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h +index d810fd73d574..1ccb1831382a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h +@@ -31,20 +31,25 @@ struct amdgpu_iv_entry; + * R6xx+ IH ring + */ + struct amdgpu_ih_ring { +- struct amdgpu_bo *ring_obj; +- volatile uint32_t *ring; +- unsigned rptr; + unsigned ring_size; +- uint64_t gpu_addr; + uint32_t ptr_mask; +- atomic_t lock; +- bool enabled; +- unsigned wptr_offs; +- unsigned rptr_offs; + u32 doorbell_index; + bool use_doorbell; + bool use_bus_addr; +- dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */ ++ ++ struct amdgpu_bo *ring_obj; ++ volatile uint32_t *ring; ++ uint64_t gpu_addr; ++ ++ uint64_t wptr_addr; ++ volatile uint32_t *wptr_cpu; ++ ++ uint64_t rptr_addr; ++ volatile uint32_t *rptr_cpu; ++ ++ bool enabled; ++ unsigned rptr; ++ atomic_t lock; + }; + + /* provided by the ih block */ +diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c +index 884aa9b81e86..721c757156e8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c ++++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c +@@ -103,9 +103,9 @@ static void cik_ih_disable_interrupts(struct amdgpu_device *adev) + */ + static int cik_ih_irq_init(struct amdgpu_device *adev) + { ++ struct amdgpu_ih_ring *ih = &adev->irq.ih; + int rb_bufsz; + u32 interrupt_cntl, ih_cntl, ih_rb_cntl; +- u64 wptr_off; + + /* disable irqs */ + cik_ih_disable_interrupts(adev); +@@ -131,9 +131,8 @@ static int cik_ih_irq_init(struct amdgpu_device *adev) + ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK; + + /* set the writeback address whether it's enabled or not */ +- wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); +- WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); +- WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); ++ WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); ++ WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); + + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + +@@ -188,7 +187,7 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev, + { + u32 wptr, tmp; + +- wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]); ++ wptr = le32_to_cpu(*ih->wptr_cpu); + + if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { + wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; +diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c +index c59eed041fb5..61024b9c7a4b 100644 +--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c ++++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c +@@ -103,9 +103,9 @@ static void cz_ih_disable_interrupts(struct amdgpu_device *adev) + */ + static int cz_ih_irq_init(struct amdgpu_device *adev) + { +- int rb_bufsz; ++ struct amdgpu_ih_ring *ih = &adev->irq.ih; + u32 interrupt_cntl, ih_cntl, ih_rb_cntl; +- u64 wptr_off; ++ int rb_bufsz; + + /* disable irqs */ + cz_ih_disable_interrupts(adev); +@@ -133,9 +133,8 @@ static int cz_ih_irq_init(struct amdgpu_device *adev) + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); + + /* set the writeback address whether it's enabled or not */ +- wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); +- WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); +- WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); ++ WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); ++ WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); + + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + +@@ -190,7 +189,7 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev, + { + u32 wptr, tmp; + +- wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]); ++ wptr = le32_to_cpu(*ih->wptr_cpu); + + if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { + wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); +diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +index f006ed509db3..b1626e1d2f5d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c ++++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +@@ -103,9 +103,9 @@ static void iceland_ih_disable_interrupts(struct amdgpu_device *adev) + */ + static int iceland_ih_irq_init(struct amdgpu_device *adev) + { ++ struct amdgpu_ih_ring *ih = &adev->irq.ih; + int rb_bufsz; + u32 interrupt_cntl, ih_cntl, ih_rb_cntl; +- u64 wptr_off; + + /* disable irqs */ + iceland_ih_disable_interrupts(adev); +@@ -133,9 +133,8 @@ static int iceland_ih_irq_init(struct amdgpu_device *adev) + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); + + /* set the writeback address whether it's enabled or not */ +- wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); +- WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); +- WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); ++ WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); ++ WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); + + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + +@@ -190,7 +189,7 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev, + { + u32 wptr, tmp; + +- wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]); ++ wptr = le32_to_cpu(*ih->wptr_cpu); + + if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { + wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); +diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c +index 5cabc9687f76..8c50c9cab455 100644 +--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c ++++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c +@@ -57,9 +57,9 @@ static void si_ih_disable_interrupts(struct amdgpu_device *adev) + + static int si_ih_irq_init(struct amdgpu_device *adev) + { ++ struct amdgpu_ih_ring *ih = &adev->irq.ih; + int rb_bufsz; + u32 interrupt_cntl, ih_cntl, ih_rb_cntl; +- u64 wptr_off; + + si_ih_disable_interrupts(adev); + WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8); +@@ -76,9 +76,8 @@ static int si_ih_irq_init(struct amdgpu_device *adev) + (rb_bufsz << 1) | + IH_WPTR_WRITEBACK_ENABLE; + +- wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); +- WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); +- WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); ++ WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); ++ WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); + WREG32(IH_RB_CNTL, ih_rb_cntl); + WREG32(IH_RB_RPTR, 0); + WREG32(IH_RB_WPTR, 0); +@@ -105,7 +104,7 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev, + { + u32 wptr, tmp; + +- wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]); ++ wptr = le32_to_cpu(*ih->wptr_cpu); + + if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { + wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; +diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +index 30e3911dedb5..a20b711a6756 100644 +--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c ++++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +@@ -99,9 +99,9 @@ static void tonga_ih_disable_interrupts(struct amdgpu_device *adev) + */ + static int tonga_ih_irq_init(struct amdgpu_device *adev) + { +- int rb_bufsz; + u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr; +- u64 wptr_off; ++ struct amdgpu_ih_ring *ih = &adev->irq.ih; ++ int rb_bufsz; + + /* disable irqs */ + tonga_ih_disable_interrupts(adev); +@@ -118,10 +118,7 @@ static int tonga_ih_irq_init(struct amdgpu_device *adev) + WREG32(mmINTERRUPT_CNTL, interrupt_cntl); + + /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ +- if (adev->irq.ih.use_bus_addr) +- WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8); +- else +- WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); ++ WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8); + + rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); + ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); +@@ -136,12 +133,8 @@ static int tonga_ih_irq_init(struct amdgpu_device *adev) + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + + /* set the writeback address whether it's enabled or not */ +- if (adev->irq.ih.use_bus_addr) +- wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); +- else +- wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); +- WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); +- WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); ++ WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); ++ WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); + + /* set rptr, wptr to 0 */ + WREG32(mmIH_RB_RPTR, 0); +@@ -198,10 +191,7 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev, + { + u32 wptr, tmp; + +- if (adev->irq.ih.use_bus_addr) +- wptr = le32_to_cpu(ih->ring[ih->wptr_offs]); +- else +- wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]); ++ wptr = le32_to_cpu(*ih->wptr_cpu); + + if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { + wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); +@@ -263,10 +253,7 @@ static void tonga_ih_set_rptr(struct amdgpu_device *adev, + { + if (ih->use_doorbell) { + /* XXX check if swapping is necessary on BE */ +- if (ih->use_bus_addr) +- ih->ring[ih->rptr_offs] = ih->rptr; +- else +- adev->wb.wb[ih->rptr_offs] = ih->rptr; ++ *ih->rptr_cpu = ih->rptr; + WDOORBELL32(ih->doorbell_index, ih->rptr); + } else { + WREG32(mmIH_RB_RPTR, ih->rptr); +diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +index 28b0e9a6cc42..3e9ebb0de94d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c ++++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +@@ -86,11 +86,11 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) + */ + static int vega10_ih_irq_init(struct amdgpu_device *adev) + { ++ struct amdgpu_ih_ring *ih = &adev->irq.ih; + int ret = 0; + int rb_bufsz; + u32 ih_rb_cntl, ih_doorbell_rtpr; + u32 tmp; +- u64 wptr_off; + + /* disable irqs */ + vega10_ih_disable_interrupts(adev); +@@ -99,15 +99,11 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) + + ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); + /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ +- if (adev->irq.ih.use_bus_addr) { +- WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8); +- WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff); +- ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1); +- } else { +- WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); +- WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev->irq.ih.gpu_addr >> 40) & 0xff); +- ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4); +- } ++ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); ++ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ++ (adev->irq.ih.gpu_addr >> 40) & 0xff); ++ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, ++ ih->use_bus_addr ? 1 : 4); + rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); +@@ -124,12 +120,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); + + /* set the writeback address whether it's enabled or not */ +- if (adev->irq.ih.use_bus_addr) +- wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); +- else +- wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); +- WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); +- WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFFFF); ++ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, ++ lower_32_bits(ih->wptr_addr)); ++ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, ++ upper_32_bits(ih->wptr_addr) & 0xFFFF); + + /* set rptr, wptr to 0 */ + WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); +@@ -196,10 +190,7 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, + { + u32 wptr, tmp; + +- if (ih->use_bus_addr) +- wptr = le32_to_cpu(ih->ring[ih->wptr_offs]); +- else +- wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]); ++ wptr = le32_to_cpu(*ih->wptr_cpu); + + if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { + wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); +@@ -275,10 +266,7 @@ static void vega10_ih_set_rptr(struct amdgpu_device *adev, + { + if (ih->use_doorbell) { + /* XXX check if swapping is necessary on BE */ +- if (ih->use_bus_addr) +- ih->ring[ih->rptr_offs] = ih->rptr; +- else +- adev->wb.wb[ih->rptr_offs] = ih->rptr; ++ *ih->rptr_cpu = ih->rptr; + WDOORBELL32(ih->doorbell_index, ih->rptr); + } else { + WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); +-- +2.17.1 + |