diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1009-drm-amd-display-remove-sink-reference-in-dc_stream_s.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1009-drm-amd-display-remove-sink-reference-in-dc_stream_s.patch | 863 |
1 files changed, 863 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1009-drm-amd-display-remove-sink-reference-in-dc_stream_s.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1009-drm-amd-display-remove-sink-reference-in-dc_stream_s.patch new file mode 100644 index 00000000..2789150d --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1009-drm-amd-display-remove-sink-reference-in-dc_stream_s.patch @@ -0,0 +1,863 @@ +From 7e62e9e677314ae3e57ef72866a1279d3bfe5d42 Mon Sep 17 00:00:00 2001 +From: Jun Lei <Jun.Lei@amd.com> +Date: Fri, 9 Nov 2018 09:21:21 -0500 +Subject: [PATCH 1009/2940] drm/amd/display: remove sink reference in + dc_stream_state + +[why] +dc_stream_state containing a pointer to sink is poor design. +Sink describes the display, and the specifications or capabilities +it has. That information is irrelevant for dc_stream_state, which describes +hardware state, and is generally used for hardware programming. It +could further be argued that dc_sink itself is just a convenience dc +provides, and DC should be perfectly capable of programming hardware +without any dc_sinks (for example, emulated sinks). + +[how] +Phase 1: +Deprecate use of dc_sink pointer in dc_stream. Most references are trivial +to remove, but some call sites are risky (such as is_timing_changed) with +no obvious logical replacement. These will be removed in follow up change. + +Add dc_link pointer to dc_stream. This is the typical reason DC really needed +sink pointer, and most call sites are replaced with this. + +DMs also need minor updates, as all 3 DMs leverage stream->sink for +some functionality. this is replaced instead by a pointer to private data +inside dc_stream_state, which is used by DMs as a quality of life improvment +for some key functionality. it allows DMs to set pointers have to their own objects +which associate OS objects to dc_stream_states (such as DisplayTarget +and amdgpu_dm_connector). Without the private pointer, DMs would be +forced to perform a lookup for callbacks. + +Signed-off-by: Jun Lei <Jun.Lei@amd.com> +Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> +Acked-by: David Francis <David.Francis@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++-- + .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 +-- + .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 +- + drivers/gpu/drm/amd/display/dc/core/dc.c | 11 ++-- + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 54 +++++++++---------- + .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 6 +-- + .../drm/amd/display/dc/core/dc_link_hwss.c | 9 ++-- + .../gpu/drm/amd/display/dc/core/dc_resource.c | 14 ++--- + .../gpu/drm/amd/display/dc/core/dc_stream.c | 30 +++++------ + drivers/gpu/drm/amd/display/dc/dc_link.h | 1 + + drivers/gpu/drm/amd/display/dc/dc_stream.h | 13 ++++- + .../gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 10 ++-- + .../drm/amd/display/dc/dce/dce_link_encoder.c | 2 +- + .../display/dc/dce110/dce110_hw_sequencer.c | 26 ++++----- + .../amd/display/dc/dce110/dce110_resource.c | 2 +- + .../amd/display/dc/dce112/dce112_resource.c | 2 +- + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- + .../amd/display/dc/dcn10/dcn10_link_encoder.c | 2 +- + .../drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- + 19 files changed, 103 insertions(+), 101 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 17719fbfc695..c42c1a746540 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -2682,10 +2682,10 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, + timing_out->v_border_bottom = 0; + /* TODO: un-hardcode */ + if (drm_mode_is_420_only(info, mode_in) +- && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) ++ && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) + timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; + else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) +- && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) ++ && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) + timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; + else + timing_out->pixel_encoding = PIXEL_ENCODING_RGB; +@@ -2727,7 +2727,7 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, + + stream->out_transfer_func->type = TF_TYPE_PREDEFINED; + stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; +- if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) ++ if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) + adjust_colour_depth_from_display_info(timing_out, info); + } + +@@ -2921,6 +2921,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, + goto finish; + } + ++ stream->dm_stream_context = aconnector; ++ + list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { + /* Search for preferred mode */ + if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { +@@ -2972,7 +2974,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, + drm_connector, + sink); + +- update_stream_signal(stream); ++ update_stream_signal(stream, sink); + + if (dm_state && dm_state->freesync_capable) + stream->ignore_msa_timing_param = true; +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +index 39997d977efb..b0bc8314c6d5 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +@@ -192,7 +192,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( + int bpp = 0; + int pbn = 0; + +- aconnector = stream->sink->priv; ++ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; + + if (!aconnector || !aconnector->mst_port) + return false; +@@ -284,7 +284,7 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( + struct drm_dp_mst_topology_mgr *mst_mgr; + int ret; + +- aconnector = stream->sink->priv; ++ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; + + if (!aconnector || !aconnector->mst_port) + return false; +@@ -312,7 +312,7 @@ bool dm_helpers_dp_mst_send_payload_allocation( + struct drm_dp_mst_port *mst_port; + int ret; + +- aconnector = stream->sink->priv; ++ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; + + if (!aconnector || !aconnector->mst_port) + return false; +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +index 3208188b7ed4..2a2ce2998a81 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +@@ -961,7 +961,7 @@ bool dcn_validate_bandwidth( + v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/ + v->output_format[input_idx] = pipe->stream->timing.pixel_encoding == + PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444; +- v->output[input_idx] = pipe->stream->sink->sink_signal == ++ v->output[input_idx] = pipe->stream->signal == + SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp; + v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc; + if (v->output[input_idx] == dcn_bw_hdmi) { +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 5a029a2b9416..cfa468ad0f26 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -384,7 +384,7 @@ void dc_stream_set_dither_option(struct dc_stream_state *stream, + enum dc_dither_option option) + { + struct bit_depth_reduction_params params; +- struct dc_link *link = stream->sink->link; ++ struct dc_link *link = stream->link; + struct pipe_ctx *pipes = NULL; + int i; + +@@ -526,9 +526,8 @@ void dc_link_set_preferred_link_settings(struct dc *dc, + + for (i = 0; i < MAX_PIPES; i++) { + pipe = &dc->current_state->res_ctx.pipe_ctx[i]; +- if (pipe->stream && pipe->stream->sink +- && pipe->stream->sink->link) { +- if (pipe->stream->sink->link == link) ++ if (pipe->stream && pipe->stream->link) { ++ if (pipe->stream->link == link) + break; + } + } +@@ -1045,7 +1044,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c + + /* Program all planes within new context*/ + for (i = 0; i < context->stream_count; i++) { +- const struct dc_sink *sink = context->streams[i]->sink; ++ const struct dc_link *link = context->streams[i]->link; + + if (!context->streams[i]->mode_changed) + continue; +@@ -1070,7 +1069,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c + } + } + +- CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}", ++ CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}", + context->streams[i]->timing.h_addressable, + context->streams[i]->timing.v_addressable, + context->streams[i]->timing.h_total, +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +index a44d5d701f84..dde3a6064d41 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +@@ -789,7 +789,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) + return false; + } + +- sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock; ++ sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock; + sink->converter_disable_audio = converter_disable_audio; + + link->local_sink = sink; +@@ -1372,7 +1372,7 @@ static void dpcd_configure_panel_mode( + static void enable_stream_features(struct pipe_ctx *pipe_ctx) + { + struct dc_stream_state *stream = pipe_ctx->stream; +- struct dc_link *link = stream->sink->link; ++ struct dc_link *link = stream->link; + union down_spread_ctrl old_downspread; + union down_spread_ctrl new_downspread; + +@@ -1397,7 +1397,7 @@ static enum dc_status enable_link_dp( + struct dc_stream_state *stream = pipe_ctx->stream; + enum dc_status status; + bool skip_video_pattern; +- struct dc_link *link = stream->sink->link; ++ struct dc_link *link = stream->link; + struct dc_link_settings link_settings = {0}; + enum dp_panel_mode panel_mode; + +@@ -1414,8 +1414,8 @@ static enum dc_status enable_link_dp( + pipe_ctx->clock_source->id, + &link_settings); + +- if (stream->sink->edid_caps.panel_patch.dppowerup_delay > 0) { +- int delay_dp_power_up_in_ms = stream->sink->edid_caps.panel_patch.dppowerup_delay; ++ if (stream->sink_patches.dppowerup_delay > 0) { ++ int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay; + + msleep(delay_dp_power_up_in_ms); + } +@@ -1448,7 +1448,7 @@ static enum dc_status enable_link_edp( + { + enum dc_status status; + struct dc_stream_state *stream = pipe_ctx->stream; +- struct dc_link *link = stream->sink->link; ++ struct dc_link *link = stream->link; + /*in case it is not on*/ + link->dc->hwss.edp_power_control(link, true); + link->dc->hwss.edp_wait_for_hpd_ready(link, true); +@@ -1463,7 +1463,7 @@ static enum dc_status enable_link_dp_mst( + struct dc_state *state, + struct pipe_ctx *pipe_ctx) + { +- struct dc_link *link = pipe_ctx->stream->sink->link; ++ struct dc_link *link = pipe_ctx->stream->link; + + /* sink signal type after MST branch is MST. Multiple MST sinks + * share one link. Link DP PHY is enable or training only once. +@@ -1597,7 +1597,7 @@ static bool i2c_write(struct pipe_ctx *pipe_ctx, + cmd.payloads = &payload; + + if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, +- pipe_ctx->stream->sink->link, &cmd)) ++ pipe_ctx->stream->link, &cmd)) + return true; + + return false; +@@ -1651,7 +1651,7 @@ static void write_i2c_retimer_setting( + else { + i2c_success = + dal_ddc_service_query_ddc_data( +- pipe_ctx->stream->sink->link->ddc, ++ pipe_ctx->stream->link->ddc, + slave_address, &offset, 1, &value, 1); + if (!i2c_success) + /* Write failure */ +@@ -1704,7 +1704,7 @@ static void write_i2c_retimer_setting( + else { + i2c_success = + dal_ddc_service_query_ddc_data( +- pipe_ctx->stream->sink->link->ddc, ++ pipe_ctx->stream->link->ddc, + slave_address, &offset, 1, &value, 1); + if (!i2c_success) + /* Write failure */ +@@ -1929,7 +1929,7 @@ static void write_i2c_redriver_setting( + static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) + { + struct dc_stream_state *stream = pipe_ctx->stream; +- struct dc_link *link = stream->sink->link; ++ struct dc_link *link = stream->link; + enum dc_color_depth display_color_depth; + enum engine_id eng_id; + struct ext_hdmi_settings settings = {0}; +@@ -1943,7 +1943,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) + is_over_340mhz = true; + + if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { +- unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps & ++ unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & + EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; + if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { + /* DP159, Retimer settings */ +@@ -1964,11 +1964,11 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) + + if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) + dal_ddc_service_write_scdc_data( +- stream->sink->link->ddc, ++ stream->link->ddc, + stream->phy_pix_clk, + stream->timing.flags.LTE_340MCSC_SCRAMBLE); + +- memset(&stream->sink->link->cur_link_settings, 0, ++ memset(&stream->link->cur_link_settings, 0, + sizeof(struct dc_link_settings)); + + display_color_depth = stream->timing.display_color_depth; +@@ -1989,12 +1989,12 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) + static void enable_link_lvds(struct pipe_ctx *pipe_ctx) + { + struct dc_stream_state *stream = pipe_ctx->stream; +- struct dc_link *link = stream->sink->link; ++ struct dc_link *link = stream->link; + + if (stream->phy_pix_clk == 0) + stream->phy_pix_clk = stream->timing.pix_clk_khz; + +- memset(&stream->sink->link->cur_link_settings, 0, ++ memset(&stream->link->cur_link_settings, 0, + sizeof(struct dc_link_settings)); + + link->link_enc->funcs->enable_lvds_output( +@@ -2145,7 +2145,7 @@ enum dc_status dc_link_validate_mode_timing( + struct dc_link *link, + const struct dc_crtc_timing *timing) + { +- uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk; ++ uint32_t max_pix_clk = stream->link->dongle_max_pix_clk; + struct dpcd_caps *dpcd_caps = &link->dpcd_caps; + + /* A hack to avoid failing any modes for EDID override feature on +@@ -2219,7 +2219,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, + for (i = 0; i < MAX_PIPES; i++) { + if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) { + if (core_dc->current_state->res_ctx. +- pipe_ctx[i].stream->sink->link ++ pipe_ctx[i].stream->link + == link) + /* DMCU -1 for all controller id values, + * therefore +1 here +@@ -2279,7 +2279,7 @@ void core_link_resume(struct dc_link *link) + static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) + { + struct dc_link_settings *link_settings = +- &stream->sink->link->cur_link_settings; ++ &stream->link->cur_link_settings; + uint32_t link_rate_in_mbps = + link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ; + struct fixed31_32 mbps = dc_fixpt_from_int( +@@ -2386,7 +2386,7 @@ static void update_mst_stream_alloc_table( + static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) + { + struct dc_stream_state *stream = pipe_ctx->stream; +- struct dc_link *link = stream->sink->link; ++ struct dc_link *link = stream->link; + struct link_encoder *link_encoder = link->link_enc; + struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; + struct dp_mst_stream_allocation_table proposed_table = {0}; +@@ -2466,7 +2466,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) + static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) + { + struct dc_stream_state *stream = pipe_ctx->stream; +- struct dc_link *link = stream->sink->link; ++ struct dc_link *link = stream->link; + struct link_encoder *link_encoder = link->link_enc; + struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; + struct dp_mst_stream_allocation_table proposed_table = {0}; +@@ -2551,8 +2551,8 @@ void core_link_enable_stream( + DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); + + if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) { +- stream->sink->link->link_enc->funcs->setup( +- stream->sink->link->link_enc, ++ stream->link->link_enc->funcs->setup( ++ stream->link->link_enc, + pipe_ctx->stream->signal); + pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync( + pipe_ctx->stream_res.stream_enc, +@@ -2604,7 +2604,7 @@ void core_link_enable_stream( + + if (status != DC_OK) { + DC_LOG_WARNING("enabling link %u failed: %d\n", +- pipe_ctx->stream->sink->link->link_index, ++ pipe_ctx->stream->link->link_index, + status); + + /* Abort stream enable *unless* the failure was due to +@@ -2633,12 +2633,12 @@ void core_link_enable_stream( + allocate_mst_payload(pipe_ctx); + + core_dc->hwss.unblank_stream(pipe_ctx, +- &pipe_ctx->stream->sink->link->cur_link_settings); ++ &pipe_ctx->stream->link->cur_link_settings); + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + enable_stream_features(pipe_ctx); + +- dc_link_set_backlight_level(pipe_ctx->stream->sink->link, ++ dc_link_set_backlight_level(pipe_ctx->stream->link, + pipe_ctx->stream->bl_pwm_level, + 0, + pipe_ctx->stream); +@@ -2657,7 +2657,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option) + + core_dc->hwss.disable_stream(pipe_ctx, option); + +- disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal); ++ disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal); + } + + void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +index 0caacb60b02f..39562c93808d 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +@@ -1634,7 +1634,7 @@ void decide_link_settings(struct dc_stream_state *stream, + + req_bw = bandwidth_in_kbps_from_timing(&stream->timing); + +- link = stream->sink->link; ++ link = stream->link; + + /* if preferred is specified through AMDDP, use it, if it's enough + * to drive the mode +@@ -1656,7 +1656,7 @@ void decide_link_settings(struct dc_stream_state *stream, + } + + /* EDP use the link cap setting */ +- if (stream->sink->sink_signal == SIGNAL_TYPE_EDP) { ++ if (link->connector_signal == SIGNAL_TYPE_EDP) { + *link_setting = link->verified_link_cap; + return; + } +@@ -2621,7 +2621,7 @@ bool dc_link_dp_set_test_pattern( + memset(&training_pattern, 0, sizeof(training_pattern)); + + for (i = 0; i < MAX_PIPES; i++) { +- if (pipes[i].stream->sink->link == link) { ++ if (pipes[i].stream->link == link) { + pipe_ctx = &pipes[i]; + break; + } +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +index 0065ec7d5330..a179c09580c3 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +@@ -70,8 +70,7 @@ void dp_enable_link_phy( + */ + for (i = 0; i < MAX_PIPES; i++) { + if (pipes[i].stream != NULL && +- pipes[i].stream->sink != NULL && +- pipes[i].stream->sink->link == link) { ++ pipes[i].stream->link == link) { + if (pipes[i].clock_source != NULL && + pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { + pipes[i].clock_source = dp_cs; +@@ -279,10 +278,8 @@ void dp_retrain_link_dp_test(struct dc_link *link, + for (i = 0; i < MAX_PIPES; i++) { + if (pipes[i].stream != NULL && + !pipes[i].top_pipe && +- pipes[i].stream->sink != NULL && +- pipes[i].stream->sink->link != NULL && +- pipes[i].stream_res.stream_enc != NULL && +- pipes[i].stream->sink->link == link) { ++ pipes[i].stream->link != NULL && ++ pipes[i].stream_res.stream_enc != NULL) { + udelay(100); + + pipes[i].stream_res.stream_enc->funcs->dp_blank( +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index dda459f3b0da..d0af542adf19 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -1559,7 +1559,7 @@ static struct stream_encoder *find_first_free_match_stream_enc_for_link( + { + int i; + int j = -1; +- struct dc_link *link = stream->sink->link; ++ struct dc_link *link = stream->link; + + for (i = 0; i < pool->stream_enc_count; i++) { + if (!res_ctx->is_stream_enc_acquired[i] && +@@ -1748,7 +1748,7 @@ static struct dc_stream_state *find_pll_sharable_stream( + if (resource_are_streams_timing_synchronizable( + stream_needs_pll, stream_has_pll) + && !dc_is_dp_signal(stream_has_pll->signal) +- && stream_has_pll->sink->link->connector_signal ++ && stream_has_pll->link->connector_signal + != SIGNAL_TYPE_VIRTUAL) + return stream_has_pll; + +@@ -1850,7 +1850,7 @@ enum dc_status resource_map_pool_resources( + true); + + /* TODO: Add check if ASIC support and EDID audio */ +- if (!stream->sink->converter_disable_audio && ++ if (!stream->converter_disable_audio && + dc_is_audio_capable_signal(pipe_ctx->stream->signal) && + stream->audio_info.mode_count) { + pipe_ctx->stream_res.audio = find_first_free_audio( +@@ -2112,7 +2112,7 @@ static void set_avi_info_frame( + itc = true; + itc_value = 1; + +- support = stream->sink->edid_caps.content_support; ++ support = stream->content_support; + + if (itc) { + if (!support.bits.valid_content_type) { +@@ -2151,8 +2151,8 @@ static void set_avi_info_frame( + + /* TODO : We should handle YCC quantization */ + /* but we do not have matrix calculation */ +- if (stream->sink->edid_caps.qs_bit == 1 && +- stream->sink->edid_caps.qy_bit == 1) { ++ if (stream->qs_bit == 1 && ++ stream->qy_bit == 1) { + if (color_space == COLOR_SPACE_SRGB || + color_space == COLOR_SPACE_2020_RGB_FULLRANGE) { + hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE; +@@ -2596,7 +2596,7 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, + enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) + { + struct dc *core_dc = dc; +- struct dc_link *link = stream->sink->link; ++ struct dc_link *link = stream->link; + struct timing_generator *tg = core_dc->res_pool->timing_generators[0]; + enum dc_status res = DC_OK; + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +index 66e5c4623a49..8f9dc6f54bf1 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +@@ -35,20 +35,17 @@ + /******************************************************************************* + * Private functions + ******************************************************************************/ +-void update_stream_signal(struct dc_stream_state *stream) ++void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink) + { +- +- struct dc_sink *dc_sink = stream->sink; +- +- if (dc_sink->sink_signal == SIGNAL_TYPE_NONE) +- stream->signal = stream->sink->link->connector_signal; ++ if (sink->sink_signal == SIGNAL_TYPE_NONE) ++ stream->signal = stream->link->connector_signal; + else +- stream->signal = dc_sink->sink_signal; ++ stream->signal = sink->sink_signal; + + if (dc_is_dvi_signal(stream->signal)) { + if (stream->ctx->dc->caps.dual_link_dvi && + stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK && +- stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) ++ sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) + stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; + else + stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK; +@@ -61,10 +58,15 @@ static void construct(struct dc_stream_state *stream, + uint32_t i = 0; + + stream->sink = dc_sink_data; +- stream->ctx = stream->sink->ctx; +- + dc_sink_retain(dc_sink_data); + ++ stream->ctx = dc_sink_data->ctx; ++ stream->link = dc_sink_data->link; ++ stream->sink_patches = dc_sink_data->edid_caps.panel_patch; ++ stream->converter_disable_audio = dc_sink_data->converter_disable_audio; ++ stream->qs_bit = dc_sink_data->edid_caps.qs_bit; ++ stream->qy_bit = dc_sink_data->edid_caps.qy_bit; ++ + /* Copy audio modes */ + /* TODO - Remove this translation */ + for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++) +@@ -100,7 +102,7 @@ static void construct(struct dc_stream_state *stream, + /* EDID CAP translation for HDMI 2.0 */ + stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; + +- update_stream_signal(stream); ++ update_stream_signal(stream, dc_sink_data); + + stream->out_transfer_func = dc_create_transfer_func(); + stream->out_transfer_func->type = TF_TYPE_BYPASS; +@@ -339,11 +341,7 @@ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream) + stream->timing.v_total, + stream->timing.pixel_encoding, + stream->timing.display_color_depth); +- DC_LOG_DC( +- "\tsink name: %s, serial: %d\n", +- stream->sink->edid_caps.display_name, +- stream->sink->edid_caps.serial_number); + DC_LOG_DC( + "\tlink: %d\n", +- stream->sink->link->link_index); ++ stream->link->link_index); + } +diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h +index 29f19d57ff7a..8a0e57620345 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_link.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h +@@ -110,6 +110,7 @@ struct dc_link { + union ddi_channel_mapping ddi_channel_mapping; + struct connector_device_tag_info device_tag; + struct dpcd_caps dpcd_caps; ++ uint32_t dongle_max_pix_clk; + unsigned short chip_caps; + unsigned int dpcd_sink_count; + enum edp_revision edp_revision; +diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h +index be34d638e15d..39b3016f7d2e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h +@@ -51,7 +51,13 @@ struct freesync_context { + }; + + struct dc_stream_state { ++ // sink is deprecated, new code should not reference ++ // this pointer + struct dc_sink *sink; ++ ++ struct dc_link *link; ++ struct dc_panel_patch sink_patches; ++ union display_content_support content_support; + struct dc_crtc_timing timing; + struct dc_crtc_timing_adjust adjust; + struct dc_info_packet vrr_infopacket; +@@ -80,6 +86,9 @@ struct dc_stream_state { + enum view_3d_format view_format; + + bool ignore_msa_timing_param; ++ bool converter_disable_audio; ++ uint8_t qs_bit; ++ uint8_t qy_bit; + + unsigned long long periodic_fn_vsync_delta; + +@@ -105,6 +114,8 @@ struct dc_stream_state { + bool dpms_off; + bool apply_edp_fast_boot_optimization; + ++ void *dm_stream_context; ++ + struct dc_cursor_attributes cursor_attributes; + struct dc_cursor_position cursor_position; + uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode +@@ -256,7 +267,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( + */ + struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); + +-void update_stream_signal(struct dc_stream_state *stream); ++void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink); + + void dc_stream_retain(struct dc_stream_state *dc_stream); + void dc_stream_release(struct dc_stream_state *dc_stream); +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c +index 6da7b78ffd73..0174183c97d7 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c +@@ -480,15 +480,15 @@ void dce110_fill_display_configs( + cfg->src_height = stream->src.height; + cfg->src_width = stream->src.width; + cfg->ddi_channel_mapping = +- stream->sink->link->ddi_channel_mapping.raw; ++ stream->link->ddi_channel_mapping.raw; + cfg->transmitter = +- stream->sink->link->link_enc->transmitter; ++ stream->link->link_enc->transmitter; + cfg->link_settings.lane_count = +- stream->sink->link->cur_link_settings.lane_count; ++ stream->link->cur_link_settings.lane_count; + cfg->link_settings.link_rate = +- stream->sink->link->cur_link_settings.link_rate; ++ stream->link->cur_link_settings.link_rate; + cfg->link_settings.link_spread = +- stream->sink->link->cur_link_settings.link_spread; ++ stream->link->cur_link_settings.link_spread; + cfg->sym_clock = stream->phy_pix_clk; + /* Round v_refresh*/ + cfg->v_refresh = stream->timing.pix_clk_khz * 1000; +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +index 3e18ea84b1f9..1d794c65cc8b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +@@ -788,7 +788,7 @@ bool dce110_link_encoder_validate_output_with_stream( + case SIGNAL_TYPE_DVI_DUAL_LINK: + is_valid = dce110_link_encoder_validate_dvi_output( + enc110, +- stream->sink->link->connector_signal, ++ stream->link->connector_signal, + stream->signal, + &stream->timing); + break; +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 0247b5be3b93..43159acc8bb9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -617,12 +617,11 @@ dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx, + static enum dc_status bios_parser_crtc_source_select( + struct pipe_ctx *pipe_ctx) + { +- struct dc_bios *dcb; ++ struct dc_bios *dcb = pipe_ctx->stream->ctx->dc_bios; + /* call VBIOS table to set CRTC source for the HW + * encoder block + * note: video bios clears all FMT setting here. */ + struct bp_crtc_source_select crtc_source_select = {0}; +- const struct dc_sink *sink = pipe_ctx->stream->sink; + + crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id; + crtc_source_select.controller_id = pipe_ctx->stream_res.tg->inst + 1; +@@ -652,8 +651,6 @@ static enum dc_status bios_parser_crtc_source_select( + break; + } + +- dcb = sink->ctx->dc_bios; +- + if (BP_RESULT_OK != dcb->funcs->crtc_source_select( + dcb, + &crtc_source_select)) { +@@ -692,10 +689,10 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) + void dce110_enable_stream(struct pipe_ctx *pipe_ctx) + { + enum dc_lane_count lane_count = +- pipe_ctx->stream->sink->link->cur_link_settings.lane_count; ++ pipe_ctx->stream->link->cur_link_settings.lane_count; + + struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; +- struct dc_link *link = pipe_ctx->stream->sink->link; ++ struct dc_link *link = pipe_ctx->stream->link; + + + uint32_t active_total_with_borders; +@@ -1048,7 +1045,7 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option) + void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) + { + struct dc_stream_state *stream = pipe_ctx->stream; +- struct dc_link *link = stream->sink->link; ++ struct dc_link *link = stream->link; + struct dc *dc = pipe_ctx->stream->ctx->dc; + + if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) +@@ -1073,7 +1070,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, + { + struct encoder_unblank_param params = { { 0 } }; + struct dc_stream_state *stream = pipe_ctx->stream; +- struct dc_link *link = stream->sink->link; ++ struct dc_link *link = stream->link; + + /* only 3 items below are used by unblank */ + params.pixel_clk_khz = +@@ -1090,7 +1087,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, + void dce110_blank_stream(struct pipe_ctx *pipe_ctx) + { + struct dc_stream_state *stream = pipe_ctx->stream; +- struct dc_link *link = stream->sink->link; ++ struct dc_link *link = stream->link; + + if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { + link->dc->hwss.edp_backlight_control(link, false); +@@ -1408,7 +1405,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( + + pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; + +- pipe_ctx->stream->sink->link->psr_enabled = false; ++ pipe_ctx->stream->link->psr_enabled = false; + + return DC_OK; + } +@@ -1813,18 +1810,15 @@ static bool should_enable_fbc(struct dc *dc, + if (i == dc->res_pool->pipe_count) + return false; + +- if (!pipe_ctx->stream->sink) +- return false; +- +- if (!pipe_ctx->stream->sink->link) ++ if (!pipe_ctx->stream->link) + return false; + + /* Only supports eDP */ +- if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP) ++ if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) + return false; + + /* PSR should not be enabled */ +- if (pipe_ctx->stream->sink->link->psr_enabled) ++ if (pipe_ctx->stream->link->psr_enabled) + return false; + + /* Nothing to compress */ +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +index e33d11785b1f..3c989b8e1ae3 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +@@ -780,7 +780,7 @@ static void get_pixel_clock_parameters( + * in pll_adjust_pix_clk + */ + pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; +- pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; ++ pixel_clk_params->encoder_object_id = stream->link->link_enc->id; + pixel_clk_params->signal_type = pipe_ctx->stream->signal; + pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; + /* TODO: un-hardcode*/ +diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +index 969d4e72dc94..c2a713399726 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +@@ -763,7 +763,7 @@ static struct clock_source *find_matching_pll( + const struct resource_pool *pool, + const struct dc_stream_state *const stream) + { +- switch (stream->sink->link->link_enc->transmitter) { ++ switch (stream->link->link_enc->transmitter) { + case TRANSMITTER_UNIPHY_A: + return pool->clock_sources[DCE112_CLK_SRC_PLL0]; + case TRANSMITTER_UNIPHY_B: +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 46a92788e17e..231df1f3e473 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -2523,7 +2523,7 @@ static void dcn10_config_stereo_parameters( + timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA || + timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) { + enum display_dongle_type dongle = \ +- stream->sink->link->ddc->dongle_type; ++ stream->link->ddc->dongle_type; + if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER || + dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER || + dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c +index 477ab9222216..aefe8974469d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c +@@ -738,7 +738,7 @@ bool dcn10_link_encoder_validate_output_with_stream( + case SIGNAL_TYPE_DVI_DUAL_LINK: + is_valid = dcn10_link_encoder_validate_dvi_output( + enc10, +- stream->sink->link->connector_signal, ++ stream->link->connector_signal, + stream->signal, + &stream->timing); + break; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +index 5d4772dec0ba..6ab1ca221579 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +@@ -975,7 +975,7 @@ static void get_pixel_clock_parameters( + { + const struct dc_stream_state *stream = pipe_ctx->stream; + pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; +- pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; ++ pixel_clk_params->encoder_object_id = stream->link->link_enc->id; + pixel_clk_params->signal_type = pipe_ctx->stream->signal; + pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; + /* TODO: un-hardcode*/ +-- +2.17.1 + |