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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1001-drm-amd-display-Fix-runtime-errors-for-diagnostic-te.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1001-drm-amd-display-Fix-runtime-errors-for-diagnostic-te.patch318
1 files changed, 318 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1001-drm-amd-display-Fix-runtime-errors-for-diagnostic-te.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1001-drm-amd-display-Fix-runtime-errors-for-diagnostic-te.patch
new file mode 100644
index 00000000..c459bc9f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1001-drm-amd-display-Fix-runtime-errors-for-diagnostic-te.patch
@@ -0,0 +1,318 @@
+From 81be5a90726f543ceb0430b65bb089391bf39b0b Mon Sep 17 00:00:00 2001
+From: Eric Bernstein <eric.bernstein@amd.com>
+Date: Fri, 9 Nov 2018 16:51:55 -0500
+Subject: [PATCH 1001/2940] drm/amd/display: Fix runtime errors for diagnostic
+ tests
+
+1) Rename and make public definition of input CSC matrix struct.
+2) Make wm_read_state() function an interface of hubbub, and check
+ if watermark registers exist before read/write to them.
+3) Check if OTG_INTERLACE_CONTROL register exists before updating
+4) Add dummy functions for set_input/output_transfer function to avoid
+ errors due to differences in CM registers.
+5) Added missing register field definition in header file
+
+Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 12 +--
+ .../drm/amd/display/dc/dcn10/dcn10_hubbub.c | 73 +++++++++++--------
+ .../drm/amd/display/dc/dcn10/dcn10_hubbub.h | 12 ---
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
+ .../dc/dcn10/dcn10_hw_sequencer_debug.c | 2 +-
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 21 +++---
+ .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 15 ++++
+ drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 5 ++
+ 8 files changed, 78 insertions(+), 64 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+index 116977eb24e2..41f0f4c912e7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+@@ -51,10 +51,6 @@
+
+ #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
+
+-struct dcn10_input_csc_matrix {
+- enum dc_color_space color_space;
+- uint16_t regval[12];
+-};
+
+ enum dcn10_coef_filter_type_sel {
+ SCL_COEF_LUMA_VERT_FILTER = 0,
+@@ -99,7 +95,7 @@ enum gamut_remap_select {
+ GAMUT_REMAP_COMB_COEFF
+ };
+
+-static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = {
++static const struct dpp_input_csc_matrix dpp_input_csc_matrix[] = {
+ {COLOR_SPACE_SRGB,
+ {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
+ {COLOR_SPACE_SRGB_LIMITED,
+@@ -454,7 +450,7 @@ void dpp1_program_input_csc(
+ {
+ struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+ int i;
+- int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
++ int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
+ const uint16_t *regval = NULL;
+ uint32_t cur_select = 0;
+ enum dcn10_input_csc_select select;
+@@ -467,8 +463,8 @@ void dpp1_program_input_csc(
+
+ if (tbl_entry == NULL) {
+ for (i = 0; i < arr_size; i++)
+- if (dcn10_input_csc_matrix[i].color_space == color_space) {
+- regval = dcn10_input_csc_matrix[i].regval;
++ if (dpp_input_csc_matrix[i].color_space == color_space) {
++ regval = dpp_input_csc_matrix[i].regval;
+ break;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+index c7d1e678ebf5..eb31a5ed6dff 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+@@ -275,14 +275,16 @@ void hubbub1_program_watermarks(
+ watermarks->a.urgent_ns, prog_wm_value);
+ }
+
+- if (safe_to_lower || watermarks->a.pte_meta_urgent_ns > hubbub->watermarks.a.pte_meta_urgent_ns) {
+- hubbub->watermarks.a.pte_meta_urgent_ns = watermarks->a.pte_meta_urgent_ns;
+- prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
+- DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->a.pte_meta_urgent_ns, prog_wm_value);
++ if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A)) {
++ if (safe_to_lower || watermarks->a.pte_meta_urgent_ns > hubbub->watermarks.a.pte_meta_urgent_ns) {
++ hubbub->watermarks.a.pte_meta_urgent_ns = watermarks->a.pte_meta_urgent_ns;
++ prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
++ DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->a.pte_meta_urgent_ns, prog_wm_value);
++ }
+ }
+
+ if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
+@@ -338,14 +340,16 @@ void hubbub1_program_watermarks(
+ watermarks->b.urgent_ns, prog_wm_value);
+ }
+
+- if (safe_to_lower || watermarks->b.pte_meta_urgent_ns > hubbub->watermarks.b.pte_meta_urgent_ns) {
+- hubbub->watermarks.b.pte_meta_urgent_ns = watermarks->b.pte_meta_urgent_ns;
+- prog_wm_value = convert_and_clamp(watermarks->b.pte_meta_urgent_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
+- DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->b.pte_meta_urgent_ns, prog_wm_value);
++ if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B)) {
++ if (safe_to_lower || watermarks->b.pte_meta_urgent_ns > hubbub->watermarks.b.pte_meta_urgent_ns) {
++ hubbub->watermarks.b.pte_meta_urgent_ns = watermarks->b.pte_meta_urgent_ns;
++ prog_wm_value = convert_and_clamp(watermarks->b.pte_meta_urgent_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
++ DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->b.pte_meta_urgent_ns, prog_wm_value);
++ }
+ }
+
+ if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
+@@ -401,14 +405,16 @@ void hubbub1_program_watermarks(
+ watermarks->c.urgent_ns, prog_wm_value);
+ }
+
+- if (safe_to_lower || watermarks->c.pte_meta_urgent_ns > hubbub->watermarks.c.pte_meta_urgent_ns) {
+- hubbub->watermarks.c.pte_meta_urgent_ns = watermarks->c.pte_meta_urgent_ns;
+- prog_wm_value = convert_and_clamp(watermarks->c.pte_meta_urgent_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
+- DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->c.pte_meta_urgent_ns, prog_wm_value);
++ if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C)) {
++ if (safe_to_lower || watermarks->c.pte_meta_urgent_ns > hubbub->watermarks.c.pte_meta_urgent_ns) {
++ hubbub->watermarks.c.pte_meta_urgent_ns = watermarks->c.pte_meta_urgent_ns;
++ prog_wm_value = convert_and_clamp(watermarks->c.pte_meta_urgent_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
++ DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->c.pte_meta_urgent_ns, prog_wm_value);
++ }
+ }
+
+ if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
+@@ -464,14 +470,16 @@ void hubbub1_program_watermarks(
+ watermarks->d.urgent_ns, prog_wm_value);
+ }
+
+- if (safe_to_lower || watermarks->d.pte_meta_urgent_ns > hubbub->watermarks.d.pte_meta_urgent_ns) {
+- hubbub->watermarks.d.pte_meta_urgent_ns = watermarks->d.pte_meta_urgent_ns;
+- prog_wm_value = convert_and_clamp(watermarks->d.pte_meta_urgent_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
+- DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->d.pte_meta_urgent_ns, prog_wm_value);
++ if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D)) {
++ if (safe_to_lower || watermarks->d.pte_meta_urgent_ns > hubbub->watermarks.d.pte_meta_urgent_ns) {
++ hubbub->watermarks.d.pte_meta_urgent_ns = watermarks->d.pte_meta_urgent_ns;
++ prog_wm_value = convert_and_clamp(watermarks->d.pte_meta_urgent_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
++ DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->d.pte_meta_urgent_ns, prog_wm_value);
++ }
+ }
+
+ if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
+@@ -837,6 +845,7 @@ static const struct hubbub_funcs hubbub1_funcs = {
+ .dcc_support_swizzle = hubbub1_dcc_support_swizzle,
+ .dcc_support_pixel_format = hubbub1_dcc_support_pixel_format,
+ .get_dcc_compression_cap = hubbub1_get_dcc_compression_cap,
++ .wm_read_state = hubbub1_wm_read_state,
+ };
+
+ void hubbub1_construct(struct hubbub *hubbub,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+index d0f03d152913..aca67633ee58 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+@@ -165,18 +165,6 @@ struct dcn_hubbub_mask {
+
+ struct dc;
+
+-struct dcn_hubbub_wm_set {
+- uint32_t wm_set;
+- uint32_t data_urgent;
+- uint32_t pte_meta_urgent;
+- uint32_t sr_enter;
+- uint32_t sr_exit;
+- uint32_t dram_clk_chanage;
+-};
+-
+-struct dcn_hubbub_wm {
+- struct dcn_hubbub_wm_set sets[4];
+-};
+
+ struct hubbub {
+ const struct hubbub_funcs *funcs;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 4645804f0035..cef17789b744 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -95,7 +95,7 @@ void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
+ struct dcn_hubbub_wm wm = {0};
+ int i;
+
+- hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
++ dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
+
+ DTN_INFO("HUBBUB WM: data_urgent pte_meta_urgent"
+ " sr_enter sr_exit dram_clk_change\n");
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+index cd469014baa3..82175820b0cf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+@@ -81,7 +81,7 @@ static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned i
+ const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;
+ static const unsigned int frac = 1000;
+
+- hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
++ dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
+
+ chars_printed = snprintf_count(pBuf, remaining_buffer, "wm_set_index,data_urgent,pte_meta_urgent,sr_enter,sr_exit,dram_clk_chanage\n");
+ remaining_buffer -= chars_printed;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+index 7c138615f17d..cdb3f096eb25 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+@@ -299,16 +299,17 @@ void optc1_program_timing(
+ }
+
+ /* Interlace */
+- if (patched_crtc_timing.flags.INTERLACE == 1) {
+- REG_UPDATE(OTG_INTERLACE_CONTROL,
+- OTG_INTERLACE_ENABLE, 1);
+- v_init = v_init / 2;
+- if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end)
+- v_fp2 = v_fp2 / 2;
+- } else
+- REG_UPDATE(OTG_INTERLACE_CONTROL,
+- OTG_INTERLACE_ENABLE, 0);
+-
++ if (REG(OTG_INTERLACE_CONTROL)) {
++ if (patched_crtc_timing.flags.INTERLACE == 1) {
++ REG_UPDATE(OTG_INTERLACE_CONTROL,
++ OTG_INTERLACE_ENABLE, 1);
++ v_init = v_init / 2;
++ if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end)
++ v_fp2 = v_fp2 / 2;
++ } else
++ REG_UPDATE(OTG_INTERLACE_CONTROL,
++ OTG_INTERLACE_ENABLE, 0);
++ }
+
+ /* VTG enable set to 0 first VInit */
+ REG_UPDATE(CONTROL,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+index 02f757dd70d4..dc0bb5bd8cac 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+@@ -39,6 +39,18 @@ enum segment_order {
+ segment_order__non_contiguous,
+ };
+
++struct dcn_hubbub_wm_set {
++ uint32_t wm_set;
++ uint32_t data_urgent;
++ uint32_t pte_meta_urgent;
++ uint32_t sr_enter;
++ uint32_t sr_exit;
++ uint32_t dram_clk_chanage;
++};
++
++struct dcn_hubbub_wm {
++ struct dcn_hubbub_wm_set sets[4];
++};
+
+ struct hubbub_funcs {
+ void (*update_dchub)(
+@@ -58,6 +70,9 @@ struct hubbub_funcs {
+ bool (*dcc_support_pixel_format)(
+ enum surface_pixel_format format,
+ unsigned int *bytes_per_element);
++
++ void (*wm_read_state)(struct hubbub *hubbub,
++ struct dcn_hubbub_wm *wm);
+ };
+
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+index e894e649ce5a..fb7967b39edb 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+@@ -39,6 +39,11 @@ struct dpp {
+
+ };
+
++struct dpp_input_csc_matrix {
++ enum dc_color_space color_space;
++ uint16_t regval[12];
++};
++
+ struct dpp_grph_csc_adjustment {
+ struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
+ enum graphics_gamut_adjust_type gamut_adjust_type;
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-19 22:26:00 +0000