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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0899-drm-amd-powerplay-support-SoftMin-Max-setting-for-so.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0899-drm-amd-powerplay-support-SoftMin-Max-setting-for-so.patch214
1 files changed, 214 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0899-drm-amd-powerplay-support-SoftMin-Max-setting-for-so.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0899-drm-amd-powerplay-support-SoftMin-Max-setting-for-so.patch
new file mode 100644
index 00000000..f1688071
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0899-drm-amd-powerplay-support-SoftMin-Max-setting-for-so.patch
@@ -0,0 +1,214 @@
+From e39b86e9b03e79b31c9b7bb40e1e64c270035d30 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 28 Nov 2018 16:41:02 +0800
+Subject: [PATCH 0899/2940] drm/amd/powerplay: support SoftMin/Max setting for
+ some specific DPM
+
+For some case, no need to force SoftMin/Max settings for all DPMs.
+It's OK to force on some specific DPM only.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 54 +++++++++++--------
+ 1 file changed, 32 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index 2679d1240fa1..247bf9dbec5d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -1660,14 +1660,15 @@ static uint32_t vega20_find_highest_dpm_level(
+ return i;
+ }
+
+-static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
++static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
+ {
+ struct vega20_hwmgr *data =
+ (struct vega20_hwmgr *)(hwmgr->backend);
+ uint32_t min_freq;
+ int ret = 0;
+
+- if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
++ if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
++ (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
+ min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
+ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+ hwmgr, PPSMC_MSG_SetSoftMinByFreq,
+@@ -1676,7 +1677,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
+ return ret);
+ }
+
+- if (data->smu_features[GNLD_DPM_UCLK].enabled) {
++ if (data->smu_features[GNLD_DPM_UCLK].enabled &&
++ (feature_mask & FEATURE_DPM_UCLK_MASK)) {
+ min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
+ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+ hwmgr, PPSMC_MSG_SetSoftMinByFreq,
+@@ -1692,7 +1694,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
+ return ret);
+ }
+
+- if (data->smu_features[GNLD_DPM_UVD].enabled) {
++ if (data->smu_features[GNLD_DPM_UVD].enabled &&
++ (feature_mask & FEATURE_DPM_UVD_MASK)) {
+ min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
+
+ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+@@ -1710,7 +1713,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
+ return ret);
+ }
+
+- if (data->smu_features[GNLD_DPM_VCE].enabled) {
++ if (data->smu_features[GNLD_DPM_VCE].enabled &&
++ (feature_mask & FEATURE_DPM_VCE_MASK)) {
+ min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
+
+ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+@@ -1720,7 +1724,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
+ return ret);
+ }
+
+- if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
++ if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
++ (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
+ min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
+
+ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+@@ -1733,14 +1738,15 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
+ return ret;
+ }
+
+-static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
++static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
+ {
+ struct vega20_hwmgr *data =
+ (struct vega20_hwmgr *)(hwmgr->backend);
+ uint32_t max_freq;
+ int ret = 0;
+
+- if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
++ if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
++ (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
+ max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
+
+ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+@@ -1750,7 +1756,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
+ return ret);
+ }
+
+- if (data->smu_features[GNLD_DPM_UCLK].enabled) {
++ if (data->smu_features[GNLD_DPM_UCLK].enabled &&
++ (feature_mask & FEATURE_DPM_UCLK_MASK)) {
+ max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
+
+ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+@@ -1760,7 +1767,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
+ return ret);
+ }
+
+- if (data->smu_features[GNLD_DPM_UVD].enabled) {
++ if (data->smu_features[GNLD_DPM_UVD].enabled &&
++ (feature_mask & FEATURE_DPM_UVD_MASK)) {
+ max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
+
+ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+@@ -1777,7 +1785,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
+ return ret);
+ }
+
+- if (data->smu_features[GNLD_DPM_VCE].enabled) {
++ if (data->smu_features[GNLD_DPM_VCE].enabled &&
++ (feature_mask & FEATURE_DPM_VCE_MASK)) {
+ max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
+
+ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+@@ -1787,7 +1796,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
+ return ret);
+ }
+
+- if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
++ if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
++ (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
+ max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
+
+ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+@@ -2126,12 +2136,12 @@ static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
+ data->dpm_table.mem_table.dpm_state.soft_max_level =
+ data->dpm_table.mem_table.dpm_levels[soft_level].value;
+
+- ret = vega20_upload_dpm_min_level(hwmgr);
++ ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Failed to upload boot level to highest!",
+ return ret);
+
+- ret = vega20_upload_dpm_max_level(hwmgr);
++ ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Failed to upload dpm max level to highest!",
+ return ret);
+@@ -2158,12 +2168,12 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
+ data->dpm_table.mem_table.dpm_state.soft_max_level =
+ data->dpm_table.mem_table.dpm_levels[soft_level].value;
+
+- ret = vega20_upload_dpm_min_level(hwmgr);
++ ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Failed to upload boot level to highest!",
+ return ret);
+
+- ret = vega20_upload_dpm_max_level(hwmgr);
++ ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Failed to upload dpm max level to highest!",
+ return ret);
+@@ -2176,12 +2186,12 @@ static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
+ {
+ int ret = 0;
+
+- ret = vega20_upload_dpm_min_level(hwmgr);
++ ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Failed to upload DPM Bootup Levels!",
+ return ret);
+
+- ret = vega20_upload_dpm_max_level(hwmgr);
++ ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Failed to upload DPM Max Levels!",
+ return ret);
+@@ -2239,12 +2249,12 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
+ data->dpm_table.gfx_table.dpm_state.soft_max_level =
+ data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
+
+- ret = vega20_upload_dpm_min_level(hwmgr);
++ ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Failed to upload boot level to lowest!",
+ return ret);
+
+- ret = vega20_upload_dpm_max_level(hwmgr);
++ ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Failed to upload dpm max level to highest!",
+ return ret);
+@@ -2259,12 +2269,12 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
+ data->dpm_table.mem_table.dpm_state.soft_max_level =
+ data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
+
+- ret = vega20_upload_dpm_min_level(hwmgr);
++ ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Failed to upload boot level to lowest!",
+ return ret);
+
+- ret = vega20_upload_dpm_max_level(hwmgr);
++ ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Failed to upload dpm max level to highest!",
+ return ret);
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-18 01:50:49 +0000