diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0894-drm-amdgpu-psp-Update-waiting-in-psp-mode1-reset.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0894-drm-amdgpu-psp-Update-waiting-in-psp-mode1-reset.patch | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0894-drm-amdgpu-psp-Update-waiting-in-psp-mode1-reset.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0894-drm-amdgpu-psp-Update-waiting-in-psp-mode1-reset.patch new file mode 100644 index 00000000..12296b45 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0894-drm-amdgpu-psp-Update-waiting-in-psp-mode1-reset.patch @@ -0,0 +1,47 @@ +From 0643c081c0f5b59da325e9bd2bfd9131fe6f89ed Mon Sep 17 00:00:00 2001 +From: Andrey Grodzovsky <andrey.grodzovsky@amd.com> +Date: Fri, 30 Nov 2018 12:24:33 -0500 +Subject: [PATCH 0894/2940] drm/amdgpu/psp: Update waiting in psp mode1 reset. + +No point in use mdelay unless running from interrupt context (which we are not) +This is busy wait which will block the CPU for the entirety of the wait time. +Also, reduce wait time to 500ms as it is done in refernce code because +1s might cause PSP FW TO issues during XGMI hive reset. + +Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +index e79940ec8249..13656adc6344 100644 +--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +@@ -557,7 +557,7 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp) + /*send the mode 1 reset command*/ + WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); + +- mdelay(1000); ++ msleep(500); + + offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); + +diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +index 7efb823dd3b1..7357fd56e614 100644 +--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c ++++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +@@ -592,7 +592,7 @@ static int psp_v3_1_mode1_reset(struct psp_context *psp) + /*send the mode 1 reset command*/ + WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); + +- mdelay(1000); ++ msleep(500); + + offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); + +-- +2.17.1 + |