diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0813-drm-amd-display-fix-pipe-interdependent-hubp-program.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0813-drm-amd-display-fix-pipe-interdependent-hubp-program.patch | 246 |
1 files changed, 246 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0813-drm-amd-display-fix-pipe-interdependent-hubp-program.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0813-drm-amd-display-fix-pipe-interdependent-hubp-program.patch new file mode 100644 index 00000000..8ff8669c --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0813-drm-amd-display-fix-pipe-interdependent-hubp-program.patch @@ -0,0 +1,246 @@ +From f200d901fb1b492ad2b5e77df26978f72af23c03 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Wed, 31 Oct 2018 07:59:54 -0400 +Subject: [PATCH 0813/2940] drm/amd/display: fix pipe interdependent hubp + programming + +A number of registers need to be updated for all active +pipes wherever any pipe causes a change in watermarks. + +This change separates programming of these registers into +a separate function call that is called for all active pipes +during a bw update. + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 87 +++++++++---------- + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 30 +++++++ + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 5 ++ + 3 files changed, 78 insertions(+), 44 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +index 6127fd30899b..345af015d061 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +@@ -573,19 +573,6 @@ void hubp1_program_deadline( + REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, + DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); + +- if (REG(PREFETCH_SETTINS)) +- REG_SET_2(PREFETCH_SETTINS, 0, +- DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, +- VRATIO_PREFETCH, dlg_attr->vratio_prefetch); +- else +- REG_SET_2(PREFETCH_SETTINGS, 0, +- DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, +- VRATIO_PREFETCH, dlg_attr->vratio_prefetch); +- +- REG_SET_2(VBLANK_PARAMETERS_0, 0, +- DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, +- DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); +- + REG_SET(REF_FREQ_TO_PIX_FREQ, 0, + REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); + +@@ -593,9 +580,6 @@ void hubp1_program_deadline( + REG_SET(VBLANK_PARAMETERS_1, 0, + REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); + +- REG_SET(VBLANK_PARAMETERS_3, 0, +- REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); +- + if (REG(NOM_PARAMETERS_0)) + REG_SET(NOM_PARAMETERS_0, 0, + DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); +@@ -610,27 +594,13 @@ void hubp1_program_deadline( + REG_SET(NOM_PARAMETERS_5, 0, + REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); + +- REG_SET_2(PER_LINE_DELIVERY_PRE, 0, +- REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, +- REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); +- + REG_SET_2(PER_LINE_DELIVERY, 0, + REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, + REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); + +- if (REG(PREFETCH_SETTINS_C)) +- REG_SET(PREFETCH_SETTINS_C, 0, +- VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); +- else +- REG_SET(PREFETCH_SETTINGS_C, 0, +- VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); +- + REG_SET(VBLANK_PARAMETERS_2, 0, + REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); + +- REG_SET(VBLANK_PARAMETERS_4, 0, +- REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); +- + if (REG(NOM_PARAMETERS_2)) + REG_SET(NOM_PARAMETERS_2, 0, + DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); +@@ -650,10 +620,6 @@ void hubp1_program_deadline( + QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, + QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); + +- REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, +- MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, +- QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); +- + /* TTU - per luma/chroma */ + /* Assumed surf0 is luma and 1 is chroma */ + +@@ -662,25 +628,15 @@ void hubp1_program_deadline( + QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, + QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); + +- REG_SET(DCN_SURF0_TTU_CNTL1, 0, +- REFCYC_PER_REQ_DELIVERY_PRE, +- ttu_attr->refcyc_per_req_delivery_pre_l); +- + REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, + REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, + QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, + QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); + +- REG_SET(DCN_SURF1_TTU_CNTL1, 0, +- REFCYC_PER_REQ_DELIVERY_PRE, +- ttu_attr->refcyc_per_req_delivery_pre_c); +- + REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, + REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, + QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, + QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); +- REG_SET(DCN_CUR0_TTU_CNTL1, 0, +- REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); + } + + static void hubp1_setup( +@@ -698,6 +654,48 @@ static void hubp1_setup( + hubp1_vready_workaround(hubp, pipe_dest); + } + ++static void hubp1_setup_interdependent( ++ struct hubp *hubp, ++ struct _vcs_dpi_display_dlg_regs_st *dlg_attr, ++ struct _vcs_dpi_display_ttu_regs_st *ttu_attr) ++{ ++ struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); ++ ++ REG_SET_2(PREFETCH_SETTINS, 0, ++ DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, ++ VRATIO_PREFETCH, dlg_attr->vratio_prefetch); ++ ++ REG_SET(PREFETCH_SETTINS_C, 0, ++ VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); ++ ++ REG_SET_2(VBLANK_PARAMETERS_0, 0, ++ DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, ++ DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); ++ ++ REG_SET(VBLANK_PARAMETERS_3, 0, ++ REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); ++ ++ REG_SET(VBLANK_PARAMETERS_4, 0, ++ REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); ++ ++ REG_SET_2(PER_LINE_DELIVERY_PRE, 0, ++ REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, ++ REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); ++ ++ REG_SET(DCN_SURF0_TTU_CNTL1, 0, ++ REFCYC_PER_REQ_DELIVERY_PRE, ++ ttu_attr->refcyc_per_req_delivery_pre_l); ++ REG_SET(DCN_SURF1_TTU_CNTL1, 0, ++ REFCYC_PER_REQ_DELIVERY_PRE, ++ ttu_attr->refcyc_per_req_delivery_pre_c); ++ REG_SET(DCN_CUR0_TTU_CNTL1, 0, ++ REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); ++ ++ REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, ++ MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, ++ QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); ++} ++ + bool hubp1_is_flip_pending(struct hubp *hubp) + { + uint32_t flip_pending = 0; +@@ -1186,6 +1184,7 @@ static const struct hubp_funcs dcn10_hubp_funcs = { + hubp1_program_surface_config, + .hubp_is_flip_pending = hubp1_is_flip_pending, + .hubp_setup = hubp1_setup, ++ .hubp_setup_interdependent = hubp1_setup_interdependent, + .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, + .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings, + .set_blank = hubp1_set_blank, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index a59b89b27583..994c49e81a61 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -2067,6 +2067,10 @@ void update_dchubp_dpp( + &pipe_ctx->ttu_regs, + &pipe_ctx->rq_regs, + &pipe_ctx->pipe_dlg_param); ++ hubp->funcs->hubp_setup_interdependent( ++ hubp, ++ &pipe_ctx->dlg_regs, ++ &pipe_ctx->ttu_regs); + } + + size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; +@@ -2337,6 +2341,32 @@ static void dcn10_apply_ctx_for_surface( + + dcn10_pipe_control_lock(dc, top_pipe_to_program, false); + ++ if (top_pipe_to_program->plane_state && ++ top_pipe_to_program->plane_state->update_flags.bits.full_update) ++ for (i = 0; i < dc->res_pool->pipe_count; i++) { ++ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; ++ ++ /* Skip inactive pipes and ones already updated */ ++ if (!pipe_ctx->stream || pipe_ctx->stream == stream) ++ continue; ++ ++ pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); ++ ++ pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent( ++ pipe_ctx->plane_res.hubp, ++ &pipe_ctx->dlg_regs, ++ &pipe_ctx->ttu_regs); ++ } ++ ++ for (i = 0; i < dc->res_pool->pipe_count; i++) { ++ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; ++ ++ if (!pipe_ctx->stream || pipe_ctx->stream == stream) ++ continue; ++ ++ dcn10_pipe_control_lock(dc, pipe_ctx, false); ++ } ++ + if (num_planes == 0) + false_optc_underflow_wa(dc, stream, tg); + +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +index 8f4f40646b4d..04c6989aac58 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +@@ -63,6 +63,11 @@ struct hubp_funcs { + struct _vcs_dpi_display_rq_regs_st *rq_regs, + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); + ++ void (*hubp_setup_interdependent)( ++ struct hubp *hubp, ++ struct _vcs_dpi_display_dlg_regs_st *dlg_regs, ++ struct _vcs_dpi_display_ttu_regs_st *ttu_regs); ++ + void (*dcc_control)(struct hubp *hubp, bool enable, + bool independent_64b_blks); + void (*mem_program_viewport)( +-- +2.17.1 + |