diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0525-drm-amdgpu-vcn-Apply-new-UMC-enable-for-VNC-DPG-mode.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0525-drm-amdgpu-vcn-Apply-new-UMC-enable-for-VNC-DPG-mode.patch | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0525-drm-amdgpu-vcn-Apply-new-UMC-enable-for-VNC-DPG-mode.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0525-drm-amdgpu-vcn-Apply-new-UMC-enable-for-VNC-DPG-mode.patch new file mode 100644 index 00000000..fbe7ebaa --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0525-drm-amdgpu-vcn-Apply-new-UMC-enable-for-VNC-DPG-mode.patch @@ -0,0 +1,44 @@ +From 23a6e945ccf498e00cf407deed309ea385dd1d08 Mon Sep 17 00:00:00 2001 +From: James Zhu <James.Zhu@amd.com> +Date: Tue, 9 Oct 2018 16:57:26 -0400 +Subject: [PATCH 0525/2940] drm/amdgpu/vcn:Apply new UMC enable for VNC DPG + mode + +Apply new UMC enable for VNC Dynamic Power Gate mode + +Signed-off-by: James Zhu <James.Zhu@amd.com> +Acked-by: Leo Liu <leo.liu@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +index 93e2a408a59a..153f23acf8dd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -829,13 +829,18 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) + /* enable VCPU clock */ + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); + ++ /* boot up the VCPU */ ++ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, ++ ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); ++ + /* enable UMC */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); + +- /* boot up the VCPU */ +- WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0); +- mdelay(10); ++ tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); ++ tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; ++ tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; ++ WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); + + for (i = 0; i < 10; ++i) { + uint32_t status; +-- +2.17.1 + |