diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0513-drm-amdgpu-vcn-Add-ring-W-R-PTR-check-for-VCN-DPG-mo.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0513-drm-amdgpu-vcn-Add-ring-W-R-PTR-check-for-VCN-DPG-mo.patch | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0513-drm-amdgpu-vcn-Add-ring-W-R-PTR-check-for-VCN-DPG-mo.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0513-drm-amdgpu-vcn-Add-ring-W-R-PTR-check-for-VCN-DPG-mo.patch new file mode 100644 index 00000000..94a5b6b5 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0513-drm-amdgpu-vcn-Add-ring-W-R-PTR-check-for-VCN-DPG-mo.patch @@ -0,0 +1,40 @@ +From b95bd361bfe6f5f3a3085279efa69a36c7fc9b37 Mon Sep 17 00:00:00 2001 +From: James Zhu <James.Zhu@amd.com> +Date: Wed, 3 Oct 2018 17:36:58 -0400 +Subject: [PATCH 0513/2940] drm/amdgpu/vcn:Add ring W/R PTR check for VCN DPG + mode stop + +Add ring write/read pointer check for VCN dynamic power gate mode +stop,to make sure that no job is left in ring before turn off DPG mode. + +Signed-off-by: James Zhu <James.Zhu@amd.com> +Acked-by: Leo Liu <leo.liu@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +index 029ed6d16f57..a6094868008c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -1171,6 +1171,16 @@ static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); + ++ if (ret_code) { ++ int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; ++ /* wait for read ptr to be equal to write ptr */ ++ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); ++ ++ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, ++ UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, ++ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); ++ } ++ + /* disable dynamic power gating mode */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, + ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); +-- +2.17.1 + |