diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0452-drm-amd-display-WA-for-DF-keeps-awake-after-S0i3.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0452-drm-amd-display-WA-for-DF-keeps-awake-after-S0i3.patch | 95 |
1 files changed, 95 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0452-drm-amd-display-WA-for-DF-keeps-awake-after-S0i3.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0452-drm-amd-display-WA-for-DF-keeps-awake-after-S0i3.patch new file mode 100644 index 00000000..f0bcc569 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0452-drm-amd-display-WA-for-DF-keeps-awake-after-S0i3.patch @@ -0,0 +1,95 @@ +From 78a8466f6802e4a9b4e695027276e5c250623d68 Mon Sep 17 00:00:00 2001 +From: Yongqiang Sun <yongqiang.sun@amd.com> +Date: Mon, 17 Sep 2018 10:05:51 -0400 +Subject: [PATCH 0452/2940] drm/amd/display: WA for DF keeps awake after S0i3. + +[Why] +DF keeps awake after S0i3 resume due to DRAM_STATE_CNTL +is set by bios command table during dcn init_hw. + +[How] +As a work around, check STATE_CNTL status before init_hw, +if it is 0 before init_hw and set to 1 after init_hw, +change it to 0. + +Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 17 +++++++++++++++++ + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h | 4 ++++ + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 ++++++++++++++ + 3 files changed, 35 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +index 297e1e5b53d3..4254e7e1a509 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +@@ -87,6 +87,23 @@ void hubbub1_wm_read_state(struct hubbub *hubbub, + s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); + } + ++void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub) ++{ ++ REG_UPDATE(DCHUBBUB_ARB_DRAM_STATE_CNTL, ++ DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, 0); ++} ++ ++bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub) ++{ ++ uint32_t enable = 0; ++ ++ REG_GET(DCHUBBUB_ARB_DRAM_STATE_CNTL, ++ DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, &enable); ++ ++ return true ? false : enable; ++} ++ ++ + bool hubbub1_verify_allow_pstate_change_high( + struct hubbub *hubbub) + { +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +index d6e596eef4c5..d0f03d152913 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +@@ -203,6 +203,10 @@ void hubbub1_program_watermarks( + unsigned int refclk_mhz, + bool safe_to_lower); + ++void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub); ++ ++bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubub); ++ + void hubbub1_toggle_watermark_change_req( + struct hubbub *hubbub); + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index a881ff5559ec..193184affefb 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -997,7 +997,21 @@ static void dcn10_init_hw(struct dc *dc) + } else { + + if (!dcb->funcs->is_accelerated_mode(dcb)) { ++ bool allow_self_fresh_force_enable = ++ hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub); ++ + bios_golden_init(dc); ++ ++ /* WA for making DF sleep when idle after resume from S0i3. ++ * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by ++ * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0 ++ * before calling command table and it changed to 1 after, ++ * it should be set back to 0. ++ */ ++ if (allow_self_fresh_force_enable == false && ++ hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub)) ++ hubbub1_disable_allow_self_refresh(dc->res_pool->hubbub); ++ + disable_vga(dc->hwseq); + } + +-- +2.17.1 + |