diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0162-drm-amd-display-Define-registers-for-dcn10.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0162-drm-amd-display-Define-registers-for-dcn10.patch | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0162-drm-amd-display-Define-registers-for-dcn10.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0162-drm-amd-display-Define-registers-for-dcn10.patch new file mode 100644 index 00000000..5082655d --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0162-drm-amd-display-Define-registers-for-dcn10.patch @@ -0,0 +1,38 @@ +From 4bc06d3d1f491cde5f8489f40838bbfc30f42db7 Mon Sep 17 00:00:00 2001 +From: Nikola Cornij <nikola.cornij@amd.com> +Date: Fri, 13 Jul 2018 18:19:07 -0400 +Subject: [PATCH 0162/2940] drm/amd/display: Define registers for dcn10 + +Define register for dcn10 for future changes + +Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +index 6b3e4ded155b..67f3e4dd95c1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +@@ -260,6 +260,7 @@ struct dcn10_stream_enc_registers { + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\ ++ SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\ + SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\ + SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\ +@@ -364,6 +365,7 @@ struct dcn10_stream_enc_registers { + type DP_SEC_GSP5_ENABLE;\ + type DP_SEC_GSP6_ENABLE;\ + type DP_SEC_GSP7_ENABLE;\ ++ type DP_SEC_GSP7_SEND;\ + type DP_SEC_MPG_ENABLE;\ + type DP_VID_STREAM_DIS_DEFER;\ + type DP_VID_STREAM_ENABLE;\ +-- +2.17.1 + |