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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0129-drm-amdgpu-add-freesync-ioctl.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0129-drm-amdgpu-add-freesync-ioctl.patch135
1 files changed, 135 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0129-drm-amdgpu-add-freesync-ioctl.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0129-drm-amdgpu-add-freesync-ioctl.patch
new file mode 100644
index 00000000..b7721782
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0129-drm-amdgpu-add-freesync-ioctl.patch
@@ -0,0 +1,135 @@
+From ed858912f8ab0dec9ca3c8698743efb88f081ac5 Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Wed, 15 Aug 2018 17:15:14 -0500
+Subject: [PATCH 0129/2940] drm/amdgpu: add freesync ioctl
+
+Add the ioctl to enable/disable freesync.
+
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 15 +++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 ++-
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++
+ include/uapi/drm/amdgpu_drm.h | 16 ++++++++++++++++
+ 5 files changed, 40 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 6265b88135fc..a1b9254e663b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -661,6 +661,9 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *fi
+ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
+
++int amdgpu_display_freesync_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *filp);
++
+ /* VRAM scratch page for HDP bug, default vram page */
+ struct amdgpu_vram_scratch {
+ struct amdgpu_bo *robj;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+index 642b47c5f4b8..7d6a36bca9dd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+@@ -894,3 +894,18 @@ int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
+ return AMDGPU_CRTC_IRQ_NONE;
+ }
+ }
++
++int amdgpu_display_freesync_ioctl(struct drm_device *dev, void *data,
++ struct drm_file *filp)
++{
++ int ret = -EPERM;
++ struct amdgpu_device *adev = dev->dev_private;
++
++ if (adev->mode_info.funcs->notify_freesync)
++ ret = adev->mode_info.funcs->notify_freesync(dev,data,filp);
++ else
++ DRM_DEBUG("amdgpu no notify_freesync ioctl\n");
++
++ return ret;
++}
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index a1043b421e3e..7d3d76a1a9dd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -1101,7 +1101,8 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
+ DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+- DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
++ DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
++ DRM_IOCTL_DEF_DRV(AMDGPU_FREESYNC, amdgpu_display_freesync_ioctl, DRM_MASTER)
+ };
+ const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index e98b265a1629..ca60821ca44b 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -1707,6 +1707,7 @@ static void dm_bandwidth_update(struct amdgpu_device *adev)
+ static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
+ struct drm_file *filp)
+ {
++ struct drm_amdgpu_freesync *args = data;
+ struct drm_atomic_state *state;
+ struct drm_modeset_acquire_ctx ctx;
+ struct drm_crtc *crtc;
+@@ -1716,6 +1717,9 @@ static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
+ uint8_t i;
+ bool enable = false;
+
++ if (args->op == AMDGPU_FREESYNC_FULLSCREEN_ENTER)
++ enable = true;
++
+ drm_modeset_acquire_init(&ctx, 0);
+
+ state = drm_atomic_state_alloc(dev);
+diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
+index 1ceec56de015..8dc9115ecc01 100644
+--- a/include/uapi/drm/amdgpu_drm.h
++++ b/include/uapi/drm/amdgpu_drm.h
+@@ -54,6 +54,8 @@ extern "C" {
+ #define DRM_AMDGPU_VM 0x13
+ #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
+ #define DRM_AMDGPU_SCHED 0x15
++/* not upstream */
++#define DRM_AMDGPU_FREESYNC 0x5d
+
+ #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
+ #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
+@@ -71,6 +73,7 @@ extern "C" {
+ #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
+ #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
+ #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
++#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync)
+
+ /**
+ * DOC: memory domains
+@@ -987,6 +990,19 @@ struct drm_amdgpu_info_vce_clock_table {
+ #define AMDGPU_FAMILY_AI 141 /* Vega10 */
+ #define AMDGPU_FAMILY_RV 142 /* Raven */
+
++/*
++ * Definition of free sync enter and exit signals
++ * We may have more options in the future
++ */
++#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1
++#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2
++
++struct drm_amdgpu_freesync {
++ __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */
++ /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */
++ __u32 spare[7];
++};
++
+ #if defined(__cplusplus)
+ }
+ #endif
+--
+2.17.1
+