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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0063-drm-amdgpu-include-add-thm-11.0.2-headers.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0063-drm-amdgpu-include-add-thm-11.0.2-headers.patch155
1 files changed, 155 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0063-drm-amdgpu-include-add-thm-11.0.2-headers.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0063-drm-amdgpu-include-add-thm-11.0.2-headers.patch
new file mode 100644
index 00000000..0879f333
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/0063-drm-amdgpu-include-add-thm-11.0.2-headers.patch
@@ -0,0 +1,155 @@
+From 4d2ec46145fc8ab5b99b80dba25c903eab489e37 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 26 Mar 2018 15:29:48 +0800
+Subject: [PATCH 0063/2940] drm/amdgpu/include: add thm 11.0.2 headers
+
+Headers for thermal controller.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../include/asic_reg/thm/thm_11_0_2_offset.h | 37 ++++++++
+ .../include/asic_reg/thm/thm_11_0_2_sh_mask.h | 86 +++++++++++++++++++
+ 2 files changed, 123 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
+new file mode 100644
+index 000000000000..510ec3c70626
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
+@@ -0,0 +1,37 @@
++/*
++ * Copyright (C) 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef _thm_11_0_2_OFFSET_HEADER
++#define _thm_11_0_2_OFFSET_HEADER
++
++
++#define mmCG_MULT_THERMAL_STATUS 0x005f
++#define mmCG_MULT_THERMAL_STATUS_BASE_IDX 0
++
++#define mmTHM_THERMAL_INT_ENA 0x000a
++#define mmTHM_THERMAL_INT_ENA_BASE_IDX 0
++#define mmTHM_THERMAL_INT_CTRL 0x000b
++#define mmTHM_THERMAL_INT_CTRL_BASE_IDX 0
++
++#define mmTHM_TCON_THERM_TRIP 0x0002
++#define mmTHM_TCON_THERM_TRIP_BASE_IDX 0
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h
+new file mode 100644
+index 000000000000..f69533fa6abf
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h
+@@ -0,0 +1,86 @@
++/*
++ * Copyright (C) 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef _thm_11_0_2_SH_MASK_HEADER
++#define _thm_11_0_2_SH_MASK_HEADER
++
++
++//CG_MULT_THERMAL_STATUS
++#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
++#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
++#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL
++#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L
++
++//THM_THERMAL_INT_ENA
++#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
++#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
++#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
++#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
++#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
++#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
++#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x00000001L
++#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x00000002L
++#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x00000004L
++#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x00000008L
++#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x00000010L
++#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x00000020L
++//THM_THERMAL_INT_CTRL
++#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
++#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
++#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT 0x10
++#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
++#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
++#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
++#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT 0x1b
++#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT 0x1c
++#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT 0x1d
++#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0x000000FFL
++#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0x0000FF00L
++#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK 0x00FF0000L
++#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x01000000L
++#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x02000000L
++#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x04000000L
++#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK 0x08000000L
++#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK 0x10000000L
++#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK 0xE0000000L
++
++//THM_TCON_THERM_TRIP
++#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0
++#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1
++#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2
++#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3
++#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4
++#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5
++#define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6
++#define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0xe
++#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f
++#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L
++#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L
++#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L
++#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L
++#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x00000010L
++#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L
++#define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L
++#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7FFFC000L
++#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L
++
++#endif
++
+--
+2.17.1
+