diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5561-drm-amdgpu-vcn-Apply-new-UMC-enable-for-VNC-DPG-mode.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/5561-drm-amdgpu-vcn-Apply-new-UMC-enable-for-VNC-DPG-mode.patch | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5561-drm-amdgpu-vcn-Apply-new-UMC-enable-for-VNC-DPG-mode.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5561-drm-amdgpu-vcn-Apply-new-UMC-enable-for-VNC-DPG-mode.patch new file mode 100644 index 00000000..50475516 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5561-drm-amdgpu-vcn-Apply-new-UMC-enable-for-VNC-DPG-mode.patch @@ -0,0 +1,41 @@ +From 9f2690300ba457c44fca9f38b6fa8a89cd1e2751 Mon Sep 17 00:00:00 2001 +From: James Zhu <James.Zhu@amd.com> +Date: Tue, 9 Oct 2018 13:05:15 -0400 +Subject: [PATCH 5561/5725] drm/amdgpu/vcn:Apply new UMC enable for VNC DPG + mode start + +Apply new UMC enable for VNC Dynamic Power Gate mode start + +Signed-off-by: James Zhu <James.Zhu@amd.com> +Acked-by: Leo Liu <leo.liu@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +index bc58658..0371b67 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -1023,13 +1023,14 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); + +- /* enable UMC */ +- WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, +- 0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); +- + /* boot up the VCPU */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); + ++ /* enable UMC */ ++ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, ++ 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, ++ 0xFFFFFFFF, 0); ++ + /* enable master interrupt */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, + UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); +-- +2.7.4 + |