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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5485-drm-amd-powerplay-Enable-Disable-NBPSTATE-on-On-OFF-.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/5485-drm-amd-powerplay-Enable-Disable-NBPSTATE-on-On-OFF-.patch44
1 files changed, 44 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5485-drm-amd-powerplay-Enable-Disable-NBPSTATE-on-On-OFF-.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5485-drm-amd-powerplay-Enable-Disable-NBPSTATE-on-On-OFF-.patch
new file mode 100644
index 00000000..7db568e0
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5485-drm-amd-powerplay-Enable-Disable-NBPSTATE-on-On-OFF-.patch
@@ -0,0 +1,44 @@
+From af55bdc563626770696074c47acf0b5bee61447d Mon Sep 17 00:00:00 2001
+From: Akshu Agrawal <akshu.agrawal@amd.com>
+Date: Mon, 24 Sep 2018 15:48:02 +0530
+Subject: [PATCH 5485/5725] drm/amd/powerplay: Enable/Disable NBPSTATE on
+ On/OFF of UVD
+
+We observe black lines (underflow) on display when playing a
+4K video with UVD. On Disabling Low memory P state this issue is
+not seen.
+Multiple runs of power measurement shows no imapct.
+
+Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
+Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+index 53cf787..fef111d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+@@ -1228,14 +1228,17 @@ static int smu8_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
+
+ static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
+ {
+- if (PP_CAP(PHM_PlatformCaps_UVDPowerGating))
++ if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
++ smu8_nbdpm_pstate_enable_disable(hwmgr, true, true);
+ return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF);
++ }
+ return 0;
+ }
+
+ static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
+ {
+ if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
++ smu8_nbdpm_pstate_enable_disable(hwmgr, false, true);
+ return smum_send_msg_to_smc_with_parameter(
+ hwmgr,
+ PPSMC_MSG_UVDPowerON,
+--
+2.7.4
+