diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5209-drm-amdgpu-implement-soft_recovery-for-GFX9.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/5209-drm-amdgpu-implement-soft_recovery-for-GFX9.patch | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5209-drm-amdgpu-implement-soft_recovery-for-GFX9.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5209-drm-amdgpu-implement-soft_recovery-for-GFX9.patch new file mode 100644 index 00000000..12c3da46 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5209-drm-amdgpu-implement-soft_recovery-for-GFX9.patch @@ -0,0 +1,51 @@ +From 4af0f806ce0f5025b29e01c679515553d3d9d99e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Wed, 22 Aug 2018 12:04:11 +0200 +Subject: [PATCH 5209/5725] drm/amdgpu: implement soft_recovery for GFX9 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Try to kill waves on the SQ. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Huang Rui <ray.huang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 29a7727..f588822 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -4434,6 +4434,18 @@ static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, + ref, mask); + } + ++static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) ++{ ++ struct amdgpu_device *adev = ring->adev; ++ uint32_t value = 0; ++ ++ value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); ++ value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); ++ value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); ++ value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); ++ WREG32(mmSQ_CMD, value); ++} ++ + static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, + enum amdgpu_interrupt_state state) + { +@@ -4757,6 +4769,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { + .emit_wreg = gfx_v9_0_ring_emit_wreg, + .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, + .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, ++ .soft_recovery = gfx_v9_0_ring_soft_recovery, + }; + + static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { +-- +2.7.4 + |