diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5208-drm-amdgpu-implement-soft_recovery-for-GFX8-v2.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/5208-drm-amdgpu-implement-soft_recovery-for-GFX8-v2.patch | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5208-drm-amdgpu-implement-soft_recovery-for-GFX8-v2.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5208-drm-amdgpu-implement-soft_recovery-for-GFX8-v2.patch new file mode 100644 index 00000000..56a84fba --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5208-drm-amdgpu-implement-soft_recovery-for-GFX8-v2.patch @@ -0,0 +1,53 @@ +From 66594074e644dd038e5d5b12ec4bfe6240fec9ed Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Tue, 21 Aug 2018 12:45:31 +0200 +Subject: [PATCH 5208/5725] drm/amdgpu: implement soft_recovery for GFX8 v2 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Try to kill waves on the SQ. + +v2: only for the GFX ring for now. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Huang Rui <ray.huang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 6f79369..19b65cf 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -6726,6 +6726,18 @@ static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, + amdgpu_ring_write(ring, val); + } + ++static void gfx_v8_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) ++{ ++ struct amdgpu_device *adev = ring->adev; ++ uint32_t value = 0; ++ ++ value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); ++ value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); ++ value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); ++ value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); ++ WREG32(mmSQ_CMD, value); ++} ++ + static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, + enum amdgpu_interrupt_state state) + { +@@ -7184,6 +7196,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { + .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec, + .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec, + .emit_wreg = gfx_v8_0_ring_emit_wreg, ++ .soft_recovery = gfx_v8_0_ring_soft_recovery, + }; + + static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { +-- +2.7.4 + |