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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5205-drm-amdgpu-add-amdgpu_gmc_pd_addr-helper.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/5205-drm-amdgpu-add-amdgpu_gmc_pd_addr-helper.patch196
1 files changed, 196 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5205-drm-amdgpu-add-amdgpu_gmc_pd_addr-helper.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5205-drm-amdgpu-add-amdgpu_gmc_pd_addr-helper.patch
new file mode 100644
index 00000000..065bb311
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5205-drm-amdgpu-add-amdgpu_gmc_pd_addr-helper.patch
@@ -0,0 +1,196 @@
+From 821731d132b32769926090b3385f1bc414c4fb7f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Wed, 22 Aug 2018 12:22:14 +0200
+Subject: [PATCH 5205/5725] drm/amdgpu: add amdgpu_gmc_pd_addr helper
+
+Add a helper to get the root PD address and remove the workarounds from
+the GMC9 code for that.
+
+Change-Id: I64bbd27d52938da78b38390b98febb473c08fba1
+Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
+Signed-off-by: Raveendra Talabattula <raveendra.talabattula@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 47 ++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 2 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 7 +---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 --
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 7 +---
+ 9 files changed, 55 insertions(+), 20 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index e0854bb..064dd5f7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -31,7 +31,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
+ amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
+ amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
+ amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
+- amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o amdgpu_sem.o amdgpu_amdkfd_fence.o \
++ amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o amdgpu_sem.o amdgpu_gmc.o amdgpu_amdkfd_fence.o \
+ amdgpu_debugfs.o amdgpu_ids.o
+
+ # add asic specific block
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index fb22f77..02d9ae7d2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -404,7 +404,7 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
+ return ret;
+ }
+
+- vm->pd_phys_addr = get_vm_pd_gpu_offset(vm);
++ vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
+
+ if (vm->use_cpu_for_update) {
+ ret = amdgpu_bo_kmap(pd, NULL);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index 24f2489..fd9fe69 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -962,7 +962,7 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
+ }
+
+ if (p->job->vm) {
+- p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
++ p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
+
+ r = amdgpu_bo_vm_update_pte(p);
+ if (r)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+new file mode 100644
+index 0000000..36058fe
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+@@ -0,0 +1,47 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ */
++
++#include "amdgpu.h"
++
++/**
++ * amdgpu_gmc_pd_addr - return the address of the root directory
++ *
++ */
++uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
++{
++ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
++ uint64_t pd_addr;
++
++ pd_addr = amdgpu_bo_gpu_offset(bo);
++ /* TODO: move that into ASIC specific code */
++ if (adev->asic_type >= CHIP_VEGA10) {
++ uint64_t flags = AMDGPU_PTE_VALID;
++
++ amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
++ pd_addr |= flags;
++ }
++ return pd_addr;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index 5dbbac6..f347ba9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -134,4 +134,6 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
+ return (gmc->real_vram_size == gmc->visible_vram_size);
+ }
+
++uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index c263f18..f1d9fe3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2248,7 +2248,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
+ return r;
+
+ if (vm_needs_flush) {
+- job->vm_pd_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
++ job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
+ job->vm_needs_flush = true;
+ }
+ if (resv) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+index 2baab7e..3403ded 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+@@ -37,12 +37,7 @@ u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
+
+ static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
+ {
+- uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
+-
+- BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
+- value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
+- value &= 0x0000FFFFFFFFF000ULL;
+- value |= 0x1; /*valid bit*/
++ uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
+
+ WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+ lower_32_bits(value));
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 730a589..a2625e2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -428,12 +428,8 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
+- uint64_t flags = AMDGPU_PTE_VALID;
+ unsigned eng = ring->vm_inv_eng;
+
+- amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
+- pd_addr |= flags;
+-
+ amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
+ lower_32_bits(pd_addr));
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index 800ec46..5f6a9c8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -47,12 +47,7 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
+
+ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
+ {
+- uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
+-
+- BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
+- value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
+- value &= 0x0000FFFFFFFFF000ULL;
+- value |= 0x1; /* valid bit */
++ uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
+
+ WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+ lower_32_bits(value));
+--
+2.7.4
+