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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5199-drm-amdgpu-remove-gart.table_addr.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/5199-drm-amdgpu-remove-gart.table_addr.patch255
1 files changed, 255 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5199-drm-amdgpu-remove-gart.table_addr.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5199-drm-amdgpu-remove-gart.table_addr.patch
new file mode 100644
index 00000000..11282bae
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5199-drm-amdgpu-remove-gart.table_addr.patch
@@ -0,0 +1,255 @@
+From 46940ee89ee802079dfe4ffb9998694e70f47d00 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Tue, 21 Aug 2018 17:18:22 +0200
+Subject: [PATCH 5199/5725] drm/amdgpu: remove gart.table_addr
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We can easily figure out the address on the fly.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Raveendra Talabattula <raveendra.talabattula@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 1 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 1 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 7 +++----
+ drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 9 +++++----
+ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 9 +++++----
+ drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 9 +++++----
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 7 +++----
+ 9 files changed, 24 insertions(+), 25 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+index b2e0083..5586874 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+@@ -157,7 +157,6 @@ int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
+ if (r)
+ amdgpu_bo_unpin(adev->gart.bo);
+ amdgpu_bo_unreserve(adev->gart.bo);
+- adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+ return r;
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
+index 35af864..5ee8f20 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
+@@ -38,7 +38,6 @@ struct amdgpu_bo;
+ #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
+
+ struct amdgpu_gart {
+- u64 table_addr;
+ struct amdgpu_bo *bo;
+ void *ptr;
+ unsigned num_gpu_pages;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index f9233be..c263f18 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2187,7 +2187,7 @@ static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
+ src_addr = num_dw * 4;
+ src_addr += job->ibs[0].gpu_addr;
+
+- dst_addr = adev->gart.table_addr;
++ dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+ dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
+ amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
+ dst_addr, num_bytes);
+@@ -2248,7 +2248,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
+ return r;
+
+ if (vm_needs_flush) {
+- job->vm_pd_addr = adev->gart.table_addr;
++ job->vm_pd_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+ job->vm_needs_flush = true;
+ }
+ if (resv) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+index acfbd2d..2baab7e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+@@ -37,11 +37,10 @@ u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
+
+ static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
+ {
+- uint64_t value;
++ uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
+
+- BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
+- value = adev->gart.table_addr - adev->gmc.vram_start
+- + adev->vm_manager.vram_base_offset;
++ BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
++ value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
+ value &= 0x0000FFFFFFFFF000ULL;
+ value |= 0x1; /*valid bit*/
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+index a0f3be9..ff045df 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+@@ -493,6 +493,7 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
+
+ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
+ {
++ uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+ int r, i;
+ u32 field;
+
+@@ -531,7 +532,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
+ /* setup context0 */
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
+- WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
++ WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
+ WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
+ (u32)(adev->dummy_page_addr >> 12));
+ WREG32(mmVM_CONTEXT0_CNTL2, 0);
+@@ -555,10 +556,10 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
+ for (i = 1; i < 16; i++) {
+ if (i < 8)
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
+- adev->gart.table_addr >> 12);
++ table_addr >> 12);
+ else
+ WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
+- adev->gart.table_addr >> 12);
++ table_addr >> 12);
+ }
+
+ /* enable context1-15 */
+@@ -578,7 +579,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
+ gmc_v6_0_flush_gpu_tlb(adev, 0);
+ dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
+ (unsigned)(adev->gmc.gart_size >> 20),
+- (unsigned long long)adev->gart.table_addr);
++ (unsigned long long)table_addr);
+ adev->gart.ready = true;
+ return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+index eadc5c2..9276792 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+@@ -604,6 +604,7 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
+ */
+ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
+ {
++ uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+ int r, i;
+ u32 tmp, field;
+
+@@ -645,7 +646,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
+ /* setup context0 */
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
+- WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
++ WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
+ WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
+ (u32)(adev->dummy_page_addr >> 12));
+ WREG32(mmVM_CONTEXT0_CNTL2, 0);
+@@ -669,10 +670,10 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
+ for (i = 1; i < 16; i++) {
+ if (i < 8)
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
+- adev->gart.table_addr >> 12);
++ table_addr >> 12);
+ else
+ WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
+- adev->gart.table_addr >> 12);
++ table_addr >> 12);
+ }
+
+ /* enable context1-15 */
+@@ -699,7 +700,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
+ gmc_v7_0_flush_gpu_tlb(adev, 0);
+ DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+ (unsigned)(adev->gmc.gart_size >> 20),
+- (unsigned long long)adev->gart.table_addr);
++ (unsigned long long)table_addr);
+ adev->gart.ready = true;
+ return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+index 18b86db..5073b76 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+@@ -810,6 +810,7 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
+ */
+ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
+ {
++ uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+ int r, i;
+ u32 tmp, field;
+
+@@ -867,7 +868,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
+ /* setup context0 */
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
+- WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
++ WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
+ WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
+ (u32)(adev->dummy_page_addr >> 12));
+ WREG32(mmVM_CONTEXT0_CNTL2, 0);
+@@ -891,10 +892,10 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
+ for (i = 1; i < 16; i++) {
+ if (i < 8)
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
+- adev->gart.table_addr >> 12);
++ table_addr >> 12);
+ else
+ WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
+- adev->gart.table_addr >> 12);
++ table_addr >> 12);
+ }
+
+ /* enable context1-15 */
+@@ -922,7 +923,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
+ gmc_v8_0_flush_gpu_tlb(adev, 0);
+ DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+ (unsigned)(adev->gmc.gart_size >> 20),
+- (unsigned long long)adev->gart.table_addr);
++ (unsigned long long)table_addr);
+ adev->gart.ready = true;
+ return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 0c83829..730a589 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -1117,7 +1117,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+
+ DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+ (unsigned)(adev->gmc.gart_size >> 20),
+- (unsigned long long)adev->gart.table_addr);
++ (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
+ adev->gart.ready = true;
+ return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index e70a0d4..800ec46 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -47,11 +47,10 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
+
+ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
+ {
+- uint64_t value;
++ uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
+
+- BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
+- value = adev->gart.table_addr - adev->gmc.vram_start +
+- adev->vm_manager.vram_base_offset;
++ BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
++ value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
+ value &= 0x0000FFFFFFFFF000ULL;
+ value |= 0x1; /* valid bit */
+
+--
+2.7.4
+