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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5091-drm-amdgpu-move-vm-definitions-into-amdgpu_vm-header.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/5091-drm-amdgpu-move-vm-definitions-into-amdgpu_vm-header.patch108
1 files changed, 108 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5091-drm-amdgpu-move-vm-definitions-into-amdgpu_vm-header.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5091-drm-amdgpu-move-vm-definitions-into-amdgpu_vm-header.patch
new file mode 100644
index 00000000..fb24597b
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5091-drm-amdgpu-move-vm-definitions-into-amdgpu_vm-header.patch
@@ -0,0 +1,108 @@
+From e551c7aab2da28721baa304ad1557713b059a729 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Fri, 3 Aug 2018 19:06:02 +0800
+Subject: [PATCH 5091/5725] drm/amdgpu: move vm definitions into amdgpu_vm
+ header
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Demangle amdgpu.h.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Raveendra Talabattula <raveendra.talabattula@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 24 ------------------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 25 +++++++++++++++++++++++++
+ 2 files changed, 25 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 59b0980..27042b2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -263,27 +263,6 @@ amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
+ int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
+ const struct amdgpu_ip_block_version *ip_block_version);
+
+-/* provided by hw blocks that can write ptes, e.g., sdma */
+-struct amdgpu_vm_pte_funcs {
+- /* number of dw to reserve per operation */
+- unsigned copy_pte_num_dw;
+-
+- /* copy pte entries from GART */
+- void (*copy_pte)(struct amdgpu_ib *ib,
+- uint64_t pe, uint64_t src,
+- unsigned count);
+-
+- /* write pte one entry at a time with addr mapping */
+- void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
+- uint64_t value, unsigned count,
+- uint32_t incr);
+- /* for linear pte/pde updates without addr mapping */
+- void (*set_pte_pde)(struct amdgpu_ib *ib,
+- uint64_t pe,
+- uint64_t addr, unsigned count,
+- uint32_t incr, uint64_t flags);
+-};
+-
+ /*
+ * BIOS.
+ */
+@@ -1301,9 +1280,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
+ #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
+ #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
+ #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
+-#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
+-#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
+-#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
+
+ /* Common functions */
+ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index a5cf0cc..b96bfed 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -163,6 +163,27 @@ struct amdgpu_vm_pt {
+ struct amdgpu_vm_pt *entries;
+ };
+
++/* provided by hw blocks that can write ptes, e.g., sdma */
++struct amdgpu_vm_pte_funcs {
++ /* number of dw to reserve per operation */
++ unsigned copy_pte_num_dw;
++
++ /* copy pte entries from GART */
++ void (*copy_pte)(struct amdgpu_ib *ib,
++ uint64_t pe, uint64_t src,
++ unsigned count);
++
++ /* write pte one entry at a time with addr mapping */
++ void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
++ uint64_t value, unsigned count,
++ uint32_t incr);
++ /* for linear pte/pde updates without addr mapping */
++ void (*set_pte_pde)(struct amdgpu_ib *ib,
++ uint64_t pe,
++ uint64_t addr, unsigned count,
++ uint32_t incr, uint64_t flags);
++};
++
+ #define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr))
+ #define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
+ #define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL)
+@@ -272,6 +293,10 @@ struct amdgpu_vm_manager {
+ unsigned n_compute_vms;
+ };
+
++#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
++#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
++#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
++
+ void amdgpu_vm_manager_init(struct amdgpu_device *adev);
+ void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
+ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+--
+2.7.4
+