diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5046-drm-amd-display-Use-calculated-disp_clk_khz-value-fo.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/5046-drm-amd-display-Use-calculated-disp_clk_khz-value-fo.patch | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5046-drm-amd-display-Use-calculated-disp_clk_khz-value-fo.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5046-drm-amd-display-Use-calculated-disp_clk_khz-value-fo.patch new file mode 100644 index 00000000..75da6292 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5046-drm-amd-display-Use-calculated-disp_clk_khz-value-fo.patch @@ -0,0 +1,83 @@ +From 4fc39b72e286bea741d0cc881eb97e53267b8fe8 Mon Sep 17 00:00:00 2001 +From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Date: Mon, 23 Jul 2018 14:13:23 -0400 +Subject: [PATCH 5046/5725] drm/amd/display: Use calculated disp_clk_khz value + for dce110 + +[Why] + +The calculated values for actual disp_clk_khz were ignored when +notifying pplib of the new display requirements. In order to honor DFS +bypass clocks from the hardware, the calculated value should be used. + +[How] + +The return value for set_dispclk is now assigned back into new_clocks +and correctly carried through into dccg->clks.phyclk_khz. When notifying +pplib of new display requirements dccg->clks.phyclk_khz is used +instead of dce.dispclk_khz. The value of dce.dispclk_khz was never +explicitly set to anything before. + +A 15% higher display clock value than calculated is no longer requested +for dce110 since it now makes use of the calculated value. + +Since dce112 makes use of dce110's set_bandwidth but not its +update_clocks it needs to have the value correctly carried through. + +Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 4 ++-- + drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +index 0db8d1d..f176779 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +@@ -463,7 +463,7 @@ static void dce12_update_clocks(struct dccg *dccg, + if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) { + clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; + clock_voltage_req.clocks_in_khz = new_clocks->dispclk_khz; +- dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz); ++ new_clocks->dispclk_khz = dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz); + dccg->clks.dispclk_khz = new_clocks->dispclk_khz; + + dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req); +@@ -661,7 +661,7 @@ static void dce_update_clocks(struct dccg *dccg, + } + + if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) { +- dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz); ++ new_clocks->dispclk_khz = dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz); + dccg->clks.dispclk_khz = new_clocks->dispclk_khz; + } + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 4fff944..afd1743 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -2511,7 +2511,7 @@ static void pplib_apply_display_requirements( + /* TODO: dce11.2*/ + pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; + +- pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz; ++ pp_display_cfg->disp_clk_khz = dc->res_pool->dccg->clks.dispclk_khz; + + dce110_fill_display_configs(context, pp_display_cfg); + +@@ -2540,7 +2540,7 @@ void dce110_set_bandwidth( + { + struct dc_clocks req_clks; + +- req_clks.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100; ++ req_clks.dispclk_khz = context->bw.dce.dispclk_khz; + req_clks.phyclk_khz = get_max_pixel_clock_for_all_paths(dc, context); + + if (decrease_allowed) +-- +2.7.4 + |