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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4889-drm-amdgpu-Make-pin_size-values-atomic.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/4889-drm-amdgpu-Make-pin_size-values-atomic.patch181
1 files changed, 181 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4889-drm-amdgpu-Make-pin_size-values-atomic.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4889-drm-amdgpu-Make-pin_size-values-atomic.patch
new file mode 100644
index 00000000..2dca34f6
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4889-drm-amdgpu-Make-pin_size-values-atomic.patch
@@ -0,0 +1,181 @@
+From 7647b85138330b2e7250f92cd97da55803bd84b5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@amd.com>
+Date: Wed, 11 Jul 2018 12:00:40 +0200
+Subject: [PATCH 4889/5725] drm/amdgpu: Make pin_size values atomic
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Concurrent execution of the non-atomic arithmetic could result in
+completely bogus values.
+
+v2:
+* Rebased on v2 of the previous patch
+
+Cc: stable@vger.kernel.org
+Bugzilla: https://bugs.freedesktop.org/106872
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Raveendra Talabattula <raveendra.talabattula@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 22 +++++++++++-----------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 14 ++++++++------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 +++---
+ 5 files changed, 26 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index e056008..2fa7976 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1651,9 +1651,9 @@ struct amdgpu_device {
+ DECLARE_HASHTABLE(mn_hash, 7);
+
+ /* tracking pinned memory */
+- u64 vram_pin_size;
+- u64 visible_pin_size;
+- u64 gart_pin_size;
++ atomic64_t vram_pin_size;
++ atomic64_t visible_pin_size;
++ atomic64_t gart_pin_size;
+
+ /* amdkfd interface */
+ struct kfd_dev *kfd;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index 62182e9..a4aaf37 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -262,7 +262,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
+ return;
+ }
+
+- total_vram = adev->gmc.real_vram_size - adev->vram_pin_size;
++ total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
+ used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
+ free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 02a5ef7..4cd3317 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -515,13 +515,13 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
+ case AMDGPU_INFO_VRAM_GTT: {
+ struct drm_amdgpu_info_vram_gtt vram_gtt;
+
+- vram_gtt.vram_size = adev->gmc.real_vram_size;
+- vram_gtt.vram_size -= adev->vram_pin_size;
+- vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size;
+- vram_gtt.vram_cpu_accessible_size -= adev->visible_pin_size;
++ vram_gtt.vram_size = adev->gmc.real_vram_size -
++ atomic64_read(&adev->vram_pin_size);
++ vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
++ atomic64_read(&adev->visible_pin_size);
+ vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
+ vram_gtt.gtt_size *= PAGE_SIZE;
+- vram_gtt.gtt_size -= adev->gart_pin_size;
++ vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
+ return copy_to_user(out, &vram_gtt,
+ min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
+ }
+@@ -530,16 +530,16 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
+
+ memset(&mem, 0, sizeof(mem));
+ mem.vram.total_heap_size = adev->gmc.real_vram_size;
+- mem.vram.usable_heap_size =
+- adev->gmc.real_vram_size - adev->vram_pin_size;
++ mem.vram.usable_heap_size = adev->gmc.real_vram_size -
++ atomic64_read(&adev->vram_pin_size);
+ mem.vram.heap_usage =
+ amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
+ mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
+
+ mem.cpu_accessible_vram.total_heap_size =
+ adev->gmc.visible_vram_size;
+- mem.cpu_accessible_vram.usable_heap_size =
+- adev->gmc.visible_vram_size - adev->visible_pin_size;
++ mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
++ atomic64_read(&adev->visible_pin_size);
+ mem.cpu_accessible_vram.heap_usage =
+ amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
+ mem.cpu_accessible_vram.max_allocation =
+@@ -547,8 +547,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
+
+ mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
+ mem.gtt.total_heap_size *= PAGE_SIZE;
+- mem.gtt.usable_heap_size = mem.gtt.total_heap_size
+- - adev->gart_pin_size;
++ mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
++ atomic64_read(&adev->gart_pin_size);
+ mem.gtt.heap_usage =
+ amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
+ mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+index 51f08a8..b483732 100755
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+@@ -956,10 +956,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
+
+ domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
+ if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
+- adev->vram_pin_size += amdgpu_bo_size(bo);
+- adev->visible_pin_size += amdgpu_vram_mgr_bo_visible_size(bo);
++ atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size);
++ atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo),
++ &adev->visible_pin_size);
+ } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
+- adev->gart_pin_size += amdgpu_bo_size(bo);
++ atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size);
+ }
+
+ error:
+@@ -1008,10 +1009,11 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
+ return 0;
+
+ if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
+- adev->vram_pin_size -= amdgpu_bo_size(bo);
+- adev->visible_pin_size -= amdgpu_vram_mgr_bo_visible_size(bo);
++ atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
++ atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
++ &adev->visible_pin_size);
+ } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
+- adev->gart_pin_size -= amdgpu_bo_size(bo);
++ atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
+ }
+
+ for (i = 0; i < bo->placement.num_placement; i++) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 529ddda..cf7f380 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -1666,7 +1666,7 @@ static int amdgpu_direct_gma_init(struct amdgpu_device *adev)
+ adev->direct_gma.dgma_bo = abo;
+
+ /* reserve in gtt */
+- adev->gart_pin_size += size;
++ atomic64_add(size,&adev->gart_pin_size);
+ r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_DGMA, size >> PAGE_SHIFT);
+ if (unlikely(r))
+ goto error_put_node;
+@@ -1682,7 +1682,7 @@ static int amdgpu_direct_gma_init(struct amdgpu_device *adev)
+ ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_DGMA);
+
+ error_put_node:
+- adev->gart_pin_size -= size;
++ atomic64_sub(size,&adev->gart_pin_size);
+
+ error_free:
+ amdgpu_bo_unref(&abo);
+@@ -1710,7 +1710,7 @@ static void amdgpu_direct_gma_fini(struct amdgpu_device *adev)
+ amdgpu_bo_unreserve(adev->direct_gma.dgma_bo);
+ }
+ amdgpu_bo_unref(&adev->direct_gma.dgma_bo);
+- adev->gart_pin_size -= (u64)amdgpu_direct_gma_size << 20;
++ atomic64_sub((u64)amdgpu_direct_gma_size << 20,&adev->gart_pin_size);
+ }
+
+ #ifdef CONFIG_ENABLE_SSG
+--
+2.7.4
+