diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4880-drm-amd-powerplay-add-vega12-SMU-gfxoff-support-v3.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4880-drm-amd-powerplay-add-vega12-SMU-gfxoff-support-v3.patch | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4880-drm-amd-powerplay-add-vega12-SMU-gfxoff-support-v3.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4880-drm-amd-powerplay-add-vega12-SMU-gfxoff-support-v3.patch new file mode 100644 index 00000000..b3a4a8ce --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4880-drm-amd-powerplay-add-vega12-SMU-gfxoff-support-v3.patch @@ -0,0 +1,115 @@ +From 9927e33a9ef6b25d569594d06204d0baffa5394c Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Wed, 4 Jul 2018 16:44:07 +0800 +Subject: [PATCH 4880/5725] drm/amd/powerplay: add vega12 SMU gfxoff support v3 + +Export apis for enabling/disabling SMU gfxoff support. + +v2: fit the latest gfxoff support framework +v3: add feature_mask control + +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Huang Rui <ray.huang at amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++ + drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 38 ++++++++++++++++++++++ + drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h | 3 ++ + 3 files changed, 46 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 5a719b0..e221eb0 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -3789,6 +3789,11 @@ static int gfx_v9_0_set_powergating_state(void *handle, + if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu) + amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true); + break; ++ case CHIP_VEGA12: ++ /* set gfx off through smu */ ++ if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu) ++ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true); ++ break; + default: + break; + } +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c +index ed17c56..cae76fe 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c +@@ -423,6 +423,11 @@ static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr) + hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit * + hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; + ++ if (hwmgr->feature_mask & PP_GFXOFF_MASK) ++ data->gfxoff_controlled_by_driver = true; ++ else ++ data->gfxoff_controlled_by_driver = false; ++ + return result; + } + +@@ -2328,6 +2333,38 @@ static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, + return 0; + } + ++static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr) ++{ ++ struct vega12_hwmgr *data = ++ (struct vega12_hwmgr *)(hwmgr->backend); ++ int ret = 0; ++ ++ if (data->gfxoff_controlled_by_driver) ++ ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff); ++ ++ return ret; ++} ++ ++static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr) ++{ ++ struct vega12_hwmgr *data = ++ (struct vega12_hwmgr *)(hwmgr->backend); ++ int ret = 0; ++ ++ if (data->gfxoff_controlled_by_driver) ++ ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff); ++ ++ return ret; ++} ++ ++static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable) ++{ ++ if (enable) ++ return vega12_enable_gfx_off(hwmgr); ++ else ++ return vega12_disable_gfx_off(hwmgr); ++} ++ + static const struct pp_hwmgr_func vega12_hwmgr_funcs = { + .backend_init = vega12_hwmgr_backend_init, + .backend_fini = vega12_hwmgr_backend_fini, +@@ -2377,6 +2414,7 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = { + .get_thermal_temperature_range = vega12_get_thermal_temperature_range, + .register_irq_handlers = smu9_register_irq_handlers, + .start_thermal_controller = vega12_start_thermal_controller, ++ .powergate_gfx = vega12_gfx_off_control, + }; + + int vega12_hwmgr_init(struct pp_hwmgr *hwmgr) +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h +index e17237c..b3e424d 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h +@@ -393,6 +393,9 @@ struct vega12_hwmgr { + struct vega12_smc_state_table smc_state_table; + + struct vega12_clock_range clk_range[PPCLK_COUNT]; ++ ++ /* ---- Gfxoff ---- */ ++ bool gfxoff_controlled_by_driver; + }; + + #define VEGA12_DPM2_NEAR_TDP_DEC 10 +-- +2.7.4 + |