diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4879-drm-amdgpu-reduce-the-idle-period-that-RLC-has-to-wa.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4879-drm-amdgpu-reduce-the-idle-period-that-RLC-has-to-wa.patch | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4879-drm-amdgpu-reduce-the-idle-period-that-RLC-has-to-wa.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4879-drm-amdgpu-reduce-the-idle-period-that-RLC-has-to-wa.patch new file mode 100644 index 00000000..e879dfca --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4879-drm-amdgpu-reduce-the-idle-period-that-RLC-has-to-wa.patch @@ -0,0 +1,50 @@ +From 8e18525e1db111f0e6659ad16244d9cc84fd09fa Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Thu, 5 Jul 2018 10:30:36 +0800 +Subject: [PATCH 4879/5725] drm/amdgpu: reduce the idle period that RLC has to + wait before request CGCG + +Gfxoff feature may depends on the CGCG(on vega12, that's the case). This +change will help to enable gfxoff feature more frequently. + +Signed-off-by: Evan Quan <evan.quan@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++++++---- + 1 file changed, 7 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 38f0a5d..5a719b0 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -3648,9 +3648,11 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, + /* update CGCG and CGLS override bits */ + if (def != data) + WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); +- /* enable 3Dcgcg FSM(0x0020003f) */ ++ ++ /* enable 3Dcgcg FSM(0x0000363f) */ + def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); +- data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | ++ ++ data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | + RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) + data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | +@@ -3697,9 +3699,10 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev + if (def != data) + WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); + +- /* enable cgcg FSM(0x0020003F) */ ++ /* enable cgcg FSM(0x0000363F) */ + def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); +- data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | ++ ++ data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | + RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) + data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | +-- +2.7.4 + |