diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4878-drm-amdgpu-no-touch-for-the-reserved-bit-of-RLC_CGTT.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4878-drm-amdgpu-no-touch-for-the-reserved-bit-of-RLC_CGTT.patch | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4878-drm-amdgpu-no-touch-for-the-reserved-bit-of-RLC_CGTT.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4878-drm-amdgpu-no-touch-for-the-reserved-bit-of-RLC_CGTT.patch new file mode 100644 index 00000000..62596a43 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4878-drm-amdgpu-no-touch-for-the-reserved-bit-of-RLC_CGTT.patch @@ -0,0 +1,54 @@ +From 152168a0dde590504efa2d0b826aeb5ec9b1db11 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Thu, 5 Jul 2018 10:26:48 +0800 +Subject: [PATCH 4878/5725] drm/amdgpu: no touch for the reserved bit of + RLC_CGTT_MGCG_OVERRIDE + +On vega12, the bit0 of RLC_CGTT_MGCG_OVERRIDE is reserved. + +Signed-off-by: Evan Quan <evan.quan@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +++++++++++---- + 1 file changed, 11 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 99d6005..38f0a5d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -3570,8 +3570,11 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { + /* 1 - RLC_CGTT_MGCG_OVERRIDE */ + def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); +- data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK | +- RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | ++ ++ if (adev->asic_type != CHIP_VEGA12) ++ data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; ++ ++ data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); + +@@ -3601,11 +3604,15 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev + } else { + /* 1 - MGCG_OVERRIDE */ + def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); +- data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK | +- RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | ++ ++ if (adev->asic_type != CHIP_VEGA12) ++ data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; ++ ++ data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); ++ + if (def != data) + WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); + +-- +2.7.4 + |