diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4849-drm-amdgpu-update-amd_pcie.h-to-include-gen4-speeds.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4849-drm-amdgpu-update-amd_pcie.h-to-include-gen4-speeds.patch | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4849-drm-amdgpu-update-amd_pcie.h-to-include-gen4-speeds.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4849-drm-amdgpu-update-amd_pcie.h-to-include-gen4-speeds.patch new file mode 100644 index 00000000..a47ae1bd --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4849-drm-amdgpu-update-amd_pcie.h-to-include-gen4-speeds.patch @@ -0,0 +1,41 @@ +From f08801a19f5fc3a87805ea33fc066be4c514f394 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Mon, 25 Jun 2018 13:03:51 -0500 +Subject: [PATCH 4849/5725] drm/amdgpu: update amd_pcie.h to include gen4 + speeds +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Internal header used by the driver to specify pcie gen +speeds of the asic and chipset. + +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/include/amd_pcie.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/amd_pcie.h b/drivers/gpu/drm/amd/include/amd_pcie.h +index 5eb895f..9cb9ceb 100644 +--- a/drivers/gpu/drm/amd/include/amd_pcie.h ++++ b/drivers/gpu/drm/amd/include/amd_pcie.h +@@ -27,6 +27,7 @@ + #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000 + #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000 + #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000 ++#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000 + #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000 + #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16 + +@@ -34,6 +35,7 @@ + #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001 + #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002 + #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004 ++#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008 + #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF + #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0 + +-- +2.7.4 + |