aboutsummaryrefslogtreecommitdiffstats
path: root/common/recipes-kernel/linux/linux-yocto-4.14.71/4840-drm-amd-pp-Convert-clock-unit-to-KHz-as-defined.patch
diff options
context:
space:
mode:
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4840-drm-amd-pp-Convert-clock-unit-to-KHz-as-defined.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/4840-drm-amd-pp-Convert-clock-unit-to-KHz-as-defined.patch165
1 files changed, 165 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4840-drm-amd-pp-Convert-clock-unit-to-KHz-as-defined.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4840-drm-amd-pp-Convert-clock-unit-to-KHz-as-defined.patch
new file mode 100644
index 00000000..f49acda3
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4840-drm-amd-pp-Convert-clock-unit-to-KHz-as-defined.patch
@@ -0,0 +1,165 @@
+From df6b61e83b70a0341e355c7002496e4c4781e1af Mon Sep 17 00:00:00 2001
+From: Rex Zhu <Rex.Zhu@amd.com>
+Date: Mon, 18 Jun 2018 18:15:15 +0800
+Subject: [PATCH 4840/5725] drm/amd/pp: Convert clock unit to KHz as defined
+
+Convert clock unit 10KHz to KHz as the data sturct defined.
+e.g.
+struct pp_clock_with_latency {
+ uint32_t clocks_in_khz;
+ uint32_t latency_in_us;
+};
+Meanwhile revert the same conversion in display side.
+
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Raveendra Talabattula <raveendra.talabattula@amd.com>
+---
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 18 ++++++---------
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 27 ++++++++++------------
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 12 ++++------
+ 3 files changed, 24 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index cf92d7a..596d49d 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -203,8 +203,7 @@ static void pp_to_dc_clock_levels(
+
+ for (i = 0; i < dc_clks->num_levels; i++) {
+ DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
+- /* translate 10kHz to kHz */
+- dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10;
++ dc_clks->clocks_in_khz[i] = pp_clks->clock[i];
+ }
+ }
+
+@@ -229,9 +228,8 @@ static void pp_to_dc_clock_levels_with_latency(
+ DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
+
+ for (i = 0; i < clk_level_info->num_levels; i++) {
+- DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz);
+- /* translate 10kHz to kHz */
+- clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10;
++ DRM_DEBUG("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
++ clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
+ clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
+ }
+ }
+@@ -257,9 +255,8 @@ static void pp_to_dc_clock_levels_with_voltage(
+ DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
+
+ for (i = 0; i < clk_level_info->num_levels; i++) {
+- DRM_INFO("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz);
+- /* translate 10kHz to kHz */
+- clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10;
++ DRM_INFO("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
++ clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
+ clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
+ }
+ }
+@@ -434,9 +431,8 @@ bool dm_pp_get_static_clocks(
+ return false;
+
+ static_clk_info->max_clocks_state = pp_clk_info.max_clocks_state;
+- /* translate 10kHz to kHz */
+- static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock * 10;
+- static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock * 10;
++ static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock;
++ static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock;
+
+ return true;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index da29871..71a6e62 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -4082,7 +4082,7 @@ static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
+ struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
+ table_info->vdd_dep_on_sclk;
+ uint32_t i;
+-
++ clocks->num_levels = 0;
+ for (i = 0; i < dep_table->count; i++) {
+ if (dep_table->entries[i].clk) {
+ clocks->data[clocks->num_levels].clocks_in_khz =
+@@ -4113,26 +4113,23 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
+ struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
+ table_info->vdd_dep_on_mclk;
+ struct vega10_hwmgr *data = hwmgr->backend;
++ uint32_t j = 0;
+ uint32_t i;
+
+- clocks->num_levels = 0;
+- data->mclk_latency_table.count = 0;
+-
+ for (i = 0; i < dep_table->count; i++) {
+ if (dep_table->entries[i].clk) {
+- clocks->data[clocks->num_levels].clocks_in_khz =
+- data->mclk_latency_table.entries
+- [data->mclk_latency_table.count].frequency =
+- dep_table->entries[i].clk * 10;
+- clocks->data[clocks->num_levels].latency_in_us =
+- data->mclk_latency_table.entries
+- [data->mclk_latency_table.count].latency =
+- vega10_get_mem_latency(hwmgr,
+- dep_table->entries[i].clk);
+- clocks->num_levels++;
+- data->mclk_latency_table.count++;
++ clocks->data[j].clocks_in_khz =
++ dep_table->entries[i].clk * 10;
++ data->mclk_latency_table.entries[j].frequency =
++ dep_table->entries[i].clk;
++ clocks->data[j].latency_in_us =
++ data->mclk_latency_table.entries[j].latency =
++ vega10_get_mem_latency(hwmgr,
++ dep_table->entries[i].clk);
++ j++;
+ }
+ }
++ clocks->num_levels = data->mclk_latency_table.count = j;
+ }
+
+ static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+index 9e9a3db..4cf2570 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+@@ -1676,10 +1676,8 @@ static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
+ MAX_NUM_CLOCKS : dpm_table->count;
+
+ for (i = 0; i < ucount; i++) {
+- clocks->data[i].clocks_in_khz =
+- data->mclk_latency_table.entries[i].frequency =
+- dpm_table->dpm_levels[i].value * 1000;
+-
++ clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000;
++ data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100;
+ clocks->data[i].latency_in_us =
+ data->mclk_latency_table.entries[i].latency =
+ vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
+@@ -1919,7 +1917,7 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
+ for (i = 0; i < clocks.num_levels; i++)
+ size += sprintf(buf + size, "%d: %uMhz %s\n",
+ i, clocks.data[i].clocks_in_khz / 1000,
+- (clocks.data[i].clocks_in_khz == now) ? "*" : "");
++ (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
+ break;
+
+ case PP_MCLK:
+@@ -1934,8 +1932,8 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
+ return -1);
+ for (i = 0; i < clocks.num_levels; i++)
+ size += sprintf(buf + size, "%d: %uMhz %s\n",
+- i, clocks.data[i].clocks_in_khz / 100,
+- (clocks.data[i].clocks_in_khz == now) ? "*" : "");
++ i, clocks.data[i].clocks_in_khz / 1000,
++ (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
+ break;
+
+ case PP_PCIE:
+--
+2.7.4
+