diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4835-drm-amdgpu-vce-simplify-vce-instance-setup.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4835-drm-amdgpu-vce-simplify-vce-instance-setup.patch | 179 |
1 files changed, 179 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4835-drm-amdgpu-vce-simplify-vce-instance-setup.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4835-drm-amdgpu-vce-simplify-vce-instance-setup.patch new file mode 100644 index 00000000..48f18591 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4835-drm-amdgpu-vce-simplify-vce-instance-setup.patch @@ -0,0 +1,179 @@ +From a1c62379895d6c73c6265426fbaad3cd4ed6d569 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Mon, 25 Jun 2018 12:41:21 -0500 +Subject: [PATCH 4835/5725] drm/amdgpu/vce: simplify vce instance setup +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Set the me instance in early init and use that rather than +calculating the instance based on the ring pointer. + +Reviewed-by: James Zhu <James.Zhu@amd.com> +Reviewed-by: Leo Liu <leo.liu@amd.com> +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 10 ++++++---- + drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 20 ++++++++++++-------- + drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 16 +++++++++------- + 3 files changed, 27 insertions(+), 19 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +index 47f7082..d48e877 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +@@ -56,7 +56,7 @@ static uint64_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring) + { + struct amdgpu_device *adev = ring->adev; + +- if (ring == &adev->vce.ring[0]) ++ if (ring->me == 0) + return RREG32(mmVCE_RB_RPTR); + else + return RREG32(mmVCE_RB_RPTR2); +@@ -73,7 +73,7 @@ static uint64_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring) + { + struct amdgpu_device *adev = ring->adev; + +- if (ring == &adev->vce.ring[0]) ++ if (ring->me == 0) + return RREG32(mmVCE_RB_WPTR); + else + return RREG32(mmVCE_RB_WPTR2); +@@ -90,7 +90,7 @@ static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring) + { + struct amdgpu_device *adev = ring->adev; + +- if (ring == &adev->vce.ring[0]) ++ if (ring->me == 0) + WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); + else + WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); +@@ -627,8 +627,10 @@ static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev) + { + int i; + +- for (i = 0; i < adev->vce.num_rings; i++) ++ for (i = 0; i < adev->vce.num_rings; i++) { + adev->vce.ring[i].funcs = &vce_v2_0_ring_funcs; ++ adev->vce.ring[i].me = i; ++ } + } + + static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = { +diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +index a71b975..99604d0 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +@@ -86,9 +86,9 @@ static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring) + else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) + WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); + +- if (ring == &adev->vce.ring[0]) ++ if (ring->me == 0) + v = RREG32(mmVCE_RB_RPTR); +- else if (ring == &adev->vce.ring[1]) ++ else if (ring->me == 1) + v = RREG32(mmVCE_RB_RPTR2); + else + v = RREG32(mmVCE_RB_RPTR3); +@@ -118,9 +118,9 @@ static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring) + else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) + WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); + +- if (ring == &adev->vce.ring[0]) ++ if (ring->me == 0) + v = RREG32(mmVCE_RB_WPTR); +- else if (ring == &adev->vce.ring[1]) ++ else if (ring->me == 1) + v = RREG32(mmVCE_RB_WPTR2); + else + v = RREG32(mmVCE_RB_WPTR3); +@@ -149,9 +149,9 @@ static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring) + else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) + WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); + +- if (ring == &adev->vce.ring[0]) ++ if (ring->me == 0) + WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); +- else if (ring == &adev->vce.ring[1]) ++ else if (ring->me == 1) + WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); + else + WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); +@@ -942,12 +942,16 @@ static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev) + int i; + + if (adev->asic_type >= CHIP_STONEY) { +- for (i = 0; i < adev->vce.num_rings; i++) ++ for (i = 0; i < adev->vce.num_rings; i++) { + adev->vce.ring[i].funcs = &vce_v3_0_ring_vm_funcs; ++ adev->vce.ring[i].me = i; ++ } + DRM_INFO("VCE enabled in VM mode\n"); + } else { +- for (i = 0; i < adev->vce.num_rings; i++) ++ for (i = 0; i < adev->vce.num_rings; i++) { + adev->vce.ring[i].funcs = &vce_v3_0_ring_phys_funcs; ++ adev->vce.ring[i].me = i; ++ } + DRM_INFO("VCE enabled in physical mode\n"); + } + } +diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +index 8fd1b74..575bf97 100755 +--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +@@ -60,9 +60,9 @@ static uint64_t vce_v4_0_ring_get_rptr(struct amdgpu_ring *ring) + { + struct amdgpu_device *adev = ring->adev; + +- if (ring == &adev->vce.ring[0]) ++ if (ring->me == 0) + return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR)); +- else if (ring == &adev->vce.ring[1]) ++ else if (ring->me == 1) + return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2)); + else + return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3)); +@@ -82,9 +82,9 @@ static uint64_t vce_v4_0_ring_get_wptr(struct amdgpu_ring *ring) + if (ring->use_doorbell) + return adev->wb.wb[ring->wptr_offs]; + +- if (ring == &adev->vce.ring[0]) ++ if (ring->me == 0) + return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR)); +- else if (ring == &adev->vce.ring[1]) ++ else if (ring->me == 1) + return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2)); + else + return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3)); +@@ -108,10 +108,10 @@ static void vce_v4_0_ring_set_wptr(struct amdgpu_ring *ring) + return; + } + +- if (ring == &adev->vce.ring[0]) ++ if (ring->me == 0) + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), + lower_32_bits(ring->wptr)); +- else if (ring == &adev->vce.ring[1]) ++ else if (ring->me == 1) + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), + lower_32_bits(ring->wptr)); + else +@@ -1088,8 +1088,10 @@ static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev) + { + int i; + +- for (i = 0; i < adev->vce.num_rings; i++) ++ for (i = 0; i < adev->vce.num_rings; i++) { + adev->vce.ring[i].funcs = &vce_v4_0_ring_vm_funcs; ++ adev->vce.ring[i].me = i; ++ } + DRM_INFO("VCE enabled in VM mode\n"); + } + +-- +2.7.4 + |