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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4808-drm-amd-pp-Unify-powergate_uvd-vce-mmhub-to-set_powe.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/4808-drm-amd-pp-Unify-powergate_uvd-vce-mmhub-to-set_powe.patch272
1 files changed, 272 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4808-drm-amd-pp-Unify-powergate_uvd-vce-mmhub-to-set_powe.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4808-drm-amd-pp-Unify-powergate_uvd-vce-mmhub-to-set_powe.patch
new file mode 100644
index 00000000..7f482729
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4808-drm-amd-pp-Unify-powergate_uvd-vce-mmhub-to-set_powe.patch
@@ -0,0 +1,272 @@
+From 97c7ec99d8ee187c1228639080f682d8f9305f63 Mon Sep 17 00:00:00 2001
+From: Rex Zhu <Rex.Zhu@amd.com>
+Date: Tue, 5 Jun 2018 13:06:11 +0800
+Subject: [PATCH 4808/5725] drm/amd/pp: Unify powergate_uvd/vce/mmhub to
+ set_powergating_by_smu
+
+Some HW ip blocks need call SMU to enter/leave power gate state.
+So export common set_powergating_by_smu interface.
+
+1. keep consistent with set_clockgating_by_smu
+2. scales easily to powergate other ip(gfx) if necessary
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 14 ++++---------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 8 +++----
+ drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 15 ++++++++++++-
+ drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 15 ++++++++++++-
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 4 ++--
+ drivers/gpu/drm/amd/include/kgd_pp_interface.h | 5 ++---
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 29 +++++++++++++++++++++++---
+ 7 files changed, 66 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+index c6d6926..ff24e1c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+@@ -287,12 +287,6 @@ enum amdgpu_pcie_gen {
+ #define amdgpu_dpm_force_performance_level(adev, l) \
+ ((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
+
+-#define amdgpu_dpm_powergate_uvd(adev, g) \
+- ((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)))
+-
+-#define amdgpu_dpm_powergate_vce(adev, g) \
+- ((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)))
+-
+ #define amdgpu_dpm_get_current_power_state(adev) \
+ ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
+
+@@ -347,6 +341,10 @@ enum amdgpu_pcie_gen {
+ ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
+ (adev)->powerplay.pp_handle, msg_id))
+
++#define amdgpu_dpm_set_powergating_by_smu(adev, block_type, gate) \
++ ((adev)->powerplay.pp_funcs->set_powergating_by_smu(\
++ (adev)->powerplay.pp_handle, block_type, gate))
++
+ #define amdgpu_dpm_get_power_profile_mode(adev, buf) \
+ ((adev)->powerplay.pp_funcs->get_power_profile_mode(\
+ (adev)->powerplay.pp_handle, buf))
+@@ -359,10 +357,6 @@ enum amdgpu_pcie_gen {
+ ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
+ (adev)->powerplay.pp_handle, type, parameter, size))
+
+-#define amdgpu_dpm_powergate_mmhub(adev) \
+- ((adev)->powerplay.pp_funcs->powergate_mmhub( \
+- (adev)->powerplay.pp_handle))
+-
+ struct amdgpu_dpm {
+ struct amdgpu_ps *ps;
+ /* number of valid power states */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index dbc8300..f30e03f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -1728,10 +1728,10 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
+
+ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
+ {
+- if (adev->powerplay.pp_funcs->powergate_uvd) {
++ if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
+ /* enable/disable UVD */
+ mutex_lock(&adev->pm.mutex);
+- amdgpu_dpm_powergate_uvd(adev, !enable);
++ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
+ mutex_unlock(&adev->pm.mutex);
+ } else {
+ if (enable) {
+@@ -1750,10 +1750,10 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
+
+ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
+ {
+- if (adev->powerplay.pp_funcs->powergate_vce) {
++ if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
+ /* enable/disable VCE */
+ mutex_lock(&adev->pm.mutex);
+- amdgpu_dpm_powergate_vce(adev, !enable);
++ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
+ mutex_unlock(&adev->pm.mutex);
+ } else {
+ if (enable) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+index b6248c0..85b3f46 100644
+--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
++++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+@@ -6764,6 +6764,19 @@ static int ci_dpm_read_sensor(void *handle, int idx,
+ }
+ }
+
++static int ci_set_powergating_by_smu(void *handle,
++ uint32_t block_type, bool gate)
++{
++ switch (block_type) {
++ case AMD_IP_BLOCK_TYPE_UVD:
++ ci_dpm_powergate_uvd(handle, gate);
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
++
+ static const struct amd_ip_funcs ci_dpm_ip_funcs = {
+ .name = "ci_dpm",
+ .early_init = ci_dpm_early_init,
+@@ -6801,7 +6814,7 @@ static const struct amd_pm_funcs ci_dpm_funcs = {
+ .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
+ .force_performance_level = &ci_dpm_force_performance_level,
+ .vblank_too_short = &ci_dpm_vblank_too_short,
+- .powergate_uvd = &ci_dpm_powergate_uvd,
++ .set_powergating_by_smu = &ci_set_powergating_by_smu,
+ .set_fan_control_mode = &ci_dpm_set_fan_control_mode,
+ .get_fan_control_mode = &ci_dpm_get_fan_control_mode,
+ .set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
+diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+index d79e6f5..cee92f8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
++++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+@@ -3305,6 +3305,19 @@ static int kv_dpm_read_sensor(void *handle, int idx,
+ }
+ }
+
++static int kv_set_powergating_by_smu(void *handle,
++ uint32_t block_type, bool gate)
++{
++ switch (block_type) {
++ case AMD_IP_BLOCK_TYPE_UVD:
++ kv_dpm_powergate_uvd(handle, gate);
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
++
+ static const struct amd_ip_funcs kv_dpm_ip_funcs = {
+ .name = "kv_dpm",
+ .early_init = kv_dpm_early_init,
+@@ -3341,7 +3354,7 @@ static const struct amd_pm_funcs kv_dpm_funcs = {
+ .print_power_state = &kv_dpm_print_power_state,
+ .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
+ .force_performance_level = &kv_dpm_force_performance_level,
+- .powergate_uvd = &kv_dpm_powergate_uvd,
++ .set_powergating_by_smu = kv_set_powergating_by_smu,
+ .enable_bapm = &kv_dpm_enable_bapm,
+ .get_vce_clock_state = amdgpu_get_vce_clock_state,
+ .check_state_equal = kv_check_state_equal,
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index 377f536..e70a0d4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -471,8 +471,8 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
+ RENG_EXECUTE_ON_REG_UPDATE, 1);
+ WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
+
+- if (adev->powerplay.pp_funcs->powergate_mmhub)
+- amdgpu_dpm_powergate_mmhub(adev);
++ if (adev->powerplay.pp_funcs->set_powergating_by_smu)
++ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
+
+ } else {
+ pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
+diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+index 0f98862..4535756 100644
+--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+@@ -232,13 +232,13 @@ struct amd_pm_funcs {
+ void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
+ int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
+ /* export to amdgpu */
+- void (*powergate_uvd)(void *handle, bool gate);
+- void (*powergate_vce)(void *handle, bool gate);
+ struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
+ int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
+ enum amd_pm_state_type *user_state);
+ int (*load_firmware)(void *handle);
+ int (*wait_for_fw_loading_complete)(void *handle);
++ int (*set_powergating_by_smu)(void *handle,
++ uint32_t block_type, bool gate);
+ int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
+ int (*set_power_limit)(void *handle, uint32_t n);
+ int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
+@@ -269,7 +269,6 @@ struct amd_pm_funcs {
+ int (*get_power_profile_mode)(void *handle, char *buf);
+ int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
+ int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
+- int (*powergate_mmhub)(void *handle);
+ };
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index f9baa04..02ba7c9 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -254,6 +254,7 @@ static int pp_set_powergating_state(void *handle,
+ /* Enable/disable GFX per cu powergating through SMU */
+ return hwmgr->hwmgr_func->powergate_gfx(hwmgr,
+ state == AMD_PG_STATE_GATE);
++
+ }
+
+ static int pp_suspend(void *handle)
+@@ -1194,14 +1195,36 @@ static int pp_dpm_powergate_mmhub(void *handle)
+ return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
+ }
+
++static int pp_set_powergating_by_smu(void *handle,
++ uint32_t block_type, bool gate)
++{
++ int ret = 0;
++
++ switch (block_type) {
++ case AMD_IP_BLOCK_TYPE_UVD:
++ case AMD_IP_BLOCK_TYPE_VCN:
++ pp_dpm_powergate_uvd(handle, gate);
++ break;
++ case AMD_IP_BLOCK_TYPE_VCE:
++ pp_dpm_powergate_vce(handle, gate);
++ break;
++ case AMD_IP_BLOCK_TYPE_GMC:
++ pp_dpm_powergate_mmhub(handle);
++ break;
++ case AMD_IP_BLOCK_TYPE_GFX:
++ break;
++ default:
++ break;
++ }
++ return ret;
++}
++
+ static const struct amd_pm_funcs pp_dpm_funcs = {
+ .load_firmware = pp_dpm_load_fw,
+ .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
+ .force_performance_level = pp_dpm_force_performance_level,
+ .get_performance_level = pp_dpm_get_performance_level,
+ .get_current_power_state = pp_dpm_get_current_power_state,
+- .powergate_vce = pp_dpm_powergate_vce,
+- .powergate_uvd = pp_dpm_powergate_uvd,
+ .dispatch_tasks = pp_dpm_dispatch_tasks,
+ .set_fan_control_mode = pp_dpm_set_fan_control_mode,
+ .get_fan_control_mode = pp_dpm_get_fan_control_mode,
+@@ -1221,6 +1244,7 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
+ .get_vce_clock_state = pp_dpm_get_vce_clock_state,
+ .switch_power_profile = pp_dpm_switch_power_profile,
+ .set_clockgating_by_smu = pp_set_clockgating_by_smu,
++ .set_powergating_by_smu = pp_set_powergating_by_smu,
+ .get_power_profile_mode = pp_get_power_profile_mode,
+ .set_power_profile_mode = pp_set_power_profile_mode,
+ .odn_edit_dpm_table = pp_odn_edit_dpm_table,
+@@ -1238,6 +1262,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
+ .set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
+ .display_clock_voltage_request = pp_display_clock_voltage_request,
+ .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
+- .powergate_mmhub = pp_dpm_powergate_mmhub,
+ };
+
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-16 12:57:04 +0000