diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4774-drm-amd-display-fix-pplib-voltage-request.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4774-drm-amd-display-fix-pplib-voltage-request.patch | 124 |
1 files changed, 124 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4774-drm-amd-display-fix-pplib-voltage-request.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4774-drm-amd-display-fix-pplib-voltage-request.patch new file mode 100644 index 00000000..bf9222f3 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4774-drm-amd-display-fix-pplib-voltage-request.patch @@ -0,0 +1,124 @@ +From eb8578390ab985f51250d8f29dc3e963c0e065f1 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Fri, 1 Jun 2018 15:01:32 -0400 +Subject: [PATCH 4774/5725] drm/amd/display: fix pplib voltage request + +This fixes incorrect clock caching and by extension fixes +the clock reporting. + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Eric Yang <eric.yang2@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 59 ++++++++++++++----------- + 1 file changed, 32 insertions(+), 27 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +index e62a21f..0a4ae0f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +@@ -570,37 +570,25 @@ static void dcn1_update_clocks(struct dccg *dccg, + bool send_request_to_increase = false; + bool send_request_to_lower = false; + ++ if (new_clocks->phyclk_khz) ++ smu_req.display_count = 1; ++ else ++ smu_req.display_count = 0; ++ + if (new_clocks->dispclk_khz > dccg->clks.dispclk_khz + || new_clocks->phyclk_khz > dccg->clks.phyclk_khz + || new_clocks->fclk_khz > dccg->clks.fclk_khz + || new_clocks->dcfclk_khz > dccg->clks.dcfclk_khz) + send_request_to_increase = true; + +- /* make sure dcf clk is before dpp clk to +- * make sure we have enough voltage to run dpp clk +- */ +- if (send_request_to_increase) { +- /*use dcfclk to request voltage*/ +- clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; +- clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks); +- dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req); +- } +- +- if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) { +- dcn1_ramp_up_dispclk_with_dpp(dccg, new_clocks); +- dccg->clks.dispclk_khz = new_clocks->dispclk_khz; +- +- send_request_to_lower = true; +- } +- + if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, dccg->clks.phyclk_khz)) { +- clock_voltage_req.clocks_in_khz = new_clocks->phyclk_khz; ++ dccg->clks.phyclk_khz = new_clocks->phyclk_khz; + + send_request_to_lower = true; + } + + if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, dccg->clks.fclk_khz)) { +- dccg->clks.phyclk_khz = new_clocks->fclk_khz; ++ dccg->clks.fclk_khz = new_clocks->fclk_khz; + clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_FCLK; + clock_voltage_req.clocks_in_khz = new_clocks->fclk_khz; + smu_req.hard_min_fclk_khz = new_clocks->fclk_khz; +@@ -610,7 +598,7 @@ static void dcn1_update_clocks(struct dccg *dccg, + } + + if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, dccg->clks.dcfclk_khz)) { +- dccg->clks.phyclk_khz = new_clocks->dcfclk_khz; ++ dccg->clks.dcfclk_khz = new_clocks->dcfclk_khz; + smu_req.hard_min_dcefclk_khz = new_clocks->dcfclk_khz; + + send_request_to_lower = true; +@@ -620,22 +608,39 @@ static void dcn1_update_clocks(struct dccg *dccg, + new_clocks->dcfclk_deep_sleep_khz, dccg->clks.dcfclk_deep_sleep_khz)) { + dccg->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; + smu_req.min_deep_sleep_dcefclk_mhz = new_clocks->dcfclk_deep_sleep_khz; ++ ++ send_request_to_lower = true; + } + +- if (!send_request_to_increase && send_request_to_lower) { ++ /* make sure dcf clk is before dpp clk to ++ * make sure we have enough voltage to run dpp clk ++ */ ++ if (send_request_to_increase) { + /*use dcfclk to request voltage*/ + clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; + clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks); + dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req); ++ if (pp_smu->set_display_requirement) ++ pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req); + } + +- if (new_clocks->phyclk_khz) +- smu_req.display_count = 1; +- else +- smu_req.display_count = 0; ++ /* dcn1 dppclk is tied to dispclk */ ++ if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) { ++ dcn1_ramp_up_dispclk_with_dpp(dccg, new_clocks); ++ dccg->clks.dispclk_khz = new_clocks->dispclk_khz; ++ ++ send_request_to_lower = true; ++ } ++ ++ if (!send_request_to_increase && send_request_to_lower) { ++ /*use dcfclk to request voltage*/ ++ clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; ++ clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks); ++ dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req); ++ if (pp_smu->set_display_requirement) ++ pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req); ++ } + +- if (pp_smu->set_display_requirement) +- pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req); + + *smu_req_cur = smu_req; + } +-- +2.7.4 + |