diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4773-drm-amd-display-fix-dccg-dcn1-ifdef.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4773-drm-amd-display-fix-dccg-dcn1-ifdef.patch | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4773-drm-amd-display-fix-dccg-dcn1-ifdef.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4773-drm-amd-display-fix-dccg-dcn1-ifdef.patch new file mode 100644 index 00000000..4ef8cdf4 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4773-drm-amd-display-fix-dccg-dcn1-ifdef.patch @@ -0,0 +1,112 @@ +From 15ec7ed92dae7822be86da5ed4423d5c63d40a16 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Fri, 1 Jun 2018 14:13:40 -0400 +Subject: [PATCH 4773/5725] drm/amd/display: fix dccg dcn1 ifdef + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Eric Yang <eric.yang2@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 10 ++++++---- + drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 2 ++ + 2 files changed, 8 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +index df6a37b..e62a21f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +@@ -478,6 +478,7 @@ static void dce12_update_clocks(struct dccg *dccg, + } + } + ++#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + static int dcn1_determine_dppclk_threshold(struct dccg *dccg, struct dc_clocks *new_clocks) + { + bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; +@@ -575,7 +576,6 @@ static void dcn1_update_clocks(struct dccg *dccg, + || new_clocks->dcfclk_khz > dccg->clks.dcfclk_khz) + send_request_to_increase = true; + +-#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + /* make sure dcf clk is before dpp clk to + * make sure we have enough voltage to run dpp clk + */ +@@ -585,7 +585,6 @@ static void dcn1_update_clocks(struct dccg *dccg, + clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks); + dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req); + } +-#endif + + if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) { + dcn1_ramp_up_dispclk_with_dpp(dccg, new_clocks); +@@ -623,14 +622,12 @@ static void dcn1_update_clocks(struct dccg *dccg, + smu_req.min_deep_sleep_dcefclk_mhz = new_clocks->dcfclk_deep_sleep_khz; + } + +-#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + if (!send_request_to_increase && send_request_to_lower) { + /*use dcfclk to request voltage*/ + clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; + clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks); + dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req); + } +-#endif + + if (new_clocks->phyclk_khz) + smu_req.display_count = 1; +@@ -642,6 +639,7 @@ static void dcn1_update_clocks(struct dccg *dccg, + + *smu_req_cur = smu_req; + } ++#endif + + static void dce_update_clocks(struct dccg *dccg, + struct dc_clocks *new_clocks, +@@ -663,11 +661,13 @@ static void dce_update_clocks(struct dccg *dccg, + } + } + ++#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + static const struct display_clock_funcs dcn1_funcs = { + .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, + .set_dispclk = dce112_set_clock, + .update_clocks = dcn1_update_clocks + }; ++#endif + + static const struct display_clock_funcs dce120_funcs = { + .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, +@@ -816,6 +816,7 @@ struct dccg *dce120_dccg_create(struct dc_context *ctx) + return &clk_dce->base; + } + ++#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct dccg *dcn1_dccg_create(struct dc_context *ctx) + { + struct dc_debug *debug = &ctx->dc->debug; +@@ -854,6 +855,7 @@ struct dccg *dcn1_dccg_create(struct dc_context *ctx) + + return &clk_dce->base; + } ++#endif + + void dce_dccg_destroy(struct dccg **dccg) + { +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h +index be5b68d..1f1899e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h +@@ -111,7 +111,9 @@ struct dccg *dce112_dccg_create( + + struct dccg *dce120_dccg_create(struct dc_context *ctx); + ++#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct dccg *dcn1_dccg_create(struct dc_context *ctx); ++#endif + + void dce_dccg_destroy(struct dccg **dccg); + +-- +2.7.4 + |