diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4629-drm-amdgpu-Changed-CU-reservation-golden-settings.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4629-drm-amdgpu-Changed-CU-reservation-golden-settings.patch | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4629-drm-amdgpu-Changed-CU-reservation-golden-settings.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4629-drm-amdgpu-Changed-CU-reservation-golden-settings.patch new file mode 100644 index 00000000..0df58a98 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4629-drm-amdgpu-Changed-CU-reservation-golden-settings.patch @@ -0,0 +1,39 @@ +From 31e74e6aa5cdb2136868174938fa3e6793410204 Mon Sep 17 00:00:00 2001 +From: Oak Zeng <Oak.Zeng@amd.com> +Date: Fri, 1 Jun 2018 17:25:06 -0400 +Subject: [PATCH 4629/5725] drm/amdgpu: Changed CU reservation golden settings + +With previous golden settings, compute task can't use +reserved LDS (32K) on CU0 and CU1. On 64K LDS system, +if compute work group allocate more than 32K LDS, then +it can't be dispatched to CU0 and CU1 because of the +reservation. This enables compute task to use reserved +LDS on CU0 and CU1. + +Change-Id: I534981622f524fd22a38d0b0bcb302b9bc00a793 +Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index ea348fe..b093777 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -88,8 +88,8 @@ static const struct soc15_reg_golden golden_settings_gc_9_0[] = + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), +- SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), +- SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x00ffff8f), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), +-- +2.7.4 + |