diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4574-drm-amd-pp-Connect-display_clock_voltage_request-to-.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4574-drm-amd-pp-Connect-display_clock_voltage_request-to-.patch | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4574-drm-amd-pp-Connect-display_clock_voltage_request-to-.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4574-drm-amd-pp-Connect-display_clock_voltage_request-to-.patch new file mode 100644 index 00000000..f51c069a --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4574-drm-amd-pp-Connect-display_clock_voltage_request-to-.patch @@ -0,0 +1,115 @@ +From be6c44933d31fe66ad96d2291c917a8219e556af Mon Sep 17 00:00:00 2001 +From: Mikita Lipski <mikita.lipski@amd.com> +Date: Tue, 29 May 2018 17:44:36 -0400 +Subject: [PATCH 4574/5725] drm/amd/pp: Connect display_clock_voltage_request + to a function pointer + +Get rid of an empty dublicate of smu10_display_clock_voltage_request + +Add display_clock_voltage_request to smu10 functions struct so it +can be called from outside the class and connect the pointer to +the function. + +That way Display driver can finally apply clock voltage requests +when needed. + +Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 64 +++++++++++------------ + 1 file changed, 31 insertions(+), 33 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +index 73c2e43..d4bc83e 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +@@ -53,8 +53,37 @@ static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic; + + + static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, +- struct pp_display_clock_request *clock_req); ++ struct pp_display_clock_request *clock_req) ++{ ++ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); ++ enum amd_pp_clock_type clk_type = clock_req->clock_type; ++ uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; ++ PPSMC_Msg msg; + ++ switch (clk_type) { ++ case amd_pp_dcf_clock: ++ if (clk_freq == smu10_data->dcf_actual_hard_min_freq) ++ return 0; ++ msg = PPSMC_MSG_SetHardMinDcefclkByFreq; ++ smu10_data->dcf_actual_hard_min_freq = clk_freq; ++ break; ++ case amd_pp_soc_clock: ++ msg = PPSMC_MSG_SetHardMinSocclkByFreq; ++ break; ++ case amd_pp_f_clock: ++ if (clk_freq == smu10_data->f_actual_hard_min_freq) ++ return 0; ++ smu10_data->f_actual_hard_min_freq = clk_freq; ++ msg = PPSMC_MSG_SetHardMinFclkByFreq; ++ break; ++ default: ++ pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); ++ return -EINVAL; ++ } ++ smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq); ++ ++ return 0; ++} + + static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps) + { +@@ -1023,39 +1052,7 @@ static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, + return 0; + } + +-static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, +- struct pp_display_clock_request *clock_req) +-{ +- struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); +- enum amd_pp_clock_type clk_type = clock_req->clock_type; +- uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; +- PPSMC_Msg msg; +- +- switch (clk_type) { +- case amd_pp_dcf_clock: +- if (clk_freq == smu10_data->dcf_actual_hard_min_freq) +- return 0; +- msg = PPSMC_MSG_SetHardMinDcefclkByFreq; +- smu10_data->dcf_actual_hard_min_freq = clk_freq; +- break; +- case amd_pp_soc_clock: +- msg = PPSMC_MSG_SetHardMinSocclkByFreq; +- break; +- case amd_pp_f_clock: +- if (clk_freq == smu10_data->f_actual_hard_min_freq) +- return 0; +- smu10_data->f_actual_hard_min_freq = clk_freq; +- msg = PPSMC_MSG_SetHardMinFclkByFreq; +- break; +- default: +- pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); +- return -EINVAL; +- } + +- smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq); +- +- return 0; +-} + + static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) + { +@@ -1188,6 +1185,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = { + .set_mmhub_powergating_by_smu = smu10_set_mmhub_powergating_by_smu, + .smus_notify_pwe = smu10_smus_notify_pwe, + .gfx_off_control = smu10_gfx_off_control, ++ .display_clock_voltage_request = smu10_display_clock_voltage_request, + }; + + int smu10_init_function_pointers(struct pp_hwmgr *hwmgr) +-- +2.7.4 + |